Protocol conversion system and method and field programmable gate array (FPGA)

Abstract

The invention provides a protocol conversion system and method and a field programmable gate array (FPGA), the system comprises an FPGA, a data sending end and a data receiving end, and the FPGA comprises a receiving module, an analysis module, a recombination module and a sending module; the receiving module is used for receiving data of a first protocol type sent by a data sending end, extracting a target receiving clock of the data of the first protocol type, obtaining parallel data of the first protocol type and sending the parallel data to the analysis module; the parsing module is used for parsing the parallel data of the first protocol type to obtain parsed data of the first protocol type and sending the parsed data to the recombination module; the recombination module is used for packaging and recombining the analyzed data of the first protocol type based on the second protocol type to obtain data of the second protocol type and sending the data of the second protocol type to the sending module; and the sending module is used for generating a sending clock of the data of the second protocol type and sending the data of the second protocol type to a data receiving end according to the sending clock so as to realize bidirectional conversion between protocols.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to a protocol conversion system, method, and field programmable gate array (FPGA). Background Art

[0002] The Scalable Low Voltage Signaling with Embedded Clock (SLVS-EC) technology is applied to image sensors, while the Video By One High Speed (V-by-One HS) transmission technology is mainly for ultra-high definition display devices. In signal transmission scenarios such as industrial cameras, medical imaging devices, and ultra-high definition display systems, there is a protocol incompatibility problem between V-by-One HS and SLVS-EC.

[0003] Currently, the conversion between the SLVS-EC protocol and the V-by-One HS protocol is mainly achieved through application-specific integrated circuit (ASIC) chips and discrete devices. However, ASICs require specialized custom design, have high costs, cannot adapt to dynamic parameter adjustment, and have poor flexibility. Discrete devices require multi-level level conversion circuits, have high hardware complexity, high power consumption, and are difficult to expand the number of channels.

[0004] Therefore, there are certain limitations in the bidirectional protocol conversion between SLVS-EC and V-by-One HS in the prior art. Summary of the Invention

[0005] The purpose of this application is to provide a protocol conversion system, method, and field programmable gate array (FPGA) to address the practical need for the limitations in the protocol conversion between SLVS-EC and V-by-One HS in the prior art.

[0006] To achieve the above objective, the technical solutions adopted in the embodiments of this application are as follows:

[0007] In a first aspect, an embodiment of this application provides a protocol conversion system, which includes: a field programmable gate array (FPGA), a data sending end, and a data receiving end that are respectively connected to the FPGA. Among them, the FPGA includes: a parallel receiving module, parsing module, recombination module, and sending module.

[0008] The receiving module is configured to receive data of a first protocol type sent by the data sending end, extract the target receiving clock of the data of the first protocol type, obtain parallel data of the first protocol type, and send the parallel data to the parsing module, wherein the parallel data of the first protocol type includes the target receiving clock;

[0009] The parsing module is configured to parse the parallel data of the first protocol type, obtain parsed data of the first protocol type, and send the parsed data to the recombination module;

[0010] The recombination module is configured to encapsulate and recombine the parsed data of the first protocol type based on a second protocol type, obtain data of the second protocol type, and send the data to the sending module;

[0011] The sending module is configured to generate a sending clock for the data of the second protocol type, and send the data of the second protocol type to the data receiving end according to the sending clock.

[0012] As an optional implementation, the FPGA further includes: a configuration module;

[0013] The configuration module is respectively connected to the receiving module, the parsing module, the recombination module, and the sending module, and is configured to send a first configuration instruction, a second configuration instruction, a third configuration instruction, and a fourth configuration instruction to the receiving module, the parsing module, the recombination module, and the sending module respectively to configure corresponding functions.

[0014] As an optional implementation, the receiving module is specifically configured to determine receiving parameters according to the first configuration instruction, where the receiving parameters include the number of receiving channels and the receiving channel rate;

[0015] According to the receiving parameters, receive the data of the first protocol type sent by the data sending end, extract the target receiving clock of the data of the first protocol type, and perform serial-to-parallel conversion processing on the data of the first protocol type according to the target receiving clock;

[0016] When the number of receiving channels is multiple, synchronously calibrate the multiple receiving channels according to the target receiving clock, obtain parallel data with aligned phases, and use the parallel data with aligned phases as the parallel data of the first protocol type.

[0017] As an optional implementation, the receiving module is specifically configured to iteratively adjust the sampling phase during serial-to-parallel conversion processing by using a dynamic phase difference algorithm, and compensate for the jitter of the receiving clock in real time to obtain the target receiving clock.

[0018] As an alternative implementation, the parsing module is specifically configured to determine a protocol parsing mode, a first resolution, and a first check enabling state according to the second configuration instruction;

[0019] Parse the header field in the parallel data of the first protocol type according to the protocol parsing mode, and extract valid image data from the parallel data of the first protocol type according to the header field and the first resolution;

[0020] Determine whether to check the valid image data according to the first check enabling state. If so, generate a first check field according to the valid image data, check the valid image data according to the first check field, and use the valid image data that passes the check as the parsed data of the first protocol type; otherwise, use the valid image data as the parsed data of the first protocol type.

[0021] As an alternative implementation, the FPGA further includes: a buffer module, and the buffer module includes a first buffer and a second buffer; the first buffer is respectively connected to the parsing module and the recombination module, and the second buffer is respectively connected to the parsing module and the recombination module;

[0022] The first buffer is configured to receive the parsed data of the first protocol type sent by the parsing module in a data reading state, and switch to a data writing state when a first preset condition is met, and send the received parsed data of the first protocol type to the recombination module in the data writing state;

[0023] The second buffer is configured to receive the parsed data of the first protocol type sent by the parsing module in the data reading state, and switch to the data writing state when a second preset condition is met, and send the received parsed data of the first protocol type to the recombination module in the data writing state; wherein, the data reading and writing states of the first buffer and the second buffer are opposite.

[0024] As an alternative implementation, the recombination module is specifically configured to determine a second resolution, a target protocol type, and a second check enabling state according to the third configuration instruction, wherein the target protocol type is the second protocol type;

[0025] Insert a preset synchronization header into the starting position of the parsed data of the first protocol type according to the second protocol type, and determine whether to generate a second check field according to the second check enabling state;

[0026] If so, generate the second check field according to the parsed data of the first protocol type, and insert the second check field at the end position of the parsed data of the first protocol type to obtain the initial data of the second protocol type; otherwise, use the parsed data of the first protocol type with the sync header inserted as the initial data of the second protocol type;

[0027] Iteratively adjust the packet length of the initial data of the second protocol type according to the second resolution to obtain the data of the second protocol type.

[0028] As an optional implementation, the sending module is specifically configured to determine sending parameters according to the fourth configuration instruction, where the sending parameters include the number of sending channels, the sending channel rate, the scrambling mode, and the electrical signal adjustment parameters;

[0029] Generate a sending clock for the data of the second protocol type according to the number of sending channels and the sending channel rate, and perform cross-clock domain synchronization through the first-in first-out buffer of the FPGA according to the sending clock and the target receiving clock;

[0030] Send the data of the second protocol type to the data receiving end through level driving according to the sending clock, the scrambling mode, and the electrical signal adjustment parameters.

[0031] In a second aspect, an embodiment of the present application provides a protocol conversion method, which is applied to the protocol conversion system described in the first aspect above; the method includes:

[0032] The receiving module receives the data of the first protocol type sent by the data sending end, extracts the target receiving clock of the data of the first protocol type, obtains the parallel data of the first protocol type and sends it to the parsing module, where the parallel data of the first protocol type includes the target receiving clock;

[0033] The parsing module parses the parallel data of the first protocol type to obtain the parsed data of the first protocol type and sends it to the recombination module;

[0034] The recombination module encapsulates and recombines the parsed data of the first protocol type based on the second protocol type to obtain the data of the second protocol type and sends it to the sending module;

[0035] The sending module generates a sending clock for the data of the second protocol type and sends the data of the second protocol type to the data receiving end according to the sending clock.

[0036] In a third aspect, an embodiment of the present application provides a field programmable gate array (FPGA), which includes: a parallel receiving module, parsing module, recombination module, and sending module;

[0037] The FPGA is used to execute the steps of the protocol conversion method described in the second aspect above.

[0038] The beneficial effects of the present application are:

[0039] The present application provides a protocol conversion system, method, and field programmable gate array (FPGA). The FPGA in the protocol conversion system includes a parallel receiving module, parsing module, recombination module, and sending module. The receiving module is used to receive data of a first protocol type sent by a data sending end in the protocol conversion system, extract a target receiving clock from the data of the first protocol type, obtain parallel data of the first protocol type including the target receiving clock, and send it to the parsing module. The parsing module is used to parse the parallel data of the first protocol type sent by the receiving module based on the first protocol type, obtain parsed data of the first protocol type, and send it to the recombination module. The recombination module is used to encapsulate the parsed data of the first protocol type according to a second protocol type, recombine it into data of the second protocol type, and send the parallel data of the second protocol type to the sending module. The sending module is used to generate a sending clock for the data of the second protocol type and send the data of the second protocol type to the data receiving end according to the sending clock. Through the parallel receiving module, parsing module, recombination module, and sending module in the FPGA, data reception, protocol parsing, data recombination, clock generation, and data sending are performed, realizing bidirectional conversion between two protocols. Description of the Drawings

[0040] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other relevant drawings can also be obtained based on these drawings.

[0041] Figure 1 It is a schematic diagram of the architecture of the protocol conversion system provided by the embodiment of the present application;

[0042] Figure 2 It is another schematic diagram of the architecture of the protocol conversion system provided by the embodiment of the present application;

[0043] Figure 3 It is yet another schematic diagram of the architecture of the protocol conversion system provided by the embodiment of the present application. Detailed Embodiments

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. It should be understood that the accompanying drawings in this application are only for the purposes of illustration and description, and are not used to limit the protection scope of this application. In addition, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate the operations implemented according to some embodiments of this application. It should be understood that the operations in the flowchart may not be implemented in sequence, and steps without logical context relationships may be reversed or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart or remove one or more operations from the flowchart under the guidance of the content of this application.

[0045] In addition, the described embodiments are only some embodiments of this application, rather than all embodiments. The components of the embodiments of this application described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of this application to be protected, but only represents the selected embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of this application.

[0046] It should be noted that the term "including" will be used in the embodiments of this application to indicate the existence of the features stated thereafter, but does not exclude the addition of other features.

[0047] In the signal transmission scenario, there is a protocol incompatibility problem between V-by-One HS and SLVS-EC. Currently, the unidirectional conversion between the SLVS-EC protocol and the V-by-One HS protocol is mainly achieved through ASICs and discrete devices. However, ASICs require specialized custom design, with high costs, inability to adapt to dynamic parameter adjustment, and poor flexibility. Discrete devices require multi-level level conversion circuits, with high hardware complexity, high power consumption, and difficulty in expanding the number of channels. And the bidirectional conversion between the SLVS-EC protocol and the V-by-One HS protocol cannot be achieved. That is, there are certain limitations in the protocol conversion between SLVS-EC and V-by-One HS in the prior art.

[0048] Based on the above problems, the embodiments of this application propose a protocol conversion system. Through the pipelined parallel design of each module inside a Field-Programmable Gate Array (FPGA for short), the bidirectional protocol conversion from SLVS-EC to V-by-One is achieved, without the need for additional chips, reducing the hardware complexity and costs, and improving the flexibility and configurability of the protocol conversion.

[0049] Figure 1 This is a schematic diagram of the architecture of the protocol conversion system provided by the embodiments of the present application. As Figure 1 shown, the protocol conversion system includes: a Field Programmable Gate Array (FPGA), a data sending end and a data receiving end respectively connected to the FPGA. Among them, the FPGA includes: a parallel receiving module 1, a parsing module 2, a recombination module 3, and a sending module 4.

[0050] Optionally, referring to Figure 1 , the protocol conversion system includes an FPGA, a data sending end, and a data receiving end. The first input end of the FPGA is connected to the output end of the data sending end, and the output end of the FPGA is connected to the input end of the data receiving end. The FPGA is used to receive data of the first protocol type sent by the data sending end, convert the data of the first protocol type into data of the second protocol type through protocol conversion, and send the data of the second protocol type to the data receiving end. Or, the FPGA can also receive data of the second protocol type sent by the data sending end, convert the data of the second protocol type into data of the first protocol type through protocol conversion, and send the data of the first protocol type to the data receiving end, realizing bidirectional conversion between the two protocols.

[0051] Among them, the FPGA adopts a pipeline parallel design internally. The FPGA includes a parallel receiving module 1, a parsing module 2, a recombination module 3, and a sending module 4. The receiving module 1 is respectively connected to the output end of the data sending end and the first input end of the parsing module 2. The output end of the parsing module 2 is connected to the first input end of the recombination module 3. The output end of the recombination module 3 is connected to the first input end of the sending module 4. The output end of the sending module 4 is connected to the input end of the data receiving end. The receiving module 1, the parsing module 2, the recombination module 3, and the sending module 4 inside the FPGA run in parallel and are all part of the pipeline design.

[0052] The receiving module 1 is used to receive data of the first protocol type sent by the data sending end, extract the target receiving clock of the data of the first protocol type, obtain parallel data of the first protocol type and send it to the parsing module 2, where the parallel data of the first protocol type includes the target receiving clock.

[0053] Optionally, a first high-speed transceiver is integrated in the receiving module 1. The receiving module 1 is configured to receive data of a first protocol type sent by a data sending end through the first high-speed transceiver. The data of the first protocol type is transmitted to the receiving module 1 in the form of differential signals. The receiving module 1 extracts a target receiving clock from the data of the first protocol type and deserializes the data of the first protocol type based on the target receiving clock to obtain parallel data of the first protocol type including the target receiving clock. The receiving module 1 sends the parallel data of the first protocol type including the target receiving clock to the parsing module 2 so that the parsing module 2 can parse the parallel data of the first protocol type including the target receiving clock.

[0054] Among them, as part of the internal pipeline design of the FPGA, the receiving module 1 is also configured to continue receiving the data of the first protocol type sent by the data sending end after sending the parallel data of the first protocol type including the target receiving clock, and extract the target receiving clock and deserialize the data to ensure the parallel processing ability of the receiving module 1.

[0055] The parsing module 2 is configured to parse the parallel data of the first protocol type to obtain parsed data of the first protocol type and send it to the recombination module 3.

[0056] Optionally, the parsing module 2 is configured to parse the parallel data of the first protocol type sent by the receiving module 1 based on the first protocol type to obtain parsed data of the first protocol type, and send the parsed data of the first protocol type to the recombination module 3. Among them, the parsed data of the first protocol type is parallel data including the target receiving clock.

[0057] Among them, as part of the internal pipeline design of the FPGA, the parsing module 2 is also configured to continue receiving and parsing the parallel data of the first protocol type sent by the receiving module 1 after sending the parsed data of the first protocol type to ensure the parallel processing ability of the parsing module 2.

[0058] The recombination module 3 is configured to encapsulate and recombine the parsed data of the first protocol type based on a second protocol type to obtain data of the second protocol type and send it to the sending module 4.

[0059] Optionally, the recombination module 3 is configured to encapsulate the parsed data of the first protocol type according to the second protocol type, recombine it into data of the second protocol type, and send the data of the second protocol type and the target receiving clock to the sending module 4. Among them, the data of the second protocol type is parallel data.

[0060] Among them, the recombination module 3, as part of the internal pipeline design of the FPGA, is also used to continue receiving and encapsulating the parsed data of the first protocol type sent by the recombination and parsing module 2 after sending the data of the second protocol type and the target receiving clock, ensuring the parallel processing ability of the recombination module 3.

[0061] The sending module 4 is used to generate the sending clock for the data of the second protocol type and send the data of the second protocol type to the data receiving end according to the sending clock.

[0062] Optionally, a Phase-Locked Loop (PLL) is integrated in the sending module 4. The sending module 4 is used to generate the sending clock for the data of the second protocol type through the PLL and, based on the target receiving clock sent by the recombination module 3, synchronize the target receiving clock of the data of the first protocol type with the sending clock of the data of the second protocol type, ensuring the timing consistency of the data of the two different protocols. The sending module 4 performs serialization processing on the parallel second-protocol data sent by the recombination module 3 to obtain the serialized data of the second protocol type.

[0063] A second high-speed transceiver is also integrated in the sending module 4. The sending module 4 is used to send the serialized data of the second protocol type to the data receiving end according to the sending clock through the second high-speed transceiver. Among them, the serialized data of the second protocol type is transmitted to the data receiving end in the form of differential signals.

[0064] Among them, the sending module 4, as part of the internal pipeline design of the FPGA, is also used to continue receiving the target receiving clock and the parallel second-protocol data sent by the recombination module 3 after sending the serialized data of the second protocol type, generate the sending clock and send the serialized data of the second protocol type to the data receiving end, ensuring the parallel processing ability of the sending module 4.

[0065] It should be noted that the data of the first protocol type is SLVS-EC data, and the data of the second protocol type is V-by-One HS data. Or, the data of the first protocol type is V-by-One HS data, and the data of the second protocol type is SLVS-EC data. Based on this, two-way conversion between SLVS-EC data and V-by-One HS data can be achieved.

[0066] In this embodiment, the FPGA in the protocol conversion system includes a parallel receiving module, parsing module, recombination module, and sending module. The receiving module is used to receive data of a first protocol type sent by the data sending end in the protocol conversion system, extract the target receiving clock from the data of the first protocol type, obtain parallel data of the first protocol type including the target receiving clock, and send it to the parsing module. The parsing module is used to parse the parallel data of the first protocol type sent by the receiving module based on the first protocol type, obtain the parsed data of the first protocol type, and send it to the recombination module. The recombination module is used to encapsulate the parsed data of the first protocol type according to the second protocol type, recombine it into data of the second protocol type, and send the parallel data of the second protocol type to the sending module. The sending module is used to generate the sending clock for the data of the second protocol type and send the data of the second protocol type to the data receiving end according to the sending clock. Through the parallel receiving module, parsing module, recombination module, and sending module in the FPGA, data reception, protocol parsing, data recombination, clock generation, and data sending are performed to achieve bidirectional conversion between the two protocols.

[0067] Figure 2 Another schematic diagram of the architecture of the protocol conversion system provided by the embodiment of the present application is shown in Figure 2 As shown, the FPGA further includes: a configuration module 5.

[0068] The configuration module 5 is respectively connected to the receiving module 1, parsing module 2, recombination module 3, and sending module 4, and is used to send a first configuration instruction, a second configuration instruction, a third configuration instruction, and a fourth configuration instruction to the receiving module 1, parsing module 2, recombination module 3, and sending module 4 respectively to configure the corresponding functions.

[0069] Optionally, referring to Figure 2 , the FPGA further includes a configuration module 5, and the configuration file of the FPGA and each dynamic parameter are pre-stored in the configuration module 5. The configuration module 5 is used to generate each configuration instruction based on the pre-stored configuration file of the FPGA and each dynamic parameter and send it to each module in the FPGA to pre-configure the corresponding functions of each module.

[0070] Specifically, the first output terminal of the configuration module 5 is connected to the second input terminal of the receiving module 1, and is used to send a first configuration instruction to the receiving module 1 to flexibly configure the data receiving function of the receiving module 1. The second output terminal of the configuration module 5 is connected to the second input terminal of the parsing module 2, and is used to send a second configuration instruction to the parsing module 2 to flexibly configure the protocol parsing function of the parsing module 2. The third output terminal of the configuration module 5 is connected to the second input terminal of the recombination module 3, and is used to send a third configuration instruction to the recombination module 3 to flexibly configure the data recombination function of the recombination module 3. The fourth output terminal of the configuration module 5 is connected to the second input terminal of the sending module 4, and is used to send a fourth configuration instruction to the sending module 4 to flexibly configure the data sending function of the sending module 4.

[0071] It should be noted that, continuing to refer to Figure 2 , the protocol conversion system further includes: a configuration memory, and the configuration memory is connected to the input terminal of the configuration module 5. The configuration memory is used to receive and store the configuration file and dynamic parameters of the FPGA sent by an external controller such as a micro control unit (MCU for short), and send the configuration file and each dynamic parameter of the FPGA to the configuration module 5, so that the configuration module 5 generates each configuration instruction based on the configuration file and each dynamic parameter of the FPGA and sends them to each module in the FPGA. Among them, the dynamic parameters can be resolution, color depth, etc.

[0072] Continuing to refer to Figure 2 , the protocol conversion system further includes a power management module, and the power management module is connected to the power supply terminal of the FPGA to supply power to the FPGA. Among them, the power management module can provide independent power supply for each module in the FPGA, reduce noise interference, and improve stability in complex electromagnetic environment scenarios.

[0073] In this embodiment, a configuration module is set in the FPGA. The configuration file and each dynamic parameter of the FPGA are pre-stored in the configuration module. The configuration module is used to generate each configuration instruction, and send the first configuration instruction, the second configuration instruction, the third configuration instruction, and the fourth configuration instruction to the receiving module, the parsing module, the recombination module, and the sending module respectively, so as to pre-configure the functions of each module in the FPGA and achieve flexible configuration during protocol conversion.

[0074] As an optional implementation manner, the receiving module 1 is specifically used to determine receiving parameters according to the first configuration instruction, where the receiving parameters include the number of receiving channels and the receiving channel rate.

[0075] Optionally, the first configuration instruction is used to indicate the receiving parameters when the receiving module 1 performs data receiving operations. The receiving module 1 determines the receiving parameters according to the first configuration instruction sent by the configuration module 5, including the number of receiving channels and the receiving channel rate.

[0076] Among them, the number of receiving channels characterizes the number of channels through which the receiving module 1 can simultaneously receive data, and the receiving channel rate characterizes the transmission rate of receiving data for each channel. Exemplarily, the number of receiving channels can be 1, 2, or 4.

[0077] According to the receiving parameters, the receiving data sending end sends data of the first protocol type, extracts the target receiving clock of the data of the first protocol type, and performs serial-to-parallel conversion processing on the data of the first protocol type according to the target receiving clock.

[0078] Optionally, the first high-speed transceiver in the receiving module 1 receives the serial data of the first protocol type from the data sending end based on the number of receiving channels and the receiving channel rate in the receiving parameters. For example, if the number of receiving channels is 4 and the receiving channel rate is 1 Gbps, the receiving module 1 will simultaneously receive the serial data of the first protocol type through 4 channels at a speed of 1 Gbps per channel.

[0079] The serial data of the first protocol type contains clock information, and the receiving module 1 extracts the target receiving clock from the serial data of the first protocol type. The target receiving clock provides a time reference for data sampling and serial-to-parallel conversion processing of the receiving module 1. The receiving module 1 also includes a serializer / deserializer (Serializer / Deserializer, abbreviated as SerDes). The SerDes in the receiving module 1 performs serial-to-parallel conversion processing on the data of the first protocol type based on the target receiving clock, and converts the serial data of the first protocol type into the initial parallel data of the first protocol type, so that the data of the first protocol type is transmitted in parallel among the modules in the FPGA, thereby improving the parallel processing efficiency of the data of the first protocol type in the FPGA.

[0080] When the number of receiving channels is multiple, multiple receiving channels are synchronously calibrated according to the target receiving clock to obtain phase-aligned parallel data, and the phase-aligned parallel data is used as the parallel data of the first protocol type.

[0081] Optionally, the receiving module 1 is further configured to determine whether to perform multi-channel synchronous calibration processing according to the number of receiving channels. If the number of receiving channels is multiple, such as 2 or 4, due to the influence of factors such as transmission delay and signal attenuation of different channels, the data of each channel may be out of phase. The receiving module 1 needs to align the phases of multiple channels in real time to eliminate transmission deviation.

[0082] Specifically, when the number of receiving channels is multiple, the receiving module 1 synchronously calibrates the multiple receiving channels according to the target receiving clock, detects the time deviation of the data arrival of each channel, and adjusts the phase of each channel through a delay line, so that the data of each channel is aligned in time. Based on the parallel data of the initial first protocol type, the parallel data after phase alignment is obtained, and the parallel data after phase alignment is used as the parallel data of the first protocol type, realizing real-time phase synchronization between multiple channels.

[0083] After performing multi-channel real-time alignment calibration, the receiving module 1 performs periodic calibration of the channels at a preset time interval to adapt to the phase drift caused by temperature or voltage fluctuations, and obtains more accurate parallel data of the first protocol type. It should be noted that if there is only one receiving channel, the receiving module 1 does not need to perform multi-channel real-time alignment calibration, but only performs periodic calibration of the channel, and directly obtains the parallel data of the first protocol type after periodic calibration based on the initial parallel data of the first protocol type.

[0084] In this embodiment, the receiving module is specifically configured to determine the receiving parameters according to the first configuration instruction issued by the configuration module. Based on the number of receiving channels and the receiving channel rate in the receiving parameters, the serial data of the first protocol type is received from the data sending end. The target receiving clock is extracted from the serial data of the first protocol type, and the target receiving clock provides a time reference for the data sampling and serial-to-parallel conversion processing of the receiving module. Based on the target receiving clock, the serial-to-parallel conversion processing of the data of the first protocol type is performed, and the serial data of the first protocol type is converted into parallel data. When the number of receiving channels is multiple, the receiving module synchronously calibrates the multiple receiving channels according to the target receiving clock, obtains the parallel data after phase alignment, and uses the parallel data after phase alignment as the parallel data of the first protocol type. The receiving module flexibly realizes data reception, clock extraction, and data deserialization based on the first configuration instruction, improving the data reception efficiency and accuracy.

[0085] As an optional implementation manner, the receiving module 1 is specifically configured to iteratively adjust the sampling phase during serial-to-parallel conversion processing by using a dynamic phase difference algorithm to compensate for the jitter of the receiving clock in real time and obtain the target receiving clock.

[0086] Optionally, the receiving module 1 further includes a phase interpolator, and the phase interpolator dynamically adjusts the sampling phase during serial-to-parallel conversion by using a dynamic phase interpolation (DPI) algorithm to compensate for the jitter (phase offset) of the receiving clock in real time, improve the clock recovery accuracy, suppress high-frequency noise, iteratively reduce the phase offset, realize phase locking, and obtain a stable target receiving clock.

[0087] Among them, the DPI algorithm dynamically adjusts the sampling phase, enabling the sampling points to dynamically track the optimal sampling positions of the data, thereby correctly extracting each bit of the serial data, achieving accurate serial-to-parallel conversion, and reducing the bit error rate.

[0088] In this embodiment, the receiving module is specifically configured to iteratively adjust the sampling phase during serial-to-parallel conversion processing by using the dynamic phase difference algorithm, compensate for the jitter of the received clock in real time, iteratively reduce the phase offset, achieve phase locking, and obtain a stable target received clock. So as to achieve accurate serial-to-parallel conversion based on the stable target received clock, reduce the bit error rate, and improve the accuracy of the parallel data of the first protocol type.

[0089] As an optional implementation manner, the parsing module 2 is specifically configured to determine the protocol parsing mode, the first resolution, and the first check enable status according to the second configuration instruction.

[0090] Optionally, the second configuration instruction is used to indicate the parsing parameters when the parsing module 2 performs protocol parsing operations, including the protocol parsing mode, the first resolution, and the first check enable status. Among them, the first resolution includes the first effective resolution and the first blanking interval parameter. Exemplarily, the first effective resolution can be 3840×2160. The parsing parameters can also include the first refresh rate and the first color depth. For example, the first refresh rate can be 60Hz, and the first color depth can be 8 bits.

[0091] The parsing module 2 is specifically configured to determine the protocol parsing mode, the first resolution, and the first check enable status according to the second configuration instruction. Specifically, different protocol types correspond to different protocol parsing modes, and the protocol parsing mode represents the specific rules followed by the parsing module 2 when parsing the protocol. The first resolution represents the fineness of the parsing module 2 for extracting image data, and the first check enable status represents whether the parsing module 2 needs to perform a check operation on the extracted image data.

[0092] Parse the header field in the parallel data of the first protocol type according to the protocol parsing mode, and extract the valid image data from the parallel data of the first protocol type according to the header field and the first resolution.

[0093] Optionally, the parsing module 2 identifies and parses the header (Header) field from the parallel data of the first protocol type based on the rules of the protocol parsing mode. Among them, the Header field contains the meta information of the parallel data of the first protocol type, such as data type, data length, and frame rate, etc.

[0094] After obtaining the Header field, the parsing module 2 accurately extracts the valid image data from the parallel data of the first protocol type in combination with the first resolution. Specifically, according to the starting position and length of the valid image data indicated in the header field, and in combination with the pixel arrangement rule characterized by the first resolution, control information such as frame synchronization codes is stripped, and the image data is extracted from the parallel data of the first protocol type.

[0095] According to the first check enable state, it is determined whether to check the valid image data. If so, a first check field is generated based on the valid image data, and the valid image data is checked according to the first check field, and the valid image data with successful check is used as the parsed data of the first protocol type; otherwise, the valid image data is used as the parsed data of the first protocol type.

[0096] Optionally, the parsing module 2 determines whether to check the valid image data based on the first check enable state. Specifically, if the first check enable state is the enable state, the parsing module 2 generates a first check field according to the extracted valid image data, and the first check field is used to compare with the check information in the received parallel data of the first protocol type to determine whether the valid image data is abnormal during transmission and extraction. Exemplarily, the first check field can be a Cyclic Redundancy Check (CRC) field.

[0097] If the check is successful, it means that the valid image data has no abnormality during transmission and extraction, and the parsing module 2 uses the valid image data with successful check as the parsed data of the first protocol type; if the check fails, measures such as retransmission or re-parsing and extraction may need to be taken to ensure the accuracy of the valid image data.

[0098] If the first check enable state is the disabled state, indicating that there is no need to check the valid image data, the parsing module 2 directly uses the extracted valid image data as the parsed data of the first protocol type, improving the protocol parsing efficiency.

[0099] In this embodiment, the parsing module is specifically configured to determine a protocol parsing mode, a first resolution, and a first check enabling state according to a second configuration instruction issued by the configuration module. Based on the protocol parsing mode, the header fields are identified and parsed from the parallel data of the first protocol type, and in combination with the first resolution, the valid image data is accurately extracted from the parallel data of the first protocol type. According to the first check enabling state, it is determined whether to check the valid image data. If the first check enabling state is the enabling state, the parsing module generates a first check field according to the extracted valid image data, and checks the valid image data according to the first check field, and uses the valid image data that passes the check as the parsed data of the first protocol type. If the first check enabling state is the disabled state, the parsing module directly uses the extracted valid image data as the parsed data of the first protocol type. The parsing module flexibly implements protocol parsing, data extraction, and checking based on the second configuration instruction.

[0100] Figure 3 Another schematic diagram of the architecture of the protocol conversion system provided by the embodiment of the present application is shown in Figure 3 As shown, the FPGA further includes: a buffer module 6, and the buffer module 6 includes a first buffer 61 and a second buffer 62; the first buffer 61 is respectively connected to the parsing module 2 and the recombination module 3, and the second buffer 62 is respectively connected to the parsing module 2 and the recombination module 3.

[0101] Optionally, referring to Figure 3 , the FPGA further includes a buffer module 6, and the buffer module 6 includes a first buffer 61 and a second buffer 62 that perform alternating read and write operations. Among them, the input ends of the first buffer 61 and the second buffer 62 are both connected to the output end of the parsing module 2, and the output ends of the first buffer 61 and the second buffer 62 are both connected to the first input end of the recombination module 3. Exemplarily, the first buffer 61 may be Buffer A, and the second buffer 62 may be Buffer B. The alternately read and written Buffer A and Buffer B form a ping-pong buffer.

[0102] The first buffer 61 is configured to receive the parsed data of the first protocol type sent by the parsing module 2 in the data reading state, and switch to the data writing state when a first preset condition is met, and send the received parsed data of the first protocol type to the recombination module 3 in the data writing state.

[0103] Optionally, the first buffer 61 is used to receive and store the parsed data of the first protocol type sent by the parsing module 2 in the data reading state. At this time, the second buffer 62 is in the data writing state and sends the previously read and stored parsed data of the first protocol type to the recombination module 3 in the data writing state. That is to say, the data reading and writing states of the first buffer 61 and the second buffer 62 are always opposite.

[0104] When the first preset condition is met, the first buffer 61 automatically switches from the data reading state to the data writing state and sends the received parsed data of the first protocol type to the recombination module 3 in the data writing state. At this time, the second buffer 62 automatically switches from the data writing state to the data reading state and receives and stores the parsed data of the first protocol type sent by the parsing module 2 in the data reading state. The first preset condition may be that the data storage amount of the first buffer 61 reaches a preset threshold, or the data reception duration of the first buffer 61 reaches a preset duration, etc.

[0105] The second buffer 62 is used to receive the parsed data of the first protocol type sent by the parsing module 2 in the data reading state and, when the second preset condition is met, switches to the data writing state and sends the received parsed data of the first protocol type to the recombination module 3 in the data writing state; the data reading and writing states of the first buffer 61 and the second buffer 62 are opposite.

[0106] Optionally, the second buffer 62 is used to receive and store the parsed data of the first protocol type sent by the parsing module 2 in the data reading state. At this time, the first buffer 61 is in the data writing state and sends the previously read and stored parsed data of the first protocol type to the recombination module 3 in the data writing state.

[0107] When the second preset condition is met, the second buffer 62 automatically switches from the data reading state to the data writing state and sends the received parsed data of the first protocol type to the recombination module 3 in the data writing state. At this time, the first buffer 61 automatically switches from the data writing state to the data reading state and receives and stores the parsed data of the first protocol type sent by the parsing module 2 in the data reading state. The second preset condition may be that the data storage amount of the second buffer 62 reaches a preset threshold, or the data reception duration of the second buffer 62 reaches a preset duration, etc.

[0108] The working mode of alternating reading and writing of the first buffer 61 and the second buffer 62 enables the continuous reception and sending of data, avoids the pause time in the data processing process, and realizes continuous and efficient data transmission.

[0109] In this embodiment, the FPGA further includes a buffer module, which includes a first buffer and a second buffer. Both the first buffer and the second buffer are respectively connected to the parsing module and the recombination module. The first buffer is used to receive and store the parsed data of the first protocol type sent by the parsing module in the data reading state, and switch to the data writing state when the first preset condition is met. In the data writing state, the received parsed data of the first protocol type is sent to the recombination module. The second buffer is used to receive the parsed data of the first protocol type sent by the parsing module in the data reading state, and switch to the data writing state when the second preset condition is met. In the data writing state, the received parsed data of the first protocol type is sent to the recombination module. The data reading and writing states of the first buffer and the second buffer are always opposite. Through the alternating reading and writing of the first buffer and the second buffer, the continuous reception and transmission of data are realized, avoiding the pause time in the data processing process, and achieving continuous and efficient data transmission. The transmission efficiency of data between the protocol module and the recombination module is improved.

[0110] As an optional implementation manner, the recombination module 3 is specifically configured to determine a second resolution, a target protocol type, and a second check enable state according to a third configuration instruction, where the target protocol type is a second protocol type.

[0111] Optionally, the third configuration instruction is used to indicate the recombination parameters when the recombination module 3 performs data encapsulation and recombination, including a second resolution, a target protocol type, and a second check enable state. Among them, the second resolution includes a second effective resolution and a second blanking interval parameter. The second effective resolution is the same as the first effective resolution, and the second blanking interval parameter is different from the first blanking interval parameter.

[0112] The recombination module 3 is specifically configured to determine a second resolution, a target protocol type, and a second check enable state according to the third configuration instruction. Specifically, the target protocol type represents the specific rules followed by the recombination module 3 when encapsulating and recombining data, such as the sync header format and the check method, etc. The target protocol type is a second protocol type. The second resolution represents the image resolution required by the second protocol type, so that the recombination module 3 can adjust the data format to adapt to the display requirements of the data receiving end. The second check enable state represents whether the recombination module 3 needs to add a check field when encapsulating and recombining data.

[0113] Insert a preset sync header into the starting position of the parsed data of the first protocol type according to the second protocol type, and determine whether to generate a second check field according to the second check enable state.

[0114] Optionally, the recombination module 3 determines a preset synchronization header (Sync Code) according to the second protocol type, and inserts the synchronization header into the starting position of the parsed data of the first protocol type, so that the data receiving end can identify the data frame boundary based on the synchronization header. Exemplarily, when the second protocol type is the V-By-One protocol, the synchronization header includes meta-information such as frame type and data length.

[0115] The recombination module 3 determines whether to generate a second check field based on the second check enable state. Specifically, if the second check enable state is the enabled state, it is determined to generate a second check field; if the second check enable state is the disabled state, it is determined that there is no need to generate a second check field. Among them, the second check field can be a CRC check field.

[0116] If so, a second check field is generated according to the parsed data of the first protocol type, and the second check field is inserted into the termination position of the parsed data of the first protocol type to obtain the initial data of the second protocol type; otherwise, the parsed data of the first protocol type with the synchronization header inserted is used as the initial data of the second protocol type.

[0117] Optionally, if the second check enable state is the enabled state and it is determined to generate a second check field, the recombination module 3 generates a second check field according to the parsed data of the first protocol type, and inserts the second check field into the termination position of the parsed data of the first protocol type, and uses the parsed data of the first protocol type with the synchronization header and the second check field inserted as the initial data of the second protocol type.

[0118] If the second check enable state is the disabled state and it is determined that there is no need to generate a second check field, the recombination module 3 directly uses the parsed data of the first protocol type with the synchronization header inserted as the initial data of the second protocol type.

[0119] According to the second resolution, the packet length of the initial data of the second protocol type is iteratively adjusted to obtain the data of the second protocol type.

[0120] Optionally, the recombination module dynamically adjusts the packet length of the initial data of the second protocol type based on the second resolution to adapt to the output requirements of different resolutions, and uses the initial data of the second protocol type when the adjustment of the packet length is completed as the data of the second protocol type.

[0121] In this embodiment, the recombination module is specifically configured to determine a second resolution, a target protocol type, and a second check enabling state based on a third configuration instruction issued by the configuration module, where the target protocol type is the second protocol type. The recombination module determines a preset synchronization header according to the second protocol type and inserts the synchronization header at the starting position of the parsed data of the first protocol type, so that the data receiving end can identify the data frame boundary based on the synchronization header. The recombination module determines whether to generate a second check field based on the second check enabling state. If so, the recombination module generates a second check field according to the parsed data of the first protocol type and inserts the second check field at the ending position of the parsed data of the first protocol type to obtain the initial data of the second protocol type. Otherwise, the recombination module directly uses the parsed data of the first protocol type with the synchronization header inserted as the initial data of the second protocol type. The recombination module dynamically adjusts the packet length of the initial data of the second protocol type based on the second resolution to adapt to the output requirements of different resolutions and obtains the data of the second protocol type. The recombination module flexibly implements data encapsulation and recombination based on the third configuration instruction.

[0122] As an alternative embodiment, the sending module 4 is specifically configured to determine sending parameters according to a fourth configuration instruction, where the sending parameters include the number of sending channels, the sending channel rate, the scrambling mode, and the electrical signal adjustment parameters.

[0123] Optionally, the fourth configuration instruction is used to indicate the sending parameters when the sending module 4 performs the always generation and sending operations. The sending module 4 determines the sending parameters according to the fourth configuration instruction issued by the configuration module 5, including the number of sending channels, the sending channel rate, the scrambling mode, and the electrical signal adjustment parameters.

[0124] Among them, the number of sending channels represents the number of channels through which the sending module 4 can simultaneously send data, and the sending channel rate represents the transmission rate of sending data through each channel. Exemplarily, the number of sending channels can be 1, 2, or 4. Scrambling is to randomize the data to avoid continuous identical bits in the data, improve the spectral characteristics of the signal, and reduce electromagnetic interference. Different scrambling modes have different randomization rules, and the scrambling mode represents the specific rules followed by the sending module 4 when randomizing the data. The electrical signal adjustment parameters represent the driving parameters for the sending module 4 to adjust the sending signal, such as the amplitude, pre-emphasis, and de-emphasis of the signal.

[0125] Generate a sending clock for the data of the second protocol type according to the number of sending channels and the sending channel rate, and perform cross-clock domain synchronization through the first-in-first-out buffer of the FPGA according to the sending clock and the target receiving clock.

[0126] Optionally, the PLL in the sending module 4 calculates the sending clock for the data of the second protocol type based on the number of sending channels and the sending channel rate in the sending parameters. The sending clock characterizes the time rhythm of the sending module 4 to send data, ensuring that the data is sent at a predetermined rate and timing.

[0127] Since the sending clock for the data of the second protocol type and the target receiving clock for the data of the first protocol type may be different, cross-clock domain issues will occur during data transmission. To avoid data loss or errors, the sending module 4 uses the First In First Out (FIFO) buffer of the FPGA to achieve cross-clock domain synchronization. The FIFO buffer can buffer data between different clock domains, ensuring that the data can be correctly transmitted under the control of different clock signals and achieving synchronization of the target receiving clock for the data of the first protocol type.

[0128] According to the sending clock, scrambling pattern, and electrical signal adjustment parameters, the data of the second protocol type is sent to the data receiving end through level driving.

[0129] Optionally, the sending module 4 also includes a SerDes. The SerDes in the sending module 4 serializes the parallel data of the second protocol sent by the recombination module 3 based on the sending clock, converting the parallel data of the second protocol into serial data of the second protocol type. And based on the scrambling pattern and electrical signal adjustment parameters, the serialized data of the second protocol type after randomization processing is converted into an appropriate differential electrical signal and sent to the data receiving end through level driving.

[0130] In this embodiment, the sending module is specifically configured to determine the sending parameters according to the fourth configuration instruction issued by the configuration module. Based on the number of sending channels and the sending channel rate in the sending parameters, generate the sending clock for the data of the second protocol type, and perform cross-clock domain synchronization through the FIFO buffer of the FPGA according to the sending clock and the target receiving clock. The sending module sends the data of the second protocol type to the data receiving end through level driving according to the sending clock, scrambling pattern, and electrical signal adjustment parameters in the sending parameters. The sending module flexibly realizes sending clock generation, cross-clock domain synchronization, data serialization, and level driving sending based on the fourth configuration instruction.

[0131] Based on the same inventive concept, the embodiments of the present application also provide a protocol conversion method corresponding to the protocol conversion system. Since the principle of solving problems in the method in the embodiments of the present application is similar to that of the above-mentioned protocol conversion system in the embodiments of the present application, the implementation of the method can refer to the implementation of the system, and the repeated parts will not be described again.

[0132] The protocol conversion method is applied to the protocol conversion system described in the above embodiment. The method includes:

[0133] The receiving module 1 receives the data of the first protocol type sent by the data sending end, extracts the target receiving clock of the data of the first protocol type, obtains the parallel data of the first protocol type and sends it to the parsing module. The parallel data of the first protocol type includes the target receiving clock.

[0134] The parsing module 2 parses the parallel data of the first protocol type, obtains the parsed data of the first protocol type and sends it to the recombination module 3.

[0135] The recombination module 3 encapsulates and recombines the parsed data of the first protocol type based on the second protocol type, obtains the data of the second protocol type and sends it to the sending module 4.

[0136] The sending module 4 generates the sending clock of the data of the second protocol type, and sends the data of the second protocol type to the data receiving end according to the sending clock.

[0137] As an optional implementation manner, the FPGA further includes: a configuration module 5.

[0138] The configuration module 5 is respectively connected to the receiving module 1, the parsing module 2, the recombination module 3 and the sending module 4, and is used to send a first configuration instruction, a second configuration instruction, a third configuration instruction and a fourth configuration instruction to the receiving module 1, the parsing module 2, the recombination module 3 and the sending module 4 respectively, so as to configure the corresponding functions.

[0139] As an optional implementation manner, the receiving module 1 determines the receiving parameters according to the first configuration instruction, where the receiving parameters include the number of receiving channels and the receiving channel rate. According to the receiving parameters, it receives the data of the first protocol type sent by the data sending end, extracts the target receiving clock of the data of the first protocol type, and performs serial-to-parallel conversion processing on the data of the first protocol type according to the target receiving clock. When the number of receiving channels is multiple, synchronously calibrates the multiple receiving channels according to the target receiving clock, obtains the parallel data after phase alignment, and uses the parallel data after phase alignment as the parallel data of the first protocol type.

[0140] As an optional implementation manner, the receiving module 1 adopts a dynamic phase difference algorithm to iteratively adjust the sampling phase during the serial-to-parallel conversion process, and compensates for the jitter of the receiving clock in real time to obtain the target receiving clock.

[0141] As an alternative implementation, the parsing module 2 determines a protocol parsing mode, a first resolution, and a first check enabling state according to the second configuration instruction. The header field in the parallel data of the first protocol type is parsed according to the protocol parsing mode, and the valid image data is extracted from the parallel data of the first protocol type according to the header field and the first resolution. According to the first check enabling state, it is determined whether to check the valid image data. If so, a first check field is generated according to the valid image data, and the valid image data is checked according to the first check field, and the successfully checked valid image data is used as the parsed data of the first protocol type; otherwise, the valid image data is used as the parsed data of the first protocol type.

[0142] As an alternative implementation, the FPGA further includes: a buffer module 6, and the buffer module 6 includes a first buffer 61 and a second buffer 62; the first buffer 61 is respectively connected to the parsing module 2 and the recombination module 3, and the second buffer 62 is respectively connected to the parsing module 2 and the recombination module 3.

[0143] The first buffer 61 receives the parsed data of the first protocol type sent by the parsing module 2 in the data reading state, and switches to the data writing state when a first preset condition is satisfied, and sends the received parsed data of the first protocol type to the recombination module 3 in the data writing state.

[0144] The second buffer 62 receives the parsed data of the first protocol type sent by the parsing module 2 in the data reading state, and switches to the data writing state when a second preset condition is satisfied, and sends the received parsed data of the first protocol type to the recombination module 3 in the data writing state; wherein, the data reading and writing states of the first buffer 61 and the second buffer 62 are opposite.

[0145] As an alternative implementation, the recombination module 3 determines a second resolution, a target protocol type, and a second check enabling state according to the third configuration instruction, where the target protocol type is the second protocol type. According to the second protocol type, a preset synchronization header is inserted into the starting position of the parsed data of the first protocol type, and according to the second check enabling state, it is determined whether to generate a second check field. If so, a second check field is generated according to the parsed data of the first protocol type, and the second check field is inserted into the ending position of the parsed data of the first protocol type to obtain the initial data of the second protocol type; otherwise, the parsed data of the first protocol type with the synchronization header inserted is used as the initial data of the second protocol type. According to the second resolution, the packet length of the initial data of the second protocol type is iteratively adjusted to obtain the data of the second protocol type.

[0146] As an alternative embodiment, the sending module 4 determines sending parameters according to a fourth configuration instruction, where the sending parameters include the number of sending channels, the sending channel rate, the scrambling mode, and the electrical signal adjustment parameter. According to the number of sending channels and the sending channel rate, a sending clock for data of a second protocol type is generated, and cross-clock domain synchronization is performed through the first-in first-out buffer of the FPGA according to the sending clock and the target receiving clock. According to the sending clock, the scrambling mode, and the electrical signal adjustment parameter, the data of the second protocol type is sent to the data receiving end through level driving.

[0147] The embodiment of the present application further provides a field programmable gate array (FPGA), where the FPGA includes: a parallel receiving module, parsing module, recombination module, and sending module; each module in the FPGA is used to execute the steps of the protocol conversion method described in the foregoing embodiment.

[0148] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described systems and devices can refer to the corresponding processes in the method embodiments, and will not be described in detail in this application. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation. For another example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some communication interfaces, and the indirect coupling or communication connection of the devices or modules can be in an electrical, mechanical, or other form.

[0149] In addition, each functional unit in various embodiments of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. If the function is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, may be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several configuration instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0150] The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application.

Claims

1. A protocol conversion system, characterized in that: include: A field programmable gate array FPGA and a data transmitting end and a data receiving end respectively connected to the FPGA, wherein the FPGA comprises: a parallel receiving module, a parsing module, a reassembly module, and a sending module; The receiving module is used to receive data of the first protocol type sent by the data sending end, and extract the target receiving clock of the data of the first protocol type, obtain parallel data of the first protocol type and send it to the parsing module, wherein the parallel data of the first protocol type includes the target receiving clock; The parsing module is used to parse the parallel data of the first protocol type, obtain the parsed data of the first protocol type and send it to the reassembly module; The reassembly module is used to encapsulate and reassemble the parsed data of the first protocol type based on the second protocol type, obtain the data of the second protocol type and send it to the sending module; The sending module is used to generate a sending clock for the data of the second protocol type, and send the data of the second protocol type to the data receiving end according to the sending clock.

2. The system according to claim 1, characterized in that The FPGA also includes: a configuration module; The configuration module is respectively connected to the receiving module, the parsing module, the reorganization module and the sending module, and is used to send a first configuration instruction, a second configuration instruction, a third configuration instruction and a fourth configuration instruction to the receiving module, the parsing module, the reorganization module and the sending module respectively to configure corresponding functions.

3. The system according to claim 2, characterized in that The receiving module is specifically configured to determine receiving parameters according to the first configuration instruction, wherein the receiving parameters include the number of receiving channels and the receiving channel rate; receiving, according to the receiving parameters, data of the first protocol type sent by the data transmitting end, extracting a target receiving clock of the data of the first protocol type, and performing serial-to-parallel conversion processing on the data of the first protocol type according to the target receiving clock; When there are multiple receiving channels, synchronization calibration is performed on the multiple receiving channels according to the target receiving clock to obtain phase-aligned parallel data, and the phase-aligned parallel data is used as the parallel data of the first protocol type.

4. The system according to claim 3, characterized in that The receiving module is specifically used to iteratively adjust the sampling phase during the serial-to-parallel conversion process by adopting a dynamic phase difference algorithm, and to compensate for the jitter of the receiving clock in real time to obtain the target receiving clock.

5. The system according to claim 2, characterized in that The parsing module is specifically used to determine the protocol parsing mode, the first resolution and the first verification enable state according to the second configuration instruction; Parsing the parallel data of the first protocol type to obtain a header field according to the protocol parsing mode, and extracting valid image data from the parallel data of the first protocol type according to the header field and the first resolution; Determine whether to verify the valid image data according to the first verification enable state, and if so, generate a first verification field according to the valid image data, verify the valid image data according to the first verification field, and use the verified valid image data as the parsed data of the first protocol type; Otherwise, the valid image data is used as parsed data of the first protocol type.

6. The system according to claim 1, characterized in that The FPGA further includes: a buffer module, the buffer module including a first buffer and a second buffer; the first buffer is connected to the analysis module and the reorganization module respectively, and the second buffer is connected to the analysis module and the reorganization module respectively; The first buffer is used to receive the parsed data of the first protocol type sent by the parsing module in a data reading state, and switch to a data writing state when a first preset condition is met, and send the received parsed data of the first protocol type to the reassembly module in the data writing state; The second buffer is used to receive the parsed data of the first protocol type sent by the parsing module in the data reading state, and switch to the data writing state when a second preset condition is met, and send the received parsed data of the first protocol type to the reorganization module in the data writing state; wherein the data reading and writing states of the first buffer and the second buffer are opposite.

7. The system according to claim 2, characterized in that The reorganization module is specifically used to determine a second resolution, a target protocol type, and a second verification enable state according to the third configuration instruction, wherein the target protocol type is a second protocol type; According to the second protocol type, inserting a preset synchronization header into the starting position of the parsed data of the first protocol type, and determining whether to generate a second check field according to the second check enable state; If yes, then generate the second check field according to the parsed data of the first protocol type, and insert the second check field into the end position of the parsed data of the first protocol type to obtain the initial data of the second protocol type; otherwise, use the parsed data of the first protocol type inserted into the synchronization header as the initial data of the second protocol type; According to the second resolution, the data packet length of the initial data of the second protocol type is iteratively adjusted to obtain data of the second protocol type.

8. The system according to claim 2, characterized in that The sending module is specifically configured to determine sending parameters according to the fourth configuration instruction, wherein the sending parameters include the number of sending channels, the sending channel rate, the scrambling mode, and the electrical signal adjustment parameter; Generate a transmission clock for the data of the second protocol type according to the number of transmission channels and the transmission channel rate, and perform cross-clock domain synchronization through a first-in first-out buffer of the FPGA according to the transmission clock and the target receiving clock; The data of the second protocol type is sent to the data receiving end through level driving according to the sending clock, the scrambling mode and the electrical signal adjustment parameter.

9. A protocol conversion method, characterized in that: The method is applied to the protocol conversion system according to any one of claims 1 to 8; the method comprises: The receiving module receives the data of the first protocol type sent by the data sending end, extracts the target receiving clock of the data of the first protocol type, obtains the parallel data of the first protocol type and sends it to the parsing module, wherein the parallel data of the first protocol type includes the target receiving clock; The parsing module parses the parallel data of the first protocol type to obtain the parsed data of the first protocol type and sends the parsed data to the reassembly module; The reassembly module encapsulates and reassembles the parsed data of the first protocol type based on the second protocol type, obtains the data of the second protocol type and sends it to the sending module; The sending module generates a sending clock for the data of the second protocol type, and sends the data of the second protocol type to the data receiving end according to the sending clock.

10. A field programmable gate array FPGA, characterized in that: The FPGA includes: a parallel receiving module, a parsing module, a reassembly module, and a sending module; The FPGA is used to execute the steps of the protocol conversion method described in claim 9.

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