Semiconductor device and method of manufacturing the same

Abstract

Provided are a semiconductor structure and a method for manufacturing the same. The method comprises providing a substrate; the substrate is formed with a stack structure, the stack structure comprising first stack layers and second stack layers alternately stacked on the substrate along a first direction, the first direction intersecting a plane in which the substrate is located; forming a first hole and a second hole extending along the first direction in the stack structure; forming an oxide active layer in the first hole; forming a gate structure in the first hole in which the oxide active layer is formed; and annealing the semiconductor structure in an oxygen environment, oxygen entering the first stack layers through the second hole, and oxygen in the first stack layers moving to the oxide active layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular to a semiconductor device, a dynamic random access memory and a manufacturing method thereof. BACKGROUND

[0002] Development of dynamic random access memory (DRAM) pursues performance indexes such as high speed, high integration density and low power consumption. With the miniaturization of semiconductor device structure, technical barriers encountered by existing structures are becoming more and more obvious. Therefore, developing more novel structures on the basis of existing structures is a favorable means to break through the existing technical barriers.

[0003] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM including multilayer horizontal cells (MHC), generally includes multiple transistors stacked on a substrate, which meets the above-mentioned requirements.

[0004] In the current 3D DRAM structure, a new technical route is developed, and an oxide semiconductor material is applied as an active layer in the transistor to prepare a 3D DRAM structure. SUMMARY

[0005] According to a first aspect of embodiments of the present disclosure, a preparation method of a semiconductor structure is provided, comprising:

[0006] providing a substrate; the substrate is formed with a stack structure, the stack structure includes first stack layers and second stack layers alternately stacked on the substrate along a first direction, the first direction intersects with a plane where the substrate is located;

[0007] forming a first hole and a second hole extending along the first direction in the stack structure;

[0008] forming an oxide active layer in the first hole;

[0009] forming a gate structure in the first hole with the oxide active layer;

[0010] annealing the semiconductor structure in an oxygen environment, the oxygen enters the first stack layer through the second hole, and oxygen in the first stack layer moves to the oxide active layer.

[0011] In some embodiments, further comprising: filling a thermally conductive polymer in the second hole.

[0012] In some embodiments, a bit line structure is formed in the second stack layer, and the bit line structure is electrically connected with the oxide active layer.

[0013] In some embodiments, a storage node is formed in the second stack layer, and the storage node is electrically connected with the oxide active layer.

[0014] In some embodiments, at least part of the oxide active layer corresponding to the first stack layer is removed.

[0015] In some embodiments, titanium nitride is contained in the gate structure and / or the bit line structure.

[0016] In some embodiments, the first stack layer comprises an oxide insulating material.

[0017] In some embodiments, the oxide active layer comprises one or more of indium gallium zinc oxide, indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, gallium oxide or tin oxide.

[0018] In some embodiments, the annealing step is performed at a temperature of 350-450 degrees Celsius for 1.5-2.5 hours.

[0019] According to a second aspect of the embodiments of the present disclosure, a semiconductor structure is provided, which is prepared according to the aforementioned preparation method.

[0020] The embodiments provided by the present disclosure can improve the electrical performance of the device by repairing the oxide active layer through annealing in an oxygen environment; and the embodiments provided by the present disclosure can improve the heat dissipation performance of the device and improve the stability of the device by filling the second hole slot with a heat-conducting polymer. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a schematic diagram of a semiconductor device according to an exemplary embodiment;

[0022] Figure 2a is a schematic diagram of a semiconductor device according to an exemplary embodiment, along the D1-D2 plane through the gate structure;

[0023] Figure 2b is a schematic diagram of a semiconductor device according to an exemplary embodiment, along the D1-D3 plane through the gate structure and the heat-conducting structure;

[0024] Figures 3-9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 22 is a schematic diagram of a semiconductor device according to an exemplary embodiment, along the D1-D2 plane through the gate structure position in a step of a preparation method of the semiconductor device;

[0025] Figure 10 ,Figure 12 , Figure 14 , Figure 16 , Figures 18-21 , Figures 23-24 This is a schematic diagram illustrating a step in a method for fabricating a semiconductor device according to an exemplary embodiment, showing the position of the gate structure and the heat-conducting structure along the plane containing D1-D3. Detailed Implementation

[0026] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0027] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0028] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0029] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0030] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0031] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0032] According to a first aspect of the embodiments of this disclosure, such as Figure 1 , Figure 2aand Figure 2b As shown, a semiconductor structure 10 is disclosed, comprising a substrate 100, a memory array structure stacked on the substrate along a first direction (D1) and arranged along a second direction (D2). The first direction (D1) intersects the plane of the substrate, the second direction (D2) is parallel to the plane of the substrate, and the third direction (D3) intersects the second direction and is parallel to the plane of the substrate.

[0033] In some embodiments, the substrate is selected from a semiconductor material such as single crystal silicon, silicon germanium, silicon carbide, or silicon on insulator.

[0034] In some embodiments, the substrate can contain structures formed therein in advance, such as select transistors or connection structures disposed in through holes of the substrate.

[0035] In some embodiments, the memory array structure is a plurality of memory array structures arranged on the substrate opposite to each other along the second direction (D2), and the memory array structures are filled with a protection layer P1.

[0036] In some embodiments, the protection layer contains silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof.

[0037] The memory array structure includes a plurality of memory cells, each memory cell having a transistor 800 and a memory node 600, the transistor including an oxide active layer 200 and a gate structure 400, and the memory node being electrically connected to the oxide active layer. The layers of the memory array structure are separated by an interlayer insulating layer S1. The gate structures of the memory cells corresponding to different layers in the D1 direction are connected, and the memory cells arranged in the same layer are electrically connected to the same bit line structure 500 extending along the D3 direction. The memory array structure further includes a heat conduction structure 300 extending along the D1 direction, the heat conduction structure containing a material with high thermal conductivity.

[0038] In some embodiments, the heat conduction structure contains a heat conductive polymer.

[0039] In some embodiments, the heat conduction structure is directly in contact with the bit line structure.

[0040] In some embodiments, a pseudo-oxide active layer is disposed between the heat conduction structure and the bit line structure.

[0041] In some embodiments, the memory node is selected from one or more of a memory capacitor, a phase change memory, a magnetoresistive memory, or a ferroelectric memory. Here, the memory node is taken as an example of a memory capacitor, the memory capacitor including a lower electrode, a capacitor dielectric layer, and an upper electrode. The lower electrode of the memory capacitor is electrically connected to the oxide active layer of the transistor, the capacitor dielectric layer covers the lower electrode, the upper electrode covers the capacitor dielectric layer, and a plurality of memory capacitors share the upper electrode.

[0042] In some embodiments, the capacitive dielectric layer of the storage capacitor is formed of or includes at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0043] In some embodiments, the lower electrode of the storage capacitor comprises a metal, a metal nitride, a metal oxide, a metal silicide, a conductive carbon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof, or a polysilicon, a gallium indium tin oxide, an indium tin oxide, or other non-metallic material or combinations thereof.

[0044] In some embodiments, the lower electrode of the storage capacitor is titanium nitride.

[0045] In some embodiments, the upper electrode of the storage capacitor comprises a metal, a metal nitride, a metal oxide, a metal silicide, a conductive carbon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof, or a polysilicon, a gallium indium tin oxide, an indium tin oxide, or other non-metallic material or combinations thereof.

[0046] In some embodiments, the upper electrode of the storage capacitor is a multi-layer structure of titanium nitride and polysilicon.

[0047] In some embodiments, the oxide active layer comprises one or more of indium gallium zinc oxide, indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, gallium oxide, or tin oxide.

[0048] In some embodiments, the interlayer insulating layer comprises an oxide insulating material.

[0049] In some embodiments, the interlayer insulating layer comprises silicon oxide, silicon oxynitride, and combinations thereof or a metal oxide such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof, or the like.

[0050] In some embodiments, the material of the interlayer insulating layer is silicon oxide.

[0051] In some embodiments, the gate structure comprises a metal, a metal nitride, a metal oxide, a metal silicide, a conductive carbon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof, or a polysilicon, a gallium indium tin oxide, a tin indium oxide, or other non-metallic materials or combinations thereof.

[0052] In some embodiments, the gate structure comprises a gate electrode and a gate insulating layer.

[0053] In some embodiments, the gate electrode is titanium nitride.

[0054] In some embodiments, the gate electrode is a stack structure of titanium nitride and tungsten, the titanium nitride is disposed as a barrier layer between the tungsten and the gate insulating layer.

[0055] In some embodiments, the gate insulating layer is made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a metal oxide such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof, or other non-metallic materials or combinations thereof.

[0056] In some embodiments, the bit line structure comprises a metal, a metal nitride, a metal oxide, a metal silicide, a conductive carbon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof, or a polysilicon, a gallium indium tin oxide, a tin indium oxide, or other non-metallic materials or combinations thereof.

[0057] In some embodiments, the bit line structure comprises a bit line electrode and a pull-out pad electrically connected thereto.

[0058] In some embodiments, the bit line electrode is titanium nitride.

[0059] In some embodiments, the semiconductor structure is a component of a three-dimensional dynamic random access memory, the three-dimensional dynamic random access memory further comprising a sense amplifier (SA) and a word line driver (WD), the gate structure is electrically connected to the word line driver, and the bit line structure is electrically connected to the sense amplifier.

[0060] According to a second aspect of the embodiments of the present disclosure, as shown in Figures 3-24 , a method for manufacturing a semiconductor structure is disclosed, which combines Figure 1 , Figure 2a and Figure 2bA substrate 100 is provided. The substrate is formed with a stack structure 700, which includes first stack layers M1 and second stack layers M2 alternately stacked on the substrate along a first direction. First and second via trenches V1 and V2 extending along the first direction are formed in the stack structure. An oxide active layer 200 is formed in the first via trench. A gate structure 400 is formed in the first via trench with the oxide active layer. The semiconductor structure is annealed T in an oxygen environment. Oxygen enters the first stack layer through the second via trench. Oxygen in the first stack layer moves to the oxide active layer.

[0061] In some embodiments, as shown in FIG. 1, first stack layers M1 and second stack layers M2 are alternately formed on a substrate (not shown). The first stack layers M1 and the second stack layers M2 represent two different materials selected. Figure 3

[0062] In some embodiments, after the two initial material layers are alternately formed on the substrate, the two initial material layers are replaced by an etching process and a deposition process to form the stack structure composed of the first stack layers M1 and the second stack layers M2. The two initial material layers are selected from silicon nitride and silicon oxide deposited alternately, or monocrystalline silicon and monocrystalline silicon germanium made by epitaxial growth, or two different thin film materials with high etching selectivity alternately prepared.

[0063] In some embodiments, the first stack layers M1 are oxide insulating materials.

[0064] In some embodiments, the material of the first stack layers is selected from silicon oxide, silicon oxynitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof.

[0065] In some embodiments, the etching process for making the stack structure includes anisotropic etching or isotropic etching, such as dry etching or wet etching.

[0066] In some embodiments, the deposition process for making the stack structure includes physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, epitaxial growth (EPI), etc.

[0067] In some embodiments, as shown in FIG. 2, first trenches T1 are formed in the stack structure. Figure 4

[0068] ​​In some embodiments, the method of forming the first trench can be prepared by a patterning process, specifically, the patterning process includes forming a photoresist on the substrate, exposing and developing the photoresist to form a photoresist with a preset pattern, etching the stack structure through the patterned photoresist to form the first trench. Optionally, the etching process includes anisotropic etching or isotropic etching, such as dry etching or wet etching.

[0069] In some embodiments, the patterning process further includes forming a hard mask on the substrate, forming a photoresist on the hard mask, exposing and developing the photoresist to form a photoresist with a preset pattern, etching the hard mask through the patterned photoresist to transfer the preset pattern to the hard mask, stripping the photoresist, and etching the stack structure through the patterned hard mask to form the first trench.

[0070] In some embodiments, as the semiconductor manufacturing process develops, the integration level improves, and the size shrinks. A single patterning process cannot form the preset width of the active region and the isolation trench, and multiple patterning processes are needed. For example, twice exposure and etching (LELE), or self-aligned double patterning (SADP), or self-aligned quadruple patterning (SAQP), etc.

[0071] In some embodiments, as shown in FIG. 1C, a second trench T2 is formed in the second stack layer through the first trench in the stack structure with the first trench. Figure 5

[0072] In some embodiments, the second stack layer is removed by lateral etching to form the second trench.

[0073] In some embodiments, the method of etching the second stack layer laterally can be a liquid etching process. It can be understood that the etching rate of the etching liquid of the liquid etching process on the second stack layer is greater than the etching rate of the etching liquid on the first stack layer.

[0074] In some embodiments, as shown in FIG. 1D, a bit line structure 500 is formed in the second trench of the stack structure. Figures 6-7

[0075] In some embodiments, a third material layer M3 is deposited in the first trench and the second trench of the stack structure, the third material layer on the sidewall of the first trench is removed, and the remaining third material layer in the second trench forms the bit line structure 500.

[0076] ​​In some embodiments, the third material layer is selected from a group consisting of metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polysilicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. The third material layer is formed by a method selected from a group consisting of physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, tube furnace deposition, and the like. Preferably, the third material layer is formed by an atomic layer deposition (ALD) method.

[0077] In some embodiments, the method of removing the third material layer from the first trench sidewall is an anisotropic etching process including dry etching process, plasma etching process, and the like.

[0078] In some embodiments, as shown in FIG. 6B, after the formation of the bit line structure, a protection layer P1 is formed in the first trench. Figure 8

[0079] In some embodiments, the method of forming the protection layer P1 is selected from a group consisting of physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, tube furnace deposition, and the like.

[0080] In some embodiments, the method of forming the protection layer P1 further comprises a chemical mechanical polishing (CMP) planarization process on the substrate with the deposited protection layer.

[0081] In some embodiments, a method similar to the formation of the bit line structure is used to form a trench in the stack structure, then a portion of the second stack layer is laterally etched away, then a lower electrode 601 of a storage capacitor is formed, then a capacitor dielectric layer and an upper electrode are formed on the lower electrode.

[0082] In some embodiments, the method of forming the lower electrode of the storage capacitor is selected from a group consisting of physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, tube furnace deposition, and the like. Preferably, the method of forming the lower electrode is an atomic layer deposition (ALD) method.

[0083] In some embodiments, the method of forming the capacitor dielectric layer of the storage capacitor is selected from a group consisting of physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, tube furnace deposition, and the like. ​

[0084] In some embodiments, the method for forming the upper electrode of the storage capacitor is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0085] In some embodiments, the upper electrode of the storage capacitor is a multilayer structure of titanium nitride and polycrystalline silicon, wherein the titanium nitride is formed by atomic layer deposition (ALD) and the polycrystalline silicon is formed by furnace tube deposition.

[0086] In some embodiments, a protective layer is formed in the trench after the storage node is fabricated, similar to forming a protective layer P1 in the first trench.

[0087] In some embodiments, the method for forming the protective layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0088] In some embodiments, the method of forming a protective layer further includes planarizing the substrate on which the protective layer is deposited by chemical mechanical polishing (CMP).

[0089] In some embodiments, such as Figures 9-10 As shown, in the stacked structure with bit line structure and memory node, a first slot V1 and a second slot V2 are formed.

[0090] In some embodiments, the method of forming the first and second slots includes forming them by a patterning process, which is similar to that described above and will not be repeated here.

[0091] In some embodiments, the first and second slots have the same critical dimensions and are formed in the same process steps.

[0092] In some embodiments, the critical dimensions of the first and second vias are smaller than the distance between the bitline structure and the memory node. The sidewalls of the first and second vias include a first stacked layer and a second stacked layer.

[0093] In some embodiments, such as Figures 11-12 As shown, a third trench T3 is formed by lateral etching of the second stacked layer through the first and second vias, exposing the bit line structure 500 and the memory node. Taking the memory capacitor as an example, the lower electrode 601 is exposed.

[0094] In some embodiments, such as Figures 13-14As shown, a fourth material layer M4 is deposited in the first and second hole sidewalls and the third trench, the fourth material layer is connected with the bit line structure and the storage capacitor lower electrode. The material of the fourth material layer is selected from one or more of indium gallium zinc oxide, indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, gallium oxide or tin oxide. The forming method of the fourth material layer is selected from physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0095] In some embodiments, the fourth material layer is a multi-layer structure formed by multiple depositions, and the material of each layer is selected from one or more of indium gallium zinc oxide, indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, gallium oxide or tin oxide.

[0096] In some embodiments, as shown, the fourth material layer of the first and second hole sidewalls is removed, and the fourth material layer in the remaining third trench forms an active layer. The active layer in the third trench in the first hole forms an oxide active layer 200, and the active layer in the third trench in the second hole forms a pseudo-oxide active layer 200'. Figures 15-16

[0097] In some embodiments, the method of removing the fourth material layer is an anisotropic etching process including dry etching process, plasma etching process, etc.

[0098] In some embodiments, as shown, a gate structure 400 is formed in the first hole, and a pseudo-gate structure 400' is formed in the second hole. The gate structure and the pseudo-gate structure are formed in the same process step. Figures 17-18

[0099] In some embodiments, the gate structure and the pseudo-gate structure both include a gate insulating layer and a gate electrode.

[0100] In some embodiments, the forming method of the gate insulating layer includes physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0101] In some embodiments, the forming method of the gate electrode includes physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0102] In some embodiments, as shown, the pseudo-gate structure is removed to expose the second hole V2 again. Figure 19

[0103] ​​​In some embodiments, removing the dummy gate structure includes etching the dummy gate structure by a patterning process to form the second via.

[0104] In some embodiments, as shown in FIG. 3, after the first via and the second via are formed in the stack structure, an annealing process is performed on the semiconductor structure to repair the oxygen vacancies in the oxide active layer. Figure 24 In some embodiments, as shown in FIG. 3, after the first via and the second via are formed in the stack structure, an annealing process is performed on the semiconductor structure to repair the oxygen vacancies in the oxide active layer.

[0105] In some embodiments, the annealing process performed on the semiconductor structure is at a temperature of 350-450 degrees Celsius for a duration of 1.5-2.5 hours.

[0106] In some embodiments, as shown in FIG. 3, after the first via and the second via are formed in the stack structure, an annealing process is performed on the semiconductor structure to repair the oxygen vacancies in the oxide active layer. Figure 20 In some embodiments, as shown in FIG. 3, after the first via and the second via are formed in the stack structure, an annealing process is performed on the semiconductor structure to repair the oxygen vacancies in the oxide active layer.

[0107] In some embodiments, as shown in FIG. 3, after the first via and the second via are formed in the stack structure, an annealing process is performed on the semiconductor structure to repair the oxygen vacancies in the oxide active layer. Figure 21 In some embodiments, as shown in FIG. 3, after the first via and the second via are formed in the stack structure, an annealing process is performed on the semiconductor structure to repair the oxygen vacancies in the oxide active layer. The second protective layer P2 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, polysilicon, or metal oxide such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof. The second protective layer P2 can be formed by physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, and the like.

[0108] In some embodiments, as shown in FIG. 3, after the first via and the second via are formed in the stack structure, an annealing process is performed on the semiconductor structure to repair the oxygen vacancies in the oxide active layer. Figures 22-23As shown, in the stack structure with the bit line structure and the storage node, the first hole and the second hole are formed. The critical dimension of the first hole and the second hole is equal to or slightly greater than the distance between the bit line structure and the storage node. The sidewall of the first hole and the second hole exposes the bit line structure and the lower electrode of the storage capacitor. Then, the fourth material layer M4 and the gate structure 400 are sequentially formed in the first hole by the same process step, and the fourth material layer M4 and the dummy gate structure 400' are sequentially formed in the second hole. Optionally, the second protective layer is filled in the second hole first, and then the fourth material layer and the gate structure are sequentially formed in the first hole. Then, the second stack layer is removed to expose the fourth material layer corresponding to the first stack layer, and the fourth material layer corresponding to the first stack layer is removed by an etching process. The remaining fourth material layer in the first hole forms an oxide active layer. The third protective layer is deposited again on the stack structure with the oxide active layer to fill the space left by the first stack layer. The material of the third protective layer is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, or metal oxide such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof. The formation method of the third protective layer includes physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0109] In some embodiments, the material of the third protective layer is the same as the material of the first stack layer.

[0110] In some embodiments, the step of performing the annealing process in the oxygen environment is performed after the third protective layer is made.

[0111] In some embodiments, the step of performing the annealing process in the oxygen environment is completed before the first stack layer is removed.

[0112] In some embodiments, the method of removing the second stack layer includes wet etching.

[0113] In some embodiments, the etching process of removing the fourth material layer corresponding to the first stack layer includes wet etching.

[0114] According to a third aspect of the embodiments of the present disclosure, a semiconductor structure is made according to the semiconductor structure manufacturing method of the foregoing embodiments of the present disclosure.

[0115] In the process of manufacturing semiconductor structures, it is inevitable to involve hydrogen-rich processes, such as the preparation of titanium nitride. After the formation of the oxide active layer, such hydrogen-rich processes can cause hydrogen to diffuse in the semiconductor structure and into the oxide active layer to combine with the oxygen contained therein. This results in an increase in oxygen vacancies in the oxide active layer, and it is known that an increase in oxygen vacancies in the oxide semiconductor material increases the conductivity of the oxide semiconductor material, thus changing the threshold voltage of the oxide active layer and thereby affecting the performance of the transistor. Annealing the oxide active layer in an oxygen environment can repair the oxygen vacancies in the oxide active layer and thereby improve the performance of the transistor. However, the oxide active layer is surrounded by an electrode structure, and in particular, the titanium nitride structure is dense and oxygen is difficult to penetrate, so how to anneal the oxide active layer is a problem to be solved.

[0116] The present disclosure enables oxygen to diffuse into the oxide active layer through the design of the second via and the first stack layer, thereby repairing the oxygen vacancies in the oxide active layer and improving the performance of the semiconductor structure.

[0117] The accumulation of thermal effects in a multilayer stacked semiconductor structure is also a problem to be solved. The formation of a heat conduction structure in the second via not only enables a semiconductor structure with better electrical performance to be obtained, but also solves the thermal effects of the device and improves the stability of the product.

[0118] The various semiconductor devices shown in the specific embodiments can be used in electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be realized by a memory such as a dynamic random access memory (DRAM), a ferroelectric random access memory (FRAM), a phase change memory (PCM), a magnetic random access memory (MRAM), or a resistive random access memory (RRAM).

[0119] The above merely describes specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, comprising: providing a substrate, wherein the substrate is formed with a stack structure, and the stack structure comprises first stack layers and second stack layers which are alternately stacked on the substrate along a first direction intersecting a plane in which the substrate is located; forming a first via and a second via in the stack structure along the first direction; forming an oxide active layer in the stack structure through the first via; forming a gate structure in the first via; annealing the semiconductor structure in an oxygen environment, wherein the oxygen enters the first stack layers through the second via, and oxygen in the first stack layers moves to the oxide active layer; and further comprising: filling a thermally conductive polymer in the second via. 3.The method of claim 1, wherein: a bit line structure is formed in the second stack layers, and the bit line structure is electrically connected to the oxide active layer. 4.The method of claim 1, wherein: a storage node is formed in the second stack layers, and the storage node is electrically connected to the oxide active layer. 5.The method of claim 3, wherein: the gate structure and / or the bit line structure comprises titanium nitride. 6.The method of claim 1, wherein: the first stack layers comprise oxide insulating material. 7.The method of claim 1, wherein: the oxide active layer comprises one or more of indium gallium zinc oxide, indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, gallium oxide, or tin oxide.

2. The method of claim 1, wherein, 8.The method of claim 1, wherein: the annealing step is performed at a temperature of 350-450 degrees Celsius for 1.5-2.5 hours. The semiconductor structure is manufactured according to any one of claims 1-8. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 9. A semiconductor structure, characterized by ​

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