Memory device and manufacturing method of memory device

Abstract

The invention relates to a memory device and a manufacturing method of the memory device. A method of manufacturing a memory device includes forming a stack structure including first material layers and second material layers alternately stacked; forming a channel layer comprising amorphous silicon in an opening extending through the stack structure; converting the first part of the channel layer into monocrystalline silicon; doping a first portion of the channel layer with a conductive material; doping a second portion of the channel layer different from the first portion with a conductive material; and converting the second portion of the channel layer into polysilicon using a conductive material.

Description

Technical Field

[0001] Various embodiments of the present disclosure generally relate to a memory device and a method of manufacturing the memory device, and more particularly, to a memory device including a three-dimensional memory block and a method of manufacturing the memory device. Background Art

[0002] A memory device may include a non-volatile memory device that retains stored data even when power supply is interrupted. According to the arrangement structure of memory cells, the non-volatile memory device may be classified into a two-dimensional structure or a three-dimensional structure. Memory cells of a non-volatile memory device having a two-dimensional structure may be arranged in a single layer on a substrate, while memory cells of a non-volatile memory device having a three-dimensional structure may be stacked in a vertical direction on the substrate. Because the integration degree of a non-volatile memory device having a three-dimensional structure is higher than that of a non-volatile memory device having a two-dimensional structure, electronic devices using a non-volatile memory device having a three-dimensional structure have recently become more and more popular. Summary of the Invention

[0003] According to an embodiment, a method of manufacturing a memory device may include: forming a stacked structure including alternately stacked first and second material layers; forming a channel layer including amorphous silicon in an opening extending through the stacked structure; converting a first portion of the channel layer into single-crystalline silicon; doping the first portion of the channel layer with a conductive material; doping a second portion of the channel layer different from the first portion of the channel layer with a conductive material; and converting the second portion of the channel layer into polycrystalline silicon using the conductive material.

[0004] According to an embodiment, a memory device may include: a stacked structure; and a channel layer formed in an opening extending through the stacked structure, wherein the channel layer includes a first portion including single-crystalline silicon and a second portion including polycrystalline silicon, and wherein the first portion and the second portion are adjacent to each other.

[0005] According to one embodiment, a method may include: forming an opening extending through a stacked structure; forming a channel layer including amorphous silicon in the opening; converting a first portion of the channel layer into single-crystalline silicon; doping the first portion of the channel layer and a second portion of the channel layer adjacent to the first portion with a conductive material; and converting the second portion of the channel layer into polycrystalline silicon using the conductive material. Brief Description of the Drawings

[0006] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure;

[0007] Figure 2 is a diagram illustrating a memory block of a memory device according to an embodiment of the present disclosure;

[0008] Figure 3 is a plan view illustrating a layout of a memory device according to an embodiment of the present disclosure;

[0009] Figure 4 is a cross-sectional view of a memory device according to an embodiment of the present disclosure;

[0010] Figures 5A to 5I is a view illustrating a cross-sectional view of a memory device formed by a method of manufacturing a memory device according to an embodiment of the present disclosure;

[0011] Figure 6 is a view illustrating an embodiment of a memory card system including a memory device according to an embodiment of the present disclosure; and

[0012] Figure 7 is a view illustrating an embodiment of a solid state drive (SSD) system including a plurality of memory devices according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0013] The specific structural or functional descriptions described in the present disclosure are examples of describing embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure may be implemented in various forms and should not be construed as limited to the specific embodiments set forth in the present disclosure.

[0014] Embodiments of the present disclosure are described in detail with reference to the accompanying drawings to describe details sufficient to enable those skilled in the art to easily implement the technical aspects of the present disclosure. The cross-hatching throughout the drawings illustrates corresponding or similar regions between the drawings, rather than indicating the materials of these regions.

[0015] Terms such as "under", "above", "over", "below", "left", "right", "lower", "downward" and other terms implying spatial relationships are provided only for the purpose of facilitating description or reference to the accompanying drawings and are not otherwise limiting.

[0016] Various embodiments relate to a memory device capable of increasing the current flowing in a memory cell and a method of manufacturing the memory device.

[0017] Figure 1 is a view illustrating a memory device 100 according to an embodiment of the present disclosure.

[0018] Referring to Figure 1 , the memory device 100 includes a memory cell array 110, a peripheral circuit 170, and a control circuit 180.

[0019] The memory cell array 110 includes memory blocks BLK1 to BLKi, where i is a positive integer. Each of the first memory block BLK1 to the i-th memory block BLKi includes memory cells capable of storing data. Drain selection lines DSL, word lines WL, source selection lines SSL, and source lines SL are coupled to each of the memory blocks BLK1 to BLKi, and bit lines BL are commonly coupled to the memory blocks BLK1 to BLKi.

[0020] The memory blocks BLK1 to BLKi have a three-dimensional structure. The memory blocks having a three-dimensional structure may include, for example, memory cells stacked on a substrate in a vertical direction.

[0021] According to the programming method, a single memory cell can store one-bit data, two-bit data, three-bit data, four-bit data, five-bit data, etc. For example, the method of storing one-bit data in one memory cell is called the single-level cell (SLC) method, and the method of storing two-bit data in one memory cell is called the multi-level cell (MLC) method. The method of storing three-bit data in one memory cell is called the triple-level cell (TLC) method, and the method of storing four-bit data in one memory cell is called the quad-level cell (QLC) method.

[0022] The peripheral circuit 170 is configured to perform a programming operation of storing data in the memory cell array 110, a read operation of outputting the data stored in the memory cell array 110, and an erase operation of erasing the data stored in the memory cell array 110. For example, the peripheral circuit 170 includes a voltage generator 120, a row decoder 130, a page buffer bank 140, a column decoder 150, and an input / output circuit 160.

[0023] The voltage generator 120 generates various operation voltages Vop used during the programming operation, read operation, or erase operation in response to an operation code OPCD. For example, the voltage generator 120 may be configured to generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verify voltage, a read voltage, a pass voltage, or an erase voltage in response to the operation code OPCD. The operation voltages Vop generated by the voltage generator 120 are applied by the row decoder 130 to the drain selection line DSL, word line WL, source selection line SSL, and source line SL of the selected memory block.

[0024] The programming voltage is applied to the selected word line among word lines WL during a programming operation and is used to increase the threshold voltage of the memory cells connected to the selected word line. The conduction voltage is applied to the drain select line DSL and the source select line SSL and is used to turn on the drain select transistor and the source select transistor. The cut-off voltage is applied to the drain select line DSL and the source select line SSL and is used to turn off the drain select transistor and the source select transistor. For example, the cut-off voltage can be set to 0V. The pre-charge voltage can be higher than 0V and can be applied to the bit line BL during a read operation. The verification voltage is used to determine whether the threshold voltage of the selected memory cell has increased to a target level during a verification operation. The verification voltage can be set to various levels according to the target level and can be applied to the selected word line.

[0025] During a read operation of the selected memory cell, the read voltage is applied to the selected word line. For example, the read voltage can be set to various levels according to the programming method of the selected memory cell. During a programming operation or a read operation, the pass voltage is applied to the unselected word lines among the word lines WL and is used to turn on the memory cells connected to the unselected word lines. The erase voltage is used to erase the memory cells included in the selected memory block during an erase operation and is applied to the source line SL.

[0026] The row decoder 130 is configured to transmit the operation voltage Vop to the drain select line DSL, the word line WL, the source select line SSL, and the source line SL connected to the selected memory block according to the row address RADD. For example, the row decoder 130 is connected to the voltage generator 120 through a global line and is connected to the memory blocks BLK1 to BLKi through the drain select line DSL, the word line WL, the source select line SSL, and the source line SL.

[0027] The page buffer group 140 includes a plurality (i) of page buffers (not shown) respectively connected to the memory blocks BLK1 to BLKi. The page buffers (not shown) are connected to the memory blocks BLK1 to BLKi through the bit line BL. During a read operation, the page buffers (not shown) sense the current or voltage that varies according to the threshold voltage of the selected memory cell on the bit line BL in response to the page buffer control signal PBSIG and temporarily store the sensed data.

[0028] The column decoder 150 is configured to facilitate data transfer between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 is connected to the page buffer group 140 through the column line CL and transmits an enable signal through the column line CL. The page buffers (not shown) included in the page buffer group 140 receive data or output data to the input / output circuit 160 through the data line DL in response to the enable signal.

[0029] The input / output circuit 160 is configured to receive or output a command CMD, an address ADD, and data via input / output lines I / O. For example, the input / output circuit 160 transfers the command CMD and the address ADD received from an external controller via the input / output lines I / O to the control circuit 180, and transfers the data DATA received from the external controller via the input / output lines I / O to the page buffer group 140. In addition, the input / output circuit 160 outputs the data DATA transferred from the page buffer group 140 to the external controller via the input / output lines I / O.

[0030] The control circuit 180 outputs at least one of an opcode OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to the command CMD and the address ADD. For example, when the command CMD input to the control circuit 180 corresponds to a programming operation, the control circuit 180 controls the peripheral circuit 170 to perform a programming operation on the memory block selected according to the address ADD. When the command CMD input to the control circuit 180 corresponds to a read operation, the control circuit 180 controls the peripheral circuit 170 to perform a read operation on the memory block selected according to the address ADD and output read data. When the command CMD input to the control circuit 180 corresponds to an erase operation, the control circuit 180 controls the peripheral circuit 170 to perform an erase operation on the selected memory block.

[0031] Figure 2 is a diagram illustrating a memory block of the memory device 100 according to an embodiment of the present disclosure.

[0032] Referring to Figure 2 , the memory device 100 includes memory blocks BLK1 to BLKi provided on a peripheral circuit structure PC, and the peripheral circuit structure PC is provided on a substrate SUB. The memory blocks BLK1 to BLKi at least partially overlap with the peripheral circuit structure PC.

[0033] The substrate SUB may be a single crystal semiconductor layer. For example, the substrate SUB may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed by a selective epitaxial growth method.

[0034] The peripheral circuit structure PC includes, for example, a peripheral circuit 170, and the peripheral circuit 170 includes a row decoder 130, a column decoder 150, a page buffer group 140, and a control circuit 180 that controls the operations of the memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC may include NMOS transistors, PMOS transistors, resistors, and capacitors electrically connected to the memory blocks BLK1 to BLKi. In Figure 2 the example of, the peripheral circuit structure PC is provided between the substrate SUB and the memory blocks BLK1 to BLKi.

[0035] Each of the memory blocks BLK1 to BLKi includes a source structure, a bit line, a cell string electrically connected to the source structure and the bit line, a word line electrically connected to the cell string, and a select line electrically connected to the cell string. Each cell string includes a select transistor and a memory cell connected in series through a cell plug. Each select line serves as a gate electrode of a corresponding select transistor, and each word line serves as a gate electrode of a corresponding memory cell.

[0036] In another embodiment, the substrate SUB, the peripheral circuit structure PC, and the memory blocks BLK1 to BLKi may be stacked in an order opposite to the Figure 2 order shown. For example, the peripheral circuit structure PC may be disposed above the memory blocks BLK1 to BLKi.

[0037] In another embodiment, Figure 2 in contrast, the peripheral circuit structure PC may be disposed above some regions of the substrate SUB that do not overlap with the memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC and the memory blocks BLK1 to BLKi may be disposed in non-overlapping regions of the substrate SUB.

[0038] Figure 3 is a plan view illustrating a layout of a memory device according to an embodiment of the present disclosure.

[0039] Referring to Figure 3 , the j-th memory block BLKj and the nearest memory blocks (the memory blocks BLKj-1 and BLKj+1, partially shown in Figure 3 ) are separated by a slit SI, where j is a positive integer less than i. For example, the slit SI is disposed or extends along the X direction of the j-th memory block BLKj and is adjacent to two different memory blocks disposed along the Y direction (e.g., the memory blocks BLKj and BLKj-1, or the memory blocks BLKj and BLKj+1). The slit SI is interposed between consecutive memory blocks.

[0040] Each of the memory blocks BLK1 to BLKi including the j-th memory block BLKj includes a plurality of cell plugs CPL. The cell plugs CPL extend in the Z direction with respect to a substrate such as Figure 2 the substrate SUB in Figure 3 . As shown in the example of Figure 3 , each row of the plurality of rows includes cell plugs CPL spaced apart from each other in the X direction. The plurality of rows are spaced apart from each other in the Y direction. The centers of each of the cell plugs CPL included in odd rows and the centers of each of the cell plugs CPL included in even rows may be offset from each other. In other words, the centers of the cell plugs CPL in consecutive rows are offset from each other.

[0041] Each cell plug CPL includes a blocking layer BX, a charge trapping layer CT, a tunnel isolation layer TX, a channel layer CH, and a core pillar CO. The blocking layer BX may have a cylindrical shape. The charge trapping layer CT is in contact with the inner surface of the blocking layer BX. The tunnel isolation layer TX is in contact with the inner surface of the charge trapping layer CT. The channel layer CH is in contact with the inner surface of the tunnel isolation layer TX. The core pillar CO fills the inside of the channel layer CH or is surrounded by the channel layer CH. For example, the core pillar CO may have a cylindrical shape in the region surrounded by the channel layer CH. An overlying layer (not shown) may optionally be formed over the core pillar CO.

[0042] The blocking layer BX and the tunnel isolation layer TX may each include an oxide layer (e.g., a silicon oxide layer), a nitride oxide layer (e.g., a silicon oxynitride layer), or a combination thereof. The charge trapping layer CT may include a nitride layer or a variable resistance material. The channel layer CH may include an undoped silicon layer or a doped silicon layer. The core pillar CO may include an insulating layer or a conductive layer. Each of the blocking layer BX, the charge trapping layer CT, the tunnel isolation layer TX, the channel layer CH, and the core pillar CO included in each cell plug CPL extends in the Z direction with respect to the drawing.

[0043] Figure 4 is a cross-sectional view of a memory device 100 according to an embodiment of the present disclosure. Figure 4 shows a cross-sectional view taken along Figure 3 line A-A′.

[0044] Referring to Figure 4 , the memory device 100 (e.g., the i-th memory block BLKi) includes a stacked structure STK. The stacked structure STK includes a plurality of gate conductive layers CD and a plurality of interlayer insulating layers IIL stacked alternately. As Figure 4 shown, the gate conductive layers CD and the interlayer insulating layers IIL are stacked alternately in the Z direction. The gate conductive layer CD may include at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polysilicon (polySi). The interlayer insulating layer IIL may include an oxide layer, e.g., a silicon oxide layer. Each gate conductive layer CD corresponds to Figure 1 one of the drain select line DSL, the word line WL, and the source select line SSL.

[0045] The memory device 100 (such as the i-th memory block BLKi) includes a cell plug CPL. The cell plug CPL penetrates the stacked structure STK. For example, the cell plug CPL is located inside a first opening OP1 that penetrates the stacked structure STK. As Figure 4 shown, the cell plug CPL extends in the Z direction. Figure 1 and Figure 2The memory cell or the select transistor described in

[0046] is formed at the intersection (not shown) of the cell plug CPL and the gate conductive layer CD. The cell plug CPL includes a memory layer ML. The memory layer ML includes a blocking layer BX, a charge trapping layer CT, and a tunnel isolation layer TX. The memory layer ML penetrates or extends through the stack structure STK. The memory layer ML is formed along the inner wall of the first opening OP1. For example, the blocking layer BX contacts the inner surface of the first opening OP1. Thus, the memory layer ML contacts the inner wall of the stack structure STK. The memory layer ML extends along the outer surface of the channel layer CH. For example, the tunnel isolation layer TX contacts the outer surface of the channel layer CH.

[0047] The cell plug CPL includes a core column CO. The core column CO fills the inside of the channel layer CH or is surrounded by the inside of the channel layer CH. The core column CO contacts the inner surface of the channel layer CH. The core column CO is surrounded by the channel layer CH.

[0048] The cell plug CPL includes a channel layer CH. The channel layer CH penetrates or extends through the stack structure STK. The channel layer CH extends in the Z direction. The channel layer CH may have a cylindrical shape. As Figure 4 shown in the example, the channel layer CH includes a first portion P1 and a second portion P2. The second portion P2 is located below the first portion P1. The lower surface of the first portion P1 contacts the upper surface of the second portion P2. The first end (such as the upper surface) of the second portion P2 is adjacent to the first end (such as the lower surface) of the first portion. In the present disclosure, although the first portion P1 and the second portion P2 may not be physically separated from each other and may include a single unified structure, for the sake of convenience of description, the first portion P1 and the second portion P2 are described as being separated or divided from each other. For example, the interface between the first portion P1 and the second portion P2 may be undetectable.

[0049] In the present embodiment, the first portion P1 of the channel layer CH contains single crystal silicon. In the first portion P1, there may be no grain boundary GB, or the grain boundary GB may be so small that it is undetectable.

[0050] In the present embodiment, the second portion P2 of the channel layer CH includes polycrystalline silicon. The second portion P2 of the channel layer CH includes one or more grain boundaries GB. In the present embodiment, the second portion P2 includes polycrystalline silicon containing a plurality of grains. Thus, the grain boundary GB is located in the second portion P2 of the channel layer CH. The size of the grains contained in the second portion P2 may not be limited to Figure 4 the embodiment shown. Figure 4 Only the grain boundary GB formed in the second portion P2 is shown, although the position and shape of the grain boundary GB are not limited to Figure 4 the position and shape of the grain boundary GB shown.

[0051] Figures 5A to 5I FIG. is a cross-sectional view of a memory device formed by a method of manufacturing a memory device according to an embodiment of the present disclosure. Figures 5A to 5I Each shows a cross-section taken along Figure 3 line A-A' of.

[0052] Referring to Figure 5A , a preliminary stack structure pSTK is formed. The preliminary stack structure pSTK includes a first material layer IIL and a second material layer SF alternately stacked in the Z direction. The first material layer IIL may include an insulating material. For example, the first material layer IIL may include an oxide layer (e.g., a silicon oxide layer). The second material layer SF may include a material that can be selectively removed in a subsequent process. Therefore, the second material layer SF may include a material having an etch selectivity different from that of the first material layer IIL. For example, the second material layer SF may include a nitride layer.

[0053] A first opening OP1 is formed through the preliminary stack structure pSTK. The first opening OP1 penetrates or extends through the first material layer IIL and the second material layer SF of the preliminary stack structure pSTK. The first opening OP1 extends in the Z direction. The first opening OP1 may have, for example, a circular, elliptical, conical, triangular, or rectangular shape.

[0054] Referring to Figure 5B , a preliminary barrier layer pBX, a preliminary charge trapping layer pCT, a preliminary tunnel isolation layer pTX, and a preliminary channel layer pCH are formed over the preliminary stack structure pSTK. For example, the preliminary barrier layer pBX, the preliminary charge trapping layer pCT, the preliminary tunnel isolation layer pTX, and the preliminary channel layer pCH are sequentially formed on the upper surface of the preliminary stack structure pSTK and the inner surface of the preliminary stack structure pSTK surrounding or adjacent to the first opening OP1. Therefore, the preliminary channel layer pCH is formed on the inner surface of the first opening OP1 and the upper surface of the preliminary stack structure pSTK.

[0055] The preliminary barrier layer pBX, the preliminary charge trapping layer pCT, the preliminary tunnel isolation layer pTX, and the preliminary channel layer pCH are sequentially or continuously positioned starting from the inner wall of the preliminary stack structure pSTK surrounding the first opening OP1. The preliminary barrier layer pBX, the preliminary charge trapping layer pCT, the preliminary tunnel isolation layer pTX, and the preliminary channel layer pCH extend through the preliminary stack structure pSTK.

[0056] In Figure 5B , the preliminary channel layer pCH includes, for example, amorphous silicon. The preliminary channel layer pCH can be formed by a process including depositing amorphous silicon on the upper surface of the preliminary stack structure pSTK and the inner wall of the preliminary stack structure pSTK surrounding the first opening OP1.

[0057] A preliminary cover layer pCV is formed over the preliminary channel layer pCH. The preliminary cover layer pCV fills the interior of the preliminary channel layer pCH or is disposed between the walls of the preliminary channel layer pCH. Within the first opening OP1, the preliminary cover layer pCV covers at least a portion of the inner surface of the preliminary channel layer pCH. In addition, the preliminary cover layer pCV covers at least a portion of the upper surface of the preliminary channel layer pCH formed over the preliminary stack structure pSTK. In another embodiment, the preliminary cover layer pCV may fill the first opening OP1 and may not be formed over the preliminary stack structure pSTK. The preliminary cover layer pCV may include an oxide layer.

[0058] Refer to Figure 5C , a portion or a section of the preliminary cover layer pCV is removed to form a cover layer CV. For example, the upper portion of the preliminary cover layer pCV may be etched to form a recess RC above the upper portion of the cover layer CV. After removing a portion of the preliminary cover layer pCV, a portion of the inner surface of the preliminary channel layer pCH is exposed. A portion of the inner surface of the preliminary channel layer pCH is exposed through the recess RC. For example, the cover layer CV covers the lower portion of the inner surface of the preliminary channel layer pCH and does not cover the upper portion of the inner surface of the preliminary channel layer pCH. Thus, the upper portion of the inner surface of the preliminary channel layer pCH is exposed through the recess RC. In addition, the upper surface of the preliminary channel layer pCH formed over the preliminary stack structure pSTK is exposed. A wet etching process, a dry etching process, etc. may be performed to selectively etch or remove a portion of the preliminary cover layer pCV.

[0059] A conductive layer CC is formed over the preliminary channel layer pCH exposed through the recess RC. The conductive layer CC covers the portion of the preliminary channel layer pCH not covered by the cover layer CV. For example, the conductive layer CC is formed on the upper surface of the preliminary channel layer pCH located over the preliminary stack structure pSTK. In addition, the conductive layer CC is formed on a portion (e.g., the upper portion) of the inner surface of the preliminary channel layer pCH within the first opening OP1. The conductive layer CC may include a metal such as nickel (Ni).

[0060] Refer to Figure 5D , the conductive layer CC can be converted into a silicide layer SS. The conductive layer CC is converted into the silicide layer SS through a first heat treatment. The conductive layer CC in contact with the surface of the preliminary channel layer pCH is converted into the silicide layer SS. The silicide layer SS may include a silicide such as nickel silicide (NiSi2).

[0061] Refer to Figure 5E, a part of the preliminary channel layer pCH can be crystallized by using the silicide layer SS. The silicide layer SS is used to convert the said part of the preliminary channel layer pCH into single-crystalline silicon. For example, during the second heat treatment, the preliminary channel layer pCH is induced to crystallize by using the silicide layer SS. The crystallization of the preliminary channel layer pCH by using the silicide layer SS is called the metal-induced lateral crystallization (MILC) method or process.

[0062] In Figure 5D , the silicide layer SS contacts the upper part of the preliminary channel layer pCH. Therefore, during the metal-induced lateral crystallization (MILC) as shown in Figure 5E , crystallization proceeds from the upper part to the lower part of the preliminary channel layer pCH with respect to the figure. For example, when the second heat treatment is performed, the silicide layer SS moves in the downward direction (e.g., the negative Z direction) with respect to the figure. Therefore, the upper part of the preliminary channel layer pCH crystallizes before the lower part of the preliminary channel layer pCH. Therefore, as shown in Figure 5E , the upper part of the preliminary channel layer pCH contains single-crystalline silicon, while the lower part of the preliminary channel layer pCH contains amorphous silicon.

[0063] The part of the preliminary channel layer pCH that is crystallized by using the silicide layer SS is called the first part P1 or the first part P1 of the preliminary channel layer pCH. The first part P1 crystallized by the MILC method contains single-crystalline silicon. After the second heat treatment is performed, the part of the preliminary channel layer pCH located above or over the silicide layer SS is called the first part P1. Another part of the preliminary channel layer pCH located below or under the silicide layer SS with respect to the drawing is called the second part P2 or the second part P2 of the preliminary channel layer pCH. The silicide layer SS is located between the first part P1 and the second part P2 of the preliminary channel layer pCH. In Figure 5E , the first part P1 may contain single-crystalline silicon, while the second part P2 may contain amorphous silicon. When the preliminary channel layer pCH is induced to crystallize by using the silicide layer SS, the silicide layer SS moves in the downward direction with respect to the drawing. The lower surface of the first part P1 may be located below the upper surface of the cover layer CV in the negative Z direction, for example.

[0064] Referring to Figure 5E , the height of the silicide layer SS (e.g., the position of the silicide layer SS in the Z direction) can vary with respect to the X direction and / or the Y direction or the X-Y plane. When the second heat treatment is performed, the moving speed of the silicide layer SS can vary according to the position of the silicide layer SS in the X-Y plane. Therefore, the silicide layer SS can be formed at different heights or positions in the Z direction on the preliminary channel layer pCH within any cell plug CPL. For example, as shown in Figure 5E , the silicide layer SS on the left side in the figure is lower in the Z direction than the silicide layer SS on the right side in the figure.

[0065] Refer to Figure 5F , the cover layer CV is removed to form a second opening OP2. The inner surface of the preliminary channel layer pCH is exposed through the second opening OP2. Therefore, both the upper surface and the inner surface of the preliminary channel layer pCH are exposed.

[0066] The preliminary channel layer pCH is doped with a conductive material DP. In Figure 5F the example, the conductive material DP is doped into the upper surface and the inner surface of the preliminary channel layer pCH. For example, the inner surface of the preliminary channel layer pCH is doped with the conductive material DP through the second opening OP2. The conductive material DP may include a metal such as nickel (Ni).

[0067] A first portion P1 of the preliminary channel layer pCH is doped with the conductive material DP. In addition, a second portion P2 of the preliminary channel layer pCH is doped with the conductive material DP. The process of doping the conductive material DP into the first portion P1 and the second portion P2 can be performed simultaneously.

[0068] The conductive material DP is doped not only into the second portion P2 containing amorphous silicon but also into the first portion P1 containing single crystal silicon. Therefore, the conductive material DP is doped not only into the second portion P2 to promote crystallization but also into the already crystallized first portion P1. In addition, a portion of the conductive material DP may be doped into the silicide layer SS.

[0069] Refer to Figure 5G , the preliminary channel layer pCH is crystallized using the conductive material DP. The second portion P2' of the preliminary channel layer pCH is transformed into polycrystalline silicon. A third heat treatment is used to induce crystallization of the preliminary channel layer pCH (e.g., the second portion P2') using the conductive material DP. Crystallization of the preliminary channel layer pCH using the conductive material DP is called the metal-induced recrystallization (MIC) method or process.

[0070] The second portion P2' of the preliminary channel layer pCH may be crystallized based on the position where the conductive material DP is doped. For example, the second portion P2' may be crystallized around or near the position where the conductive material DP is doped. Therefore, the crystallized second portion P2' includes a plurality of grains. The second portion P2' of the preliminary channel layer pCH includes grain boundaries GB.

[0071] Although the conductive material DP is doped into the first portion P1 of the preliminary channel layer pCH, since the first portion P1 contains single crystal silicon, the crystalline state of the first portion P1 does not have to be changed.

[0072] When performing the third heat treatment, the silicide layer SS diffuses into the preliminary channel layer pCH. For example, in crystallization using the metal-induced recrystallization (MIC) method, the metal material contained in the silicide layer SS can be utilized. Therefore, as Figure 5G shown, the silicide layer SS may not be detectable.

[0073] Referring to Figure 5H , the conductive material DP in the preliminary channel layer pCH is removed. In addition, Figure 5C the remaining material contained in the conductive layer CC shown can be advantageously removed together with the conductive material DP.

[0074] The preliminary channel layer pCH from which the conductive material DP has been removed includes a first portion P1 containing single-crystalline silicon and a second portion P2' containing polycrystalline silicon. The first portion P1 is located above the second portion P2' with respect to the drawing.

[0075] A preliminary core pCO is formed in the second opening OP2. At least a portion of the preliminary core pCO is surrounded by the preliminary channel layer pCH. Another portion of the preliminary core pCO is optionally formed above the preliminary stack structure pSTK. In this example, the preliminary core pCO is in contact with the upper surface and the inner surface of the preliminary channel layer pCH.

[0076] Referring to Figure 5I , the preliminary core pCO, the preliminary channel layer pCH, the preliminary tunnel isolation layer pTX, the preliminary charge trapping layer pCT, and the preliminary barrier layer pBX located above or over the preliminary stack structure pSTK in the Z direction are removed. Thus, the upper surface of the preliminary stack structure pSTK is exposed.

[0077] The barrier layer BX, the charge trapping layer CT, the tunnel isolation layer TX, and the channel layer CH remaining after removing the material layer above the preliminary stack structure pSTK constitute the unit plug CPL. In addition, the channel layer CH can include a first portion P1' having a cylindrical shape and a second portion P2' below the first portion P1' or extending downward from the first portion P1'. The first portion P1' contains single-crystalline silicon, and the second portion P2' contains polycrystalline silicon.

[0078] The second material layer SF is replaced by a third material layer CD to form the stack structure STK. The third material layer CD includes a conductive material.

[0079] When forming the channel layer CH according to an embodiment of the present disclosure, the grain size of the silicon included in the channel layer CH can be increased. Compared with an example of forming a channel layer using either a metal-induced lateral recrystallization (MILC) method or a metal-induced crystallization (MIC), the silicon included in the channel layer CH according to an embodiment of the present disclosure can have a larger grain size. For example, since the channel layer CH of the present disclosure includes not only a second portion (P2, P2') containing amorphous silicon but also a first portion (P1, P1') containing single-crystalline silicon, the channel layer CH can have a larger average grain size than a channel layer containing only amorphous silicon. As the grain size of the silicon included in the channel layer CH increases, the resistance of the grain boundaries GB included in the channel layer CH decreases. According to the present disclosure, the amount of current flowing through the memory cells in the memory device 100 can be increased.

[0080] Figure 6 FIG. is an exemplary diagram illustrating an embodiment of a memory card system 3000 including a memory device 3200 according to the present disclosure.

[0081] Referring to Figure 6 , the memory card system 3000 includes a controller 3100, a memory device 3200, and a connector 3300.

[0082] The controller 3100 is coupled to the memory device 3200. The controller 3100 is configured to access the memory device 3200. For example, the controller 3100 is configured to control programming operations, read operations, erase operations, and background operations of the memory device 3200. The controller 3100 is configured to provide an interface between the memory device 3200 and a host. The controller 3100 is configured to drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0083] The controller 3100 communicates with an external device via the connector 3300. The controller 3100 communicates with the external device (e.g., a host) according to a specific communication protocol. For example, the controller 3100 may be configured to communicate with the external device via at least one of various communication protocols such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), WiFi, Bluetooth, and NVMe protocol. For example, the connector 3300 may be configured according to at least one of the above communication protocols.

[0084] The memory device 3200 includes a plurality of memory cells and is configured in the same manner as the memory device 100 Figure 1 shown and is formed using a method of manufacturing a memory device according to the method described above Figures 5A to 5I herein.

[0085] The controller 3100 and the memory device 3200 are integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 may form a memory card such as a Personal Computer (PC) Card (Personal Computer Memory Card International Association (PCMCIA)), CompactFlash (CF) card, SmartMedia card (SM or SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, microMMC, or eMMC), SD card (SD, miniSD, microSD, or SDHC), or Universal Flash Storage (UFS).

[0086] Figure 7 FIG. is an illustration of an embodiment of a Solid State Drive (SSD) system 4000 including a plurality of memory devices 4221 to 422n according to the present disclosure.

[0087] Referring to Figure 7 , the SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals with the host 4100 via a signal connector 4001 and receives power via a power connector 4002. The SSD 4200 includes a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0088] The controller 4210 controls a plurality of memory devices 4221 to 422n in response to signals received from the host 4100. For example, the signals may be based on the interface between the host 4100 and the SSD 4200. For example, the signals may be configured or constructed according to at least one of a plurality of interfaces such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), WiFi, Bluetooth, and NVMe interface.

[0089] Each of the plurality of memory devices 4221 to 422n includes a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n is configured in the same manner as the memory device 100 shown, and is formed using a method of manufacturing a memory device according to the method described above with reference to Figure 1 The memory device 100 is configured and formed using a method of manufacturing a memory device according to the method described above with reference to Figures 5A to 5I The plurality of memory devices 4221 to 422n communicate with the controller 4210 through channels CH1 to CHn.

[0090] The auxiliary power supply 4230 is connected to the host 4100 through a power connector 4002. The auxiliary power supply 4230 receives power input from the host 4100 and can adjust the power according to the needs of the SSD. When the power supply of the host 4100 is uneven or unstable, the auxiliary power supply 4230 supplies power to the SSD 4200. For example, the auxiliary power supply 4230 may be located inside or outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on the main board and provide auxiliary power to the SSD 4200.

[0091] The buffer memory 4240 serves as the buffer memory of the SSD 4200. For example, the buffer memory 4240 temporarily stores data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or may temporarily store metadata of the memory devices 4221 to 422n, such as a mapping table. The buffer memory 4240 may include volatile memories such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0092] According to an embodiment of the present disclosure, the current flowing in a memory cell can be increased by increasing the grain size of silicon included in a channel layer of a semiconductor device. According to an embodiment, a method may include three separate heat treatment processes. According to an embodiment, a method may further include forming a conductive layer on an exposed inner surface of the channel layer; converting the conductive layer into a silicide layer using a first heat treatment; inducing crystallization of a first portion using the silicide layer during a second heat treatment; and converting a second portion into polysilicon using a third heat treatment.

[0093] The concepts related to various embodiments are described above. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should be considered from an exemplary rather than a restrictive perspective. Accordingly, the scope of the present disclosure should not be limited to the above embodiments. All variations within the equivalent meaning and scope of the claims should be included within its scope.

[0094] Cross - reference to related applications

[0095] This application claims the priority of Korean Patent Application No. 10 - 2023 - 0179620, filed with the Korean Intellectual Property Office on December 12, 2023, the entire disclosure of which is incorporated herein by reference.

Claims

1. A method for manufacturing a memory device, the method comprising the steps of: forming a stacked structure including alternately stacked first material layers and second material layers; forming a channel layer including amorphous silicon in an opening extending through the stacked structure; converting a first portion of the channel layer into single crystal silicon; doping the first portion of the channel layer with a conductive material; doping a second portion of the channel layer with the conductive material, wherein the second portion is different from the first portion; as well as The second portion of the channel layer is converted into polysilicon using the conductive material.

2. The method according to claim 1, wherein: The step of forming the channel layer comprises the following steps: forming the opening extending through the stacked structure; forming a memory layer on an inner surface of the stacked structure surrounding the opening and on an outer surface of the stacked structure; and The channel layer is formed on the memory layer.

3. The method according to claim 2, wherein: During the formation of the channel layer on the memory layer, the channel layer is formed on the inner surface of the stacked structure surrounding the opening and the outer surface of the stacked structure, wherein the outer surface of the stacked structure and the inner surface of the stacked structure are located on continuous sides of the stacked structure.

4. The method according to claim 1, wherein: The step of converting the first portion into the single crystal silicon comprises the following steps: forming a cover layer so that a portion of the inner surface of the channel layer is exposed through the recessed portion; forming a conductive layer on the exposed inner surface of the channel layer; and The first portion is converted into the single crystal silicon using the conductive layer.

5. The method according to claim 4, wherein: The step of forming the covering layer comprises the following steps: forming a preliminary capping layer inside the channel layer; and forming the recessed portion by removing a portion of the preliminary covering layer, Wherein, the portion of the inner surface of the channel layer is exposed through the recessed portion.

6. The method according to claim 4, wherein: The step of converting the first portion into the single crystal silicon using the conductive layer comprises the following steps: converting the conductive layer into a silicide layer using a first thermal process; and The first portion is induced to crystallize using the silicide layer during a second thermal treatment.

7. The method according to claim 6, wherein: During the second thermal treatment, the silicide layer moves toward the capping layer.

8. The method according to claim 4, wherein: The first surface of the covering layer is adjacent to the recess, and the first surface of the covering layer is disposed between the recess and a first end of the first portion of the channel layer, the first end of the first portion of the channel layer being formed during conversion of the first portion into the single crystal silicon using the conductive layer.

9. The method according to claim 1, wherein: Doping the first portion with the conductive material and doping the second portion with the conductive material are performed simultaneously.

10. The method according to claim 1, wherein: The second portion is converted to polysilicon using a third thermal treatment.

11. The method according to claim 1, wherein: The first end of the second portion is formed adjacent to the first end of the first portion.

12. The method according to claim 1, further comprising the steps of: After converting the second portion to polysilicon, the conductive material is removed from the channel layer.

13. A memory device, the memory device comprising: Layered structure; as well as a channel layer formed in an opening extending through the stacked structure, The channel layer includes a first portion including single crystal silicon and a second portion including polycrystalline silicon, wherein the first portion is adjacent to the second portion. 14 . The memory device of claim 13 , further comprising a memory layer formed in the opening extending through the stack structure and extending along an outer surface of the channel layer.

15. The memory device of claim 14, wherein: The memory layer comprises: a barrier layer in contact with an inner surface of the stacked structure; a charge-trapping layer in contact with an inner surface of the barrier layer; and A tunnel isolation layer is in contact with the inner surface of the charge trapping layer and the outer surface of the channel layer. 16 . The memory device of claim 13 , further comprising a stem located inside the channel layer.

17. A method of manufacturing a memory device, the method comprising the steps of: forming an opening extending through the laminate structure; forming a channel layer including amorphous silicon in the opening; converting a first portion of the channel layer into single crystal silicon; doping the first portion of the channel layer and a second portion of the channel layer with a conductive material, wherein the second portion is adjacent to the first portion; as well as The second portion of the channel layer is converted into polysilicon using the conductive material.

18. The method of claim 17, further comprising three separate heat treatment processes.

19. The method according to claim 17, further comprising the steps of: forming a conductive layer on the exposed inner surface of the channel layer; converting the conductive layer into a silicide layer using a first thermal process; inducing crystallization of the first portion using the silicide layer during a second thermal treatment; as well as The second portion is converted to polysilicon using a third thermal treatment.

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