Diamond / 3C-SiC heterojunction field effect transistor and preparation method thereof
By depositing high (111) orientation quasi-single crystal diamond on the 3C-SiC substrate, as a P-type well region material, the problem of field effect transistors requiring high-temperature annealing during the preparation process is solved, and its shutdown voltage and stability are improved.
Patent Information
- Application Number
- CN202510310185.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2025-06-17
AI Technical Summary
The existing field effect transistors require high-temperature annealing during the preparation process, and the 3C-SiC material used has a small bandwidth, resulting in low shutdown voltage and poor stability.
High (111) orientation quasi-single crystal diamond is deposited in the trench by pulse bias enhancement MPCVD device on a 3C-SiC substrate. As a P-type well region material, high-temperature annealing treatment is avoided and the band gap width is improved.
It avoids the need for high-temperature annealing treatment, improves the shutdown voltage and stability of the field effect transistor, and reduces the leakage current situation.
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Figure CN120166728A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a diamond / 3C-SiC heterojunction field effect transistor and a preparation method thereof. Background Art
[0002] In the process of preparing a field effect transistor, an ion implantation method is usually used to fabricate a P-type well region. However, ion implantation will cause great damage to the lattice structure inside the field effect transistor. In order to repair the damaged lattice and activate the implanted ions, a high-temperature annealing treatment is required, which poses strict requirements on the high-temperature resistance performance of the field effect transistor.
[0003] In addition, the current field effect transistor usually selects 3C-SiC as the material of the P-type well region. However, the bandgap width of 3C-SiC is relatively small, only 2.36 eV, which results in a small turn-off voltage of the field effect transistor and is prone to leakage current, thereby making the stability of the field effect transistor in the off state poor. Summary of the Invention
[0004] The purpose of the embodiments of the present invention is to provide a diamond / 3C-SiC heterojunction field effect transistor and a preparation method thereof to avoid high-temperature annealing treatment and improve the stability of the field effect transistor in the off state. The specific technical solutions are as follows:
[0005] In a first aspect, an embodiment of the present application provides a preparation method of a diamond / 3C-SiC heterojunction field effect transistor, the method comprising:
[0006] Epitaxially growing a 3C-SiC buffer layer and an n-type drift layer on the upper surface of a 3C-SiC substrate in sequence;
[0007] Etching a preset number of parallel grooves on the upper surface of the n-type drift layer;
[0008] Using a pulsed bias enhanced MPCVD device to deposit high (111)-oriented quasi-single crystal diamond in the grooves to obtain a P-type well region, wherein the gases introduced during the deposition process include: CH4 gas with a gas ratio greater than 0 and not exceeding 4%, O2 gas with a gas ratio greater than 0 and not exceeding 2%, 5-10% Ar gas, B2H6 gas with a gas ratio greater than 0 and not exceeding 2%, and 82-95% H2, the deposition temperature is 700-1000 °C, the deposition pressure is 5 KPa-50 KPa, the pulsed voltage is -50-200 V, and the pulsed time is 10-100 s;
[0009] Growing a dielectric layer on the non-diamond array region on the upper surface of the n-type drift layer;
[0010] Deposit a first metal and a second metal in sequence on the diamond array region on the upper surface of the n-type drift layer to obtain an ohmic contact layer, and deposit a third metal and a fourth metal in sequence on the lower surface of the 3C-SiC substrate to obtain a back metal contact layer;
[0011] Deposit a gate on the upper surface of the dielectric layer to obtain a diamond / 3C-SiC heterojunction field effect transistor.
[0012] Optionally, the B ion concentration in the high (111)-oriented quasi-single crystal diamond deposited in the trench is 1×10 18 / cm -3 ~1×10 20 / cm -3 .
[0013] Optionally, the high (111)-oriented quasi-single crystal diamond deposited in the trench has a diamond Raman characteristic peak when irradiated with an excitation light with a wavelength of 532 nm.
[0014] Optionally, the full width at half maximum of the diamond Raman characteristic peak is not greater than 200 arcsec.
[0015] Optionally, the full width at half maximum of the diamond Raman characteristic peak is 50 or 100 arcsec.
[0016] Optionally, the surface roughness of the upper surface of the high (111)-oriented quasi-single crystal diamond deposited in the trench is less than 0.2 nm.
[0017] Optionally, the 3C-SiC substrate is polished on the upper surface of an original 3C-SiC substrate with a carrier concentration of 1×10 18 / cm -3 ~1×10 20 / cm -3 and a size of 2-8 inches to obtain a substrate with a crystal orientation of (111), an inclination angle of 0-4°, and a surface roughness less than 0.2 nm on the upper surface.
[0018] Optionally, the thickness of the 3C-SiC buffer layer is greater than 0 and does not exceed 5 μm, the thickness of the n-type drift layer is 1-100 μm, the carrier concentration of the 3C-SiC buffer layer is 1×10 18 / cm -3 ~8×10 18 / cm -3 , and the carrier concentration of the n-type drift layer is 1×10 14 / cm -3 ~1×10 18 / cm -3 .
[0019] Optionally,
[0020] The depth of the groove is 1 to 10 μm, and the depth-to-width ratio is 1 to 10;
[0021] and / or,
[0022] The thickness of the dielectric layer is 20 to 50 nm;
[0023] and / or,
[0024] The thickness of the first metal is 20 nm, the thickness of the second metal is 80 nm, the thickness of the third metal is 20 nm, and the thickness of the fourth metal is 80 nm;
[0025] and / or,
[0026] The thickness of the gate is 100 nm.
[0027] In a second aspect, an embodiment of the present application provides a diamond / 3C-SiC heterojunction field effect transistor, which is prepared by the preparation method described in the first aspect above.
[0028] Beneficial effects of the embodiments of the present invention:
[0029] In the solution provided by the embodiments of the present invention, a diamond / 3C-SiC heterojunction field effect transistor can be prepared through the following steps: epitaxially grow a 3C-SiC buffer layer and an n-type drift layer on the upper surface of a 3C-SiC substrate in sequence; etch a preset number of parallel grooves on the upper surface of the n-type drift layer; use a pulsed bias enhanced MPCVD device to deposit high (111)-oriented quasi-single crystal diamond in the grooves to obtain a P-type well region, wherein the gases introduced during the deposition process include: CH4 gas with a gas ratio greater than 0 and not exceeding 4%, O2 gas with a gas ratio greater than 0 and not exceeding 2%, 5 to 10% Ar gas, B2H6 gas with a gas ratio greater than 0 and not exceeding 2%, and 82 to 95% H2, the deposition temperature is 700 to 1000 °C, the deposition pressure is 5 KPa to 50 KPa, the pulsed voltage is -50 to 200 V, and the pulsed time is 10 to 100 s; grow a dielectric layer on the non-diamond array region on the upper surface of the n-type drift layer; deposit an ohmic contact layer on the diamond array region on the upper surface of the n-type drift layer, and deposit a back metal contact layer on the lower surface of the 3C-SiC substrate; deposit a gate on the upper surface of the dielectric layer to obtain a diamond / 3C-SiC heterojunction field effect transistor.
[0030] Since the P-type well region in the solution provided by the embodiment of the present invention is fabricated by depositing high (111)-oriented quasi-single crystal diamond in the trench, rather than by ion implantation, there is no need for high-temperature annealing treatment to repair the damaged lattice and activate the implanted ions. Therefore, the high-temperature annealing treatment is avoided, and the requirement for the high-temperature resistance performance of the field-effect transistor is reduced. In addition, in the solution provided by the embodiment of the present invention, high (111)-oriented quasi-single crystal diamond with a bandgap width of 5.50 eV is used as the P-type well region material. Compared with 3C-SiC with a bandgap width of only 2.36 eV, which is commonly used as the P-type well region material, the turn-off voltage of the field-effect transistor can be effectively increased, the occurrence of leakage current is greatly reduced, and the stability of the field-effect transistor in the off state is significantly improved.
[0031] Of course, it is not necessary for any product or method implementing the present invention to achieve all the above-mentioned advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other embodiments based on these drawings.
[0033] Figure 1 A schematic flow chart of a method for fabricating a diamond / 3C-SiC heterojunction field-effect transistor provided by an embodiment of the present application;
[0034] Figure 2 Another schematic flow chart of a method for fabricating a diamond / 3C-SiC heterojunction field-effect transistor provided by an embodiment of the present application;
[0035] Figure 3 Based on Figure 1 A schematic diagram showing the variation of the Raman peak intensity of the deposited high (111)-oriented quasi-single crystal diamond with wavelength in the shown embodiment;
[0036] Figure 4 A schematic structural diagram of a diamond / 3C-SiC heterojunction field-effect transistor provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art based on the present application belong to the scope of protection of the present invention.
[0038] To avoid high-temperature annealing treatment and improve the stability of the field-effect transistor in the off state, an embodiment of the present application provides a diamond / 3C-SiC heterojunction field-effect transistor and a preparation method thereof. First, the preparation method of the diamond / 3C-SiC heterojunction field-effect transistor provided by the embodiment of the present application will be introduced below.
[0039] As Figure 1 shown, Figure 1 is a schematic flowchart of a preparation method of a diamond / 3C-SiC heterojunction field-effect transistor provided by an embodiment of the present application. The method includes:
[0040] S101, epitaxially grow a 3C-SiC buffer layer and an n-type drift layer on the upper surface of a 3C-SiC substrate in sequence.
[0041] First, a 3C-SiC substrate with a carrier concentration of 1×10 18 / cm -3 ~1×10 20 / cm -3 and a size of 2 to 8 inches can be selected as the original substrate. Then, polish the upper surface of the original substrate so that the crystal orientation of the upper surface of the original substrate is (111), the inclination angle is 0 to 4°, and the surface roughness is less than 0.2 nm, thereby obtaining a 3C-SiC substrate. Among them, the polishing method can be CMP (Chemical Mechanical Polishing), etc., which is not specifically limited herein.
[0042] Then, the polished 3C-SiC substrate can be cleaned through a standard cleaning process. On the upper surface of the cleaned 3C-SiC substrate, epitaxially grow a 3C-SiC buffer layer with a thickness greater than 0 and not exceeding 5 μm and a carrier concentration of 1×10 18 / cm -3 ~8×10 18 / cm -3 . Furthermore, on the 3C-SiC buffer layer, epitaxially grow an n-type drift layer with a thickness of 1 to 100 μm and a carrier concentration of 1×10 14 / cm -3 ~1×10 18 / cm -3 .
[0043] Among them, the different carrier concentrations in the 3C-SiC buffer layer and the n-type drift layer can be achieved by adjusting the ratio between the respective growth gases. For example, in the case of epitaxial growth using gases such as SiH4 (providing a silicon source), C3H8 (providing a carbon source), and nitrogen (a dopant), when epitaxially growing the 3C-SiC buffer layer, the ratio of nitrogen in the growth gas can be appropriately increased, so that more nitrogen atoms enter the grown 3C-SiC buffer layer, thereby increasing the carrier concentration of the 3C-SiC buffer layer. When epitaxially growing the n-type drift layer, the ratio of nitrogen in the growth gas can be appropriately decreased, so that fewer nitrogen atoms enter the grown n-type drift layer, thereby decreasing the carrier concentration of the n-type drift layer.
[0044] The intermediate device obtained through step S101 can be as Figure 2 shown in subfigure (a) of Figure 2 In subfigure (a) of Figure 2 where 3C-SiC N+ is the 3C-SiC substrate, 3C-SiC N- is the n-type drift layer, and the 3C-SiC buffer layer (
[0045] not shown in subfigure (a) of
[0046] is located between 3C-SiC N+ and 3C-SiC N-.
[0047] After obtaining the n-type drift layer through step S101, a preset number of parallel grooves with a depth of 1 - 10 μm and an aspect ratio of 1 - 10 can be etched on the upper surface of the n-type drift layer. Among them, the method of etching the grooves can be wet etching, electron beam etching, ion beam etching, etc., and the specific method of etching the grooves is not limited in the embodiments of the present application. The number of grooves can be flexibly set according to the specific type of the field effect transistor, and the specific number of grooves is not limited in the embodiments of the present application. For the sake of more clearly explaining the solution of the present application, the subsequent embodiments will take the preset number as 2 for specific illustration.
[0048] For example, an SiO2 thin film can be grown on the upper surface of the n-type drift layer by means of thermal oxidation or CVD (Chemical Vapor Deposition), and then a metal Al film can be deposited on the SiO2 thin film by means of PVD (Physical Vapor Deposition) and the like, so as to form a mask layer on the n-type drift layer. Then, photoresist can be uniformly coated on the metal Al film, and the photoresist is exposed by using a lithography machine and a mask plate, so that the photoresist is exposed to form two parallel trench patterns. Further, an etching gas (such as chlorine gas) is used to etch the metal Al film not protected by the photoresist, and an SiO2 thin film is etched with a fluorine-based gas (such as CF4) to expose the n-type drift layer, thereby completing the etching of the mask layer. Finally, the n-type drift layer not protected by the mask layer is etched by an etching gas (such as a mixed gas of SF6 and O2), so as to etch two parallel trenches on the upper surface of the n-type drift layer.
[0049] The intermediate device obtained through step S102 may be as Figure 2 shown in the subfigure (b) of Figure 2 At this time, the upper surface of the n-type drift layer (i.e., 3C-SiC N- in the subfigure (b) of
[0050] S103. Deposit high (111)-oriented quasi-single-crystal diamond in the trenches by using a pulsed bias enhanced MPCVD device to obtain a P-type well region.
[0051] After the trenches are etched through step S102, the intermediate device obtained through steps S101 - S102 can be cleaned first to remove impurities on the surface of the intermediate device. For example, in the case where a mask layer is formed by SiO2 and Al to etch the trenches, after the etching is completed, the obtained intermediate device can be subjected to standard RCA cleaning and BOE (Buffered Oxide Etch) solution cleaning to remove Al and SiO2 on the surface of the intermediate device.
[0052] When depositing diamond, since for diamond, in terms of electrical properties, the consistency of its crystal orientation can make the carrier transport characteristics better, can reduce electron scattering, etc., and is helpful for improving the performance of diamond-based electronic devices. Therefore, when depositing diamond in the trenches, the pulsed bias function of the pulsed bias enhanced MPCVD device can be used to guide the carbon atoms to deposit in a specific direction, thereby promoting the growth of diamond crystals along a specific crystal orientation, improving the orientation degree of diamond, and thus depositing high (111)-oriented quasi-single-crystal diamond. In addition, by precisely controlling the ratio of deposition gases and the parameters of the pulsed bias (such as pulse frequency, pulse voltage, etc.), the orientation performance of diamond can be further optimized.
[0053] Therefore, after cleaning the intermediate device obtained through steps S101 - S102, a pulsed bias can be used to enhance the MPCVD device to deposit high (111)-oriented quasi-single crystal diamond in the trench until the trench is completely filled with the high (111)-oriented quasi-single crystal diamond, obtaining the P-type well region of the field effect transistor. The gases introduced during the deposition process may include: CH4 gas with a gas ratio greater than 0 and not exceeding 4% (providing a carbon source), O2 gas greater than 0 and not exceeding 2% (etching non-diamond phases), 5 - 10% Ar gas (increasing plasma density), B2H6 gas greater than 0 and not exceeding 2% (P-type doping source), and 82 - 95% H2 (the gas flow rate can be 500 - 5000 sccm). The deposition temperature is 700 - 1000 °C, the deposition pressure is 5 KPa - 50 KPa, the pulsed voltage is -50 - 200 V, and the pulsed time is 10 - 100 s.
[0054] Among them, the ratio of CH4 gas is maintained at greater than 0 and not exceeding 4%. This can not only ensure the concentration of the carbon source, thereby increasing the growth rate of diamond, but also avoid an excessive concentration of the carbon source leading to an increase in the formation of non-diamond phases (such as graphite), which affects the purity and orientation quality of diamond. The ratio of O2 gas is greater than 0 and not exceeding 2%, which can etch non-diamond phases, improve purity, and trim the diamond growth surface to promote orientation growth. The proportion of Ar gas is 5 - 10%, which can dilute the reaction gases to make the reaction uniform, enhance the plasma, and control the growth rate and grain size of diamond. The proportion of H2 gas is 82 - 95%, which can effectively etch non-diamond phases, activate the carbon source, maintain the balance of carbon and hydrogen radicals, and is conducive to the growth of high (111)-oriented quasi-single crystal diamond. That is to say, through the ratios of the above-mentioned deposition gases, the growth of high (111)-oriented quasi-single crystal diamond can also be promoted.
[0055] The B ion concentration in the high (111)-oriented quasi-single crystal diamond deposited by the above method is 1×10 18 / cm -3 ~1×10 20 / cm -3 Moreover, when the high (111)-oriented quasi-single crystal diamond is irradiated with an excitation light with a wavelength of 532 nm, it has a diamond Raman characteristic peak, and the full width at half maximum of the diamond Raman characteristic peak is not greater than 200 arcsec. More preferably, the full width at half maximum of the diamond Raman characteristic peak is 50 or 100 arcsec.
[0056] For example, as Figure 3 shown in the relationship between wavelength and intensity, when irradiated with an excitation light with a wavelength of 532 nm, the high (111)-oriented quasi-single crystal diamond deposited by the above method produces a diamond Raman characteristic peak near a wavelength of 572.81 nm.
[0057] The intermediate device obtained through step S103 can be as shown in the sub-diagram (c) of Figure 2 . In the sub-diagram (c) of Figure 2 , the P+ region in the sub-diagram (c) is the P-type well region. The region between the P+ region and the 3C-SiC N- (n-type drift layer) is the region where high (111)-oriented quasi-single crystal diamond is deposited in the trench. After the P+ region is obtained, holes in the P+ region diffuse into the 3C-SiC N-, and electrons in the 3C-SiC N- diffuse into the P+ region, thereby forming a space charge region, that is, a depletion layer, near the interface between the two.
[0058] It should be noted here that during the process of depositing high (111)-oriented quasi-single crystal diamond in the trench, if high (111)-oriented quasi-single crystal diamond is accidentally deposited on the upper surface of the 3C-SiC N-, the upper surface of the 3C-SiC N- can be polished to remove the excess high (111)-oriented quasi-single crystal diamond on the upper surface of the 3C-SiC N-.
[0059] S104, grow a dielectric layer on the non-diamond array region on the upper surface of the n-type drift layer.
[0060] As shown in the sub-diagram (c) of Figure 2 , after depositing high (111)-oriented quasi-single crystal diamond in two parallel trenches of the n-type drift layer, the upper surface of the n-type drift layer can be divided into a diamond array region and a non-diamond array region. Among them, the diamond array region only includes the deposited diamond and a partial region in the region of the depletion layer around it, and the non-diamond array region includes the region where the 3C-SiC is located, and other partial regions in the region of the deposited diamond and the depletion layer around it.
[0061] On this basis, a dielectric layer with a thickness of 20 - 50 nm can be grown on the non-diamond array region on the upper surface of the n-type drift layer. Among them, during the process of growing the dielectric layer, a mask layer can be made to ensure that the dielectric layer grows on the non-diamond array region. Specifically, a mask layer can be first made on the diamond array region on the upper surface of the n-type drift layer, and after the dielectric layer is grown on the non-diamond array region, the mask layer on the diamond array region can be further removed. It should be noted here that in addition to step S104, deposition or generation at specific positions in other steps (such as depositing high (111)-oriented quasi-single crystal diamond in the trench, depositing the first to fourth metals, etc.) can also be achieved by making a mask layer, and the specific method will not be elaborated.
[0062] Among them, the material of the dielectric layer can be SiO2, or can be materials with high dielectric constants such as HfO2 and BaTiO3. The embodiments of the present application do not limit the specific type of the material of the dielectric layer.
[0063] The intermediate device obtained through step S104 can be as Figure 2 shown in subfigure (d) of Figure 2 In subfigure (d) of Figure 2 a dielectric layer is grown on the non-diamond array region on the upper surface of 3C-SiC N- (n-type drift layer). As can be seen from subfigure (d) of
[0064] S105, deposit a first metal and a second metal in sequence on the diamond array region on the upper surface of the n-type drift layer to obtain an ohmic contact layer, and deposit a third metal and a fourth metal in sequence on the lower surface of the 3C-SiC substrate to obtain a back metal contact layer.
[0065] For the diamond array region on the upper surface of the n-type drift layer, the first metal can be deposited in this region first to act as a bonding layer to enhance the adhesion between the metal and the diamond, and then the second metal can be continuously deposited on the deposited first metal layer to obtain the ohmic contact layer. Among them, for the diamond array regions corresponding to the two grooves on the upper surface of the n-type drift layer, the first metal and the second metal can be deposited in sequence in the above manner to obtain Figure 2 S (source) and D (drain) shown in subfigure (e) of
[0066] In one implementation manner, in order to ensure the uniform deposition of the ohmic contact layer and improve the interfacial bonding force between the diamond and the ohmic contact layer, after depositing high (111)-oriented quasi-single crystal diamond, the deposited diamond can be polished so that the surface roughness of the upper surface of the high (111)-oriented quasi-single crystal diamond deposited in the groove is less than 0.2 nm, and the upper surface of the deposited high (111)-oriented quasi-single crystal diamond and the upper surface of the surrounding 3C-SiC are maintained in the same plane. Correspondingly, when depositing the first metal and the second metal in sequence on the diamond array region, specifically, the first metal and the second metal can be deposited in sequence on the polished diamond array region. Among them, the polishing method can be CMP, etc. The embodiments of the present application do not limit the specific polishing method.
[0067] Similarly, a third metal can also be deposited on the lower surface of the 3C-SiC substrate first to act as a bonding layer and enhance the adhesion between the metal and the diamond. Then, a fourth metal can be continuously deposited on the deposited third metal layer to obtain Figure 2 the back metal contact layer shown in subfigure (f) of Figure 2 , which is located on the lower surface of the 3C-SiC N+ (3C-SiC substrate).
[0068] S106: Deposit a gate on the upper surface of the dielectric layer to obtain a diamond / 3C-SiC heterojunction field effect transistor.
[0069] After depositing the ohmic contact layer, Ni, Al, Ti, polysilicon, etc. can be deposited on the upper surface of the dielectric layer between the two ohmic contact layers to obtain Figure 2 the G (gate) shown in subfigure (f) of Figure 2 , which is located on the upper surface of the dielectric layer. In the embodiment of the present application, the thickness of the gate is not specifically limited. As an example, the thickness of the gate can be 100 nm.
[0070] Through the above steps S101 - S106, a diamond / 3C-SiC heterojunction field effect transistor with a P-type well region fabricated by depositing high (111)-oriented quasi-single crystal diamond can be prepared.
[0071] Among them, the thicknesses of the deposited metals (the first metal, the second metal, the third metal, and the fourth metal) can be set according to actual usage requirements. In the embodiment of the present application, the thicknesses of the metals are not specifically limited. As an example, the thickness of the first metal can be 20 nm, the thickness of the second metal can be 80 nm, the thickness of the third metal can be 20 nm, and the thickness of the fourth metal can be 80 nm.
[0072] It should be noted here that the above expressions of the first metal, the second metal, the third metal, and the fourth metal are only to distinguish that the two types of metals in the ohmic contact layer are different, and the two types of metals in the back metal contact layer are different. However, "the first metal or the second metal" and "the third metal or the fourth metal" can be the same. And the specific types of the first metal, the second metal, the third metal, and the fourth metal can be selected according to the type of the field effect transistor to be fabricated. In the embodiment of the present application, the types of the metals are not specifically limited. For example, the first metal and the third metal can be selected from metals such as Ti / Ni, and the second metal and the fourth metal can be selected from metals such as Au / Al / Ti.
[0073] In the solution provided by the embodiment of the present application, since the P-type well region is fabricated by depositing high (111)-oriented quasi-single crystal diamond in the trench instead of using ion implantation, there is no need for high-temperature annealing treatment to repair the damaged lattice and activate the implanted ions. Therefore, the high-temperature annealing treatment is avoided, and the requirement for the high-temperature resistance performance of the field-effect transistor is reduced. Moreover, in the solution provided by the embodiment of the present invention, high (111)-oriented quasi-single crystal diamond with a bandgap width of 5.50 eV is used as the P-type well region material. Compared with 3C-SiC, which is commonly used as the P-type well region material and has a bandgap width of only 2.36 eV, it can effectively increase the turn-off voltage of the field-effect transistor, greatly reduce the occurrence of leakage current, and significantly improve the stability of the field-effect transistor in the off state. In addition, the critical breakdown electric field strength of diamond is higher than that of 3C-SiC. After replacing 3C-SiC with diamond as the P-type well region material, the field-effect transistor can withstand a higher voltage without breakdown, which can significantly improve the application of the field-effect transistor in high-voltage and high-power scenarios. Moreover, the thermal conductivity of diamond is as high as 2200 W / (m·K). Using it as the P-type well region material can enable the heat generated by the field-effect transistor to be quickly conducted away, improving the high-temperature resistance performance of the field-effect transistor.
[0074] Corresponding to the above preparation method of the diamond / 3C-SiC heterojunction field-effect transistor, the embodiment of the present application also provides a diamond / 3C-SiC heterojunction field-effect transistor. The diamond / 3C-SiC heterojunction field-effect transistor provided by the embodiment of the present application will be introduced below.
[0075] As Figure 4 shown, a diamond / 3C-SiC heterojunction field-effect transistor, prepared by the preparation method described in any of the above embodiments, may include:
[0076] a 3C-SiC substrate 401, a back metal contact layer 402, an n-type drift layer 403, a 3C-SiC buffer layer (located between the 3C-SiC substrate 401 and the n-type drift layer 403, Figure 4 not shown in the figure), a P-type well region 404, a depletion layer 405, a dielectric layer 406, an ohmic contact layer (including a drain 407 and a source 408), and a gate 409.
[0077] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising said element.
[0078] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the embodiment of the diamond / 3C-SiC heterojunction field effect transistor, since it is basically similar to the embodiment of the preparation method, the description is relatively simple. For the relevant parts, reference can be made to the partial description of the embodiment of the preparation method.
[0079] The above are only the preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are all included in the protection scope of the present invention.
Claims
1. A method for preparing a diamond / 3C-SiC heterojunction field effect transistor, characterized in that: The method comprises: epitaxially growing a 3C-SiC buffer layer and an n-type drift layer on the upper surface of the 3C-SiC substrate in sequence; Etching a preset number of parallel grooves on the upper surface of the n-type drift layer; A pulse bias enhanced MPCVD device is used to deposit high (111) oriented quasi-single crystal diamond in the groove to obtain a P-type well region, wherein the gas introduced during the deposition process includes: a gas ratio of CH4 gas greater than 0 and not more than 4%, an O2 gas greater than 0 and not more than 2%, an Ar gas of 5-10%, a B2H6 gas greater than 0 and not more than 2%, and 82-95% H2, the deposition temperature is 700-1000° C., the deposition pressure is 5 KPa-50 KPa, the pulse voltage is -50-200 V, and the pulse time is 10-100 s; growing a dielectric layer on a non-diamond array region on the upper surface of the n-type drift layer; Depositing a first metal and a second metal in sequence on the diamond array region in the upper surface of the n-type drift layer to obtain an ohmic contact layer, and depositing a third metal and a fourth metal in sequence on the lower surface of the 3C-SiC substrate to obtain a back metal contact layer; A gate is deposited on the upper surface of the dielectric layer to obtain a diamond / 3C-SiC heterojunction field effect transistor.
2. The method according to claim 1, characterized in that The B ion concentration in the highly (111) oriented quasi-single-crystalline diamond deposited in the groove is 1×10 18 / cm -3 ~1×10 20 / cm -3 .
3. The method according to claim 1, characterized in that The high (111) oriented quasi-single crystal diamond deposited in the groove has a diamond Raman characteristic peak when irradiated with an excitation light with a wavelength of 532nm.
4. The method according to claim 3, characterized in that The half-width of the diamond Raman characteristic peak is no more than 200 arcsec.
5. The method according to claim 4, characterized in that The half-maximum width of the diamond Raman characteristic peak is 50 or 100 arcsec.
6. The method according to claim 1, characterized in that The surface roughness of the upper surface of the high (111) oriented quasi-single-crystalline diamond deposited in the groove is less than 0.2 nm.
7. The method according to claim 1, characterized in that The 3C-SiC substrate has a carrier concentration of 1×10 18 / cm -3 ~1×10 20 / cm -3 The upper surface of an original 3C-SiC substrate with a size of 2 to 8 inches is polished to obtain a substrate with a crystal orientation of (111) on the upper surface, an inclination angle of 0 to 4°, and a surface roughness of less than 0.2 nm.
8. The method according to claim 1, characterized in that The thickness of the 3C-SiC buffer layer is greater than 0 and does not exceed 5 μm, the thickness of the n-type drift layer is 1 to 100 μm, and the carrier concentration of the 3C-SiC buffer layer is 1×10 18 / cm -3 ~8×10 18 / cm -3 , the carrier concentration of the n-type drift layer is 1×10 14 / cm -3 ~1×10 18 / cm -3 .
9. The method according to claim 1, characterized in that: The groove has a depth of 1 to 10 μm and an aspect ratio of 1 to 10; and / or, The thickness of the dielectric layer is 20 to 50 nm; and / or, The thickness of the first metal is 20 nm, the thickness of the second metal is 80 nm, the thickness of the third metal is 20 nm, and the thickness of the fourth metal is 80 nm; and / or, The thickness of the gate is 100 nm.
10. A diamond / 3C-SiC heterojunction field effect transistor, characterized in that: Prepared by the preparation method according to any one of claims 1 to 9.