Manufacturing method of sapphire GaN HEMT power chip

Abstract

The invention relates to a manufacturing method of a sapphire GaN HEMT (High Electron Mobility Transistor) power chip, which comprises a sapphire-based GaN epitaxy, an HEMT device structure is manufactured above the sapphire-based GaN epitaxy, a silicon substrate part corresponding to a source electrode and a drain electrode of the HEMT device structure is etched to block a conductive channel passing through the silicon substrate, an insulating material AlN with good thermal conductivity is deposited, and the GaN-based HEMT power chip is manufactured. A high-thermal-conductivity material is continuously deposited, so that the thermal conductivity and the mechanical strength of the chip are improved; the GaN HEMT power device has the advantages that the problem of stray capacitance and inductance caused by a traditional interconnection mode of a GaN HEMT power device and a driving module is solved, and the problems of reduction of high-frequency performance of a GaN device and various reliability caused by spike voltage / LC oscillation and the like caused by parasitism are solved. Meanwhile, the problems that a large area is occupied and the packaging cost is increased due to the fact that a traditional independent GaN HEMT-based power device is connected with the driving module are solved.

Description

Technical Field

[0001] The present invention relates to a manufacturing method of a sapphire GaN HEMT power chip. Background Art

[0002] Based on the large bandgap width of its material itself and the high switching frequency of the device, the gallium nitride-based high electron mobility transistor (GaN HEMT) can greatly improve the power density. Therefore, it has extremely broad application prospects in radio frequency and electronic power systems. In most cases, gallium nitride devices are fabricated on a dedicated GaN epitaxial substrate, and the peripheral control circuits are fabricated on a silicon substrate. Then, the gallium nitride devices and the control circuits are separately packaged and integrated together on a PCB board through interconnection, or the gallium nitride devices and the control circuits are directly interconnected and packaged together. Since the integration of the gallium nitride device and the control circuit is based on the interconnection of discrete GaN chips and Si driver chips, it occupies a large area, increases the packaging cost, and at the same time, the parasitic capacitance and inductance brought by this interconnection method are inevitable. Problems such as the spike voltage / LC oscillation brought by this parasitism will reduce the high-frequency performance of the gallium nitride device and cause various reliability problems. Summary of the Invention

[0003] The purpose of the present invention is to provide a manufacturing method of a sapphire GaN HEMT power chip to solve the problems mentioned in the above background art.

[0004] To solve the above technical problems, the technical solution provided by the present invention is: a manufacturing method of a sapphire GaN HEMT power chip, including sapphire-based GaN epitaxy. An HEMT device structure is fabricated above the sapphire-based GaN epitaxy. The silicon substrate part corresponding to the source and drain of the HEMT device structure is etched away to block the conductive channel through the silicon substrate, and an insulating material AlN with good thermal conductivity is deposited, and a high thermal conductivity material is continuously deposited to improve the thermal conductivity and mechanical strength of the chip;

[0005] Specifically, it includes the following steps: providing a substrate; forming a GaN HEMT power device and a driving module, and forming a first epitaxial layer and a second epitaxial layer; the GaN HEMT power device and the driving module are respectively formed in a first area and a second area on the substrate; the first epitaxial layer and the second epitaxial layer are formed between the driving module and the substrate, and the first epitaxial layer and the second epitaxial layer are sequentially formed on the substrate in a direction away from the substrate.

[0006] As a preferred solution, the first epitaxial layer is N+-type doped, N--type doped or N-type doped, and the second epitaxial layer is P+-type doped.

[0007] As a preferred solution, after forming the GaN HEMT power device and the drive module, and forming the first epitaxial layer and the second epitaxial layer, it further includes: forming a low-K dielectric layer and a metal interconnection layer.

[0008] As a preferred solution, forming the GaN HEMT power device and the drive module, and forming the first epitaxial layer and the second epitaxial layer specifically include:

[0009] A buffer layer, a channel layer, a barrier layer, and a patterned photoresist are sequentially formed on the substrate in a direction away from the substrate; the patterned photoresist covers the surface of the barrier layer in the first region; the patterned photoresist is used as a mask to etch the barrier layer, the channel layer, and the buffer layer in the second region, and an etching cavity is formed in the second region of the substrate; the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are formed; the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are sequentially formed in the etching cavity in a direction away from the substrate; and the height of the third epitaxial layer is flush with the height of the barrier layer; the first drain, the first gate, the first source, and the first passivation layer are formed; the second source, the second gate, the second drain, and the second passivation layer are formed.

[0010] As a preferred solution, forming the low-K dielectric layer and the metal interconnection layer specifically includes:

[0011] A low-K dielectric material layer is deposited on the top of the GaN HEMT power device and the drive module; the low-K dielectric material layer covers the tops of the first passivation layer, the second passivation layer, the second drain, the second gate, the second source, the first drain, the first gate, and the first source; the low-K dielectric material layer on the tops of the second drain, the second gate, the second source, the first drain, the first gate, and the second source is etched respectively to form a plurality of metal interconnection cavities; metal materials are filled in the plurality of metal interconnection cavities respectively, and the metal interconnection layer on the top of the second gate is connected to the metal interconnection layer on the top of the first source; the metal interconnection layer on the top of the second source is connected to the metal interconnection layer on the top of the first drain to form a metal interconnection layer.

[0012] The advantages of the present invention are as follows: It avoids the problems of parasitic capacitance and inductance brought by the interconnection method of traditional GaN HEMT power devices and drive modules, and problems such as peak voltage / LC oscillation brought by parasitics will reduce the high-frequency performance of gallium nitride devices and cause various reliability problems. At the same time, it avoids the interconnection of traditional discrete GaN HEMT power devices and drive modules, which occupies a large area and increases the packaging cost. Specific embodiments

[0013] The following uses specific embodiments to illustrate the present invention, which is not a limitation to the present invention.

[0014] Embodiment 1

[0015] Fabrication method of a sapphire GaN HEMT power chip, including sapphire-based GaN epitaxy, fabricating a HEMT device structure above the sapphire-based GaN epitaxy, etching away the silicon substrate part corresponding to the source and drain of the HEMT device structure to block the conductive channel through the silicon substrate, and depositing an insulating material AlN with good thermal conductivity, and continuing to deposit a high thermal conductivity material to improve the thermal conductivity and mechanical strength of the chip;

[0016] Specifically, it includes the following steps: providing a substrate; forming a GaN HEMT power device and a driving module, and forming a first epitaxial layer and a second epitaxial layer; the GaN HEMT power device and the driving module are respectively formed in a first area and a second area on the substrate; the first epitaxial layer and the second epitaxial layer are formed between the driving module and the substrate, and the first epitaxial layer and the second epitaxial layer are sequentially formed on the substrate in a direction away from the substrate.

[0017] As a preferred solution of this embodiment, the first epitaxial layer is N+-type doped, and the second epitaxial layer is P+-type doped.

[0018] As a preferred solution of this embodiment, after forming the GaN HEMT power device and the driving module, and forming the first epitaxial layer and the second epitaxial layer, it further includes: forming a low-K dielectric layer and a metal interconnect layer.

[0019] As a preferred solution of this embodiment, forming the GaN HEMT power device and the driving module, and forming the first epitaxial layer and the second epitaxial layer specifically includes:

[0020] Sequentially forming a buffer layer, a channel layer, a barrier layer and a patterned photoresist on the substrate in a direction away from the substrate; the patterned photoresist covers the surface of the barrier layer in the first area; using the patterned photoresist as a mask to etch the barrier layer, the channel layer and the buffer layer in the second area, forming an etching cavity in the second area of the substrate; forming a first epitaxial layer, a second epitaxial layer and a third epitaxial layer; the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are sequentially formed in the etching cavity in a direction away from the substrate; and the height of the third epitaxial layer is flush with the height of the barrier layer; forming a first drain, a first gate, a first source and a first passivation layer; forming a second source, a second gate and a second drain and a second passivation layer.

[0021] As a preferred solution of this embodiment, forming the low-K dielectric layer and the metal interconnect layer specifically includes:

[0022] Deposit a low-K dielectric material layer on the top of the GaN HEMT power device and the drive module; the low-K dielectric material layer covers the top of the first passivation layer, the second passivation layer, the second drain, the second gate, the second source, the first drain, the first gate, and the first source; etch the low-K dielectric material layer on the top of the second drain, the second gate, the second source, the first drain, the first gate, and the second source respectively to form a plurality of metal interconnect cavities; fill the metal material in the plurality of metal interconnect cavities respectively, and connect the metal interconnect layer on the top of the second gate with the metal interconnect layer on the top of the first source; connect the metal interconnect layer on the top of the second source with the metal interconnect layer on the top of the first drain to form a metal interconnect layer.

[0023] Embodiment 2

[0024] A manufacturing method of a sapphire GaN HEMT power chip, including sapphire-based GaN epitaxy, fabricating a HEMT device structure above the sapphire-based GaN epitaxy, etching away the silicon substrate portion corresponding to the source and drain of the HEMT device structure to block the conductive channel through the silicon substrate, and depositing a thermally conductive insulating material AlN and continuing to deposit a high thermal conductivity material to improve the thermal conductivity and mechanical strength of the chip;

[0025] Specifically, it includes the following steps: providing a substrate; forming a GaN HEMT power device and a drive module, and forming a first epitaxial layer and a second epitaxial layer; the GaN HEMT power device and the drive module are respectively formed in a first region and a second region on the substrate; the first epitaxial layer and the second epitaxial layer are formed between the drive module and the substrate, and the first epitaxial layer and the second epitaxial layer are sequentially formed on the substrate in a direction away from the substrate.

[0026] As a preferred solution of this embodiment, the first epitaxial layer is N-type doped, and the second epitaxial layer is P+-type doped.

[0027] As a preferred solution of this embodiment, after forming the GaN HEMT power device and the drive module, and forming the first epitaxial layer and the second epitaxial layer, it further includes: forming a low-K dielectric layer and a metal interconnect layer.

[0028] As a preferred solution of this embodiment, forming the GaN HEMT power device and the drive module, and forming the first epitaxial layer and the second epitaxial layer specifically includes:

[0029] A buffer layer, a channel layer, a barrier layer, and a patterned photoresist are sequentially formed on a substrate in a direction away from the substrate; the patterned photoresist covers the surface of the barrier layer in the first region; the patterned photoresist is used as a mask to etch the barrier layer, the channel layer, and the buffer layer in the second region, and an etching cavity is formed in the second region of the substrate; a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer are formed; the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are sequentially formed in the etching cavity in a direction away from the substrate; and the height of the third epitaxial layer is flush with the height of the barrier layer; a first drain, a first gate, a first source, and a first passivation layer are formed; a second source, a second gate, a second drain, and a second passivation layer are formed.

[0030] As a preferred solution of this embodiment, a low-K dielectric layer and a metal interconnect layer are formed, specifically including:

[0031] A low-K dielectric material layer is deposited on the top of the GaN HEMT power device and the driving module; the low-K dielectric material layer covers the tops of the first passivation layer, the second passivation layer, the second drain, the second gate, the second source, the first drain, the first gate, and the first source; the low-K dielectric material layer on the tops of the second drain, the second gate, the second source, the first drain, the first gate, and the second source is etched respectively to form a plurality of metal interconnect cavities; metal materials are filled in the plurality of metal interconnect cavities respectively, and the metal interconnect layer on the top of the second gate is connected to the metal interconnect layer on the top of the first source; the metal interconnect layer on the top of the second source is connected to the metal interconnect layer on the top of the first drain to form a metal interconnect layer.

[0032] Embodiment 3

[0033] A manufacturing method of a sapphire GaN HEMT power chip includes sapphire-based GaN epitaxy, manufacturing a HEMT device structure above the sapphire-based GaN epitaxy, etching off a part of the silicon substrate corresponding to the source and drain of the HEMT device structure to block the conductive channel passing through the silicon substrate, and depositing an insulating material AlN with good thermal conductivity and continuing to deposit a high thermal conductivity material to improve the thermal conductivity and mechanical strength of the chip.

[0034] Specifically, the following steps are included: providing a substrate; forming a GaN HEMT power device and a driving module, and forming a first epitaxial layer and a second epitaxial layer; the GaN HEMT power device and the driving module are respectively formed in the first region and the second region on the substrate; the first epitaxial layer and the second epitaxial layer are formed between the driving module and the substrate, and the first epitaxial layer and the second epitaxial layer are sequentially formed on the substrate in a direction away from the substrate.

[0035] As a preferred solution of this embodiment, the first epitaxial layer is N-type doped and the second epitaxial layer is P+-type doped.

[0036] As a preferred solution of this embodiment, after forming the GaN HEMT power device and the drive module, and forming the first epitaxial layer and the second epitaxial layer, it further includes: forming a low-K dielectric layer and a metal interconnection layer.

[0037] As a preferred solution of this embodiment, forming the GaN HEMT power device and the drive module, and forming the first epitaxial layer and the second epitaxial layer specifically includes:

[0038] A buffer layer, a channel layer, a barrier layer and a patterned photoresist are sequentially formed on the substrate in a direction away from the substrate; the patterned photoresist covers the surface of the barrier layer in the first region; the patterned photoresist is used as a mask to etch the barrier layer, the channel layer and the buffer layer in the second region, and an etching cavity is formed in the second region of the substrate; the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are formed; the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are sequentially formed in the etching cavity in a direction away from the substrate; and the height of the third epitaxial layer is flush with the height of the barrier layer; the first drain, the first gate, the first source and the first passivation layer are formed; the second source, the second gate, the second drain and the second passivation layer are formed.

[0039] As a preferred solution of this embodiment, forming the low-K dielectric layer and the metal interconnection layer specifically includes:

[0040] A low-K dielectric material layer is deposited on the top of the GaN HEMT power device and the drive module; the low-K dielectric material layer covers the tops of the first passivation layer, the second passivation layer, the second drain, the second gate, the second source, the first drain, the first gate and the first source; the low-K dielectric material layer on the tops of the second drain, the second gate, the second source, the first drain, the first gate and the second source is etched respectively to form a plurality of metal interconnection cavities; metal materials are filled in the plurality of metal interconnection cavities respectively, and the metal interconnection layer on the top of the second gate is connected to the metal interconnection layer on the top of the first source; the metal interconnection layer on the top of the second source is connected to the metal interconnection layer on the top of the first drain to form a metal interconnection layer.

[0041] Embodiment 4

[0042] A manufacturing method of a sapphire GaN HEMT power chip, including sapphire-based GaN epitaxy, manufacturing a HEMT device structure above the sapphire-based GaN epitaxy, etching away a part of the silicon substrate corresponding to the source and drain of the HEMT device structure to block the conductive channel through the silicon substrate, and depositing a thermally conductive insulating material AlN, and continuing to deposit a high thermal conductivity material to improve the thermal conductivity and mechanical strength of the chip;

[0043] Specifically, it includes the following steps: providing a substrate; forming a GaN HEMT power device and a driving module, and forming a first epitaxial layer and a second epitaxial layer; the GaN HEMT power device and the driving module are respectively formed in a first region and a second region on the substrate; the first epitaxial layer and the second epitaxial layer are formed between the driving module and the substrate, and the first epitaxial layer and the second epitaxial layer are sequentially formed on the substrate in a direction away from the substrate.

[0044] As a preferred solution of this embodiment, the first epitaxial layer is N+-type doped or N--type doped, and the second epitaxial layer is P+-type doped.

[0045] As a preferred solution of this embodiment, after forming the GaN HEMT power device and the driving module, and forming the first epitaxial layer and the second epitaxial layer, it further includes: forming a low-K dielectric layer and a metal interconnection layer.

[0046] As a preferred solution of this embodiment, forming the GaN HEMT power device and the driving module, and forming the first epitaxial layer and the second epitaxial layer specifically includes:

[0047] Sequentially forming a buffer layer, a channel layer, a barrier layer, and a patterned photoresist on the substrate in a direction away from the substrate; the patterned photoresist covers the surface of the barrier layer in the first region; using the patterned photoresist as a mask to etch the barrier layer, the channel layer, and the buffer layer in the second region of the substrate to form an etching cavity in the second region of the substrate; forming a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer; the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are sequentially formed in the etching cavity in a direction away from the substrate; and the height of the third epitaxial layer is flush with the height of the barrier layer; forming a first drain, a first gate, a first source, and a first passivation layer; forming a second source, a second gate, a second drain, and a second passivation layer.

[0048] As a preferred solution of this embodiment, forming the low-K dielectric layer and the metal interconnection layer specifically includes:

[0049] Depositing a low-K dielectric material layer on the top of the GaN HEMT power device and the driving module; the low-K dielectric material layer covers the tops of the first passivation layer, the second passivation layer, the second drain, the second gate, the second source, the first drain, the first gate, and the first source; respectively etching the low-K dielectric material layer on the tops of the second drain, the second gate, the second source, the first drain, the first gate, and the second source to form a plurality of metal interconnection cavities; respectively filling metal materials in the plurality of metal interconnection cavities, and respectively connecting the metal interconnection layer on the top of the second gate and the metal interconnection layer on the top of the first source; connecting the metal interconnection layer on the top of the second source and the metal interconnection layer on the top of the first drain to form a metal interconnection layer.

[0050] Embodiment 5

[0051] Method for fabricating a sapphire GaN HEMT power chip, including sapphire-based GaN epitaxy, fabricating a HEMT device structure above the sapphire-based GaN epitaxy, etching away a part of the silicon substrate corresponding to the source and drain of the HEMT device structure to block the conductive channel through the silicon substrate, and depositing an insulating material AlN with good thermal conductivity, and continuing to deposit a high thermal conductivity material to improve the thermal conductivity and mechanical strength of the chip;

[0052] Specifically, it includes the following steps: providing a substrate; forming a GaN HEMT power device and a driving module, and forming a first epitaxial layer and a second epitaxial layer; the GaN HEMT power device and the driving module are respectively formed in a first region and a second region on the substrate; the first epitaxial layer and the second epitaxial layer are formed between the driving module and the substrate, and the first epitaxial layer and the second epitaxial layer are sequentially formed on the substrate in a direction away from the substrate.

[0053] As a preferred solution of this embodiment, the first epitaxial layer is N-type doped or N+ doped, and the second epitaxial layer is P+ doped.

[0054] As a preferred solution of this embodiment, after forming the GaN HEMT power device and the driving module, and forming the first epitaxial layer and the second epitaxial layer, it further includes: forming a low-K dielectric layer and a metal interconnect layer.

[0055] As a preferred solution of this embodiment, forming the GaN HEMT power device and the driving module, and forming the first epitaxial layer and the second epitaxial layer specifically includes:

[0056] Sequentially forming a buffer layer, a channel layer, a barrier layer and a patterned photoresist on the substrate in a direction away from the substrate; the patterned photoresist covers the surface of the barrier layer in the first region; using the patterned photoresist as a mask to etch the barrier layer, the channel layer and the buffer layer in the second region to form an etching cavity in the second region of the substrate; forming a first epitaxial layer, a second epitaxial layer and a third epitaxial layer; the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are sequentially formed in the etching cavity in a direction away from the substrate; and the height of the third epitaxial layer is flush with the height of the barrier layer; forming a first drain, a first gate, a first source and a first passivation layer; forming a second source, a second gate and a second drain and a second passivation layer.

[0057] As a preferred solution of this embodiment, forming the low-K dielectric layer and the metal interconnect layer specifically includes:

[0058] Deposit a low-K dielectric material layer on the top of the GaN HEMT power device and the driver module; the low-K dielectric material layer covers the top of the first passivation layer, the second passivation layer, the second drain, the second gate, the second source, the first drain, the first gate, and the first source; etch the low-K dielectric material layer on the top of the second drain, the second gate, the second source, the first drain, the first gate, and the second source respectively to form a plurality of metal interconnect cavities; fill the plurality of metal interconnect cavities with metal materials respectively, and connect the metal interconnect layer on the top of the second gate with the metal interconnect layer on the top of the first source; connect the metal interconnect layer on the top of the second source with the metal interconnect layer on the top of the first drain to form a metal interconnect layer.

[0059] Example 6

[0060] A manufacturing method of a sapphire GaN HEMT power chip, including sapphire-based GaN epitaxy, fabricating a HEMT device structure above the sapphire-based GaN epitaxy, etching away the silicon substrate part corresponding to the source and drain of the HEMT device structure to block the conductive channel through the silicon substrate, and depositing a thermally conductive insulating material AlN and continuing to deposit a high thermal conductivity material to improve the thermal conductivity and mechanical strength of the chip;

[0061] Specifically, it includes the following steps: providing a substrate; forming a GaN HEMT power device and a driver module, and forming a first epitaxial layer and a second epitaxial layer; the GaN HEMT power device and the driver module are respectively formed in a first region and a second region on the substrate; the first epitaxial layer and the second epitaxial layer are formed between the driver module and the substrate, and the first epitaxial layer and the second epitaxial layer are sequentially formed on the substrate in a direction away from the substrate.

[0062] As a preferred solution of this embodiment, the first epitaxial layer is N+-type doped or N-type doped, and the second epitaxial layer is P+-type doped.

[0063] As a preferred solution of this embodiment, after forming the GaN HEMT power device and the driver module, and forming the first epitaxial layer and the second epitaxial layer, it further includes: forming a low-K dielectric layer and a metal interconnect layer.

[0064] As a preferred solution of this embodiment, forming the GaN HEMT power device and the driver module, and forming the first epitaxial layer and the second epitaxial layer specifically includes:

[0065] A buffer layer, a channel layer, a barrier layer, and a patterned photoresist are sequentially formed on a substrate in a direction away from the substrate; the patterned photoresist covers the surface of the barrier layer in a first region; the patterned photoresist is used as a mask to etch the barrier layer, the channel layer, and the buffer layer in a second region, and an etching cavity is formed in the second region of the substrate; a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer are formed; the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are sequentially formed in the etching cavity in a direction away from the substrate; and the height of the third epitaxial layer is flush with the height of the barrier layer; a first drain, a first gate, a first source, and a first passivation layer are formed; a second source, a second gate, a second drain, and a second passivation layer are formed.

[0066] As a preferred solution of this embodiment, a low-K dielectric layer and a metal interconnect layer are formed, specifically including:

[0067] A low-K dielectric material layer is deposited on the top of the GaN HEMT power device and the driving module; the low-K dielectric material layer covers the tops of the first passivation layer, the second passivation layer, the second drain, the second gate, the second source, the first drain, the first gate, and the first source; the low-K dielectric material layer on the tops of the second drain, the second gate, the second source, the first drain, the first gate, and the second source is respectively etched to form a plurality of metal interconnect cavities; metal materials are respectively filled in the plurality of metal interconnect cavities, and the metal interconnect layer on the top of the second gate is respectively connected to the metal interconnect layer on the top of the first source; the metal interconnect layer on the top of the second source is connected to the metal interconnect layer on the top of the first drain to form a metal interconnect layer.

[0068] When the present invention is specifically implemented, the GaN HEMT power device and the driving module are formed on the same substrate, and a first epitaxial layer and a second epitaxial layer are sequentially formed between the driving module and the substrate in a direction away from the substrate; since the GaN HEMT power device and the driving module are formed on the same substrate. The problems of parasitic capacitance and inductance brought by the traditional interconnection method of the GaN HEMT power device and the driving module are avoided, and problems such as peak voltage / LC oscillation brought by parasitics will reduce the high-frequency performance of the gallium nitride device and cause various reliability problems. At the same time, the problem of occupying a large area and increasing the packaging cost due to the traditional interconnection of discrete GaN HEMT power devices and driving modules is avoided. Since the first epitaxial layer and the second epitaxial layer are sequentially formed between the driving module and the substrate in a direction away from the substrate, it is equivalent to isolating between the driving module and the substrate, and greatly reducing the back-gate problem that may occur in the high-voltage application of the GaN HEMT power device.

[0069] As described above, it is only the preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution and inventive concept of the present invention, makes equivalent substitutions or changes, and should be covered within the protection scope of the present invention.

Claims

1. A method for manufacturing a sapphire GaN HEMT power chip, characterized in that: It includes sapphire-based GaN epitaxy, a HEMT device structure is fabricated on the sapphire-based GaN epitaxy, a silicon substrate portion corresponding to the source and drain of the HEMT device structure is etched away to block the conductive path through the silicon substrate, and an insulating material AlN with good thermal conductivity is deposited, and a high thermal conductivity material is continuously deposited to improve the thermal conductivity and mechanical strength of the chip; The method specifically includes the following steps: providing a substrate; forming a GaN HEMT power device and a driving module, and forming a first epitaxial layer and a second epitaxial layer; the GaN HEMT power device and the driving module are formed in a first region and a second region on the substrate respectively; the first epitaxial layer and the second epitaxial layer are formed between the driving module and the substrate, and the first epitaxial layer and the second epitaxial layer are formed on the substrate in sequence in a direction away from the substrate.

2. The method for manufacturing a sapphire GaN HEMT power chip according to claim 1, characterized in that: The first epitaxial layer is N+ doped, N- doped or N- doped, and the second epitaxial layer is P+ doped.

3. The method for manufacturing a sapphire GaN HEMT power chip according to claim 1, characterized in that: After forming the GaN HEMT power device and the driving module, and forming the first epitaxial layer and the second epitaxial layer, the method further includes: forming a low-K dielectric layer and a metal interconnection layer.

4. The method for manufacturing a sapphire GaN HEMT power chip according to claim 3, characterized in that: Forming GaN HEMT power devices and driver modules, and forming the first epitaxial layer and the second epitaxial layer, specifically including: A buffer layer, a channel layer, a barrier layer and a patterned photoresist are sequentially formed on a substrate in a direction away from the substrate; the patterned photoresist covers the surface of the barrier layer in region No. 1; the barrier layer, the channel layer and the buffer layer in region No. 2 are etched using the patterned photoresist as a mask to form an etching cavity in region No. 2 of the substrate; a No. 1 epitaxial layer, a No. 2 epitaxial layer and a No. 3 epitaxial layer are formed sequentially in the etching cavity in a direction away from the substrate; and the height of the No. 3 epitaxial layer is flush with the height of the barrier layer; a No. 1 drain, a No. 1 gate, a No. 1 source and a No. 1 passivation layer are formed; a No. 2 source, a No. 2 gate, a No. 2 drain and a No. 2 passivation layer are formed.

5. The method for manufacturing a sapphire GaN HEMT power chip according to claim 4, characterized in that: Forming a low-K dielectric layer and a metal interconnect layer, specifically including: A low-K dielectric material layer is deposited on the top of the GaN HEMT power device and the driving module; the low-K dielectric material layer covers the top of the No. 1 passivation layer, the No. 2 passivation layer, the No. 2 drain, the No. 2 gate, the No. 2 source, the No. 1 drain, the No. 1 gate and the No. 1 source; the low-K dielectric material layer on the top of the No. 2 drain, the No. 2 gate, the No. 2 source, the No. 1 drain, the No. 1 gate and the No. 2 source is etched respectively to form a number of metal interconnection cavities; metal materials are filled in the several metal interconnection cavities respectively, and the metal interconnection layer on the top of the No. 2 gate is connected to the metal interconnection layer on the top of the No. 1 source respectively; the metal interconnection layer on the top of the No. 2 source is connected to the metal interconnection layer on the top of the No. 1 drain to form a metal interconnection layer.