Thin film transistor, preparation method thereof and array substrate
By adopting stacked active layer structure and energy density gradient technology in laser annealing treatment in thin film transistors, the problem that the optimal process window requirements for different active layer materials are difficult to meet is solved, and the device performance is improved and consistency is achieved.
Patent Information
- Application Number
- CN202510342173.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-21
- Publication Date
- 2025-06-17
AI Technical Summary
The prior art is difficult to meet the optimal process window requirements for different active layer materials at the same time, resulting in the failure of device performance to achieve an ideal state.
By adopting a stacked active layer structure in the thin film transistor, sub-active layers are arranged layer by layer, and the energy density gradient processing is achieved in the laser annealing process, so that each layer of material can be annealed within its optimal process window.
The active layers of different materials are achieved at the same time in a laser annealing process, which improves the overall performance and performance consistency of the device and shortens the post-processing time.
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Figure CN120166735A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technologies, and particularly to a thin film transistor, a preparation method thereof, and an array substrate. Background Art
[0002] In the development process of thin film transistor (TFT) technology, the optimization of the active layer material has always been the focus of research. Common active layer materials include amorphous silicon (a-Si), polycrystalline silicon (poly-Si), and metal oxide semiconductors (such as IGZO, IZO, etc.). However, with the development of display technologies towards high resolution, high stability, and flexibility, the active layer of a single material gradually becomes difficult to meet diverse application requirements, while the thin film transistor with multiple active layers exhibits more excellent electrical and optical properties.
[0003] In the actual preparation process, the optimal process parameters of different active layer materials are not the same, but common post-treatment methods (for example, overall annealing) usually can only process the device as a whole, and cannot perform differential treatment for different active layer materials, thus it is difficult to simultaneously meet the optimal process window requirements of multiple active layer materials and results in the device performance not reaching the ideal state. Summary of the Invention
[0004] The main purpose of the present application is to provide a thin film transistor, a preparation method thereof, and an array substrate, so as to realize that in a single laser annealing treatment, the active layers of different materials in the thin film transistor are simultaneously post-treated within their respective optimal process windows, thereby improving the overall performance of the device.
[0005] To achieve the above purpose, an embodiment of the present application provides a method for preparing a thin film transistor, including the following steps:
[0006] Successively prepare a gate electrode, an insulating layer, and a stacked active layer, wherein the stacked active layer includes a plurality of sub-active layers, and the laser treatment energy density of each sub-active layer gradually increases from the side close to the insulating layer to the side far from the insulating layer;
[0007] Perform laser annealing treatment on the stacked active layer;
[0008] Prepare a source electrode and a drain electrode to obtain a thin film transistor.
[0009] An embodiment of the present application further provides a thin film transistor, which is obtained by the thin film transistor preparation method as described above.
[0010] An embodiment of the present application further provides an array substrate, which includes the thin film transistor as described above, or a thin film transistor obtained by the thin film transistor preparation method as described above.
[0011] One or more technical solutions proposed in the embodiments of the present application have at least the following technical effects: A method for manufacturing a thin film transistor is provided. First, a gate electrode, an insulating layer, and a stacked active layer are sequentially manufactured. The stacked active layer includes a plurality of sub-active layers, and the laser treatment energy density of each sub-active layer gradually increases from the side close to the insulating layer to the side far from the insulating layer. Second, a laser annealing treatment is performed on the stacked active layer; since there is an energy attenuation characteristic in the transmission of laser energy in the active layer, in the embodiments of the present application, the sub-active layer that receives a higher laser energy density in the stacked active layer is arranged on the top layer (i.e., the side far from the insulating layer), so as to receive a laser annealing treatment with a higher laser energy density; as the laser is transmitted layer by layer, the laser energy gradually attenuates, so that the sub-active layer on the bottom layer (i.e., the side close to the insulating layer) can be annealed at a lower laser energy density, avoiding performance degradation or structural damage caused by excessive energy. Finally, a source electrode and a drain electrode are manufactured to obtain a thin film transistor. Through the position setting of the sub-active layers in the stacked active layer in the embodiments of the present application, a gradient processing of the energy density in a single laser annealing treatment is realized, so that each layer of material can complete annealing within its optimal process window, thereby giving full play to their respective advantages. Compared with the conventional overall annealing or other uniform processing methods, this method not only significantly shortens the post-processing time of the active layer, but also improves the performance consistency of the entire device. Brief Description of the Drawings
[0012] Figure 1 It is a schematic flowchart of the method for manufacturing a thin film transistor according to the solution of the embodiment of the present application.
[0013] The realization of the purpose, functional features, and advantages of the present application will be further described in conjunction with the embodiments with reference to the drawings. Detailed Embodiments
[0014] To make the purpose, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below. Those not specified in the embodiments are carried out according to conventional conditions or conditions recommended by the manufacturer. The reagents or instruments not specified in the manufacturer are all conventional products that can be obtained through commercial purchase.
[0015] Hereinafter, embodiments of the thin film transistor, its manufacturing method, and the array substrate of the present application specifically disclosed will be described in detail with appropriate reference to the drawings. However, there may be cases where unnecessary detailed descriptions are omitted. For example, there are cases where detailed descriptions of well-known matters and repeated descriptions of actually identical structures are omitted. This is to avoid the following description from becoming unnecessarily lengthy and to facilitate the understanding of those skilled in the art. In addition, the drawings and the following description are provided for those skilled in the art to fully understand the present application and are not intended to limit the subject matter described in the claims.
[0016] The "ranges" disclosed in this application are defined in the form of a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, and the selected lower limit and upper limit define the boundaries of a particular range. The ranges defined in this way can include the end values or not include the end values, and can be combined arbitrarily, that is, any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60-120 and 80-110 are listed for a specific parameter, ranges of 60-110 and 80-120 are also contemplated. In addition, if the minimum range values 1 and 2 are listed, and if the maximum range values 3, 4, and 5 are listed, the following ranges are all contemplated: 1-3, 1-4, 1-5, 2-3, 2-4, and 2-5. In this application, unless otherwise stated, the numerical range "a-b" represents an abbreviated representation of any real number combination between a and b, where a and b are both real numbers. For example, the numerical range "0-5" means that all real numbers between "0-5" are fully listed herein, and "0-5" is only an abbreviated representation of these numerical combinations. In addition, when stating that a certain parameter is an integer ≥2, it is equivalent to disclosing that the parameter is, for example, the integers 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.
[0017] If there is no special instruction, all embodiments and optional embodiments of this application can be combined with each other to form new technical solutions.
[0018] If there is no special instruction, all technical features and optional technical features of this application can be combined with each other to form new technical solutions.
[0019] If there is no special instruction, all steps of this application can be carried out in sequence or randomly, preferably in sequence. For example, the method includes steps (a) and (b), which means that the method can include steps (a) and (b) carried out in sequence, or can also include steps (b) and (a) carried out in sequence. For example, when it is mentioned that the method may further include step (c), it means that step (c) can be added to the method in any order. For example, the method can include steps (a), (b), and (c), or can also include steps (a), (c), and (b), or can also include steps (c), (a), and (b), etc.
[0020] If there is no special instruction, the "including" and "comprising" mentioned in this application mean open-ended or can also be closed-ended. For example, "including" and "comprising" can mean that other components not listed can also be included or comprised, or can only include or comprise the listed components.
[0021] Unless otherwise specified, the term "or" is inclusive in this application. For example, the phrase "A or B" means "A, B, or both A and B". More specifically, any of the following conditions satisfies the condition "A or B": A is true (or exists) and B is false (or does not exist); A is false (or does not exist) and B is true (or exists); or both A and B are true (or exist).
[0022] To make the above objects, features, and advantages of this application more apparent and understandable, the technical solutions of this application will be further described below in conjunction with the accompanying drawings and embodiments. However, this application is not limited to the listed embodiments and should also include any other well-known changes within the scope of the rights claimed in this application.
[0023] As used herein, the term "one embodiment" or "embodiment" refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. The appearances of "in one embodiment" in different places in this specification do not all refer to the same embodiment, nor are they separate or alternative embodiments that are mutually exclusive of other embodiments.
[0024] To better understand the technical solutions of this application, the following will be described in detail in conjunction with the drawings of the specification and specific implementation manners.
[0025] In conventional technologies, the optimal process parameters of different active layer materials are not the same. However, common post-treatment methods (e.g., overall annealing) usually can only process the device as a whole and cannot perform differential processing for different active layer materials, making it difficult to simultaneously meet the optimal process window requirements of multiple active layer materials and resulting in the device performance not reaching the ideal state.
[0026] In the embodiment of the present application, first, a gate electrode, an insulating layer, and a stacked active layer are sequentially prepared. The stacked active layer includes a plurality of sub-active layers, and the laser processing energy density of each sub-active layer gradually increases from the side close to the insulating layer to the side far from the insulating layer. Secondly, a laser annealing treatment is performed on the stacked active layer; since there is an energy attenuation characteristic in the transmission of laser energy in the active layer, in the embodiment of the present application, the sub-active layer that receives a higher laser energy density in the stacked active layer is arranged on the top layer (i.e., the side far from the insulating layer), so as to receive a laser annealing treatment with a higher laser energy density; as the laser is transmitted layer by layer, the laser energy gradually attenuates, so that the sub-active layer at the bottom layer (i.e., the side close to the insulating layer) can be annealed at a lower laser energy density, avoiding performance degradation or structural damage caused by excessive energy. Finally, a source electrode and a drain electrode are prepared to obtain a thin film transistor. By setting the positions of the sub-active layers in the stacked active layer in the embodiment of the present application, a gradient processing of the energy density in a single laser annealing treatment is realized, so that each layer of material can complete annealing within its optimal process window, thereby giving full play to their respective advantages. Compared with the conventional overall annealing or other uniform processing methods, this method not only significantly shortens the post-processing time of the active layer, but also improves the performance consistency of the entire device.
[0027] In the first aspect of the embodiment of the present application, a method for manufacturing a thin film transistor is provided. Referring to Figure 1 , the method includes the following steps:
[0028] Step S10: Sequentially prepare a gate electrode, an insulating layer, and a stacked active layer, where the stacked active layer includes a plurality of sub-active layers, and the laser processing energy density of each sub-active layer gradually increases from the side close to the insulating layer to the side far from the insulating layer.
[0029] In a feasible embodiment, a gate electrode is prepared, an insulating layer is prepared on one side surface of the gate electrode, and a stacked active layer is prepared on the side surface of the insulating layer far from the gate electrode. The stacked active layer includes a plurality of sub-active layers. Compared with a single-layer active layer, the stacked active layer includes a plurality of sub-active layers, so the performance can be optimized through the combination of different materials. For example, by optimizing the layer interface and material properties, the interface defect density can be reduced, and the generation of defect states such as oxygen vacancies can be reduced, so as to better adapt to different application scenarios.
[0030] Optionally, the laser processing energy density of each sub-active layer gradually increases from the side close to the insulating layer to the side far from the insulating layer. The sub-active layer on the side far from the insulating layer is located at the top layer of the device during the laser annealing process and thus receives the strongest laser energy. Therefore, in the embodiments of the present application, the sub-active layer with the highest required laser processing energy density is set here. As the laser propagates through each sub-active layer, the laser energy gradually attenuates. Therefore, the sub-active layer at the bottom layer (i.e., the side close to the insulating layer) can be annealed at a lower laser energy density, avoiding performance degradation or structural damage caused by excessive energy. Through the position setting of the sub-active layers in the stacked active layer, a gradient processing of the energy density in a single laser annealing process is achieved, enabling each layer of material to complete annealing within its optimal process window, thereby fully exerting their respective advantages.
[0031] Optionally, each sub-active layer can be sequentially prepared on the side surface of the insulating layer far from the gate electrode, where the laser processing energy density of the sub-active layer with a relatively early preparation sequence is lower than that of the sub-active layer with a later preparation sequence.
[0032] Optionally, the stacked active layer includes a first sub-active layer and a second sub-active layer prepared in sequence, and the laser processing energy density of the first sub-active layer is lower than that of the second sub-active layer.
[0033] Optionally, the laser processing energy density refers to the laser processing energy density within the optimal process window of the sub-active layer and can enable the sub-active layer to achieve optimal performance.
[0034] In a feasible embodiment, the material of the gate electrode includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium, cobalt, and neodymium-doped aluminum. The gate electrode is one of the core components of the thin-film transistor, and its main function is to apply a voltage to generate an electric field, thereby controlling the conductivity of the active layer and realizing the turn-on and turn-off of the device.
[0035] Optionally, the thickness of the gate electrode is 100 - 500 nm; for example, the thickness of the gate electrode is 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, etc. If the gate electrode is too thick, it may cause an increase in the overall size of the device, increasing the material cost and preparation time. In addition, the too-thick gate electrode may also generate relatively large stress during the thermal expansion process, resulting in film cracking or peeling from the substrate. If the gate electrode is too thin, it may lead to an increase in resistivity, affecting the uniform distribution of the electric field, thereby reducing the switching speed and performance of the device. In addition, the too-thin gate electrode may also be unable to effectively block diffusion, resulting in an interaction between the electrode material and the active layer or the insulating layer, affecting the device stability. Therefore, in the embodiments of the present application, the thickness of the gate electrode is determined to be 100 - 500 nm.
[0036] Optionally, the gate electrode can be prepared by magnetron sputtering.
[0037] Exemplarily, the gate electrode is formed by direct current magnetron sputtering of aluminum doped with neodymium (Al:Nd), where the sputtering power is 50 - 150 w, the sputtering atmosphere is Ar gas, and the working pressure is 0.5 - 1.5 mTorr.
[0038] In a feasible embodiment, the material of the insulating layer includes at least one of silicon dioxide, silicon nitride, aluminum oxide, and aluminum oxide doped with neodymium. The insulating layer is located between the gate electrode and the active layer, and its main function is to prevent current from directly flowing from the gate electrode to the active layer, while allowing the electric field to pass through to adjust the conductivity of the active layer.
[0039] Optionally, the thickness of the insulating layer is 100 - 300 nm; for example, the thickness of the insulating layer is 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, etc. If the insulating layer is too thick, it may increase the parasitic capacitance of the device, reduce the switching speed, and may lead to the complication of the manufacturing process and an increase in production cost. In addition, the too thick insulating layer may also undergo electrical breakdown under high voltage, affecting the reliability of the device. If the insulating layer is too thin, it may not effectively block charge injection, resulting in an increase in leakage current and a reduction in the switching ratio of the device. In addition, the thin insulating layer may be etched or damaged during the process, affecting the electrical performance of the device. Therefore, the embodiments of the present application determine that the thickness of the insulating layer is 100 - 300 nm.
[0040] Exemplarily, an anodization process is used to grow aluminum oxide doped with neodymium (Al2O3:Nd) on the gate electrode (Al:Nd) as the insulating layer.
[0041] In a feasible embodiment, the material of the sub-active layer includes at least one of zinc oxide, indium oxide, gallium oxide, indium zinc oxide, zinc tin oxide, zirconium indium oxide, indium gallium zinc oxide, indium hafnium zinc oxide, and indium silicon zinc oxide.
[0042] Exemplarily, the stacked active layer includes a first sub-active layer close to the insulating layer and a second sub-active layer far from the insulating layer; the material of the first sub-active layer is indium zinc oxide (IZO), and the material of the second sub-active layer is indium gallium zinc oxide (IGZO).
[0043] Exemplarily, the first sub-active layer IZO and the second sub-active layer IGZO are sequentially deposited on the insulating layer by radio frequency magnetron sputtering, where the sputtering power is 50 - 150 w, the sputtering atmosphere is Ar gas, and the working pressure is 2.5 - 4.5 mTorr; the indium-to-zinc molar ratio of the IZO target used is 1:4, and the gallium-to-indium-to-zinc molar ratio of the IGZO target used is 1:1:2.
[0044] In a feasible embodiment, the thickness of the sub-active layer is 10 - 30 nm; for example, the thickness of the sub-active layer is 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, etc.
[0045] In a feasible embodiment, the thickness of the stacked active layer is 20 - 80 nm; for example, the thickness of the stacked active layer is 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, etc. If the active layer is too thick, it may increase the parasitic capacitance of the device, reduce the mobility, and may cause the carrier transport path to become longer, increasing the resistance. In addition, the too-thick active layer may form a polycrystalline structure during the annealing process, increasing the density of interface defect states and affecting the stability and uniformity of the device. If the active layer is too thin, it may lead to insufficient carrier concentration, a positive shift in the threshold voltage, and a reduction in the on-state current of the device. In addition, the too-thin active layer may also be affected by back-channel scattering, resulting in a sharp drop in mobility and a reduction in the on-off ratio. Therefore, the embodiments of the present application determine that the thickness of the stacked active layer is 20 - 80 nm; and / or, the thickness of the sub-active layer is 10 - 30 nm.
[0046] Step S20, performing laser annealing treatment on the stacked active layer;
[0047] In a feasible embodiment, the sample is placed on a laser processing platform, and laser annealing treatment is performed on the stacked active layer.
[0048] In a feasible embodiment, the stacked active layer is subjected to laser annealing treatment by excimer laser. Excimer laser is a pulsed laser based on a mixture of inert gas and halogen gas. Its working principle is to excite gas molecules through an electron beam, causing them to jump from the excited state to the ground state and release high-energy ultraviolet light. Its ground-state molecules are extremely unstable and usually decompose into free particles rapidly within the vibrational relaxation time, while the excited state is relatively stable and decays in the form of radiation. This characteristic enables the excimer laser to have the characteristics of high gain, short pulse, and high energy output. Due to the high pulse energy and short wavelength (usually in the ultraviolet band) of the excimer laser, its photon energy is relatively high, which can efficiently interact with the material and avoid the accumulation of thermal effects. When this high-energy ultraviolet light penetrates the material, it will gradually attenuate due to the absorption and scattering of the material, thereby forming an energy gradient inside the material. Compared with other laser processing techniques (such as continuous-wave laser or long-pulse laser), the pulse width of the excimer laser is extremely short (usually at the nanosecond level), and the energy is released rapidly, enabling the material to be processed in a short time without causing the material to overheat. This characteristic enables the excimer laser to achieve the optimal performance optimization of different materials through one laser annealing treatment when processing the stacked active layer.
[0049] In one embodiment, the laser energy of the laser annealing is 100-180 mJ / cm 2 ; For example, the laser energy for laser annealing is 100mJ / cm 2 、110mJ / cm 2 、120mJ / cm 2 、130mJ / cm 2 、140mJ / cm 2 、150mJ / cm 2 、160mJ / cm 2 、170mJ / cm 2 、180mJ / cm 2 Etc. If the laser energy is too high, it may cause overheating of the active layer material, which may cause structural damage or lattice distortion of the material, increase the defect state density, and thus reduce the mobility and switching performance of the device. In addition, too high energy may also cause excessive evaporation of the material surface, affecting the uniformity and thickness control of the film. When the laser energy is insufficient, the carriers in the active layer cannot be effectively activated, resulting in an unclear annealing effect and an inability to fully repair defect states in the material, such as oxygen vacancies. This will reduce the mobility and switching ratio of the device, affecting the overall performance. Therefore, the embodiment of the present application determines that the laser energy for laser annealing is 100 to 180 mJ / cm 2 .
[0050] In one feasible embodiment, the laser pulse frequency of laser annealing is 4 to 15 Hz; for example, the laser pulse frequency is 4 Hz, 5 Hz, 6 Hz, 7 Hz, 8 Hz, 9 Hz, 10 Hz, 11 Hz, 12 Hz, 13 Hz, 14 Hz, 15 Hz, etc. If the pulse frequency is too high, it may cause the material to absorb too much energy in a short period of time, and there is no time to dissipate the heat, thereby causing local overheating and thermal damage. This heat accumulation effect may cause structural degradation of the material, increase the interface defect density, and reduce the stability and reliability of the device. If the pulse frequency is too low, the heat treatment time of the material is extended, which may lead to uneven energy distribution and affect the annealing effect. In addition, a pulse frequency that is too low may not be able to complete an effective annealing process in a short period of time, prolong the process time, and reduce production efficiency. Therefore, the embodiment of the present application determines that the laser pulse frequency of laser annealing is 4 to 15 Hz.
[0051] In one feasible implementation, the number of laser pulses for laser annealing is 8 to 20; for example, the number of laser pulses is 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, etc. If the number of laser pulses is too many, the material may repeatedly undergo heating and cooling processes, increasing the risk of thermal stress and structural damage. This may cause the lattice distortion and defect state density of the material to increase, thereby reducing the electrical properties of the device. If the number of laser pulses is insufficient, the annealing treatment is insufficient and the crystallinity and electrical properties of the material cannot be effectively improved. This may cause the mobility and switching ratio of the device to fail to reach the ideal level, affecting the overall performance of the device. Therefore, the embodiment of the present application determines that the number of laser pulses for laser annealing is 8 to 20.
[0052] Step S30, preparing a source electrode and a drain electrode to obtain a thin film transistor.
[0053] In a feasible embodiment, a source electrode and a drain electrode are prepared on the surface of the laminated active layer after the retreat process to obtain a thin film transistor. The source electrode and the drain electrode are two electrodes of the thin film transistor, which respectively define the inflow and outflow channels of the current. They are usually made of metal with good conductivity. This structure can effectively prevent the metal from diffusing into the active layer, thereby improving the stability of the device.
[0054] Alternatively, the source and / or drain may be fabricated by magnetron sputtering.
[0055] In one possible embodiment, the material of the source electrode includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt.
[0056] In one possible embodiment, the material of the drain electrode includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt.
[0057] Exemplarily, Al electrodes are deposited as source and drain electrodes on the stacked active layer after laser annealing by a vacuum magnetron sputtering apparatus, wherein the sputtering power is 50-150W, the sputtering atmosphere is Ar gas, and the working gas pressure is 0.5-1.5mTorr.
[0058] In this embodiment, first, a gate electrode, an insulating layer, and a stacked active layer are sequentially fabricated. The stacked active layer includes a plurality of sub-active layers, and the laser processing energy density of each sub-active layer gradually increases from the side close to the insulating layer to the side far from the insulating layer. Secondly, a laser annealing treatment is performed on the stacked active layer. Since there is an energy attenuation characteristic in the transmission of laser energy in the active layer, in the stacked active layer of this application embodiment, the sub-active layer that receives a higher laser energy density is arranged on the top layer (i.e., the side far from the insulating layer), so as to receive a laser annealing treatment with a higher laser energy density. As the laser is transmitted layer by layer, the laser energy gradually attenuates, enabling the sub-active layer at the bottom layer (i.e., the side close to the insulating layer) to be annealed at a lower laser energy density, avoiding performance degradation or structural damage caused by excessive energy. Finally, a source electrode and a drain electrode are fabricated to obtain a thin-film transistor. Through the position setting of the sub-active layers in the stacked active layer in the embodiment of this application, a gradient processing of the energy density in a single laser annealing treatment is realized, enabling each layer of material to complete annealing within its optimal process window, thereby fully exerting their respective advantages. Compared with conventional overall annealing or other uniform processing methods, this method not only significantly shortens the post-processing time of the active layer but also improves the performance consistency of the entire device.
[0059] In the second aspect of the embodiment of this application, a thin-film transistor is further provided, which is fabricated by the above thin-film transistor fabrication method.
[0060] The thin-film transistor provided in the embodiment of this application can, in a single laser annealing treatment, enable the active layers of different materials in the thin-film transistor to be post-processed simultaneously within their respective optimal process windows, improving the overall performance of the device. Compared with the prior art, the beneficial effects of the thin-film transistor provided in the embodiment of this application are the same as those of the thin-film transistor fabrication method provided in the above embodiment, and other technical features in the thin-film transistor are the same as those disclosed in the above embodiment method, which will not be elaborated here.
[0061] In the third aspect of the embodiment of this application, an array substrate is further provided, which includes a thin-film transistor fabricated by the above thin-film transistor fabrication method.
[0062] The array substrate provided in the embodiment of this application can, in a single laser annealing treatment, enable the active layers of different materials in the thin-film transistors included therein to be post-processed simultaneously within their respective optimal process windows, improving the overall performance of the device. Compared with the prior art, the beneficial effects of the array substrate provided in the embodiment of this application are the same as those of the thin-film transistor fabrication method provided in the above embodiment, and other technical features in the array substrate are the same as those disclosed in the above embodiment method, which will not be elaborated here.
[0063] The above are only the preferred embodiments of the present application, and do not limit the patent scope of the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the patent protection scope of the present application.
Claims
1. A method for preparing a thin film transistor, characterized in that: The method comprises the following steps: Sequentially preparing a gate electrode, an insulating layer and a stacked active layer, wherein the stacked active layer includes a plurality of sub-active layers, and the laser processing energy density of each of the sub-active layers gradually increases from a side close to the insulating layer to a side far from the insulating layer; Performing laser annealing on the stacked active layer; A source electrode and a drain electrode are prepared to obtain a thin film transistor.
2. The method for preparing a thin film transistor according to claim 1, wherein: The step of performing laser annealing on the stacked active layer comprises: The stacked active layer is subjected to laser annealing treatment by using an excimer laser.
3. The method for preparing a thin film transistor according to claim 1 or 2, characterized in that: The laser energy of the laser annealing is 100-180 mJ / cm 2 , the laser pulse frequency is 4 to 15 Hz, and the number of laser pulses is 8 to 20.
4. The method for preparing a thin film transistor according to claim 1, wherein: The thickness of the laminated active layer is 20 to 80 nm; And / or, the thickness of the sub-active layer is 10-30 nm.
5. The method for preparing a thin film transistor according to claim 1, wherein: The material of the sub-active layer includes at least one of zinc oxide, indium oxide, gallium oxide, indium zinc oxide, zinc tin oxide, zirconium indium oxide, indium gallium zinc oxide, indium hafnium zinc oxide and indium silicon zinc oxide.
6. The method for preparing a thin film transistor according to claim 1, wherein: The material of the gate electrode includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium, cobalt and neodymium-doped aluminum; And / or, the material of the source electrode includes: at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt; And / or, the material of the drain electrode includes at least one of titanium, aluminum, copper, nickel, iridium, rhodium, ruthenium, platinum, gold, silver, palladium and cobalt.
7. The method for preparing a thin film transistor according to claim 1, wherein: The material of the insulating layer includes at least one of silicon dioxide, silicon nitride, aluminum oxide and neodymium-doped aluminum oxide.
8. The method for preparing a thin film transistor according to claim 1, wherein: At least one of the gate electrode, the stacked active layer, the source electrode and the drain electrode is prepared by magnetron sputtering.
9. A thin film transistor, characterized in that: The thin film transistor is manufactured by the thin film transistor manufacturing method according to any one of claims 1 to 8.
10. An array substrate, characterized in that: The array substrate includes a thin film transistor manufactured by the thin film transistor manufacturing method according to any one of claims 1 to 8, or the thin film transistor according to claim 9.