Split trench gate metal oxide semiconductor field effect transistor with high reverse withstand voltage

Abstract

The invention provides a split trench gate metal oxide semiconductor field effect transistor with high reverse withstand voltage, a shielding gate structure is arranged in a groove provided with an epitaxial layer in the field effect transistor, and the shielding gate structure comprises an oxide layer, a first conductive type shielding gate polycrystalline silicon layer and a first conductive type gate polycrystalline silicon layer, the oxide layer wraps and isolates the first conductive type shielding grid polycrystalline silicon layer and the first conductive type grid polycrystalline silicon layer, and first conductive type charge balance regions with the same height as the first conductive type shielding grid polycrystalline silicon layer are arranged on the two sides of the groove. The influence of trapped charges in the oxide layer on the first conduction type drift region is reduced through the first conduction type charge balance region, so that the reverse withstand voltage value of the device is improved, and the split trench gate metal oxide semiconductor field effect transistor is wider in application scene.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor power electronic devices, and particularly to a split-gate trench metal oxide semiconductor field effect transistor with high reverse breakdown voltage. Background Art

[0002] Power semiconductor devices are the key to the efficient development of high-tech industries. Among them, the power metal oxide semiconductor field effect transistor (MOSFET), as a unipolar conductive device, shows significant advantages in low-voltage applications. It not only has a faster switching speed than the insulated gate bipolar transistor (IGBT), but also avoids the phenomenon of current "tail", becoming the first choice for high-frequency power switches. Moreover, its built-in reverse-conducting PN structure can effectively act as a freewheeling diode in the rectifier circuit. In addition, using power MOSFET can also increase the power density and reduce the total chip area.

[0003] In the field of medium and low voltage applications, due to its unique device structure and working principle, the split-gate trench metal oxide semiconductor field effect transistor (SGTMOS) not only has the characteristics of low on-resistance and low gate-drain capacitance, but also has low power consumption and good switching characteristics. Compared with the traditional MOSFET, when the SGTMOS is under reverse breakdown voltage, the shielding gate has a modulation effect on the electric field in the drift region, changing the traditional triangular electric field distribution into a rectangular distribution. Although the SGTMOS has higher reverse breakdown voltage characteristics than the traditional MOSFET, in some application scenarios, the reverse breakdown voltage of the SGTMOS still cannot meet the operating conditions of the circuit, and there is a risk of SGTMOS damage.

[0004] Therefore, how to provide a split-gate trench metal oxide semiconductor field effect transistor with higher reverse breakdown voltage is an urgent problem to be solved at present. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the present invention provides a split-gate trench metal oxide semiconductor field effect transistor with high reverse breakdown voltage to solve at least one of the above technical problems.

[0006] To achieve the above and other related objectives, the technical solutions provided in this application are as follows.

[0007] In a first aspect, this application provides a split-gate trench metal oxide semiconductor field effect transistor with high reverse breakdown voltage, including:

[0008] A drain metal layer and a second conductive type substrate layer, an epitaxial layer and a source metal layer sequentially stacked on the drain metal layer;

[0009] A shielding gate structure is arranged in the groove of the epitaxial layer, and the shielding gate structure includes an oxide layer, a first conductive type shielding gate polysilicon layer and a first conductive type gate polysilicon layer, and the oxide layer wraps and isolates the first conductive type shielding gate polysilicon layer and the first conductive type gate polysilicon layer; a first conductive type charge balance region is arranged on both sides of the groove, and the first conductive type charge balance region has the same height as the first conductive type shielding gate polysilicon layer.

[0010] In one embodiment of the present invention, the epitaxial layer also includes: a first conductive type drift region, which is arranged on the side of the second conductive type substrate layer away from the drain metal layer; a second conductive type body region, which is arranged on the side of the first conductive type drift region away from the second conductive type substrate layer; a second conductive type contact region and a first conductive type source region are both arranged on the side of the second conductive type body region away from the first conductive type drift region; the groove is formed by the first conductive type drift region, the second conductive type body region and the first conductive type source region.

[0011] In one embodiment of the present invention, the oxide layer is arranged on the side of the first conductive type drift region away from the second conductive type substrate layer, and the top of the oxide layer is at the same height as the top of the first conductive type source region; the first conductive type shielding gate polysilicon layer is arranged on the side of the first conductive type drift region away from the second conductive type substrate layer, and the side of the first conductive type shielding gate polysilicon layer close to the first conductive type gate polysilicon layer is lower than the side of the second conductive type body region away from the second conductive type contact region; the first conductive type gate polysilicon layer is arranged on the side of the first conductive type shielding gate polysilicon layer away from the second conductive type substrate layer.

[0012] In one embodiment of the present invention, the first conductivity type charge balance region and the second conductivity type body region are isolated by the first conductivity type drift region.

[0013] In one embodiment of the present invention, the source metal layer covers the oxide layer, the second conductivity type contact region and the first conductivity type source region.

[0014] In an embodiment of the present invention, one side of the second-conductivity-type contact region is in contact with the first-conductivity-type source region. One side of the first-conductivity-type source region that faces away from the second-conductivity-type contact region is in contact with the oxide layer. One side of the oxide layer that is in contact with the first-conductivity-type source region is also in contact with one side of the second-conductivity-type body region, one side of the first-conductivity-type drift region, and one side of the first-conductivity-type charge balance region.

[0015] In an embodiment of the present invention, the thickness of the first-conductivity-type gate polysilicon layer ranges from 50 nm to 90 nm, and the width ranges from 0.1 μm to 0.16 μm; the thickness of the first-conductivity-type shield gate polysilicon layer ranges from 40 nm to 80 nm, and the width ranges from 30 nm to 70 nm; the thickness of the oxide layer existing between the first-conductivity-type gate polysilicon layer and the first-conductivity-type shield gate polysilicon layer ranges from 0.2 μm to 0.3 μm; on the side of the first-conductivity-type shield gate polysilicon layer that faces away from the first-conductivity-type gate polysilicon layer, the thickness of the oxide layer between the first-conductivity-type shield gate polysilicon layer and the first-conductivity-type drift region ranges from 0.13 μm to 0.18 μm, and the thickness of the first-conductivity-type charge balance region ranges from 1.9 μm to 2.2 μm.

[0016] In an embodiment of the present invention, the thickness of the second-conductivity-type body region ranges from 0.3 μm to 0.7 μm, the thickness of the second-conductivity-type contact region ranges from 0.2 μm to 0.6 μm, and the thickness range of the first-conductivity-type source region is equal to the thickness range of the second-conductivity-type contact region.

[0017] In an embodiment of the present invention, the doping concentration of the first-conductivity-type drift region ranges from 9×10 14 cm -3 to 7×10 15 cm -3 , the doping concentration of the first-conductivity-type gate polysilicon layer ranges from 1×10 19 cm -3 to 1×10 20 cm -3 , the doping concentration of the first-conductivity-type shield gate polysilicon layer ranges from 1×10 19 cm -3 to 1×10 20 cm -3 , the doping concentration of the first-conductivity-type charge balance region ranges from 8×10 16 cm -3 to 5×10 17 cm-3 。

[0018] In one embodiment of the present invention, the doping concentration of the second conductivity type body region ranges from 8×10 16 cm -3 to 2×10 17 cm -3 , the doping concentration of the first conductivity type source region ranges from 5×10 18 cm -3 to 5×10 19 cm -3 , and the doping concentration of the second conductivity type contact region ranges from 5×10 18 cm -3 to 5×10 19 cm -3 。

[0019] The present application provides a split trench gate metal oxide semiconductor field effect transistor with high reverse breakdown voltage. An epitaxial layer is provided in the field effect transistor, and a shielding gate structure is provided in the groove of the epitaxial layer. The shielding gate structure includes an oxide layer, a first conductivity type shielding gate polysilicon layer, and a first conductivity type gate polysilicon layer. The oxide layer wraps and isolates the first conductivity type shielding gate polysilicon layer and the first conductivity type gate polysilicon layer. A first conductivity type charge balance region having the same height as the first conductivity type shielding gate polysilicon layer is provided on both sides of the groove. When the field effect transistor withstands a reverse voltage, the influence of trap charges in the oxide layer on the first conductivity type drift region is reduced through the first conductivity type charge balance region, thereby increasing the reverse breakdown voltage value of the device and making the application scenario of the split trench gate metal oxide semiconductor field effect transistor wider.

[0020] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present invention and used together with the specification to explain the principles of the present invention. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts. In the drawings:

[0022] Figure 1 is a cross-sectional view of a split trench gate metal oxide semiconductor field effect transistor with high reverse breakdown voltage in an exemplary embodiment of the present application;

[0023] Figure 2A comparison chart of the reverse breakdown voltage characteristics between the split trench gate metal oxide semiconductor field effect transistor with high reverse breakdown voltage in an exemplary embodiment of the present application and the existing field effect transistor;

[0024] Description of reference numerals: 1 - Drain metal layer; 2 - Substrate layer of the second conductivity type; 3 - Drift region of the first conductivity type; 4 - Body region of the second conductivity type; 5 - Contact region of the second conductivity type; 6 - Source region of the first conductivity type; 7 - Oxide layer; 8 - Shield gate polysilicon layer of the first conductivity type; 9 - Charge balance region of the first conductivity type; 10 - Gate polysilicon layer of the first conductivity type; 11 - Source metal layer. Detailed implementation manners

[0025] The following will describe the implementation manners of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for explaining the present invention and not for limiting the protection scope of the present invention.

[0026] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0027] In the following description, a large number of details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0028] Insulated Gate Bipolar Transistor (IGBT) is a composite fully controlled voltage-driven power semiconductor device, which combines the advantages of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and BJT (Bipolar Junction Transistor), and has characteristics such as high input impedance, low on-state voltage drop, and high current handling ability.

[0029] As described in the background art, power semiconductor devices are the key to the efficient development of the high-tech industry. Among them, the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), as a unipolar conductive device, exhibits significant advantages in low-voltage applications. It not only has a faster switching speed than the Insulated Gate Bipolar Transistor (IGBT), but also avoids the occurrence of current "tail" phenomenon, making it the first choice for high-frequency power switches. Moreover, its built-in reverse-conducting PN structure can effectively act as a freewheeling diode in the rectifier circuit. In addition, using power MOSFET can increase the power density and reduce the total chip area.

[0030] In the field of medium and low voltage applications, the Split-Gate Trench MOSFET (SGTMOS), due to its unique device structure and working principle, not only has the characteristics of low on-resistance and low gate-drain capacitance, but also has low power consumption and good switching characteristics. Compared with the traditional MOSFET, when the SGTMOS has reverse breakdown voltage, the shielding gate modulates the electric field in the drift region, transforming the traditional triangular electric field distribution into a rectangular distribution. Although the SGTMOS has a higher reverse breakdown voltage characteristic than the traditional MOSFET, in some application scenarios, the reverse breakdown voltage of the SGTMOS still cannot meet the operating conditions of the circuit, and there is a risk of SGTMOS damage.

[0031] In a first aspect, as Figure 1 shown, the present application provides a split-gate trench metal-oxide-semiconductor field-effect transistor with high reverse breakdown voltage, including:

[0032] a drain metal layer 1, and a second-conductivity-type substrate layer 2, an epitaxial layer 110, and a source metal layer 11 stacked on the drain metal layer 1 in sequence;

[0033] wherein, a shielding gate structure is arranged in the groove of the epitaxial layer 110. The shielding gate structure includes an oxide layer 7, a first-conductivity-type shielding gate polysilicon layer 8, and a first-conductivity-type gate polysilicon layer 10. The oxide layer 7 wraps and isolates the first-conductivity-type shielding gate polysilicon layer 8 and the first-conductivity-type gate polysilicon layer 10; first-conductivity-type charge balance regions 9 are arranged on both sides of the groove, and the first-conductivity-type charge balance regions 9 have the same height as the first-conductivity-type shielding gate polysilicon layer 8.

[0034] Specifically, as Figure 1As shown, the epitaxial layer 110 further includes: a first conductivity type drift region 3 disposed on a side of the second conductivity type substrate layer 2 away from the drain metal layer 1; a second conductivity type body region 4 disposed on a side of the first conductivity type drift region 3 away from the second conductivity type substrate layer 2; a second conductivity type contact region 5 and a first conductivity type source region 6 are both disposed on a side of the second conductivity type body region 4 away from the first conductivity type drift region 3; a groove is formed through the first conductivity type drift region 3, the second conductivity type body region 4, and the first conductivity type source region 6.

[0035] More specifically, as Figure 1 shown, an oxide layer 7 is disposed on a side of the first conductivity type drift region 3 away from the second conductivity type substrate layer 2, and the top of the oxide layer 7 is at the same height as the top of the first conductivity type source region 6; a first conductivity type shield gate polysilicon layer 8 is disposed on a side of the first conductivity type drift region 3 away from the second conductivity type substrate layer 2, and a side of the first conductivity type shield gate polysilicon layer 8 close to the first conductivity type gate polysilicon layer 10 is lower than a side of the second conductivity type contact region 5 away from the second conductivity type body region 4; a first conductivity type gate polysilicon layer 10 is disposed on a side of the first conductivity type shield gate polysilicon layer 8 away from the second conductivity type substrate layer 2.

[0036] Specifically, as Figure 1 shown, the first conductivity type charge balance region 9 is isolated from the second conductivity type body region 4 by the first conductivity type drift region 3.

[0037] Specifically, the source metal layer 11 covers the oxide layer 7, the second conductivity type contact region 5, and the first conductivity type source region 6.

[0038] Specifically, one side of the second conductivity type contact region 5 is in contact with the first conductivity type source region 6, a side of the first conductivity type source region 6 away from the second conductivity type contact region 5 is in contact with the oxide layer 7, and a side of the oxide layer 7 in contact with the first conductivity type source region 6 is also in contact with a side of the second conductivity type body region 4, a side of the first conductivity type drift region 3, and a side of the first conductivity type charge balance region 9. Specifically, as Figure 1 shown, both the second conductivity type contact region 5 and the first conductivity type source region 6 are located on a side of the second conductivity type body region 4 away from the first conductivity type drift region 3. In a direction parallel to the drain metal layer 1 of the second conductivity type contact region 5, one side of the second conductivity type contact region 5 is in contact with a side surface of the first conductivity type source region 6. In a direction parallel to the drain metal layer 1 of the second conductivity type contact region 5, a side of the first conductivity type source region 6 away from the second conductivity type contact region 5 is in contact with the oxide layer 7, and a contact surface where the oxide layer 7 is in contact with the first conductivity type source region 6 is also in contact with side walls of the second conductivity type body region 4, the first conductivity type drift region 3, and the first conductivity type charge balance region 9.

[0039] It should be noted that when the field effect transistor is in the reverse conduction state, the first conductive type charge balance region 9 is used to reduce the influence of the trapped charges in the oxide layer 7 on the first conductive type drift region 3, so as to improve the reverse withstand voltage value of the field effect transistor. That is, when the split trench gate metal oxide semiconductor field effect transistor with high reverse withstand voltage is in the reverse conduction state, the first conductive type shielding gate polysilicon layer 8, the first conductive type gate polysilicon layer 10, and the source metal layer 11 of the field effect transistor are grounded, the drain metal layer 1 is connected to a positive voltage, and a certain amount of trapped charges exists in the oxide layer 7 arranged between the first conductive type shielding gate polysilicon layer 8 and the first conductive type drift region 3. The first conductive type charge balance region 11 is used to widen the spacing distance between the oxide layer 7 with trapped charges and the first conductive type drift region 3, thereby reducing the influence of the trapped charges on the equivalent doping concentration and electric field distribution of the first conductive type drift region 3, thereby improving the reverse withstand voltage capability of the device.

[0040] When the field effect transistor is in a forward conduction state, the contact surface between the oxide layer 7 and the second conductive type contact region 5 is affected by the electric field to form an inversion layer, thereby constituting a current conduction channel.

[0041] In detail, Figure 1 As shown, the width of the split trench gate metal oxide semiconductor field effect transistor with high reverse withstand voltage provided by the present application ranges from 0.8μm to 1.2μm, the thickness of the first conductive type gate polysilicon layer 10 ranges from 50nm to 90nm, and the width ranges from 0.1μm to 0.16μm; the thickness of the first conductive type shielding gate polysilicon layer 8 ranges from 40nm to 80nm, and the width ranges from 30nm to 70nm; the first conductive type gate polysilicon layer 8 is located at the first conductive type gate polysilicon layer 8. The thickness of the oxide layer 7 between the layer 10 and the first conductive type shielding gate polysilicon layer 8 is in the range of 0.2μm to 0.3μm; on the side of the first conductive type shielding gate polysilicon layer 8 away from the first conductive type gate polysilicon layer 10, the thickness of the oxide layer 7 between the first conductive type shielding gate polysilicon layer 8 and the first conductive type drift region 3 is in the range of 0.13μm to 0.18μm, and the thickness of the first conductive type charge balance region 9 is in the range of 1.9μm to 2.2μm.

[0042] The thickness of the first conductive type drift region 3 ranges from 1.5 μm to 3.5 μm, and the overall thickness of the oxide layer 10 ranges from 1.8 μm to 2.6 μm.

[0043] In detail, Figure 1As shown, the thickness of the second-conductivity-type body region 4 ranges from 0.3 μm to 0.7 μm, the thickness of the second-conductivity-type contact region 5 ranges from 0.2 μm to 0.6 μm, the thickness range of the first-conductivity-type source region 6 is equal to that of the second-conductivity-type contact region 5, and the thickness range of the first-conductivity-type source region 6 is from 0.2 μm to 0.6 μm.

[0044] Specifically, the main material of the high reverse breakdown voltage split trench gate metal oxide semiconductor field effect transistor provided by this application is silicon material. The second-conductivity-type substrate layer 2, the second-conductivity-type contact region 5, the first-conductivity-type source region 6, the first-conductivity-type shield gate polysilicon layer 8, the first-conductivity-type charge balance region 9, and the first-conductivity-type gate polysilicon layer 10 are of heavy doping type; the first-conductivity-type drift region 3 is of light doping type, and the doping concentration range of the first-conductivity-type drift region 3 is from 9×10 14 cm -3 to 7×10 15 cm -3 The doping concentration range of the first-conductivity-type gate polysilicon layer 10 is from 1×10 19 cm -3 to 1×10 20 cm -3 The doping concentration range of the first-conductivity-type shield gate polysilicon layer 8 is from 1×10 19 cm -3 to 1×10 20 cm -3 The doping concentration range of the first-conductivity-type charge balance region 9 is from 8×10 16 cm -3 to 5×10 17 cm -3 .

[0045] Specifically, the doping concentration range of the second-conductivity-type body region 4 is from 8×10 16 cm -3 to 2×10 17 cm -3 The doping concentration range of the first-conductivity-type source region 6 is from 5×10 18 cm -3 to 5×10 19 cm -3 The doping concentration range of the second-conductivity-type contact region 5 is from 5×10 18 cm -3 to 5×10 19 cm -3 .

[0046] As Figure 2As shown, the split trench gate metal oxide semiconductor field effect transistor with high reverse breakdown voltage provided by the present application has a larger reverse breakdown voltage value compared with the field effect transistors existing in the prior art.

[0047] The present application provides a split trench gate metal oxide semiconductor field effect transistor with high reverse breakdown voltage. An epitaxial layer is provided in the field effect transistor, and a shielding gate structure is provided in the groove of the epitaxial layer. The shielding gate structure includes an oxide layer, a first conductivity type shielding gate polysilicon layer and a first conductivity type gate polysilicon layer. The oxide layer wraps and isolates the first conductivity type shielding gate polysilicon layer and the first conductivity type gate polysilicon layer. A first conductivity type charge balance region with the same height as the first conductivity type shielding gate polysilicon layer is provided on both sides of the groove. When the field effect transistor withstands a reverse voltage, the influence of trap charges in the oxide layer on the first conductivity type drift region is reduced through the first conductivity type charge balance region, thereby improving the reverse breakdown voltage value of the device and making the application scenario of the split trench gate metal oxide semiconductor field effect transistor wider.

[0048] The above embodiments merely exemplarily illustrate the principles and effects of the present invention, rather than limiting the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A split trench gate metal oxide semiconductor field effect transistor with high reverse withstand voltage, characterized in that: include: A drain metal layer and a second conductive type substrate layer, an epitaxial layer and a source metal layer sequentially stacked on the drain metal layer; A shielding gate structure is arranged in the groove of the epitaxial layer, and the shielding gate structure includes an oxide layer, a first conductive type shielding gate polysilicon layer and a first conductive type gate polysilicon layer, and the oxide layer wraps and isolates the first conductive type shielding gate polysilicon layer and the first conductive type gate polysilicon layer; a first conductive type charge balance region is arranged on both sides of the groove, and the first conductive type charge balance region has the same height as the first conductive type shielding gate polysilicon layer.

2. The high reverse withstand voltage split trench gate metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The epitaxial layer further comprises: A first conductive type drift region is disposed on a side of the second conductive type substrate layer away from the drain metal layer; A second conductive type body region, which is arranged on a side of the first conductive type drift region away from the second conductive type substrate layer; The second conductive type contact region and the first conductive type source region are both arranged on a side of the second conductive type body region away from the first conductive type drift region; The groove is formed by the first conductive type drift region, the second conductive type body region and the first conductive type source region.

3. The high reverse withstand voltage split trench gate metal oxide semiconductor field effect transistor according to claim 2, characterized in that: The oxide layer is arranged on a side of the first conductive type drift region away from the second conductive type substrate layer, and the top of the oxide layer is at the same height as the top of the first conductive type source region; The first conductive type shielding gate polysilicon layer is arranged on a side of the first conductive type drift region away from the second conductive type substrate layer, and a side of the first conductive type shielding gate polysilicon layer close to the first conductive type gate polysilicon layer is lower than a side of the second conductive type body region away from the second conductive type contact region; The first conductive type gate polysilicon layer is disposed on a side of the first conductive type shielding gate polysilicon layer away from the second conductive type substrate layer.

4. The high reverse withstand voltage split trench gate metal oxide semiconductor field effect transistor according to claim 2, characterized in that: The first conductivity type charge balance region is isolated from the second conductivity type body region by the first conductivity type drift region.

5. The high reverse withstand voltage split trench gate metal oxide semiconductor field effect transistor according to claim 2, characterized in that: The source metal layer covers the oxide layer, the second conductive type contact region and the first conductive type source region.

6. The high reverse withstand voltage split trench gate metal oxide semiconductor field effect transistor according to claim 2, characterized in that: One side of the second conductive type contact region is in contact with the first conductive type source region, the side of the first conductive type source region facing away from the second conductive type contact region is in contact with the oxide layer, and the side of the oxide layer in contact with the first conductive type source region is also in contact with one side of the second conductive type body region, one side of the first conductive type drift region and one side of the first conductive type charge balance region.

7. The high reverse withstand voltage split trench gate metal oxide semiconductor field effect transistor according to claim 3, characterized in that: The thickness of the first conductive type gate polysilicon layer ranges from 50nm to 90nm, and the width ranges from 0.1μm to 0.16μm; the thickness of the first conductive type shielding gate polysilicon layer ranges from 40nm to 80nm, and the width ranges from 30nm to 70nm; the thickness of the oxide layer between the first conductive type gate polysilicon layer and the first conductive type shielding gate polysilicon layer ranges from 0.2μm to 0.3μm; on the side of the first conductive type shielding gate polysilicon layer away from the first conductive type gate polysilicon layer, the thickness of the oxide layer between the first conductive type shielding gate polysilicon layer and the first conductive type drift region ranges from 0.13μm to 0.18μm, and the thickness of the first conductive type charge balance region ranges from 1.9μm to 2.2μm.

8. The high reverse withstand voltage split trench gate metal oxide semiconductor field effect transistor according to claim 2, characterized in that: The thickness range of the second conductive type body region is 0.3 μm to 0.7 μm, the thickness range of the second conductive type contact region is 0.2 μm to 0.6 μm, and the thickness range of the first conductive type source region is equal to the thickness range of the second conductive type contact region.

9. The high reverse withstand voltage split trench gate metal oxide semiconductor field effect transistor according to claim 7, characterized in that: The doping concentration of the first conductive type drift region is in the range of 9×10 14 cm -3 Up to 7×10 15 cm -3 The doping concentration of the first conductive type gate polysilicon layer is in the range of 1×10 19 cm -3 Up to 1×10 20 cm -3 The doping concentration of the first conductive type shielding gate polysilicon layer is in the range of 1×10 19 cm -3 Up to 1×10 20 cm -3 The doping concentration of the first conductive type charge balance region is in the range of 8×10 16 cm -3 Up to 5×10 17 cm -3 .

10. The high reverse withstand voltage split trench gate metal oxide semiconductor field effect transistor according to claim 8, characterized in that: The doping concentration of the second conductive type body region ranges from 8×10 16 cm -3 Up to 2×10 17 cm -3 The doping concentration of the first conductive type source region is in the range of 5×10 18 cm -3 Up to 5×10 19 cm -3 The doping concentration of the second conductive type contact region is in the range of 5×10 18 cm -3 Up to 5×10 19 cm -3 .

Images