Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a first well comprising a first main well region and a plurality of first interdigital regions extending outward from the first main well region, ions in the first well being uniformly distributed; a second well comprising a second main well region and a plurality of second interdigital regions extending outward from the second main well region, ions in the second well being uniformly distributed and having a conductive type opposite to that of the first well, the second interdigital regions extending toward the first main body region, the first interdigital regions extending toward the second main body region, and each first interdigital region and each second interdigital region being arranged in a staggered manner; a drain region located in the first well; a source region located in the second well and electrically connected with the first interdigital regions; and a gate region located above the first well and the second well. The semiconductor structure and the preparation method thereof can make the ion concentration of each region of the device more uniform, the HCI effect of the device is not significant, and the reliability of the device can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method. Background Technology

[0002] Power MOSFETs are most commonly used in switches. However, in applications such as startup circuits, surge protection, solid-state relays, and constant current sources, power MOSFETs need to operate as normally "on" switches. That is, when the gate voltage is zero, the power MOSFET is turned on and current flows through it. When the gate voltage is negative, the power MOSFET is turned off and no current flows through it. This type of power MOSFET is generally called a depletion-mode MOSFET.

[0003] The most common structure of a depletion-mode MOSFET is to inject an additional N-type injection region on the surface of the P-well containing the source region and make it electrically contacted with the N-well containing the drain region. This makes the surface of the P-well and the gap between the P-well and the N-well inverted. In this way, the drain and source regions can be turned on without the gate region being energized, and the current path can be turned off by applying a negative voltage to the gate to achieve surface inversion.

[0004] The disadvantage of this structure is that the additional N-type implantation region also increases the N-type ion concentration on the surface of the N-well where the drain region is located, and a denser N-type ion doped region appears at the bottom of the gate region. This makes the HCI effect (Hot Carrier Injection) of the MOSFET device more significant, resulting in reduced reliability and lifespan. It also reduces the breakdown voltage of the MOSFET device, requiring an increase in device size to meet the breakdown voltage requirements, which in turn increases the cost to some extent. Summary of the Invention

[0005] The purpose of this application is to provide a semiconductor structure and its fabrication method, which results in more uniform ion concentration in each region of the device, less significant HCl effect, and improved device reliability.

[0006] To achieve the above objectives, this application provides the following technical solution:

[0007] This application provides a semiconductor structure, the semiconductor structure comprising:

[0008] The first well includes a first main well region and a plurality of first interdigitated regions extending outward from the first main well region, and the ions in the first well are uniformly distributed.

[0009] The second well includes a second main well region and a plurality of second interdigitated regions extending outward from the second main well region. The ions in the second well are uniformly distributed and have the opposite conductivity type to the ions in the first well. The second interdigitated regions extend toward the first main well region, and the first interdigitated regions extend toward the second main well region. Each first interdigitated region and each second interdigitated region are interspersed with each other.

[0010] The leak region is located within the first well;

[0011] The source region is located within the second well and is in electrical contact with the first interdigitated region;

[0012] The gate region is located above the first well and the second well.

[0013] In one embodiment, there is a gap between each of the first interdigital regions and each of the second interdigital regions.

[0014] In one embodiment, there is an overlapping area between each of the first interdigital regions and each of the second interdigital regions.

[0015] In one embodiment, there is a gap between the first interdigitated region and the second main well region.

[0016] In one embodiment, there is a gap between the second interdigitated region and the first main well region.

[0017] In one embodiment, the semiconductor structure further includes a field plate located above the gate region and a portion of the first well, and extending above a portion of the drain region.

[0018] In one embodiment, the semiconductor structure further includes an active region, wherein both the first well and the second well are located within the active region.

[0019] In one embodiment, the source region is also located within a portion of the first interdigital region.

[0020] This application also provides a method for preparing a semiconductor structure, used to prepare the semiconductor structure as described above, the method comprising:

[0021] A first well ion implantation and a second well ion implantation are performed on a semiconductor substrate. The conductivity type of the ions implanted in the second well ion implantation is opposite to that of the ions implanted in the first well ion implantation, forming a first well and a second well. The first well includes a first main well region and a plurality of first interdigitated regions extending outward from the first main well region. The second well includes a second main well region and a plurality of second interdigitated regions extending outward from the second main well region. The second interdigitated regions extend toward the first main well region, and the first interdigitated regions extend toward the second main well region. Each first interdigitated region and each second interdigitated region are interleaved with each other.

[0022] A gate region is formed above the first well and the second well;

[0023] Drain ion implantation is performed in the first well to form a drain region, and source ion implantation is performed in the second well to form a source region, wherein the source region is electrically contacted with the first interdigitated region.

[0024] In one embodiment, the preparation method further includes:

[0025] A field plate is formed above the gate region and a portion of the first well, the field plate extending above a portion of the drain region.

[0026] Compared with the prior art, the technical solution of this application has the following beneficial effects:

[0027] In the semiconductor structure and fabrication method described in this application, a first well including a first interdigitated region and a second well including a second interdigitated region are formed. The ions in the second well have the opposite conductivity type to those in the first well. The second interdigitated region extends towards the first main region, and the first interdigitated region extends towards the second main region. The first and second interdigitated regions are interleaved, and the source region is electrically contacted with the first interdigitated region. This ensures that the drain region in the first well and the source region in the second well are normally open. Compared to traditional depletion-type MOSFETs, this semiconductor structure reduces the need for locally implanted ion implantation regions to form normally open current channels. The ion concentration in each region of the device is more uniform, the HCl effect is less significant, and the device reliability is improved. Furthermore, the uniform ion concentration in each region of the device ensures that the device's breakdown voltage is not affected, guaranteeing a higher breakdown voltage. This eliminates the need to increase the device size to improve its breakdown voltage. The smaller size compared to existing devices allows for increased integration and reduced costs. The current channel required for the semiconductor structure is realized in the step of preparing the well (which is then used to prepare the drain region). No additional ion implantation step or additional photomask is required. Only the photomask originally used to prepare the well needs to be adapted and adjusted. This makes it compatible with the preparation method of ordinary MOS devices, further reducing the process cost of the product. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1A planar top view of a semiconductor structure provided for the first embodiment of this application;

[0030] Figure 1A for Figure 1 A cross-sectional view along the AA direction;

[0031] Figure 1B for Figure 1 A cross-sectional view along the BB direction;

[0032] Figure 2 A plan view of another semiconductor structure provided in the first embodiment of this application;

[0033] Figure 3 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to the second embodiment of this application;

[0034] Figures 4-8 They are respectively Figure 3 The diagram shows cross-sectional views of the semiconductor structure at each step of the process. Detailed Implementation

[0035] The technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application. Moreover, in the following embodiments, the description of each embodiment has its own emphasis, and for parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0036] Figure 1 This is a top view of the semiconductor structure provided in the first embodiment of this application. Figure 1A for Figure 1 Cross-sectional view along the AA direction. Figure 1B for Figure 1 A sectional view along the BB direction, in which the relationships between the various structures are shown more clearly. Figure 1 The drain region 30 and the source region 40 are not shown in the diagram. Figure 1 and Figure 1B The diagram shows the drain region 30 and the source region 40, and the boundaries between the first main well region 11 and the first interdigitated region 12, and between the second main well region 21 and the second interdigitated region 22 are indicated by dashed lines. Please refer to the attached diagram. Figure 1 , Figure 1A and Figure 1B As shown, the semiconductor structure of this application may include:

[0037] Semiconductor substrate (not shown). The semiconductor substrate may be a silicon substrate.

[0038] The first well 10 is located within the substrate. The first well 10 may include a first main well region 11 and a plurality of first interdigitated regions 12 extending outward from the first main well region 11. Ions are uniformly distributed within the first well 10.

[0039] The second well 20 is located within the substrate. The second well 20 may include a second main well region 21 and a plurality of second interdigitated regions 22 extending outward from the second main well region 21. Ions in the second well 20 are uniformly distributed and have the opposite conductivity type to those in the first well 10. The second interdigitated regions 22 extend toward the first main well region, and the first interdigitated regions 12 extend toward the second main well region. Each first interdigitated region 12 and each second interdigitated region 22 are interleaved with each other.

[0040] The leak area 30 is located within the first sink 10.

[0041] The source region 40 is located within the second well 20 and is in electrical contact with the first interdigitated region 12.

[0042] Gate region 50 is located above the first well 10 and the second well 20.

[0043] More specifically, the gate region 50 is located above the first interdigitated region 12 (and the second interdigitated region 22), the first interdigitated region 12 is located below the gate region 50 and crosses the gate region 50, and the first interdigitated region 12 serves as a current path between the source region 40 and the drain region 30.

[0044] In one embodiment, the first main well region 11 and the second main well region 21 are located on both sides of the gate region 50, and the gate region 50 is also located above a portion of the first main well region 11.

[0045] In one embodiment, the first interdigitated region 12 has a dimension greater than 0 that crosses the gate region 50, meaning that a portion of the first interdigitated region 12 extends into the gate region 50 biased toward the second well 20.

[0046] In one embodiment, the source region 40 is located within the second well 20 and within a portion of the first interdigitated region 12, i.e., within the first interdigitated region 12 of the gate region 50 biased toward the second well 20, so that the source region 40 is in electrical contact with the first interdigitated region 12.

[0047] In one specific embodiment, the semiconductor structure is a depletion-type MOSFET. The first well 10 is an N-well, implanted with N-type ions and lightly doped; the second well 20 is a P-well, implanted with P-type ions and lightly doped; the drain region 30 and the source region 40 are both implanted with N-type ions and heavily doped. The source region 40 is electrically contacted with the first interdigitated region 12, and then electrically contacted with the drain region 30 via the first interdigitated region 12 and the first main well region 11, so that the semiconductor structure is in a normally on (conducting) state. When a negative voltage is applied to the gate region 50, the inversion depletion of the first interdigitated region 12 can pinch off the current path, causing the device (semiconductor structure) to turn off.

[0048] In the above embodiments, by forming a first well including a first interdigitated region and a second well including a second interdigitated region, the ions in the second well have the opposite conductivity type to the ions in the first well. The second interdigitated region extends toward the first main region, and the first interdigitated region extends toward the second main region. The first interdigitated regions and the second interdigitated regions are interleaved with each other. The source region is electrically contacted with the first interdigitated region, so that the drain region located in the first well and the source region located in the second well are in a normally open state. Therefore, compared with the traditional depletion-type MOSFET, the semiconductor structure of this application reduces the locally implanted ion implantation region that forms the normally open current channel. The ion concentration in each region of the device is more uniform, the HCI effect of the device is not significant, and the reliability of the device can be improved.

[0049] In this embodiment of the application, there is no particular limitation on the size and number of the first interdigital region 12 and the second interdigital region 22, which can be set according to the actual product application requirements.

[0050] Among them, Figure 1 In the specific embodiment shown, there is a gap between each of the first interdigital regions 12 and each of the second interdigital regions 22.

[0051] In another specific embodiment, please refer to the comparison. Figure 2 As shown, there is an overlapping area between each of the first interdigital regions 12 and each of the second interdigital regions 22.

[0052] In another specific embodiment, there is a gap between the first interdigitated region 12 and the second main well region 21.

[0053] In another specific embodiment, there is a gap between the second interdigitated region 22 and the first main well region 11.

[0054] In the above embodiments, the turn-on voltage of the device can be adjusted by regulating the size of the gap or the size of the overlapping area between the first interdigitated region, the second interdigitated region, the first main well region, and the second main well region, thereby improving the device's adaptability. Through testing, the applicant has demonstrated that the semiconductor structure of this application can achieve a turn-on voltage between 0 and -2V, meeting the requirements of practical applications.

[0055] Moreover, compared to traditional depletion-type MOSFETs, the semiconductor structure of this application does not have a separate local ion implantation region, resulting in uniform ion concentration in all areas of the device. This ensures that the device's breakdown voltage is not affected and guarantees a high breakdown voltage. It does not require increasing the device size to improve the breakdown voltage. Compared to existing devices, the device is smaller in size, which can increase the device's integration density and reduce costs.

[0056] In one embodiment, the number of first interdigital regions 12 and second interdigital regions 22 can be equal, for example, both being 3 first interdigital regions 12 and 3 second interdigital regions 22.

[0057] In another embodiment, the number of the first interdigital region 12 and the second interdigital region 22 may be unequal, with a difference of 1 between the number of the second interdigital region 22 and the number of the first interdigital region 12. For example... Figure 1 As shown, the number of first interdigital regions 12 can be 3, and the number of second interdigital regions 22 can be 4. Any first interdigital region 12 can be located between two adjacent second interdigital regions 22. Alternatively, the number of first interdigital regions 12 can be 4, and the number of second interdigital regions 22 can be 3. Any second interdigital region 22 can be located between two adjacent first interdigital regions 12.

[0058] Those skilled in the art will understand that this application does not specifically limit the number of the first interdigital region 12 and the second interdigital region 22. In other embodiments, the first interdigital region 12 and the second interdigital region 22 may also be other numbers.

[0059] In this embodiment, the withstand voltage of the semiconductor structure is achieved through the field plate 60.

[0060] In one embodiment, the semiconductor structure may further include a field plate 60 located above the gate region 50 and a portion of the first well 10, and extending above a portion of the drain region 30.

[0061] In this embodiment, by adjusting the length of the field plate 60, the withstand voltage of the device can be easily set between 10V and 40V to meet the application requirements.

[0062] In one embodiment, the semiconductor structure may further include an active region 70, within which both the first well 10 and the second well 20 are located. Thus, in one specific embodiment, a complete depletion-type MOSFET is formed. In actual products, the edges of the first well 10 and the second well 20 extend beyond the edge of the active region 70 to ensure that the active region 70 is entirely located in a region with uniform ion concentration, thereby ensuring device performance.

[0063] Please see Figure 3 As shown, the second embodiment of this application provides a method for preparing a semiconductor structure as described above, and please refer to the following in conjunction with the existing documentation. Figures 4-7 As shown, the preparation method may include:

[0064] Step 1: Fabricate multiple isolation structures 80 on a semiconductor substrate, with active regions 70 formed between each isolation structure 80 (please refer to [reference needed]). Figure 4 (As shown).

[0065] In this embodiment, the isolation structure 80 may be a shallow trench isolation structure (STI).

[0066] Step two: First well ion implantation and second well ion implantation are performed on the semiconductor substrate. The conductivity type of the ions implanted in the second well is opposite to that of the ions implanted in the first well, forming a first well 10 and a second well 20. The first well 10 includes a first main well region 11 and a plurality of first interdigitated regions 12 extending outward from the first main well region 11. The second well 20 includes a second main well region 21 and a plurality of second interdigitated regions 22 extending outward from the second main well region 21. The second interdigitated regions 22 extend toward the first main well region, and the first interdigitated regions 12 extend toward the second main well region. The first interdigitated regions 12 and the second interdigitated regions 22 are interleaved with each other (please refer to the relevant documentation). Figure 1 and Figure 5 (As shown).

[0067] In this embodiment, the order of the first trap ion implantation and the second trap ion implantation is not specifically limited.

[0068] Step 3: Form a gate region 50 above the first well 10 and the second well 20 (see reference). Figure 6 (As shown).

[0069] In this embodiment, the first main well region 11 and the second main well region 21 are located on both sides of the gate region 50, and the gate region 50 is also located above a portion of the first main well region 11. A portion of the first interdigitated region 12 extends to the side of the gate region 50 that is biased towards the second well 20.

[0070] Step four: Drain ion implantation is performed in the first well 10 to form a drain region 30, and source ion implantation is performed in the second well 20 to form a source region 40, wherein the source region 40 is in electrical contact with the first interdigitated region 12 (please refer to the relevant documentation). Figure 1 and Figure 7 (As shown).

[0071] In this embodiment, the order of drain ion implantation and source ion implantation is not specifically limited. During source ion implantation, ions are implanted both into the second well 20 and into a portion of the first interdigitated region 12, specifically the first interdigitated region 12 on the side of the gate region 50 biased towards the second well 20. This means that the portion of the first interdigitated region 12 on the side of the gate region 50 biased towards the second well 20 is also simultaneously implanted with source ions and thus becomes part of the source region 40. The portion of the first interdigitated region 12 without source ion implantation then forms an electrical contact with the source region 40.

[0072] In this application's fabrication method, the first interdigitated region 12, formed simultaneously with the first main well region 11 (later used to fabricate the drain region 30), provides the current channel required for the semiconductor structure. This eliminates the need for additional ion implantation steps or photomasks; only adjustments to the original photomask used for well fabrication are required. This method is compatible with conventional MOS device fabrication methods, further reducing product processing costs. Furthermore, since the first interdigitated region 12 and the first main well region 11 are formed simultaneously in the same ion implantation step, the ion concentration in each region is uniform, thus achieving the aforementioned advantages such as minimal HCl effect, high reliability, and no impact on device breakdown voltage. In actual products, the edges of the first well 10 and the second well 20 extend beyond the edge of the active region 70 to ensure that the active region 70 is entirely located in a region with uniform ion concentration, thereby ensuring device performance and improving process yield.

[0073] Please refer to the following at the same time. Figure 3 and Figure 8 As shown, in one embodiment, the preparation method may further include:

[0074] Step 5: A field plate 60 is formed above the gate region 50 and a portion of the first well 10, the field plate 60 extending above a portion of the drain region 30. This provides the field plate 60 required for the device's withstand voltage, thus fulfilling the device's withstand voltage requirements.

[0075] For specific descriptions of semiconductor structure in the preparation method of this application, please refer to the corresponding descriptions in the foregoing semiconductor structure embodiments, which will not be repeated here.

[0076] Compared with the prior art, the technical solution of this application has the following beneficial effects:

[0077] This application discloses a semiconductor structure and its fabrication method. By forming a first well including a first interdigitated region and a second well including a second interdigitated region, the ions in the second well have the opposite conductivity type to those in the first well. The second interdigitated regions extend towards the first main region, and the first interdigitated regions extend towards the second main region. The first interdigitated regions and the second interdigitated regions are interleaved with each other, and the source region is electrically contacted with the first interdigitated region. This ensures that the drain region in the first well and the source region in the second well are in a normally open state. Compared with traditional depletion-type MOSFETs, the semiconductor structure of this application reduces the need for locally implanted ion implantation regions to form normally open current channels. The ion concentration in each region of the device is more uniform, the HCI effect of the device is not significant, and the reliability of the device can be improved. Moreover, the uniform ion concentration in each region of the device does not affect the breakdown voltage of the device, ensuring a higher breakdown voltage. It is not necessary to increase the device size to improve the breakdown voltage. Compared with existing devices, the device size is smaller, which can increase the device integration and reduce costs. The current channel required for the semiconductor structure is realized in the step of preparing the well (which is then used to prepare the drain region). No additional ion implantation step or additional photomask is required. Only the photomask originally used to prepare the well needs to be adapted and adjusted. This makes it compatible with the preparation method of ordinary MOS devices, further reducing the process cost of the product.

[0078] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of protection of the claims. Furthermore, specific examples have been used in the specification to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application, and the content of this specification should not be construed as a limitation of this application.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: The first well includes a first main well region and a plurality of first interdigitated regions extending outward from the first main well region, and the ions in the first well are uniformly distributed. The second well includes a second main well region and a plurality of second interdigitated regions extending outward from the second main well region. The ions in the second well are uniformly distributed and have the opposite conductivity type to the ions in the first well. The second interdigitated regions extend toward the first main well region, and the first interdigitated regions extend toward the second main well region. Each first interdigitated region and each second interdigitated region are interspersed with each other. The leak region is located within the first well; The source region is located within the second well and is in electrical contact with the first interdigitated region; The gate region is located above the first well and the second well.

2. The semiconductor structure according to claim 1, characterized in that, There is a gap between each of the first interdigital regions and each of the second interdigital regions.

3. The semiconductor structure according to claim 1, characterized in that, There is an overlapping area between each of the first interdigital regions and each of the second interdigital regions.

4. The semiconductor structure according to claim 1, characterized in that, There is a gap between the first interdigitated region and the second main well region.

5. The semiconductor structure according to claim 1, characterized in that, There is a gap between the second interdigitated region and the first main well region.

6. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a field plate located above the gate region and a portion of the first well, and extending above a portion of the drain region.

7. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes an active region, wherein both the first well and the second well are located within the active region.

8. The semiconductor structure according to claim 1, characterized in that, The source region is also located within a portion of the first interdigital region.

9. A method for preparing a semiconductor structure, used to prepare the semiconductor structure as described in any one of claims 1-8, characterized in that, The preparation method includes: A first well ion implantation and a second well ion implantation are performed on a semiconductor substrate. The conductivity type of the ions implanted in the second well is opposite to that of the ions implanted in the first well, forming a first well and a second well. The first well includes a first main well region and a plurality of first interdigitated regions extending outward from the first main well region. The second well includes a second main well region and a plurality of second interdigitated regions extending outward from the second main well region. The second interdigitated regions extend toward the first main well region, and the first interdigitated regions extend toward the second main well region. Each first interdigitated region and each second interdigitated region are interleaved with each other. A gate region is formed above the first well and the second well; Drain ion implantation is performed in the first well to form a drain region, and source ion implantation is performed in the second well to form a source region, wherein the source region is electrically contacted with the first interdigitated region.

10. The preparation method according to claim 9, characterized in that, The preparation method further includes: A field plate is formed above the gate region and a portion of the first well, the field plate extending above a portion of the drain region.

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