Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A pad is formed on an interlayer insulating film, and an insulating film is formed to cover the interlayer insulating film and the pad. An opening is formed in the insulating film to expose a portion of the pad. In the opening, a nickel plating film is formed on the pad, a first gold plating film is formed on the nickel plating film, and a second gold plating film is formed on the first gold plating film. The nickel plating film has a phosphorus concentration of 2% by mass or more and 7% by mass or less.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2023-212395, including the specification, drawings, and abstract, filed on December 15, 2023, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a method for manufacturing the same, and is suitably applicable to, for example, a semiconductor device including an electrode pad and a method for manufacturing the same. Background Art

[0004] The following-listed technologies are disclosed.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2020-120133

[0006] An OPM (on-pad metal) film is formed on an electrode pad in a semiconductor device. Patent Document 1 discloses a technique using a stacked film of a nickel plating layer and a gold plating layer as the OPM film.

[0007] In a semiconductor device including a pad and an OPM film, it is desired to improve its reliability.

[0008] Other problems and novel features will be apparent from the description and drawings of this specification.

[0009] According to an embodiment, a semiconductor device includes an electrode pad, a nickel plating film formed on the electrode pad in an opening of a passivation film, a first gold plating film formed on the nickel plating film, and a second gold plating film formed on the first gold plating film. The phosphorus concentration of the nickel plating film is 2 mass% or more and 7 mass% or less.

[0010] According to an embodiment, the reliability of the semiconductor device can be improved. Brief Description of the Drawings

[0011] Figure 1 is a top view of a semiconductor device according to a first embodiment;

[0012] Figure 2 is a rear view of a semiconductor device according to a first embodiment;

[0013] Figure 3 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment;

[0014] Figure 4 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment;

[0015] Figure 5is a cross-sectional view of a main part during steps of manufacturing a semiconductor device according to a first embodiment;

[0016] Figure 6 is from Figure 5 is a cross-sectional view of a main part during steps of manufacturing a semiconductor device continuing from the steps illustrated;

[0017] Figure 7 is from Figure 6 is a cross-sectional view of a main part during steps of manufacturing a semiconductor device continuing from the steps illustrated;

[0018] Figure 8 is from Figure 7 is a cross-sectional view of a main part during steps of manufacturing a semiconductor device continuing from the steps illustrated;

[0019] Figure 9 is the same as Figure 8 is a cross-sectional view of a main part during steps of manufacturing a semiconductor device the same as the steps illustrated;

[0020] Figure 10 is from Figure 8 is a cross-sectional view of a main part during steps of manufacturing a semiconductor device continuing from the steps illustrated;

[0021] Figure 11 is the same as Figure 10 is a cross-sectional view of a main part during steps of manufacturing a semiconductor device the same as the steps illustrated;

[0022] Figure 12 is from Figure 10 is a cross-sectional view of a main part during steps of manufacturing a semiconductor device continuing from the steps illustrated;

[0023] Figure 13 is the same as Figure 12 is a cross-sectional view of a main part during steps of manufacturing a semiconductor device the same as the steps illustrated;

[0024] Figure 14 is from Figure 12 is a cross-sectional view of a main part during steps of manufacturing a semiconductor device continuing from the steps illustrated;

[0025] Figure 15 is the same as Figure 14 is a cross-sectional view of a main part during steps of manufacturing a semiconductor device the same as the steps illustrated;

[0026] Figure 16 is an explanatory diagram of a displacement reaction occurring in an immersion Au plating process;

[0027] Figure 17 is from Figure 14Cross-sectional view of the main part during the steps of manufacturing a semiconductor device in which the illustrated steps continue;

[0028] Figure 18 is the same as Figure 17 Cross-sectional view of the main part during the steps of manufacturing a semiconductor device in which the illustrated steps continue;

[0029] Figure 19 Cross-sectional view of a semiconductor package according to the first embodiment;

[0030] Figure 20 Cross-sectional view of the main part of a semiconductor device in the first inspection example;

[0031] Figure 21 Cross-sectional view of the main part of a semiconductor device in the first inspection example;

[0032] Figure 22 Cross-sectional view of the main part during the steps of manufacturing a semiconductor device in the second inspection example;

[0033] Figure 23 is from Figure 22 Cross-sectional view of the main part during the steps of manufacturing a semiconductor device in which the illustrated steps continue;

[0034] Figure 24 Cross-sectional view of the main part of a semiconductor device in the third inspection example;

[0035] Figure 25 Cross-sectional view of the main part of a semiconductor device according to the first embodiment;

[0036] Figure 26 Graph showing the correlation between the thickness of the low-density layer formed in the surface layer part of the nickel plating film and the phosphorus concentration of the nickel plating film during the displacement plating Au process;

[0037] Figure 27 Table showing the correlation between the phosphorus concentration of the nickel plating film and the heat resistance of the nickel plating film;

[0038] Figure 28 Cross-sectional view of the main part during the steps of manufacturing a semiconductor device according to the second embodiment; and

[0039] Figure 29 is from Figure 28 Cross-sectional view of the main part during the steps of manufacturing a semiconductor device in which the illustrated steps continue. Detailed Description

[0040] In the embodiments described below, for convenience, the present invention will be described in multiple sections or embodiments when necessary. However, unless otherwise stated, these sections or embodiments are not independent of each other, and one section or embodiment relates to all or part of other sections or embodiments as its modified examples, details, or supplementary explanations. Moreover, in the embodiments described below, when referring to the number of elements (including the number of segments, values, quantities, ranges, etc.), the number of elements is not limited to a specific number unless otherwise stated or except in cases where the number is clearly limited to a specific number in principle. Quantities greater than or less than the specified number are also applicable. Further, in the embodiments described below, it goes without saying that unless otherwise stated or except in cases where the components (including element steps) are clearly indispensable in principle, the components are not always indispensable. Similarly, in the embodiments described below, when the shape of a component, its positional relationship, etc. are mentioned, substantially approximate and similar shapes, etc. are included therein, unless otherwise stated or except in cases where they can be clearly excluded in principle. The same applies to the above numerical values and ranges.

[0041] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that in all the drawings used to describe the embodiments, components having the same function are denoted by the same reference symbols, and their repeated description will be omitted. Additionally, in the following embodiments, unless particularly necessary, the description of the same or similar parts will not be repeated in principle.

[0042] Moreover, in some of the drawings used in the embodiments, even in sectional views, hatching may be omitted to make the drawings easier to view. Hatching may also be added in plan views to make the drawings easier to view.

[0043] (First Embodiment)

[0044] <Structure of Semiconductor Device>

[0045] A semiconductor device according to an embodiment will be described with reference to the accompanying drawings.

[0046] Figure 1 is a top view of a semiconductor device CP according to the present embodiment. Figure 2 is a rear view of a semiconductor device CP according to the present embodiment. Figure 3 and 4 Each of them is a sectional view of a main part of a semiconductor device CP according to the present embodiment. The sectional view taken along the line A - A illustrated in Figure 1 almost corresponds to Figure 3 and the sectional view taken along the line B - B illustrated in Figure 1 almost corresponds to Figure 4 .

[0047] AsFigures 1 to 4 As shown, the semiconductor device CP according to this embodiment includes a semiconductor substrate SB, an interlayer insulating film IL, a back surface electrode BE, a source pad PDS, a gate pad PDG, a gate wiring portion GEW, an insulating film PA, and a coating film PL. The semiconductor device CP further includes a trench gate electrode TG, an n-type semiconductor region NR formed in the semiconductor substrate SB, and a p-type semiconductor region PR formed in the semiconductor substrate SB.

[0048] The semiconductor substrate SB is made of, for example, n-type single crystal silicon doped with an n-type impurity such as arsenic (As). A semiconductor substrate (so-called epitaxial wafer) may also be used as the semiconductor substrate SB, which includes a substrate main body made of an n-type single crystal silicon substrate and an epitaxial layer made of n-type single crystal silicon formed on the substrate main body.

[0049] The semiconductor substrate SB has a main surface and a back surface opposite to the main surface. The interlayer insulating film IL is formed on the main surface of the semiconductor substrate SB, and the back surface electrode BE is formed on the back surface of the semiconductor substrate SB.

[0050] In the semiconductor substrate SB, a trench gate type MISFET (metal insulator semiconductor field effect transistor) is formed. The trench gate type MISFET has a trench gate structure. The trench gate structure corresponds to a gate electrode structure embedded in a trench formed in the substrate.

[0051] The specific configuration of the trench gate type MISFET formed in the semiconductor substrate SB will be described below.

[0052] A trench gate type MISFET forming a power transistor (power semiconductor element) is formed on the main surface of the semiconductor substrate SB. Specifically, a plurality of unit transistor cells Q1 are formed on the main surface of the semiconductor substrate SB. The plurality of unit transistor cells Q1 formed on the semiconductor substrate SB are connected in parallel to form a power transistor. Each of the unit transistor cells Q1 in the unit transistor cells Q1 is made of a trench gate type MISFET. Here, a planar region where the plurality of unit transistor cells Q1 forming the power transistor are formed on the main surface of the semiconductor substrate SB is called a transistor cell region.

[0053] The semiconductor substrate SB functions as a drain region for each unit transistor cell Q1 in the unit transistor cell Q1. A back surface electrode BE for the drain is formed on the back surface of the semiconductor substrate SB. The back surface electrode BE is formed on the entire back surface of the semiconductor substrate SB. The back surface electrode BE serves as a drain terminal. The back surface electrode BE is made of, for example, a stacked film of a titanium (Ti) film in contact with the semiconductor substrate SB, a nickel (Ni) film on the titanium film, and a gold (Au) film or a silver (Ag) film on the nickel film.

[0054] A p-type semiconductor region PR is formed in the semiconductor substrate SB in the transistor cell region. The p-type semiconductor region PR functions as a channel formation region for each unit transistor cell Q1 in the unit transistor cell Q1.

[0055] In the semiconductor substrate SB, an n-type semiconductor region (source region) NR is formed on the p-type semiconductor region PR. The n-type semiconductor region NR functions as a source region for each unit transistor cell Q1 in the unit transistor cell Q1. The p-type semiconductor substrate PR exists under the n-type semiconductor region NR. The conductivity of the semiconductor substrate SB between the p-type semiconductor region PR and the back surface electrode BE remains n-conductive type, and the semiconductor substrate SB functions as a drain region for each unit transistor cell Q1 in the unit transistor cell Q1.

[0056] A trench (groove) TR is formed in the main surface of the semiconductor substrate SB, and a trench gate electrode TG is embedded in the trench TR through a gate insulating film GF. The trench gate electrode TG is made of a conductor film, such as a doped polysilicon film embedded in the trench TR of the semiconductor substrate SB. The gate insulating film GF is formed on the bottom surface and the side surfaces of the trench TR. The gate insulating film GF is made of, for example, a silicon oxide film. Although not shown, the trench TR is formed to have, for example, a stripe pattern or a grid pattern on the main surface of the semiconductor substrate SB in a plan view.

[0057] The description of the plan view of the components of the semiconductor device CP corresponds to the case of observing a plane substantially parallel to the main surface of the semiconductor substrate SB on which the semiconductor device CP is formed.

[0058] The trench TR is formed to penetrate the n-type semiconductor region NR and the p-type semiconductor region PR from the main surface of the semiconductor substrate SB. The bottom surface of the trench TR is deeper than the bottom surface of the n-type semiconductor region NR and deeper than the bottom surface of the p-type semiconductor region PR.

[0059] Then, the structure of the layer above the semiconductor substrate SB will be described.

[0060] An interlayer insulating film IL is formed on the main surface of a semiconductor substrate SB to cover a trench gate electrode TG. The interlayer insulating film IL is made of, for example, a silicon oxide film.

[0061] The trench gate electrodes TG in a plurality of unit transistor cells Q1 are integrally connected to each other in a region not shown in the cross-sectional view of Figure 3 and 4 . A gate lead-out portion TGL integrally formed with each of the trench gate electrodes TG in the trench gate electrodes TG is formed above the main surface of the semiconductor substrate SB outside the trench TR through a gate insulating film GF (see Figure 4 ).

[0062] Contact holes CT1 and CT2 are formed in the interlayer insulating film IL. The contact hole CT1 is a contact hole for the source. In a plan view, the contact hole CT1 is arranged between adjacent trenches TR.

[0063] The contact hole CT2 is a contact hole for the gate. The contact hole CT2 is arranged on the gate lead-out portion TGL. A part of the gate lead-out portion TGL is exposed from the contact hole CT2.

[0064] A source pad (source electrode pad) PDS, a gate pad (gate electrode pad) PDG, and a gate wiring portion GEW are formed on the interlayer insulating film IL. The source pad PDS, the gate pad PDG, and the gate wiring portion GEW are each made of a patterned conductor film CD. The conductor film CD is made of a metal film mainly including aluminum (Al), and more specifically, an aluminum film or an aluminum alloy film.

[0065] The gate pad PDG and the gate wiring portion GEW are integrally formed. Therefore, the gate pad PDG and the gate wiring portion GEW are electrically connected to each other. The source pad PDS is separated from the gate pad PDG and the gate wiring portion GEW.

[0066] A part of the source pad PDS is embedded in the contact hole CT1 for the source. A part of the source pad PDS (i.e., the part embedded in the contact hole CT1 for the source) is referred to as a via portion for the source.

[0067] A part of the gate wiring portion GEW is embedded in the contact hole CT2 for the gate. A part of the gate wiring portion GEW (i.e., the part embedded in the contact hole CT2 for the gate) is referred to as a via portion for the gate.

[0068] The via portion for the gate is electrically connected to the gate lead-out portion TGL while being in contact therewith. The gate pad PDG is electrically connected to the trench gate electrode TG in each of the plurality of unit transistor cells Q1 through the gate wiring portion GEW, the via portion for the gate, and the gate lead-out portion TGL.

[0069] The source pad PDS is formed to cover the transistor cell region in a plan view.

[0070] The contact hole CT1 for the source penetrates the interlayer insulating film IL and the n-type semiconductor region NR to reach the p-type semiconductor region PR. Accordingly, the via portion for the source embedded in the contact hole CT1 for the source penetrates the interlayer insulating film IL and the n-type semiconductor region NR to reach the p-type semiconductor region PR. The via portion for the source contacts both the n-type semiconductor region NR and the p-type semiconductor region PR, and thus is electrically connected to both the n-type semiconductor region NR and the p-type semiconductor region PR.

[0071] The source regions (n-type semiconductor regions NR) and the channel formation regions (p-type semiconductor regions PR) in the plurality of unit transistor cells Q1 arranged in the transistor cell region are electrically connected to the common source pad PDS through a plurality of via portions for the source, respectively. In this case, the source pad PDS serves as a source wiring for electrically connecting the source regions (n-type semiconductor regions NR) in the plurality of unit transistor cells Q1 to each other. The source wiring for electrically connecting the source regions (n-type semiconductor regions NR) in the plurality of unit transistor cells Q1 to each other can be formed on the interlayer insulating film IL, and the source pad PDS can be formed in a layer above the source wiring. Similarly, the gate wiring portion GEW can be formed on the interlayer insulating film IL, and the gate pad PDG can be formed in a layer above the gate wiring portion GEW.

[0072] The insulating film PA is formed as a passivation film on the interlayer insulating film IL to cover a part of the source pad PDS, a part of the gate pad PDG, and the gate wiring portion GEW. The insulating film PA is a protective film in the uppermost layer of the semiconductor device CP. The insulating film PA is made of, for example, a resin film made of a polyimide resin or the like.

[0073] Openings OPS and OPG are formed in the insulating film PA. At least a part of the source pad PDS is exposed from the opening OPS of the insulating film PA. At least a part of the gate pad PDG is exposed from the opening OPG of the insulating film PA. The coating film PL is formed on each of the source pad PDS exposed from the opening OPS of the insulating film PA and the gate pad PDG exposed from the opening OPG of the insulating film PA.

[0074] The coated film PL is an OPM film. The upper surface of the insulating film PA and the upper surface of the coated film PL form the upper surface of the semiconductor device CP. The front surface of the back surface electrode BE forms the back surface of the semiconductor device CP. The gate wiring portion GEW is not exposed from the insulating film PA. The entire gate wiring portion GEW is covered with the insulating film PA. The coated film PL is not formed on the gate wiring portion GEW.

[0075] The coated film PL is selectively formed on the source pad PDS exposed from the opening OPS of the insulating film PA and on the gate pad PDG exposed from the opening OPG of the insulating film PA. That is, the coated film PL is formed on the source pad PDS in the opening OPS, and the coated film PL is formed on the gate pad PDG in the opening OPG. The coated film PL is not formed on each of the source pad PDS covered with the insulating film PA and the gate pad PDG covered with the insulating film PA.

[0076] The coated film PL is made of a stacked film of a nickel (Ni) plated film PL1 and a gold (Au) plated film PL2 formed on the nickel plated film PL1.

[0077] The nickel plated film PL1 is respectively formed on the source pad PDS to contact the source pad PDS in the opening OPS, and is formed on the gate pad PDG to contact the gate pad PDG in the opening OPG. The gold plated film PL2 is formed on the nickel plated film PL1 to contact the nickel plated film PL1.

[0078] The nickel plated film PL1 contains phosphorus (P). The phosphorus (P) concentration of the nickel plated film PL1 is 2% or more and 7% or less by mass, preferably 2% or more and 5.7% or less by mass, more preferably 2% or more and 4.0% or less by mass. Note that the unit "mass percentage" can be referred to as "weight percentage".

[0079] The gold plated film PL2 is made of a stacked film of a gold (Au) plated film PL2a formed on the nickel plated film PL1 and a gold (Au) plated film PL2b formed on the gold plated film PL2a. The gold plated film PL2a is a displacement gold plated film formed by a displacement plating Au (gold) process. The gold plated film PL2b is a reduction gold plated film formed by a reduction plating Au (gold) process. The gold plated film PL2a is formed on the nickel plated film PL1 to contact the nickel plated film PL1. The gold plated film PL2b is formed on the gold plated film PL2a to contact the gold plated film PL2a.

[0080] Therefore, the coated film PL is made of a stacked film including a nickel-plated film PL1, a gold-plated film PL2a formed on the nickel-plated film PL1, and a gold-plated film PL2b formed on the gold-plated film PL2a. The gold-plated film PL2b is positioned at the uppermost layer of the coated film PL. The upper surface of the gold-plated film PL2b forms the upper surface of the coated film PL.

[0081] The source pad PDS is formed to cover the transistor cell region in a plan view. Therefore, the area of the source pad PDS is larger than the area of the gate pad PDG. Accordingly, the area of the opening OPS is larger than the area of the opening OPG. The planar shape of each of the openings OPG and OPS is, for example, rectangular.

[0082] The combination of the source pad PDS and the coated film PL on the source pad PDS is referred to as a bonding pad BPS for the source. The combination of the gate pad PDG and the coated film PL on the gate pad PDG is referred to as a bonding pad BPG for the gate.

[0083] When connected to the bonding pad by solder, the nickel-plated film PL1 of the coated film PL serves as a barrier layer (solder barrier layer), which prevents the solder components from diffusing into the conductor film CD after passing through the coated film PL. The nickel-plated film PL1 also has a function of ensuring the bonding strength of the solder. The gold-plated film PL2 of the coated film PL is provided to prevent oxidation of the nickel-plated film PL1 and improve the wettability of the solder.

[0084] When performing wire bonding with the bonding pad, the gold-plated film PL2 has a function of facilitating wire connection.

[0085] In the semiconductor device CP having such a configuration, the operating current of the power transistor flows between the source pad PDS and the back surface electrode BE for the drain. That is, the operating current of the trench gate type MISFET formed in the transistor cell region flows in the thickness direction of the semiconductor substrate SB. Therefore, the trench gate type MISFET formed in the transistor cell region is a vertical transistor. Here, the vertical transistor corresponds to a transistor whose operating current flows in the thickness direction of the semiconductor substrate SB.

[0086] In the present embodiment, the case where the trench gate type MISFET is applied as a semiconductor element formed on or in the semiconductor substrate SB has been described. However, the present invention is not limited to this case, but another type of semiconductor element may also be formed on or in the semiconductor substrate SB.

[0087] For example, a trench gate type IGBT may also be formed in the semiconductor substrate SB instead of the trench gate type MISFET. If the trench gate type IGBT is applied, a p-type semiconductor substrate region for the collector is formed near the back surface of the semiconductor substrate SB. If the trench gate type IGBT is applied, the back surface electrode BE serves as the collector electrode, the n-type semiconductor region NR serves as the n-type semiconductor region for the emitter, and the source pad PDS serves as the emitter pad (the electrode pad for the emitter). The back surface electrode BE is made of, for example, a stacked film of an aluminum-silicon alloy (AlSi) film in contact with the semiconductor substrate SB, a nickel (Ni) film on the aluminum-silicon alloy (AlSi) film, and a gold (Au) film or a silver (Ag) film on the nickel film.

[0088] An LDMOSFET (lateral diffused metal oxide semiconductor field effect transistor) may also be formed in the semiconductor substrate SB instead of the trench gate type MISFET.

[0089] The semiconductor device CP may also have bonding pads other than the bonding pad BPS for the source and the bonding pad BPG for the gate. In this case, each of the bonding pads in the bonding pads is made of a pad (electrode pad) formed of a conductor film CD and a coating film PL formed on the pad.

[0090] This embodiment may also be applied to a case where a wiring structure (multi-layer wiring structure) including a plurality of wiring layers is formed on the main surface of the semiconductor substrate SB. In this case, pads are formed in the uppermost wiring layer among the plurality of wiring layers included in the wiring structure.

[0091] <Steps of manufacturing a semiconductor device>

[0092] The steps of manufacturing the semiconductor device CP according to this embodiment will be described with reference to Figures 5 to 18 Description. Figures 5 to 15 Each of FIGS. 17 and 18 is a cross-sectional view of a main part during the steps of manufacturing the semiconductor device CP according to this embodiment. Figure 16 is an explanatory diagram of a displacement reaction occurring in the displacement plating Au process. Figure 5 、 6 、7, 8, 10, 12, 14, and 17 each illustrate a cross-section corresponding to Figure 3 Corresponding. Figure 9 、 11 、13, 15, and 18 each illustrate a cross-section corresponding to Figure 4 Corresponding.

[0093] As Figure 5 Illustrated, a semiconductor substrate SB (semiconductor wafer) made of, for example, n-type single crystal silicon is prepared. An epitaxial wafer may also be used as the semiconductor substrate SB.

[0094] Then, as Figure 5 illustrated, a trench TR is formed on the main surface of a semiconductor substrate SB. The trench TR can be formed by a photolithography technique and an etching technique.

[0095] Then, a gate insulating film GF made of a thin silicon oxide film or the like is formed on the side surface and the bottom surface of the trench TR and on the main surface of the semiconductor substrate SB, for example, by a thermal oxidation method.

[0096] Then, a conductor film PS made of a polysilicon film or the like is formed on the main surface of the semiconductor substrate SB by a CVD method or the like to fill the trench TR.

[0097] Then, a photoresist pattern (not shown) is formed on a part of the conductor film PS, and then the conductor film PS is etched back by an anisotropic etching technique. By the etch-back, the conductor film PS remains in the trench TR and under the photoresist pattern, while the other conductor film PS is removed. Then, the photoresist pattern is removed. Thus, as Figure 6 illustrated, a trench gate electrode TG made of the conductor film PS remaining in the trench TR is formed. The above-mentioned gate lead-out portion TGL is made of the conductor film PS remaining under the photoresist pattern.

[0098] Then, as Figure 7 illustrated, a p-type semiconductor region PR is formed in the semiconductor substrate SB by an ion implantation method.

[0099] Then, an n-type semiconductor region NR is formed in the semiconductor substrate SB by an ion implantation method. The bottom surface of the p-type semiconductor region PR is shallower than the bottom surface of the trench TR. The bottom surface of the n-type semiconductor region NR is shallower than the bottom surface of the p-type semiconductor region PR. Thus, the trench TR penetrates the n-type semiconductor region NR and the p-type semiconductor region PR.

[0100] Then, as Figure 7 illustrated, an interlayer insulating film IL is formed to cover the trench gate electrode TG and the gate lead-out portion TGL on the main surface of the semiconductor substrate SB.

[0101] Then, as Figure 8 illustrated, while using a photoresist pattern (not shown) formed on the interlayer insulating film IL as an etching mask, the interlayer insulating film IL and the semiconductor substrate SB are etched, thereby forming a contact hole CT1 for a source electrode. The p-type semiconductor region PR and the n-type semiconductor region NR are exposed from the contact hole CT1 for the source electrode.

[0102] Then, as Figure 9As shown, while using another photoresist pattern (not shown) formed on the interlayer insulating film IL as an etching mask, the interlayer insulating film IL is etched to form a contact hole CT2 for the gate. The gate lead-out portion TGL is exposed from the contact hole CT2 for the gate.

[0103] Then, as Figure 8 and 9 shown, a conductor film CD mainly including aluminum (Al) is formed in the contact holes CT1 and CT2 and on the interlayer insulating film IL by a sputtering method or the like.

[0104] Then, the conductor film CD is patterned by photolithography and etching techniques to form a source pad PDS, a gate pad PDG, and a gate wiring portion GEW, as Figure 10 and 11 shown. The gate pad PDG and the gate wiring portion GEW are connected to each other and integrally formed.

[0105] The source pad PDS is formed on the interlayer insulating film IL, and a part of the source pad PDS (the via portion for the source) fills the contact hole CT1 for the source. The gate pad PDG and the gate wiring portion GEW are formed on the interlayer insulating film IL, and a part of the gate wiring portion GEW (the via portion for the gate) fills the contact hole CT2 for the gate.

[0106] The via portion for the source may also be formed by a step different from the step of forming the source pad PDS, and the via portion for the gate may also be formed by a step different from the step of forming the gate pad PDG. In this case, conductive plugs for filling the contact holes CT1 and CT2 are formed after the step of forming the contact holes CT1 and CT2 and before the step of forming the conductor film CD.

[0107] Then, as Figure 10 and 11 shown, an insulating film PA is formed as a passivation film on the interlayer insulating film IL to cover the source pad PDS, the gate pad PDG, and the gate wiring portion GEW.

[0108] Then, as Figure 12 and 13 shown, openings OPG and OPS are formed in the insulating film PA. For example, when forming the insulating film PA made of a photosensitive resin film and then exposing it to light and developing, the openings OPG and OPS can be formed. Alternatively, when forming the insulating film PA made of a resin film and then etching it using a photoresist pattern (not shown) on the insulating film PA as an etching mask, the openings OPG and OPS can be formed.

[0109] Then, asFigure 14 and 15 As shown in Figure 14 and 15 , a coating film PL is formed on the source pad PDS exposed from the opening OPS of the insulating film PA and the gate pad PDG exposed from the opening OPG of the insulating film PA by an electroplating method.

[0110] The coating film PL is made of a stacked film of a nickel plating film PL1, a gold plating film PL2a on the nickel plating film PL1, and a gold plating film PL2b on the gold plating film PL2a. Therefore, the step of forming the coating film PL includes the step of forming the nickel plating film PL1, the step of forming the gold plating film PL2a, and the step of forming the gold plating film PL2b. The step of forming the gold plating film PL2a is performed after the step of forming the nickel plating film PL1, and the step of forming the gold plating film PL2b is performed after the step of forming the gold plating film PL2a. The nickel plating film PL1, the gold plating film PL2a, and the gold plating film PL2b are formed by an electroplating method, specifically by an electroless plating method.

[0111] The nickel plating film PL1 is formed on the source pad PDS in the opening OPS to contact the source pad PDS, and is formed on the gate pad PDG in the opening OPG to contact the gate pad PDG.

[0112] The nickel plating film PL1 contains phosphorus (P). Therefore, the plating solution used in the step of forming the nickel plating film PL1 includes a nickel compound and a phosphorus compound. By adjusting the composition of the plating solution used, etc., the phosphorus (P) concentration of the nickel plating film PL1 can be controlled. The phosphorus (P) concentration of the nickel plating film PL1 is 2% or more and 7% or less by mass, preferably 2% or more and 5.7% or less by mass, more preferably 2% or more and 4.0% or less by mass.

[0113] The gold plating film PL2a is formed by a displacement plating Au (gold) process. In the step of forming the gold plating PL2a, a plating solution for displacement plating Au is used. When the surface of the nickel plating film PL1 comes into contact with the plating solution for displacement plating Au, the gold plating film PL2a is formed on the surface of the nickel plating film PL1.

[0114] In the displacement plating Au process, when the gold (Au) ions in the plating solution receive the electrons supplied by displacement with the nickel (Ni) included in the nickel plating film PL1 and are deposited as a gold (Au) coating film on the surface of the nickel plating film PL1, the gold plating film PL2a is formed.

[0115] Figure 16 is an explanatory diagram of the displacement reaction that occurs in the displacement plating Au process. As Figure 16As shown in the reaction formula, nickel (Ni) included in the nickel plating film PL1 is eluted into the plating solution and becomes nickel (Ni) ions. Then, gold (Au) ions in the plating solution are electrochemically reduced by the electrons thus generated. The chemically reduced gold (Au) is deposited as a coating film on the nickel plating film PL1, thereby forming a gold plating film PL2a.

[0116] The gold plating film PL2b is formed by a reduction plating Au process. In the step of forming the gold plating film PL2b, a plating solution for reduction plating Au is used. When the surface of the nickel plating film PL2a comes into contact with the plating solution for reduction plating Au, the gold plating film PL2b is formed on the surface of the gold plating film PL2a.

[0117] In the reduction plating Au process, when gold (Au) ions in the plating solution receive electrons supplied from a reducing agent in the plating solution and are deposited as a gold (Au) coating film on the surface of the nickel plating film PL2a, the gold plating film PL2b is formed.

[0118] Then, the back surface of the semiconductor substrate SB is ground or polished as needed to reduce the thickness of the semiconductor substrate SB.

[0119] Then, as Figure 17 and 18 shown, a back surface electrode BE is formed on the back surface of the semiconductor substrate SB. The back surface electrode BE can be formed by, for example, a sputtering method.

[0120] Then, the semiconductor substrate SB is cut by dicing. Thus, a semiconductor device CP as a semiconductor chip can be manufactured.

[0121] <Structure of semiconductor package>

[0122] Figure 19 is a cross-sectional view showing an example of a semiconductor package PKG using the semiconductor device CP.

[0123] For Figure 19 the semiconductor chip CP1 of the semiconductor package PKG shown, it is the same as the semiconductor device CP shown. Therefore, the description of the configuration of the semiconductor chip CP1 will not be repeated here. Figures 1 to 4

[0124] As Figure 19 shown, the semiconductor package PKG includes a semiconductor chip CP1, a die pad DP, a metal plate (conductor plate or clip) MP, leads LD, wires (bonding wirings) WA, and a sealing portion (sealing resin portion) MR.

[0125] The sealing portion MR is made of a resin material such as a thermosetting resin material and may also include fillers and the like.

[0126] ​The lead LD is made of a metallic material such as copper (Cu) or a copper alloy. A part of the lead LD (inner lead portion) is sealed in the sealing portion MR, and another part of the lead LD (outer lead portion) protrudes from the side surface of the sealing portion MR out of the sealing portion MR.

[0127] Although the semiconductor package PKG according to the present embodiment has a structure in which the outer lead portion of the lead LD protrudes from the side surface of the sealing portion MR and will be described based on this structure below, the present invention is not limited to such a structure. For example, the present invention can also adopt, for example, the following configuration, in which the lead LD hardly protrudes from the side surface of the sealing portion MR, and a part of the lead LD is exposed at the lower surface of the sealing portion MR (QFN type configuration).

[0128] The semiconductor chip CP1 is mounted on the upper surface of the die pad DP. The die pad DP is a chip mounting portion on which the semiconductor chip CP1 is mounted. The die pad DP is made of a metallic material such as copper (Cu) or a copper alloy.

[0129] The semiconductor chip CP1 is disposed on the upper surface of the die pad DP through a conductive bonding material (die bonding material) BD1 such that the back surface electrode BE of the semiconductor chip CP1 faces the upper surface of the die pad DP through the bonding material BD1. The bonding material BD1 is made of, for example, solder, silver (Ag) paste, or sintered Ag (sintered silver). Therefore, the back surface electrode BE of the semiconductor chip CP1 is electrically connected to the die pad DP through the conductive bonding material BD1. The semiconductor chip CP1 is sealed in the sealing portion MR and does not protrude from the sealing portion MR.

[0130] The bonding pad for the gate BPG of the semiconductor chip CP1 and the inner lead portion of the lead LD are electrically connected to each other through a wiring WA as a conductive connection member. Specifically, one end of the wiring WA is connected to the bonding pad for the gate BPG of the semiconductor chip CP1, and the other end of the wiring WA is connected to the inner lead portion of the lead LD. Therefore, one end of the wiring WA is connected to the gold plating film PL2b in the uppermost layer of the bonding pad BPG for the gate. The outer lead portion of the lead LD serves as an external terminal electrically connected to the bonding pad BPG for the gate of the semiconductor chip CP1. The wiring WA is a wire and is preferably made of a metallic wire such as a gold (Au) wire, a copper (Cu) wire, or an aluminum (Al) wire. The wiring WA is sealed in the sealing portion MR and does not protrude from the sealing portion MR.

[0131] The metal plate MP is bonded and fixed to the bonding pad BPS for the source of the semiconductor chip CP1 through the conductive bonding material BD2. The bonding material BD2 is made of solder, for example. The metal plate MP is electrically connected to the bonding pad BPS for the source of the semiconductor chip CP1 through the conductive bonding material BD2. Therefore, the metal plate MP is connected to the gold-plated film PL2b in the uppermost layer of the bonding pad BPS for the source through the bonding material BD2.

[0132] A part of the metal plate MP is exposed from the sealing portion MR. The metal plate MP exposed from the sealing portion MR serves as an external terminal electrically connected to the bonding pad BPS for the source of the semiconductor chip CP1.

[0133] The metal plate MP is made of a metal material such as copper (Cu) or a copper (Cu) alloy. The metal plate MP can also be made of aluminum (Al), an aluminum (Al) alloy, silver (Ag), or a silver (A) alloy. The width of the metal plate MP is greater than the diameter of the wiring WA. Therefore, the resistance of the metal plate MP is higher than that of the wiring WA. The metal plate MP is connected to the bonding pad BPS for the source of the semiconductor chip CP1. Therefore, the on-resistance of the power transistor formed in the semiconductor chip CP1 can be reduced. Therefore, in the semiconductor package PKG, the conduction loss can be reduced.

[0134] The semiconductor package PKG further includes a lead for the source (not shown), and the metal plate MP can also be electrically connected to the lead for the source through a conductive bonding material. In this case, the lead for the source serves as an external terminal electrically connected to the bonding pad BPS for the source of the semiconductor chip CP1. In this case, the metal plate MP is not exposed from the sealing portion MR.

[0135] The lower surface of the die pad DP is exposed from the lower surface of the sealing portion MR. The die pad DP exposed from the lower surface of the sealing portion MR serves as an external terminal electrically connected to the back surface electrode BE of the semiconductor chip CP1. Although the on-current (on-current) of the power transistor formed in the semiconductor chip CP1 mainly flows between the metal power supply MP and the die pad DP, the conduction loss can be reduced because the metal plate MP is used for the conduction path.

[0136] The heat generated during the operation of the semiconductor chip CP1 can be mainly released from the back surface of the semiconductor chip CP1 from the semiconductor package PKG through the bonding material BD1 and the die pad DP.

[0137] <Steps of manufacturing a semiconductor package>

[0138] The steps of manufacturing the semiconductor package PKG will be described.

[0139] Prepare a lead frame integrally including a die pad DP and leads LD. In the lead frame, the die pad DP and the leads LD are integrally connected to a frame (not shown) of the lead frame, respectively.

[0140] Then, perform a die bonding step to mount a semiconductor chip CP1 on the upper surface of the die pad DP of the lead frame through a conductive bonding material BD1. Accordingly, a back surface electrode BE of the semiconductor chip CP1 is bonded to the upper surface of the die pad DP through the conductive bonding material BD1. The bonding material BD1 is a die bonding material. Solder, silver (Ag) paste, sintered Ag (sintered silver), etc. can be used as the bonding material BD1.

[0141] The die bonding step includes a heating step. If the bonding material BD1 is solder, the heating step is a solder reflow step. If the bonding material BD1 is silver paste, the heating step is a heating step for curing or sintering the silver paste.

[0142] Then, perform a wire bonding step to connect a bonding pad BPG for a gate of the semiconductor chip CP1 and a lead LD of the lead frame to each other through a wire WA. In this case, one end of the wire WA is connected to the gold plating film PL2b in the uppermost layer of the bonding pad BPG for the gate. Note that the wire bonding step can also be performed after a step of bonding a metal plate MP to a bonding pad BPS for a source of the semiconductor chip CP1.

[0143] Then, the metal plate MP is bonded to a bonding pad BPS for a source of the semiconductor chip CP1 through a conductive bonding material BD2. The metal plate MP is connected to the gold plating film PL2b in the uppermost layer of the bonding pad BPS for the source through the bonding material BD2.

[0144] Then, perform a molding step to form a sealing portion MR. Then, separate the die pad DP and the leads LD from the lead frame, and bend an outer lead portion of the leads LD as needed. Accordingly, a semiconductor package PKG can be manufactured.

[0145] Although a case where the semiconductor package PKG includes one semiconductor chip CP1 has been described, the present invention is not limited thereto. The semiconductor package PKG may include a plurality of semiconductor chips.

[0146] <Background of the inspection>

[0147] The present inventors have examined the use of a stacked film of a nickel-plated film and a gold-plated film as an OPM film to be formed on a pad. Compared with the use of a stacked film of a nickel-plated film, a palladium-plated film, and a gold-plated film, the use of a stacked film of a nickel-plated film and a gold-plated film as an OPM film provides advantages such as more suppressing the formation cost of the OPM film. The present inventors have examined the use of a bonding material (silver paste) having a high sintering temperature (about 260 degrees Celsius to 300 degrees Celsius) as a die bonding material. Therefore, the present inventors have examined an OPM film that can withstand a heating step even at a high temperature of about 300 degrees Celsius.

[0148] Figure 20 is a cross-sectional view of the main part of the semiconductor device in the first examination example examined by the present inventors.

[0149] In Figure 20 and those described below Figure 21 、 22 、23, 24, 25, 28, and 29, a pad (electrode pad) PD mainly including aluminum (Al) is formed on the interlayer insulating film IL, and an insulating film (passivation film) PA is formed to cover the interlayer insulating film IL and the pad PD. An opening OP is formed in the insulating film PA to expose a part of the pad PD. The pad PD corresponds to the above-mentioned source pad PDS or gate pad PDG, and the opening OP corresponds to the above-mentioned opening OPS or opening OPG.

[0150] In the first examination example, as Figure 20 illustrated, an OPM film PL100 is formed on the pad PD in the opening OP of the insulating film PA. The OPM film PL100 is made of a stacked film of a nickel-plated film PL101 formed on the pad PD and a gold-plated film PL102 formed on the nickel-plated film PL101. The phosphorus concentration of the nickel-plated film PL101 is higher than the phosphorus concentration of the nickel-plated film PL1 in the present embodiment. For example, the phosphorus concentration of the nickel-plated film PL101 is about 9% by mass.

[0151] According to the examination performed by the present inventors, it was found that the first examination example has the following problems.

[0152] Due to various heating steps to be performed after the step of forming the OPM film, there is a risk of cracks appearing in the nickel-plated film PL101. Figure 21 Illustrated is the state in which cracks CR appear in the nickel-plated film PL101 in the semiconductor device in the first examination example.

[0153] The reason for the occurrence of cracks CR in the nickel-plated film PL101 is that by heating the nickel-plated film PL101 at a high temperature, Ni3P alloy is generated in the nickel-plated film PL101, thereby embrittling the nickel-plated film PL101 and making it easy for cracks CR to appear in the nickel-plated film PL101. The types of heating steps at high temperatures that cause the appearance of cracks CR include the sputtering step of forming the back surface electrode BE, the heating step of improving the bonding characteristics between the semiconductor substrate SB and the back surface electrode BE, the die bonding step of mounting the semiconductor chip on the die pad, and the bonding step of bonding the bonding pad BPS for the source and the metal plate MP in the case of using solder or the like. The occurrence of cracks CR in the nickel-plated film PL101 reduces the reliability of the semiconductor device.

[0154] <Main features and effects>

[0155] The present inventor has examined the phosphorus concentration of the nickel-plated film forming the OPM film. Therefore, it has been found that even when the nickel-plated film is heated at a high temperature, the generation of Ni3P alloy in the nickel-plated film can be suppressed or prevented by the low phosphorus concentration of the nickel-plated film. Therefore, the appearance of cracks in the nickel-plated film can be suppressed or prevented.

[0156] Therefore, in the present embodiment, the phosphorus concentration of the nickel-plated film PL1 is reduced. Specifically, the phosphorus concentration of the nickel-plated film PL1 is 2% or more and 7% or less by mass, preferably 2% or more and 5.7% or less by mass, and more preferably 2% or more and 4.0% or less by mass.

[0157] Therefore, the generation of Ni3P alloy in the nickel-plated film PL1 can be suppressed or prevented due to various heating steps to be performed after the step of forming the OPM film. Therefore, the appearance of cracks in the nickel-plated film PL1 can be suppressed or prevented. Therefore, the reliability of the semiconductor device can be improved.

[0158] However, according to the examination performed by the present inventor, it has been found that the low phosphorus concentration of the nickel-plated film PL1 causes the formation of a low-density layer (nickel low-density layer) LW in the nickel-plated film PL1 near the interface between the nickel-plated film PL1 and the gold-plated film on the nickel-plated film PL1.

[0159] Figure 22 and 23 Each of them is a cross-sectional view of the main part during the steps of manufacturing a semiconductor device in the second inspection example examined by the present inventor. Figure 22 Illustrates the state after forming the nickel-plated film PL1 and before forming the gold-plated film on the nickel-plated film PL1. Figure 23 Illustrates the state of forming the gold-plated film PL202 on the nickel-plated film PL1.

[0160] In the second inspection example, as can be seen fromFigure 22 and 23 As seen, an OPM film PL200 is formed on a pad PD in an opening OP of an insulating film PA. The OPM film PL200 is made of a stacked film of a nickel plating film PL1 formed on the pad PD and a gold plating film PL202 formed on the nickel plating film PL1. The gold plating film PL202 is formed by a displacement plating Au process. In the second inspection example, after the gold plating film PL202 is formed by the displacement plating Au process, a gold plating film is not formed on the gold plating film PL202 by an electroless plating Au process.

[0161] As Figure 23 shown, a low-density layer LW is formed in a layered form (continuously) in the nickel plating film PL1 near the interface between the nickel plating film PL1 and the gold plating film PL202. The density of nickel (Ni) atoms in the low-density layer LW is lower than the density of nickel (Ni) atoms in the nickel plating film PL1 below the low-density layer LW. As Figure 22 shown, the low-density layer LW is not formed at the stage of forming the nickel plating film PL1 by a nickel plating step. When the gold plating film is formed on the nickel plating film PL1 by an electroless plating Au process, the low-density layer LW is formed. The reason for forming the low-density layer LW is that during the electroless plating Au process, nickel atoms are eluted from the surface layer portion of the nickel plating film PL1 into the plating solution and become nickel ions. Since nickel is eluted from the surface layer portion of the nickel plating film PL1 into the plating solution, a low-density layer LW with a low density of nickel atoms is formed in the surface layer portion of the nickel plating film PL1.

[0162] The higher the phosphorus concentration of the nickel plating film, the higher the corrosion resistance of the nickel plating film. Therefore, if the phosphorus concentration of the nickel plating film PL101 is very high as described in the above first inspection example, it is difficult for nickel to be eluted from the nickel plating film PL101 into the plating solution during the electroless plating Au process for forming the gold plating film on the nickel plating film PL101. Therefore, if the phosphorus concentration of the nickel plating film PL101 is very high as described in the first inspection example, it is difficult to form a low-density layer LW in the nickel plating film PL101 near the interface between the nickel plating film PL101 and the gold plating film PL102.

[0163] However, if the phosphorus concentration of the nickel plating film PL1 is very low as described in this embodiment and the second inspection example, nickel is easily eluted from the nickel plating film PL1 into the plating solution during the electroless plating Au process for forming the gold plating film on the nickel plating film PL1. Therefore, a low-density layer LW is easily formed in the surface layer portion of the nickel plating film PL1.

[0164] The above wiring WA or metal plate MP is connected to a bonding pad made of a pad PD and an OPM film. When a low-density layer LW is formed in the OPM film, there is a risk of a reduction in the connection strength of the wiring WA or metal plate MP. For example, there is a risk of peeling of the wiring WA or metal plate MP connected to the bonding pad due to peeling starting from the low-density layer LW. This results in a reduction in the reliability of the semiconductor device. The greater the thickness of the low-density layer LW, the more likely peeling is to occur. Therefore, in the reduction plating Au process for forming a gold plating film on the nickel plating film PL1, it is desirable to suppress the thickness of the low-density layer LW formed in the surface layer portion of the nickel plating film PL1.

[0165] To suppress the thickness of the low-density layer LW formed in the surface layer portion of the nickel plating film PL, it is effective to suppress the thickness of the gold plating film formed on the nickel plating film PL1 by the reduction plating Au process. If the thickness of the gold plating film formed by the reduction plating Au process is small, then during the reduction plating Au process, the amount of nickel eluted from the nickel plating film PL1 into the plating solution decreases. Therefore, the thickness of the low-density layer LW formed in the surface layer portion of the nickel plating film PL1 decreases.

[0166] Figure 24 It is a cross-sectional view of the main part of the semiconductor device in the third inspection example examined by the present inventor.

[0167] In the third inspection example, as Figure 24 illustrated, an OPM film PL300 is formed on the pad PD in the opening OP of the insulating film PA. The OPM film PL300 is made of a stacked film of a nickel plating film PL1 formed on the pad PD and a gold plating film PL302 formed on the nickel plating film PL1. Similar to the gold plating film PL202 in the second inspection example, the gold plating film PL302 in the third inspection example is also formed by the displacement plating Au process. However, the thicknesses of the gold plating film PL202 in the second inspection example and the gold plating film PL302 in the third inspection example are different, and the thickness of the gold plating film PL302 is smaller than the thickness of the gold plating film PL202. In the third inspection example, after forming the gold plating film PL302 by the displacement plating Au process, similar to the second inspection example, a gold plating film is not formed on the gold plating film PL302 by the reduction plating Au process.

[0168] To reflect the fact that the thickness of the gold plating film PL302 in the third inspection example is smaller than the thickness of the gold plating film PL202 in the second inspection example, the thickness of the low-density layer LW formed in the third inspection example ( Figure 24 ) is smaller than the thickness of the low-density layer LW formed in the second inspection example ( Figure 23 ). Therefore, in the third inspection example ( Figure 24 ), similar to the second inspection example ( Figure 23)Compared with [the above], the occurrence of peeling starting from the low-density layer LW can be more suppressed, thereby more effectively preventing the reduction in the connection strength of the above-mentioned wiring WA or the metal plate MP due to the low-density layer LW.

[0169] However, in order to reflect the fact that the thickness of the gold plating film PL302 in the third inspection example is smaller than the thickness of the gold plating film PL202 in the second inspection example, during various heating steps to be performed after the step of forming the OPM film PL300 in the third inspection example ( Figure 24 ), there is a risk that nickel (Ni) in the nickel plating film PL1 penetrates through the gold plating film PL302 and extrudes to the surface of the gold plating film PL302. The types of heating steps at high temperatures that cause nickel to be extruded to the surface of the gold plating film PL302 include the sputtering step of forming the back surface electrode BE or the die bonding step of mounting a semiconductor chip on a die pad. The extrusion of nickel to the surface of the gold plating film PL302 results in a reduction in the connection strength between the above-mentioned wiring WA or the metal plate MP and the bonding pad.

[0170] Therefore, in the second inspection example ( Figure 23 ) where the thick gold plating film PL202 is formed on the nickel plating film PL1, a thick low-density layer LW is formed in the surface layer portion of the nickel plating film PL1. As a result, the connection strength of the wiring WA or the metal plate MP is reduced. On the other hand, in the third inspection example ( Figure 24 ) where the thin gold plating film PL302 is formed on the nickel plating film PL1, nickel is extruded to the front surface of the gold plating film PL302, thereby reducing the connection strength of the wiring WA or the metal plate MP. Therefore, in the second inspection example ( Figure 23 ) and the third inspection example ( Figure 24 ), the connection strength of the wiring WA or the metal plate MP is reduced. This leads to a reduction in the reliability of the semiconductor device.

[0171] Figure 25 is a cross-sectional view of the main part of the semiconductor device according to the present embodiment. In the present embodiment, as Figure 25 illustrated, a low-density layer LW is also formed in a layered form (continuously) in the nickel plating film PL1 near the interface between the nickel plating film PL1 and the gold plating film PL2a. The density of nickel (Ni) atoms in the low-density layer LW is lower than the density of nickel (Ni) atoms in the nickel plating film PL1 below the low-density layer LW.

[0172] In this embodiment, a gold plating film PL2a is formed on a nickel plating film PL1 by displacement gold plating, and a gold plating film PL2b is formed on the gold plating film PL2a by reduction gold plating. The gold plating film PL2 on the nickel plating film PL1 is made of a stacked film of the gold plating film PL2a and the gold plating film PL2b, thereby increasing the thickness of the gold plating film PL2 while suppressing the thickness of the gold plating film PL2a. Since the thickness of the gold plating film PL2a can be suppressed, the thickness of the low-density layer LW formed in the surface layer portion of the nickel plating film PL1 can be suppressed, and since the gold plating film PL2b is formed, the thickness of the gold plating film PL2 can be increased, thereby suppressing or preventing nickel from extruding onto the surface of the gold plating film PL2. Therefore, when the above wiring WA or metal plate MP is connected to a bonding pad made of the pad PD and the plating film PL, the connection strength of the wiring WA or the metal plate MP can be improved. Therefore, the reliability of the semiconductor device can be improved.

[0173] For example, assume that the thickness of the gold plating film PL2a in this embodiment ( Figure 25 ) is the same as the thickness of the gold plating film PL302 in the third inspection example, and the thickness of the gold plating film PL2 in this embodiment ( Figure 25 ) is the same as the thickness of the gold plating film PL202 in the second inspection example. In this case, the thickness of the low-density layer LW formed in the surface layer portion of the nickel plating film PL1 is the same between the third inspection example ( Figure 24 ) and this embodiment ( Figure 25 ). Therefore, in this embodiment ( Figure 25 ), compared with the second inspection example ( Figure 23 ), the thickness of the low-density layer LW formed in the surface layer portion of the nickel plating film PL1 can be more suppressed. Therefore, the occurrence of peeling starting from the low-concentration layer LW can be more suppressed, thereby more preventing a decrease in the connection strength of the wiring WA or the metal plate MP due to the low-density layer LW. In this embodiment ( Figure 25 ), the total thickness of the gold plating film formed on the nickel plating film PL1 can be increased more than that in the third inspection example ( Figure 24 ). Therefore, nickel extrusion onto the front surface of the gold plating film can be more suppressed, thereby more preventing a decrease in the connection strength of the wiring WA or the metal plate MP due to nickel extrusion. Therefore, in this embodiment ( Figure 25 ), when the wiring WA or the metal plate MP is connected to a bonding pad made of the pad PD and the OPM film, the connection strength of the wiring WA or the metal plate MP can be increased more than that in the second inspection example ( Figure 23 ) and the third inspection example ( Figure 24 ). Therefore, the reliability of the semiconductor device can be improved.

[0174] If a reduced gold plating film can be directly formed on the nickel plating film PL1 without forming a displacement gold plating film on the nickel plating film PL1, formation of a low-density layer LW in the surface layer portion of the nickel plating film PL1 can be prevented. However, it is difficult to directly form a reduced gold plating film on the nickel plating film PL1.

[0175] Therefore, a gold plating film PL2a that is formed in contact with the nickel plating film PL1 is formed by a displacement Au plating process. Thus, the gold plating film PL2a can be easily and accurately formed on the nickel plating film PL1. A gold plating film PL2b is formed on the gold plating film PL2a by a reduced Au plating process. Thus, the gold plating film PL2b can be easily and accurately formed on the gold plating film PL2a, and the thickness of the gold plating film PL2 can be increased. The gold plating film PL2b is formed to increase the overall thickness of the gold plating film PL2 without increasing the thickness of the low-density layer LW. Since the gold plating film PL2b is formed on the gold plating film PL2a, the thickness of the gold plating film PL2 can be increased while suppressing the thickness of the low-density layer LW. Accordingly, the connection strength of the wiring WA or the metal plate MP can be improved. Accordingly, the reliability of the semiconductor device can be improved.

[0176] In the present embodiment, the gold plating film PL2a is formed by a displacement Au plating process for directly forming on the nickel plating film PL1. However, when the gold plating film PL2a is formed, the low-density layer LW is formed. Therefore, it is preferable not to make the gold plating film PL2a thick. On the other hand, the gold plating film PL2b is formed to ensure the thickness of the gold plating film PL2. Therefore, it is preferable to make the gold plating film PL2b thick. In the present embodiment, half or more of the thickness of the gold plating film PL2 is preferably assigned to the gold plating film PL2b, and generally or less of the thickness of the gold plating film PL2 is preferably assigned to the gold plating film PL2a. In other words, the thickness of the gold plating film PL2b is preferably equal to or greater than the thickness of the gold plating film PL2a. Accordingly, the thickness of the gold plating film PL2 can be increased while the thickness of the low-density layer LW can be suppressed. Accordingly, the connection strength of the wiring WA or the metal plate MP can be improved. Accordingly, the reliability of the semiconductor device can be improved.

[0177] The reason for making the gold plating film PL2a thin is to make the low-density layer LW formed when the gold plating film PL2b is formed thin. The thinner the gold plating film PL2a, the thinner the low-density layer LW. In order to improve the connection strength between the wiring WA or the metal plate MP and the bonding pad, the thickness of the low-density layer LW is preferably 20 nm or less. Therefore, the thickness of the gold plating film PL2a is preferably set such that the thickness of the low-density layer LW is 20 nm or less.

[0178] However, when the thickness of the gold plating film PL2a is too small, it is difficult to form the gold plating film PL2b by a reduced Au plating process after the gold plating film PL2a is formed. From this perspective, the thickness of the gold plating film PL2a is preferably 10 nm or more.

[0179] If the thickness of the gold-plated film PL2 is too small, there is a risk that nickel (Ni) in the nickel-plated film PL1 reaches and extrudes to the surface of the gold-plated film PL2 during various heating steps to be performed after the step of forming the gold-plated film PL. From this perspective, the thickness of the gold-plated film PL2 is preferably 40 nm or more. On the other hand, if the thickness of the gold-plated film PL2 is too large, the time period taken for the step of forming the gold-plated film PL2 becomes longer, and the cost of forming the gold-plated film PL2 also becomes higher. From this perspective, the thickness of the gold-plated film PL2 is preferably 100 nm or less.

[0180] Therefore, although the thickness of the gold-plated film PL2b is preferably equal to or greater than the thickness of the gold-plated film PL2a, the thickness of the gold-plated film PL2a is more preferably 10 nm or more, and the sum of the thickness of the gold-plated film PL2a and the thickness of the gold-plated film PL2b is more preferably 40 nm or more and 100 nm or less. The thickness of the gold-plated film PL2a is preferably about 10 nm or more and 35 nm or less, although this depends on the thickness of the entire gold-plated film PL2.

[0181] The thickness of the nickel-plated film PL1 is greater than the thickness of the gold-plated film PL2, and is preferably 1 μm or more and 6 μm or less.

[0182] Figure 26 is a graph showing the correlation between the thickness of the low-density layer LW formed in the surface layer portion of the nickel-plated film and the phosphorus concentration of the nickel-plated film in the case of forming a displacement gold-plated film with a thickness of 50 nm on the nickel-plated film by a displacement plating Au process. No reduction gold-plated film is formed on the displacement gold-plated film. Figure 26 The horizontal axis of the illustrated graph corresponds to the phosphorus concentration of the nickel-plated film. Figure 26 The vertical axis of the illustrated graph corresponds to the thickness of the low-density layer LW formed in the surface layer portion (near the interface between the nickel-plated film and the displacement gold-plated film) of the nickel-plated film.

[0183] From Figure 26 As can be seen from the illustrated graph, when the phosphorus concentration of the nickel-plated film is 7% or less by mass, the lower the phosphorus concentration of the nickel-plated film, the greater the thickness of the low-density layer LW, and there is a tendency for the thickness of the low-density layer LW to exceed 20 nm. When the thickness of the low-density layer LW exceeds 20 nm, the connection strength between the wiring or the metal plate and the bonding pad is reduced, and there is a risk that the wiring or the metal plate peels off. Therefore, the thickness of the low-density layer LW is desirably set to 20 nm or less.

[0184] In this embodiment, the gold-plated film forming the OPM film is made of a stacked film of a displacement gold-plated film (PL2a) and a reduction gold-plated film (PL2b). Therefore, even when the phosphorus concentration of the nickel-plated film is 7% or less by mass, the thickness of the low-density layer LW can be suppressed, and the thickness of the low-density layer LW can be suppressed to 20 nm or less. For example, even when the thickness of the nickel-plated film is 50 nm and the phosphorus concentration of the nickel-plated film is 7% or less by mass, the thickness of the low-density layer LW can be suppressed to 20 nm or less. Therefore, applying this embodiment to the case where the phosphorus concentration of the nickel-plated film is 7% or less by mass provides a great effect.

[0185] Figure 27 is a table showing the correlation between the phosphorus concentration of a nickel-plated film and the heat resistance of the nickel-plated film in the case of using an OPM film made of a stacked film of a nickel-plated film and a gold-plated film on the nickel-plated film. Figure 27 The table shows the results obtained by the heat resistance inspection of the nickel-plated film in the respective cases where the phosphorus concentration of the nickel-plated film is 9% by mass, the phosphorus concentration of the nickel-plated film is 5.7% by mass, and the phosphorus concentration of the nickel-plated film is 4% by mass. In Figure 27 the table, the cases where cracks are generated in the OPM film due to the contact of the needle with the OPM film when the OPM film is heated at various heating temperatures are illustrated by cross marks, while the cases where no cracks are generated in the OPM film are illustrated by circle marks. Whether cracks have occurred has been verified by a microscope.

[0186] In the case where the phosphorus concentration of the nickel-plated film is 9% by mass, from Figure 27 the table, it is found that if the heating temperature is 290 °C or lower, cracks in the nickel-plated film can be prevented during heating. In the case where the phosphorus concentration of the nickel-plated film is 5.7% by mass, it is found that if the heating temperature is 315 °C or lower, cracks in the nickel-plated film can be prevented during heating. In the case where the phosphorus concentration of the nickel-plated film is 4% by mass, it is found that if the heating temperature is 330 °C or lower, cracks in the nickel-plated film can be prevented during heating. That is, the lower the phosphorus concentration of the nickel-plated film, the more the heat resistance of the nickel-plated film is improved. The reason for this is that even when the nickel-plated film is heated at a high temperature, the low phosphorus concentration in the nickel-plated film can suppress the formation of the Ni3P alloy in the nickel-plated film, thereby suppressing the occurrence of cracks in the nickel-plated film.

[0187] The present inventors have examined the use of a bonding material (silver paste) having a high sintering temperature (about 260 degrees Celsius to 300 degrees Celsius) as a die bonding material (bonding material BD1). Accordingly, the present inventors have examined an OPM film that can also withstand heating at a high temperature of about 300 degrees Celsius. When the phosphorus concentration of the nickel-plated film is 5.7% by mass, no cracks appear in the nickel-plated film even when heated at a temperature of 315 degrees Celsius, ensuring a 5% margin at 300 degrees Celsius (the maximum temperature of heating). When the phosphorus concentration of the nickel-plated film is 4.0% by mass, no cracks appear in the nickel-plated film even when heated at a temperature of 330 degrees Celsius, ensuring a 10% margin at 300 degrees Celsius (the maximum temperature of heating). Since the heat resistance of the OPM film is improved, the occurrence of cracks can be suppressed not only during the die bonding step and the bonding step for the bonding pad for the source, but also during the sputtering step for forming the back surface electrode BE and the heating step for improving the bonding characteristics between the semiconductor substrate and the back surface electrode BE, thereby increasing the yield.

[0188] Therefore, the phosphorus concentration of the nickel-plated film PL1 is preferably 5.7% or less by mass, and more preferably 4.0% by mass. Accordingly, the heat resistance of the nickel-plated film PL1 can be improved, and the occurrence of cracks in the nickel-plated film PL1 during heating can be reliably prevented. A bonding material (silver paste) having a high sintering temperature (about 260 degrees Celsius to 300 degrees Celsius) can also be used as the die bonding material (bonding material BD1).

[0189] On the other hand, when the phosphorus concentration of the nickel-plated film PL1 is too low, it is difficult to stably form the nickel-plated film PL1. Therefore, the phosphorus concentration of the nickel-plated film PL1 is preferably 2% or more by mass. Accordingly, the nickel-plated film PL1 can be easily and reliably formed.

[0190] (Second Embodiment)

[0191] Figure 28 and 29 Each of is a cross-sectional view of a main part during the steps of manufacturing a semiconductor device according to the second embodiment. Figure 28 Illustrates the state after forming the nickel-plated film PL1 and before forming the gold-plated film on the nickel-plated film PL1. Figure 29 Illustrates the state of forming the gold-plated film PL2 on the nickel-plated film PL1.

[0192] The semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment in the following points.

[0193] In the semiconductor device according to the second embodiment, the nickel plating film PL1 is made of a stacked film of a nickel plating film PL1a formed on the pad PD and a nickel plating film PL1b formed on the nickel plating film PL1a in the opening OP of the insulating film PA, as Figure 28 and 29 illustrated. The phosphorus (P) concentration of the nickel plating film PL1a is higher than that of the nickel plating film PL1b. Therefore, the step of forming the nickel plating film PL1 in the second embodiment includes the step of forming the nickel plating film PL1a on the pad PD and the step of forming the nickel plating film PL1b on the nickel plating film PL1a after this step. Except for the nickel plating film PL1, the semiconductor device according to the second embodiment has a configuration similar to that of the semiconductor device according to the first embodiment.

[0194] In the second embodiment, as Figure 28 illustrated, the nickel plating film PL1a is formed on the pad PD in the opening OP of the insulating film PA so as to be in contact with the pad PD. The nickel plating film PL1b is formed on the nickel plating film PL1a so as to be in contact with the nickel plating film PL1a. As Figure 29 illustrated, a gold plating film PL2a is formed on the nickel plating film PL1b by a displacement gold plating process so as to be in contact with the nickel plating film PL1b. A gold plating film PL2b is formed on the gold plating film PL2a by a reduction gold plating process so as to be in contact with the gold plating film PL2a.

[0195] In the second embodiment, as Figure 29 illustrated, the low-density layer LW is also formed during the displacement gold plating process for forming the gold plating film PL2a. The low-density layer LW is formed in a layered form (continuously) in the nickel plating film PL1b near the interface between the nickel plating film PL1b and the gold plating film PL2a. That is, the low-density layer LW is formed in the surface layer portion of the nickel plating film PL1b. The density of nickel (Ni) atoms in the low-density layer LW is lower than the density of nickel (Ni) atoms in the nickel plating film PL1b below the low-density layer LW.

[0196] The phosphorus concentration of each of the nickel plating films PL1a and PL1a is 2% or more and 7% or less by mass, preferably 2% or more and 5.7% or less by mass, and more preferably 2% or more and 4.0% or less by mass. Therefore, the generation of the Ni3P alloy in the nickel plating film PL1 due to various heating steps to be performed after the step of forming the coating film PL can be suppressed or prevented. Therefore, the occurrence of cracks in the nickel plating film PL1 can be suppressed or prevented. Therefore, the reliability of the semiconductor device can be improved.

[0197] The higher the phosphorus concentration of the nickel plating film, the higher the corrosion resistance of the nickel plating film. Therefore, the corrosion resistance of the nickel plating film PL1a is higher than that of the nickel plating film PL1b. The pad PD is made of the above-mentioned conductor film CD and thus includes aluminum (Al) as a main component.

[0198] After the step of forming the nickel plating film PL1, water or a gold plating solution may intrude along the interface between the pad PD and the nickel plating film PL1. If water or a gold plating solution intrudes along the interface between the pad PD and the nickel plating film PL1, there is a risk of corrosion of the nickel plating film PL1 near the interface between the pad PD and the nickel plating film PL1. If the nickel plating film PL1 is corroded near the interface between the pad PD and the nickel plating film PL1, the interface between the pad PD and the nickel plating film PL1 is likely to peel off. Therefore, the reliability of the semiconductor device is reduced. Moreover, there is a risk of an increase in the resistance between the wiring WA or the metal plate MP and the pad PD.

[0199] In the present embodiment, the nickel plating film PL1 is made of a stacked film of a nickel plating film PL1a and a nickel plating film PL1b on the nickel plating film PL1a, and the phosphorus concentration of the nickel plating film PL1a in contact with the pad PD is higher than that of the nickel plating film PL1b. The higher the phosphorus concentration of the nickel plating film, the higher the corrosion resistance of the nickel plating film. Therefore, when the phosphorus concentration of the nickel plating film PL1a is higher than that of the nickel plating film PL1b, corrosion of the nickel plating film PL1a near the interface between the pad PD and the nickel plating film PL1a can be suppressed or prevented. The lower the phosphorus concentration of the nickel plating film, the higher the heat resistance of the nickel plating film. Therefore, when the phosphorus concentration of the nickel plating film PL1b on the nickel plating film PL1a is lower than that of the nickel plating film PL1a, the heat resistance of the nickel plating film PL1b can be increased. Therefore, cracks in the nickel plating film PL1 due to various heating steps to be performed after the step of forming the coating film PL can be suppressed or prevented.

[0200] Therefore, in the second embodiment, corrosion of the nickel plating film PL1 near the interface between the pad PD and the nickel plating film PL1 and the occurrence of cracks in the nickel plating film PL1 can be suppressed or prevented. Therefore, the reliability of the semiconductor device can be further improved.

[0201] In the second embodiment, similar to the first embodiment, the gold plating film PL2 is also made of a stacked film of a gold plating film PL2a and a gold plating film PL2b on the gold plating film PL1a, thereby suppressing the thickness of the low-density layer LW and increasing the thickness of the gold plating film PL2. Therefore, when the above-mentioned wiring WA or the metal plate MP is connected to the bonding pad made of the pad PD and the coating film PL, the connection strength of the wiring WA or the metal plate MP can be increased. Therefore, the reliability of the semiconductor device can be improved.

[0202] In the foregoing, the present invention made by the inventors of the present application has been specifically described based on embodiments. However, needless to say, the present invention is not limited to the foregoing embodiments, and various modifications can be made within the scope of the present invention.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; an interlayer insulating film formed on a main surface of the semiconductor substrate; an electrode pad mainly comprising aluminum, formed on the interlayer insulating film; a passivation film formed to cover the interlayer insulating film and the electrode pad; an opening formed in the passivation film to expose a portion of the electrode pad; a nickel-plated film formed on the electrode pad in the opening; A first gold-plated film is formed on the nickel-plated film; as well as a second gold-plated film formed on the first gold-plated film, wherein the phosphorus concentration of the nickel plating film is 2% by mass or more and 7% by mass or less.

2. The semiconductor device according to claim 1, wherein the first gold-plated film is a displacement gold-plated film, and The second gold-plated film is a reduction gold-plated film.

3. The semiconductor device according to claim 1, wherein the phosphorus concentration of the nickel plating film is 2% by mass or more and 5.7% by mass or less.

4. The semiconductor device according to claim 1, wherein the phosphorus concentration of the nickel plating film is 2% by mass or more and 4.0% by mass or less.

5. The semiconductor device according to claim 1, The thickness of the second gold-plated film is the same as or greater than the thickness of the first gold-plated film.

6. The semiconductor device according to claim 5, The sum of the thickness of the first gold-plated film and the thickness of the second gold-plated film is greater than or equal to 40 nanometers and less than or equal to 100 nanometers.

7. The semiconductor device according to claim 6, The thickness of the first gold-plated film is greater than 10 nanometers.

8. The semiconductor device according to claim 1, The thickness of the nickel plating film is greater than 1 micrometer and less than 6 micrometers.

9. The semiconductor device according to claim 2, The first gold plating film is formed when Au ions receive electrons supplied by substitution with Ni and are deposited as a gold coating film on the surface of the nickel plating film.

10. The semiconductor device according to claim 2, The second gold-plated film is formed by Au ions being deposited as a gold coating film on the nickel-plated film when being supplied with electrons from a reducing agent.

11. The semiconductor device according to claim 2, wherein a nickel low-density layer is formed in the nickel-plated film near the interface between the nickel-plated film and the first gold-plated film, wherein the density of nickel atoms in the nickel low-density layer is lower than the density of nickel atoms in the nickel-plated film below the nickel low-density layer, and The thickness of the nickel low-density layer is less than 20 nanometers.

12. The semiconductor device according to claim 11, The nickel low-density layer is continuously formed in the interface between the nickel-plated film and the first gold-plated film.

13. The semiconductor device according to claim 1, wherein the nickel plated film is a stacked film of a first nickel plated film formed on the electrode pad and a second nickel plated film formed on the first nickel plated film, and The phosphorus concentration of the first nickel plating film is higher than the phosphorus concentration of the second nickel plating film.

14. The semiconductor device according to claim 1, further comprising: A wiring or a metal plate is connected to the second gold-plated film.

15. The semiconductor device according to claim 1, further comprising: a semiconductor element formed on or in the semiconductor substrate, The semiconductor element is a MISFET or an IGBT.

16. A method for manufacturing a semiconductor device, comprising the steps of: (a) forming an interlayer insulating film on a main surface of a semiconductor substrate; (b) forming an electrode pad mainly composed of aluminum on the interlayer insulating film; (c) forming a passivation film to cover the interlayer insulating film and the electrode pad; (d) forming an opening in the passivation film to expose a portion of the electrode pad; (e) forming a nickel plated film on the electrode pad in the opening; (f) forming a first gold-plated film on the nickel-plated film by a displacement Au plating process; as well as (g) forming a second gold-plated film on the first gold-plated film by a reduction Au plating process, wherein the phosphorus concentration of the nickel plating film is 2% by mass or more and 7% by mass or less.

17. The method for manufacturing the semiconductor device according to claim 16, wherein the phosphorus concentration of the nickel plating film is 2% by mass or more and 5.7% by mass or less.

18. The method for manufacturing the semiconductor device according to claim 16, wherein the phosphorus concentration of the nickel plating film is 2% by mass or more and 4.0% by mass or less.

19. The method for manufacturing the semiconductor device according to claim 16, The thickness of the second gold-plated film formed in the step (f) is the same as the thickness of the first gold-plated film formed in the step (g) or is greater than the thickness of the first gold-plated film.

20. The method for manufacturing the semiconductor device according to claim 16, wherein the nickel-plated film formed in the step (e) is a stacked film of a first nickel-plated film formed on the electrode pad and a second nickel-plated film formed on the first nickel-plated film, and The phosphorus concentration of the first nickel plating film is higher than the phosphorus concentration of the second nickel plating film.

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