An overvoltage-resistant and electromagnetic-interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure

Abstract

The present invention discloses an interconnected structure of an overvoltage-resistant and electromagnetic-interference-resistant SiC MOSFET field limiting ring and a microchannel, which relates to the field of power semiconductor device packaging. It includes a copper-coated ceramic substrate, a buffer layer, an SiC MOSFET chip, a lower substrate nano-silver solder layer, and a copper-coated ceramic substrate encapsulated in sequence from top to bottom. Among them, the SiC MOSFET chip includes a microchannel chip inlet, a microchannel chip outlet, an in-chip trench-type field limiting ring microchannel, a gate metal, a source metal, and a junction terminal. The present invention effectively improves the stability and reliability of the SiC MOSFET under overvoltage conditions, reduces electromagnetic interference at high operating frequencies, and enables it to better adapt to various power electronics application scenarios. Through the coupling packaging structure of the trench-type field limiting ring and the microchannel of the silicon nitride ceramic substrate, the heat dissipation efficiency during overvoltage impacts such as lightning strikes and switching overvoltages can be regulated.

Description

Technical Field

[0001] The present invention relates to the field of power semiconductor device packaging, and more particularly, to an overvoltage-resistant and electromagnetic interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure. Background Art

[0002] In the rapid development process of power electronics technology, SiC MOSFETs are widely used in many fields such as rail traction, new energy vehicles, new energy power generation, and industrial automation because they are superior to traditional silicon-based power devices in terms of voltage resistance, high temperature resistance, switching frequency, power density, power transmission loss, and stability. In these application scenarios, SiC MOSFETs need to cope with complex and variable electrical environments and working conditions. On the one hand, when the power system is subjected to lightning strikes, inductive load switching, grid faults, etc., various overvoltage conditions such as lightning overvoltage and switching overvoltage will be generated. These overvoltage stresses pose a serious threat to the stable operation of SiC MOSFETs and may cause internal electric field imbalance and breakdown damage. On the other hand, with the development of power electronics technology towards high frequency and high efficiency, during the high-frequency operation of SiC MOSFETs, the high-frequency harmonics caused by the parasitic inductance and capacitance of their own current loops will generate conducted electromagnetic interference and radiated electromagnetic interference, which will have a negative impact on the electromagnetic compatibility of surrounding electronic components and the entire system.

[0003] Specifically, most traditional SiC MOSFET packages follow the packaging mode of Si-based devices and are difficult to fully utilize the excellent performance of SiC MOSFETs, which is reflected in the following aspects:

[0004] 1. In terms of overvoltage resistance of SiC MOSFETs, when the power system faces lightning strikes, switching operations, etc., surges or switching overvoltages will be generated. Traditional packages lack targeted overvoltage protection design at the packaging level. When a SiC MOSFET with a traditional package is subjected to overvoltage impact, the internal electric field of the chip gets out of control, and the device is prone to exceed the critical breakdown electric field. A large amount of heat is generated near the critical breakdown electric field in a short time, forming a local high hot spot. It is difficult for the heat to dissipate quickly in a short time, resulting in local overheating of the SiC MOSFET, and then leading to electrical performance drift, accelerated aging, and shortened life. The terminal area of the SiC MOSFET is the area where high hot spots are likely to occur under overvoltage. Special heat dissipation design for the terminal area of the SiC MOSFET is crucial, but relevant research is very scarce. In addition, traditional SiC MOSFET packages usually use bonding wires and mainly dissipate heat from one side, which also limits the smoother transmission of heat flow.

[0005] 2. In terms of the electromagnetic interference resistance of SiC MOSFETs, the high-frequency switching of the device easily triggers the resonance of parasitic inductance and capacitance, generating high-frequency harmonics. The traditional power device packaging has insufficient control, and the harmonics interfere with the surrounding component devices through conduction and radiation. However, most of the traditional packaged SiC MOSFETs use bonding wires, and the harm of bonding wires is obvious. It additionally introduces parasitic inductance, exacerbates resonance, increases and strengthens high-frequency harmonics, and destroys the electromagnetic environment.

[0006] In response to the problems in the related technologies, no effective solution has been proposed yet. Summary of the Invention

[0007] In view of the deficiencies of the prior art, the present invention provides a field-limiting ring and microchannel interconnection structure for SiC MOSFETs with overvoltage and electromagnetic interference resistance, which has the advantages of enhancing the heat dissipation ability of SiC MOSFETs under overvoltage and reducing the parasitic parameters in the SiC MOSFET packaging, thereby solving the problem that most of the traditional SiC MOSFET packages follow the packaging mode of Si-based devices and it is difficult to fully exert the excellent performance of SiC MOSFETs.

[0008] To achieve the above advantages of enhancing the heat dissipation ability of SiC MOSFETs under overvoltage and reducing the parasitic parameters in the SiC MOSFET packaging, the specific technical solutions adopted by the present invention are as follows:

[0009] A field-limiting ring and microchannel interconnection structure for SiC MOSFETs with overvoltage and electromagnetic interference resistance, comprising a copper-coated ceramic substrate, a buffer layer, a SiC MOSFET chip, a lower substrate nano-silver solder layer, and a copper-coated ceramic substrate on the lower side, which are packaged in sequence from top to bottom;

[0010] Among them, the SiC MOSFET chip includes a microchannel chip inlet, a microchannel chip outlet, an in-chip trench-type field-limiting ring microchannel, a gate metal, a source metal, and a junction terminal.

[0011] Furthermore, the copper-coated ceramic substrate on the upper side includes an upper substrate copper-coated layer, an upper Si3N4 layer, a lower copper-coated layer of the upper substrate, a source terminal, and a gate terminal; the buffer layer includes an upper nano-silver solder layer, a molybdenum block buffer layer, an epoxy resin filling layer, and a lower nano-silver solder layer; the copper-coated ceramic substrate on the lower side includes a lower substrate copper-coated layer, a lower Si3N4 layer, a copper-coated layer of the lower substrate, and a drain terminal.

[0012] Further, the upper Si3N4 layer is a flat cuboid; a microchannel chip inlet connecting pipe and a microchannel chip outlet connecting pipe are provided on one side of the bottom of the upper Si3N4 layer; a first microchannel and a second microchannel are provided on both sides inside the upper Si3N4 layer, and a microchannel inlet and a microchannel outlet are provided on one side of the upper Si3N4 layer away from the microchannel chip inlet connecting pipe. The first microchannel is communicated with the microchannel inlet, and the second microchannel is communicated with the microchannel outlet.

[0013] Further, both the first microchannel and the second microchannel are continuous S-shaped curved structures; the outermost edges of the S-shaped curved turning points on one side close to the microchannel inlet and the microchannel outlet in the upper Si3N4 layer are aligned vertically with the edges of the source metal.

[0014] Further, a microchannel chip inlet connecting pipe via hole and a microchannel chip outlet connecting pipe via hole are provided on one side of the copper-clad layer under the upper substrate; the gate terminal is located above one side of the copper-clad layer under the upper substrate and between the microchannel chip inlet connecting pipe via hole and the microchannel chip outlet connecting pipe via hole, and the source terminal is located at the bottom of the other side of the copper-clad layer under the upper substrate; the gate terminal is located under the upper Si3N4 layer and is closely connected, and there is no contact between the gate terminal and the copper-clad layer under the upper substrate, and the source terminal is closely connected to the copper-clad layer under the upper substrate.

[0015] Further, the upper nano-silver solder layer includes an upper gate metal corresponding area solder layer directly above the gate metal and an upper source metal corresponding area solder layer directly above the source metal; the molybdenum block buffer layer includes a gate metal corresponding area molybdenum column directly above the gate metal and a source metal corresponding area molybdenum column directly above the source metal; the lower nano-silver solder layer includes a lower gate metal corresponding area solder layer directly above the gate metal and a lower source metal corresponding area solder layer directly above the source metal; the epoxy resin filling layer is located in the gaps between the upper nano-silver solder layer, the molybdenum block buffer layer, the lower nano-silver solder layer and the copper-clad layer under the upper substrate, and the gaps are tightly filled.

[0016] Further, the source metal is two L-shaped hexagons that are symmetric in shape and position. The gate metal is located between the corners of the two source metals, and the source metal and the gate metal do not contact each other; the junction terminal is a rectangular ring, and the junction terminal surrounds the gate metal and the source metal in the center. The microchannel chip inlet and the microchannel chip outlet are located at the top of the junction terminal close to the gate metal and are symmetric on both sides of the gate metal.

[0017] Further, the SiC MOSFET chip further includes a drain metal, an N + -type 4H-SiC substrate, and an N - -drift layer that are adjacent to each other from bottom to top. The N - -drift layer is located below the junction terminal; a terminal P + -region is provided at the inner bottom of the junction terminal, and N- The upper plane of the drift layer is provided with a plurality of grooves that match the terminal P + region, and the grooves are arranged in a rectangular ring shape in sequence from the inside to the outside of the junction terminal, and each groove is in the N - The upper plane of the drift layer is tightly surrounded by the terminal P + region, and the grooves are filled with a SiO2 layer.

[0018] Furthermore, terminal P well regions and P well regions are distributed on the upper surface of the N - drift layer and below the source metal. The terminal P well regions and the P well regions are not adjacent to each other. A terminal source P + region is provided at the top of the terminal P well region close to the edge of the source metal; Anode P + region and source N + region are provided at the part of the junction terminal far from the edge of the source metal, and the source P + region and the source N + region are surrounded by the P well region.

[0019] Furthermore, the trench-type field limiting ring microchannel in the chip starts from the microchannel chip inlet, passes through the interconnected trenches, and reaches the microchannel chip outlet to form a microchannel structure; The junction between the P well region and the upper surface of the N - drift layer is a conductive channel, and gate polysilicon is provided above the conductive channel; Inside the junction terminal, part of the SiO2 layer above the N - drift layer outside the trench-type field limiting ring microchannel and the trench region together enclose the trench-type field limiting ring microchannel in the chip.

[0020] Compared with the prior art, the present invention provides an overvoltage-resistant and electromagnetic-interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure, which has the following beneficial effects:

[0021] (1) By designing an overvoltage-resistant and electromagnetic-interference-resistant SiC MOSFET trench-type overvoltage-resistant and electromagnetic-interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure, the stability and reliability of the SiC MOSFET under overvoltage conditions are effectively improved, the electromagnetic interference at high operating frequencies is reduced, and it can better adapt to various power electronics application scenarios; Through the trench-type field limiting ring and silicon nitride ceramic substrate microchannel coupling and packaging structure, combined with the terminal area heat dissipation design, the heat dissipation efficiency of the SiC MOSFET when suffering from overvoltage impacts such as lightning strikes and switching overvoltages can be regulated, the overvoltage resistance of the device is significantly enhanced, the risk of performance degradation and device damage caused by overvoltage is greatly reduced, the heat generated by the device during overvoltage or normal operation is quickly removed, the temperature is balanced, and the reliable and stable operation of the device is ensured.

[0022] (2) The trench-type overvoltage and electromagnetic interference resistant SiC MOSFET field limiting ring and microchannel interconnection structure has no wire bonding, effectively reducing the parasitic inductance of the device package, effectively suppressing the high-frequency harmonics generated by parasitic parameters, thus significantly reducing electromagnetic interference and meeting the usage requirements of power devices in power systems for high frequency, high voltage, and high reliability. At the same time, the leadless package that eliminates the bonding wire also weakens the heat dissipation obstacle, making the heat conduction smoother and more direct, improving the heat dissipation efficiency, and enhancing the heat dissipation and operation stability under complex working conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0024] Figure 1 is an overall view of the overvoltage and electromagnetic interference resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to an embodiment of the present invention;

[0025] Figure 2 is one of the exploded views of the overvoltage and electromagnetic interference resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to an embodiment of the present invention;

[0026] Figure 3 is another exploded view of the overvoltage and electromagnetic interference resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to an embodiment of the present invention;

[0027] Figure 4 is a sectional view showing the upper copper-clad ceramic substrate and its structure of the overvoltage and electromagnetic interference resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to an embodiment of the present invention;

[0028] Figure 5 is a partial enlarged view of the upper copper layer, lower copper layer of the upper substrate, and gate terminal of the overvoltage and electromagnetic interference resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to an embodiment of the present invention;

[0029] Figure 6 is Figure 5 a partial enlarged view at D in

[0030] Figure 7 is one of the oblique top views of the upper Si3N4 layer of the overvoltage and electromagnetic interference resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to an embodiment of the present invention;

[0031] Figure 8It is the second inclined upward view of the upper Si3N4 layer in the overvoltage-resistant and electromagnetic interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to an embodiment of the present invention;

[0032] Figure 9 It is the first transparent inclined upward view of the upper Si3N4 layer in the overvoltage-resistant and electromagnetic interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to an embodiment of the present invention;

[0033] Figure 10 It is the second transparent inclined upward view of the upper Si3N4 layer in the overvoltage-resistant and electromagnetic interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to an embodiment of the present invention;

[0034] Figure 11 It is the lower substrate nano-silver solder layer in the overvoltage-resistant and electromagnetic interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to an embodiment of the present invention;

[0035] Figure 12 It is the lower copper-clad ceramic substrate and its structural layering schematic diagram in the overvoltage-resistant and electromagnetic interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to an embodiment of the present invention;

[0036] Figure 13 It is the first inclined upward view of the lower Si3N4 layer in the overvoltage-resistant and electromagnetic interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to an embodiment of the present invention;

[0037] Figure 14 It is the second inclined upward view of the lower Si3N4 layer in the overvoltage-resistant and electromagnetic interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to an embodiment of the present invention;

[0038] Figure 15 It is the first transparent inclined upward view of the lower Si3N4 layer in the overvoltage-resistant and electromagnetic interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to an embodiment of the present invention;

[0039] Figure 16 It is the second transparent inclined upward view of the lower Si3N4 layer in the overvoltage-resistant and electromagnetic interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to an embodiment of the present invention;

[0040] Figure 17 It is the buffer layer and its structural layering schematic diagram in the overvoltage-resistant and electromagnetic interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to an embodiment of the present invention;

[0041] Figure 18It is the overall chip structure diagram and the schematic diagram of the area where the microchannel is located after the chip is split up and down in the anti-overvoltage and anti-electromagnetic interference SiC MOSFET field limiting ring and microchannel interconnection structure according to the embodiments of the present invention;

[0042] Figure 19 It is the cross-sectional view of the chip junction terminal in the anti-overvoltage and anti-electromagnetic interference SiC MOSFET field limiting ring and microchannel interconnection structure according to the embodiments of the present invention;

[0043] Figure 20 It is Figure 19 The schematic diagram of the structure at point A (the cross-sectional structure of the junction terminal at the entrance and exit of the microchannel chip);

[0044] Figure 21 It is Figure 19 The schematic diagram of the structure at point B (the cross-sectional structure of the junction terminal at the edge of the source metal);

[0045] Figure 22 It is Figure 19 The schematic diagram of the structure at point C (the cross-sectional structure of the junction terminal at the edge of the gate metal);

[0046] Figure 23 It is the temperature distribution diagram of the device under the condition of no heat dissipation packaging when the power of the SiC MOSFET chip is 0.19W under overvoltage conditions according to the embodiments of the present invention;

[0047] Figure 24 It is the temperature distribution diagram of the device under the existing silver sintered double-sided heat dissipation packaging technology when the power of the SiC MOSFET chip is 5W under overvoltage conditions according to the embodiments of the present invention;

[0048] Figure 25 It is the temperature distribution diagram of the present invention when the power of the SiC MOSFET chip is 5W and the liquid convection coefficient in the microchannel is 1000W / (m²·K) under overvoltage conditions according to the embodiments of the present invention;

[0049] Figure 26 It is the comparison schematic diagram between the comparative example and the present invention according to the embodiments of the present invention.

[0050] In the figure:

[0051] 1. Copper layer on the upper substrate; 2. Upper Si3N4 layer; 3. Copper layer under the upper substrate; 4. Upper nano - silver solder layer; 5. Molybdenum block buffer layer; 6. Epoxy resin filling layer; 7. Lower nano - silver solder layer; 8. SiC MOSFET chip; 9. Nano - silver solder layer on the lower substrate; 10. Copper layer on the upper side of the lower substrate; 11. Lower Si3N4 layer; 12. Copper layer on the lower substrate; 13. Source terminal; 14. Gate terminal; 15. Drain terminal; 16. Micro - channel chip inlet connecting pipe; 17. Micro - channel chip outlet connecting pipe; 18. Micro - channel chip inlet connecting pipe via hole; 19. Micro - channel chip outlet connecting pipe via hole; 20. Solder layer in the corresponding area of the upper gate metal; 21. Solder layer in the corresponding area of the upper source metal; 22. Molybdenum column in the corresponding area of the gate metal; 23. Molybdenum column in the corresponding area of the source metal; 24. Solder layer in the corresponding area of the lower gate metal; 25. Solder layer in the corresponding area of the lower source metal; 26. Gate metal; 27. Source metal; 28. Micro - channel chip inlet; 29. Micro - channel chip outlet; 30. Junction terminal; 31. Chip - internal trench - type field - limiting ring micro - channel; 32. Micro - channel inlet; 33. First micro - channel; 34. Second micro - channel; 35. Micro - channel outlet; 36. Lower micro - channel inlet; 37. Third micro - channel; 38. Fourth micro - channel; 39. Lower micro - channel outlet; 40. SiO2 layer; 41. Terminal P + region; 42. N - drift layer; 43. N + type 4H - SiC substrate; 44. Drain metal; 45. Terminal P - well region; 46. Terminal source P+ region; 47. Gate polysilicon; 48. P - well region; 49. Source P + region; 50. Source N + region. Detailed implementation manners

[0052] To further illustrate each embodiment, the present invention provides drawings. These drawings are part of the disclosure of the present invention. They are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principle of the embodiments. With reference to these contents, those of ordinary skill in the art should be able to understand other possible implementation manners and the advantages of the present invention. The components in the figures are not drawn to scale, and similar component symbols are usually used to represent similar components.

[0053] According to an embodiment of the present invention, there is provided a SiC MOSFET field - limiting ring and micro - channel interconnection structure with over - voltage and electromagnetic interference resistance.

[0054] Some related terms explanation: In a SiC MOSFET (Silicon Carbide Metal - Oxide - Semiconductor Field - Effect Transistor) chip, the P + region is the main region doped with p - type. The material is SiC. P - type doping is achieved by doping with aluminum (Al) or boron (B). P - type doping is common knowledge in the semiconductor field.

[0055] N + The N region is a high-concentration main region with n-type doping. The material is SiC. The n-type doping is achieved by doping with nitrogen (N) or phosphorus (P), and n-type doping is common knowledge in the semiconductor field.

[0056] The N-drift layer is a low-concentration region with n-type doping. The material is SiC. The n-type doping is achieved by doping with nitrogen (N) or phosphorus (P), and n-type doping is common knowledge in the semiconductor field.

[0057] The P-well region is located below the source metal and is formed by p-type doping (such as doping with aluminum). Together with the N+ source region, it constitutes the longitudinal structure of the MOSFET and is used to control the channel formation. The P-well region is common knowledge in the semiconductor field.

[0058] Silicon nitride is an inorganic substance with the chemical formula Si3N4.

[0059] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. As Figures 1 - 3 shown, the overvoltage-resistant and electromagnetic-interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to an embodiment of the present invention includes a copper-ceramic substrate covered on the upper side, a buffer layer, an SiC MOSFET chip 8, a lower substrate nano-silver solder layer 9, and a copper-ceramic substrate covered on the lower side, which are encapsulated in sequence from top to bottom;

[0060] Among them, the SiC MOSFET chip 8 includes a microchannel chip inlet 28, a microchannel chip outlet 29, an in-chip trench-type field limiting ring microchannel 31, a gate metal 26, a source metal 27, and a junction terminal 30.

[0061] In one embodiment, the copper-ceramic substrate covered on the upper side includes an upper substrate upper copper layer 1, an upper Si3N4 layer 2, an upper substrate lower copper layer 3, a source terminal 13, and a gate terminal 14; the buffer layer includes an upper nano-silver solder layer 4, a molybdenum block buffer layer 5, an epoxy resin filling layer 6, and a lower nano-silver solder layer 7; the copper-ceramic substrate covered on the lower side includes a lower substrate upper copper layer 10, a lower Si3N4 layer 11, a lower substrate copper layer 12, and a drain terminal 15.

[0062] In one embodiment, as Figures 4 - 6 shown, the upper Si3N4 layer 2 is a flat cuboid; one side of the bottom of the upper Si3N4 layer 2 is provided with a microchannel chip inlet connection pipe 16 and a microchannel chip outlet connection pipe 17; two sides inside the upper Si3N4 layer 2 are provided with a first microchannel 33 and a second microchannel 34, and one side of the upper Si3N4 layer 2 away from the microchannel chip inlet connection pipe 16 is provided with a microchannel inlet 32 and a microchannel outlet 35. The first microchannel 33 is communicated with the microchannel inlet 32, and the second microchannel 34 is communicated with the microchannel outlet 35.

[0063] Specifically, the copper-clad layer 3 under the upper substrate includes via holes 18 for the inlet connecting pipe of the microchannel chip, via holes 19 for the outlet connecting pipe of the microchannel chip, and the area of the copper-clad layer 3 under the upper substrate corresponding to the upper part of the source metal 27 in the SiC MOSFET chip 8. The copper-clad layer 3 under the upper substrate is vertically aligned with the outer contour edge of the top view pattern of the source metal 27 in the SiC MOSFET chip 8.

[0064] The copper-clad layer 1 on the upper substrate is above and closely connected to the upper Si3N4 layer 2. The upper Si3N4 layer 2 is above and closely connected to the copper-clad layer 3 under the upper substrate. The gate terminal 14 is below and closely connected to the upper Si3N4 layer 2. The gate terminal 14 has no contact with the area of the copper-clad layer 3 under the upper substrate, and the tail end of the gate terminal 14 is vertically aligned with the upper and lower edges of the top view pattern of the gate metal 26 in the SiC MOSFET chip 8.

[0065] The source terminal 13 is closely connected to the copper-clad layer 3 under the upper substrate, and the gate terminal 14 has the same thickness and height as the source terminal 13 and the copper-clad layer 3 under the upper substrate. The inlet connecting pipe 16 of the microchannel chip and the outlet connecting pipe 17 of the microchannel chip extend from the lower plane of the upper Si3N4 layer 2 and pass through the via holes 18 for the inlet connecting pipe of the microchannel chip and the via holes 19 for the outlet connecting pipe of the microchannel chip respectively.

[0066] The outer walls of the inlet connecting pipe 16 of the microchannel chip and the outlet connecting pipe 17 of the microchannel chip are respectively in contact with the inner walls of the holes of the microchannel chip inlet 28 and the microchannel chip outlet 29 in the SiC MOSFET chip 8.

[0067] In one embodiment, as Figures 7 - 10 shown, both the first microchannel 33 and the second microchannel 34 are continuous S-shaped curved structures; the outermost edges of the S-shaped curved turns on the side close to the microchannel inlet 32 and the microchannel outlet 35 in the upper Si3N4 layer 2 are vertically aligned with the edge of the source metal 27.

[0068] Specifically, the upper Si3N4 layer 2 is a flat cuboid, and the microchannel inlet 32 and the microchannel outlet 35 in the upper Si3N4 layer 2 are located on the same side of the upper Si3N4 layer 2. The inlet of the first microchannel 33 in the upper Si3N4 layer 2 is the microchannel inlet 32 in the upper Si3N4 layer 2, and the outlet of the microchannel 34 in the upper Si3N4 layer 2 is the microchannel outlet 35 in the upper Si3N4 layer 2. The shapes of these two parts of the microchannels are continuously S-shaped bends, and the bends of the pipes are evenly distributed. The width of the microchannel is equal to the width of the source metal region on the side of the SiC MOSFET chip 8 close to the inlet and outlet of the microchannel in the upper Si3N4 layer 2. The outermost edges of the S-shaped bends on the side close to the microchannel inlet 32 and the microchannel outlet 35 in the upper Si3N4 layer 2 are aligned vertically with the edges of the source metal. The microchannel chip inlet connecting pipe 16 and the microchannel chip outlet connecting pipe 17 are respectively connected to the microchannel 33 in the upper Si3N4 layer 2 and the microchannel 34 in the upper Si3N4 layer 2 in an up-and-down communication manner.

[0069] In one embodiment, a microchannel chip inlet connecting pipe via 18 and a microchannel chip outlet connecting pipe via 19 are provided on one side of the upper substrate copper-clad layer 3; the gate terminal 14 is located above one side of the upper substrate copper-clad layer 3 and between the microchannel chip inlet connecting pipe via 18 and the microchannel chip outlet connecting pipe via 19, and the source terminal 13 is located at the bottom of the other side of the upper substrate copper-clad layer 3; the gate terminal 14 is located below the upper Si3N4 layer 2 and is closely connected, and the gate terminal 14 has no contact with the upper substrate copper-clad layer 3, and the source terminal 13 is closely connected to the upper substrate copper-clad layer 3.

[0070] Specifically, the microchannel inlet 32 in the upper Si3N4 layer 2, the microchannel 33 in the upper Si3N4 layer 2, the microchannel chip inlet connecting pipe 16, the microchannel chip inlet 28, the in-chip trench field limiting ring microchannel 31, the microchannel chip outlet 29, the microchannel chip outlet connecting pipe 17 in the upper Si3N4 layer 2, the microchannel 34 in the upper Si3N4 layer 2, and the microchannel outlet 35 in the upper Si3N4 layer 2 are sequentially connected to form a heat dissipation microchannel, and the microchannel is filled with a paraffin material.

[0071] In one embodiment, as Figures 17 - 18As shown, the upper nano-silver solder layer 4 includes an upper gate-metal corresponding region solder layer 20 directly above the gate metal 26 and an upper source-metal corresponding region solder layer 21 directly above the source metal 27; the molybdenum block buffer layer 5 includes a gate-metal corresponding region molybdenum column 22 directly above the gate metal 26 and a source-metal corresponding region molybdenum column 23 directly above the source metal 27; the lower nano-silver solder layer 7 includes a lower gate-metal corresponding region solder layer 24 directly above the gate metal 26 and a lower source-metal corresponding region solder layer 25 directly above the source metal 27; the epoxy resin filling layer 6 is located in the gaps among the upper nano-silver solder layer 4, the molybdenum block buffer layer 5, the lower nano-silver solder layer 7 and the upper substrate copper-clad layer 3, and the gaps are tightly filled.

[0072] Specifically, the gate metal 26 in the SiC MOSFET chip 8, the lower gate-metal corresponding region solder layer 24 in the lower nano-silver solder layer 7 above the gate metal, the gate-metal corresponding region molybdenum column 22 in the molybdenum block buffer layer 5, and the upper gate-metal corresponding region solder layer 20 in the upper nano-silver solder layer 4 are aligned at the upper and lower edges, adjacent and closely arranged in sequence from bottom to top, and the top-view patterns are all rectangles with the same shape and size.

[0073] The source metal 27 on the SiC MOSFET chip 8, the lower source-metal corresponding region solder layer 25 in the lower nano-silver solder layer 7 above the source metal, the source-metal corresponding region molybdenum column 23 in the molybdenum block buffer layer 5, and the upper source-metal corresponding region solder layer 21 in the upper nano-silver solder layer 4 are aligned at the upper and lower edges, adjacent and closely arranged in sequence from bottom to top, and the top-view patterns have the same shape and size, and the patterns are two L-shaped hexagons that are symmetric in shape and position.

[0074] In one embodiment, the source metal 27 is two L-shaped hexagons that are symmetric in shape and position, the gate metal 26 is located between the corners of the two source metals 27, and the source metal 27 and the gate metal 26 do not contact each other; the junction terminal 30 is a rectangular ring, and the junction terminal 30 surrounds the gate metal 26 and the source metal 27 in the center, and the microchannel chip inlet 28 and the microchannel chip outlet 29 are located at the top of the junction terminal 30 close to the gate metal 26 and are symmetric about both sides of the gate metal 26.

[0075] Specifically, the gate metal 26 is closely connected to the lower gate-metal corresponding region solder layer 24 in the lower nano-silver solder layer 7, and the top-view patterns have the same shape and size, and the shapes are all square.

[0076] The source metal 27 is closely connected to the lower source-metal corresponding region solder layer 25 in the lower nano-silver solder layer 7, and the top-view patterns have the same shape and size, and the patterns are two L-shaped hexagons that are symmetric in shape and position.

[0077] In one embodiment, as Figures 19 - 22As shown, the SiC MOSFET chip 8 further includes a drain metal 44, an N + -type 4H-SiC substrate 43, and an N - drift layer 42 that are adjacent to each other from bottom to top. The N - drift layer 42 is located below the junction termination 30. At the inner bottom of the junction termination 30, a terminal P + region 41 is provided. On the upper plane of the N - drift layer 42, a number of grooves are provided that cooperate with the terminal P + region 41. The grooves are arranged in a rectangular ring shape in sequence from the inner side to the outer side of the junction termination 30. Each groove is tightly surrounded by the terminal P - region 41 on the upper plane of the N + drift layer 42, and the groove is filled with a SiO2 layer 40.

[0078] Specifically, on the upper plane of the N - drift layer 42, a number of grooves are distributed in the junction termination region. The grooves are arranged in sequence from the inner side to the outer side of the chip and are in a rectangular ring shape in a top view. The width value of each rectangular ring is equal to and fixed with the corresponding groove width value.

[0079] The groove widths corresponding to the microchannel chip inlet 28 and the microchannel chip outlet 29 are 5 - 20 μm, which is larger than the widths of other grooves. The widths of other grooves are 0.5 - 3 μm. The spacings of all the grooves are equal, and the spacing is 0.6 - 10 μm. The grooves in the part of the rectangular ring surrounding the source metal 27 are interconnected in the junction termination cross-section, forming the cross-section of the in-chip grooved field limiting ring microchannel 31. The in-chip grooved field limiting ring microchannel 31 starts from the microchannel chip inlet 28, passes through the interconnected grooves, and reaches the microchannel chip outlet 29, forming a microchannel structure. The grooves in the part of the rectangular ring surrounding the gate metal 26 are not interconnected in the junction termination cross-section, and the grooves are filled with a SiO2 layer. Each groove is tightly surrounded by the terminal P - region 41 on the upper plane of the N - drift layer 42, and the surrounding thickness is 0.5 - 1 μm. In a part of the junction termination 30 region, the SiO2 layer 40 is respectively located above the N - drift layer 42 inside the in-chip grooved field limiting ring microchannel 31 and outside the groove region, and together with the groove, closes the in-chip grooved field limiting ring microchannel 31.

[0080] In one embodiment, on the upper surface of the N - drift layer 42 and below the source metal 27, a terminal P well region 45 and a P well region 48 are distributed. The terminal P well region 45 and the P well region 48 are not adjacent. At the top of the terminal P well region 45 on the side close to the edge of the source metal 27, a terminal source P + region 46 is provided; at the part of the junction termination 30 far from the edge of the source metal 27, a source P + region 49 and a source N+ Region 50, and source P + Region 49 and source N + Region 50 is surrounded by the P-well region 48.

[0081] In one embodiment, the trench-type field-limiting ring microchannel 31 in the chip starts from the microchannel chip inlet 28, passes through the interconnected trenches, and reaches the microchannel chip outlet 29, forming a microchannel structure; the P-well region 48 and N - The junction at the upper surface of the drift layer 42 is the conductive channel, and gate polysilicon 47 is disposed above the conductive channel. Inside the junction terminal 30, the SiO2 layer 40 and the trench located above the drift layer 42 together enclose the trench-type field-limiting ring microchannel 31 in the chip. - The part of the SiO2 layer 40 above the drift layer 42 and the trench together enclose the trench-type field-limiting ring microchannel 31 in the chip.

[0082] Specifically, the source P away from the metal edge + Region 49 and source N + Region 50 are adjacent to each other on the left and right, and the source P + Region 49 and source N + Region 50 is surrounded by the P-well region 48 and is connected to the source metal 27 above. The SiO2 layer 40 below the source metal 27 is adjacent to the N - Drift layer 42, and the gate polysilicon 47 is surrounded by the SiO2 layer 40 below the source metal 27. The junction at the upper surface of the P-well region 48 and the N - Drift layer 42 is the conductive channel of the SiC MOSFET, and the corresponding gate polysilicon 47 is above it. The conductive channel and the gate polysilicon 47 are separated by the SiO2 layer 40.

[0083] As Figure 11 shown, the lower substrate nano-silver solder layer 9 is located below the SiC MOSFET chip 8, with the upper and lower edges aligned and closely arranged, and the top-down pattern is a square with the same shape and size. The lower substrate nano-silver solder layer 9 is located above the lower substrate copper-clad layer 10, with the upper and lower edges aligned and closely arranged, and the top-down pattern is a square with the same shape and size.

[0084] In one embodiment, as Figure 12 shown, the lower copper-clad ceramic substrate and the upper copper-clad ceramic substrate have the same composition structure, that is, the lower copper-clad ceramic substrate includes the lower substrate copper-clad layer 10, the lower Si3N4 layer 11, the lower substrate copper-clad layer 12, and the drain terminal 15. Among them, the lower substrate copper-clad layer 10 is closely connected to the drain terminal 15, with the same thickness and on the same horizontal plane. The substrate copper-clad layer 10, the lower Si3N4 layer 11, and the lower substrate copper-clad layer 12 are adjacent to each other from top to bottom and closely arranged, and the top-down pattern is a square with the same shape and size.

[0085] As Figures 13 - 16As shown, the lower Si3N4 layer 11 includes a microchannel inlet 36 in the lower Si3N4 layer 11, a microchannel 37 in the lower Si3N4 layer 11, a fourth microchannel 38 in the lower Si3N4 layer 11, and a lower microchannel outlet 39 in the lower Si3N4 layer 11. Among them, the lower Si3N4 layer 11 is a flat cuboid, and the lower microchannel inlet 36 and the lower microchannel outlet 39 in the lower Si3N4 layer 11 are located on the same side of the lower Si3N4 layer 11. The inlet of the third microchannel 37 in the lower Si3N4 layer 11 is the microchannel inlet 36 in the lower Si3N4 layer 11, and the outlet of the fourth microchannel 38 in the lower Si3N4 layer 11 is the lower microchannel outlet 39 in the lower Si3N4 layer 11. The shapes of these two parts of the microchannels are continuously S-shaped bends, and the bends of the pipeline are evenly distributed. The width of the microchannel is equal to the width of the source metal region on the side of the SiC MOSFET chip 8 close to the inlet and outlet of the microchannel in the lower Si3N4 layer 11. The outermost edges of the S-shaped bends on the side close to the lower microchannel inlet 36 and the lower microchannel outlet 39 in the lower Si3N4 layer 11 are aligned with the edges of the source metal up and down. The third microchannel 37 in the lower Si3N4 layer 11 communicates with the fourth microchannel 38 in the lower Si3N4 layer 11 in the region under the gate metal 26.

[0086] To facilitate the understanding of the above technical solutions of the present invention, the working principle or operation mode of the present invention in the actual process will be described in detail below.

[0087] In practical applications, the trench field limiting ring and silicon nitride ceramic substrate microchannel interconnection and coupling heat dissipation technology. The microchannel inlet 32 in the upper Si3N4 layer 2, the first microchannel 33 in the upper Si3N4 layer 2, the microchannel chip inlet connecting pipe 16 in the upper Si3N4 layer 2, the microchannel chip inlet 28, the trench field limiting ring microchannel 31 in the chip, the microchannel chip outlet 29, the microchannel chip outlet connecting pipe 17 in the upper Si3N4 layer 2, the second microchannel 34 in the upper Si3N4 layer, and the microchannel outlet 35 in the upper Si3N4 layer 2 are connected in sequence to form a heat dissipation microchannel, and the microchannel is filled with paraffin material.

[0088] Junction terminal 30 and trench field limiting ring microchannel 31 in the chip are designed. The junction terminal 30 includes a terminal P + region 41, a part of the SiO2 layer 40 in the junction terminal 30 region, the trench field limiting ring microchannel 31 in the chip, the microchannel chip inlet 28, and the microchannel chip outlet 29. N -The upper plane of the drift layer 42 is distributed with a number of grooves in the junction terminal region. The grooves are arranged in sequence from the inner side to the outer side of the chip, presenting a rectangular ring shape in the top view. The width value of each rectangular ring is equal to and fixed with the corresponding groove width value. The groove widths corresponding to the microchannel chip inlet 28 and the microchannel chip outlet 29 are 5 - 20 μm, which is larger than the widths of other grooves. The widths of other grooves are 3 - 10 μm. The spacing between all grooves is equal, and the spacing is 2.4 - 10 μm. The grooves in the part of the rectangular ring surrounding the source metal 27 are interconnected in the junction terminal cross-section, forming the cross-section of the in-chip grooved field-limiting ring microchannel 31. The in-chip grooved field-limiting ring microchannel 31 starts from the microchannel chip inlet 28, passes through the interconnected grooves, and reaches the microchannel chip outlet 29, forming a microchannel structure. The grooves in the part of the rectangular ring surrounding the gate metal 26 are not interconnected, and the grooves are filled with the SiO2 layer. Each groove is in N - The upper plane of the drift layer 42 is tightly surrounded by the terminal P + region 41, and the surrounding thickness is 0.5 - 1 μm. In a part of the junction terminal 30 region, the SiO2 layer 40 is respectively located above the in-chip grooved field-limiting ring microchannel 31 and the N in the area outside the groove - drift layer 42, and together with the groove, closes the in-chip grooved field-limiting ring microchannel 31. The interconnected grooves in the part surrounding the source metal form the in-chip grooved field-limiting ring microchannel, realizing the efficient circulation of the coolant to take away heat; the grooves in the part surrounding the gate metal are filled with the SiO2 layer and are not interconnected, preventing electrical interference and ensuring the chip withstand voltage performance at the same time.

[0089] The gate-source metal and the silicon nitride ceramic substrate microchannel coupling heat dissipation structure. The inlet of the microchannel 33 in the upper Si3N4 layer is the microchannel inlet 32 in the upper Si3N4 layer 2, and the outlet of the microchannel 34 in the upper Si3N4 layer is the microchannel outlet 35 in the upper Si3N4 layer 2. The shapes of these two parts of the microchannel are continuously S-shaped bends, and the bends of the pipeline are evenly distributed. The width of the microchannel is equal to the width of the source metal region on the side of the inlet and outlet of the microchannel in the upper Si3N4 layer close to the SiC MOSFET chip 8. The outermost edges of the S-shaped bends at the sides close to the microchannel inlet 32 and the microchannel outlet 35 in the upper Si3N4 layer 2 are aligned with the edges of the source metal up and down. The microchannel chip inlet connecting pipe 16 and the microchannel chip outlet connecting pipe 17 are respectively connected to the first microchannel 33 in the upper Si3N4 layer 2 and the second microchannel 34 in the upper Si3N4 layer up and down.

[0090] It can be seen that the microchannel inlet 32 in the upper Si3N4 layer 2, the first microchannel 33 in the upper Si3N4 layer 2, the microchannel chip inlet connecting pipe 16 in the upper Si3N4 layer 2, the microchannel chip inlet 28, the in-chip trench-type field limiting ring microchannel 31, the microchannel chip outlet 29, the microchannel chip outlet connecting pipe 17 in the upper Si3N4 layer 2, the second microchannel 34 in the upper Si3N4 layer, and the microchannel outlet 35 in the upper Si3N4 layer 2 are connected in sequence to form a heat dissipation microchannel, and the paraffin material is filled in the microchannel.

[0091] The device can achieve efficient heat transfer in the on-state. Through the designed multi-layer composite structure, the heat of the device can be quickly conducted from the SiC MOSFET chip 8 to each heat dissipation component in the on-state. The heat generated when the chip is turned on is first diffused outward through its own substrate (such as the N + -type 4H-SiC substrate 43, the N - drift layer 42) and the metal layers (gate metal 26, source metal 27). The molybdenum block buffer layer 5, the upper nano-silver solder layer 4, and the lower nano-silver solder layer 7 in the buffer layer efficiently transfer the heat to the upper copper-ceramic substrate 1 and the lower copper-ceramic substrate 12 by virtue of their good thermal conductivity. The copper layers in the upper and lower copper-ceramic substrates further disperse the heat and finally transfer it to the microchannel in the upper Si3N4 layer 2 to maintain a low-temperature working environment for the chip. The microchannel system runs through the entire structure to form a complete coolant circulation path. The microchannels in the upper Si3N4 layer 2 and the lower Si3N4 layer 11 are continuously S-shaped bends. The outermost edges of the S-shaped bends on one side of the microchannel inlet 32 and the microchannel outlet 35 in the upper Si3N4 layer 2 are aligned vertically with the edges of the source metal, so that the shape of the microchannel is adapted to the source metal. The heat generation area of the chip in the on-state is concentrated in the chip area where the source metal is located. There are corresponding microchannel areas above and below each position in the area where the source metal of the chip is located, and the heat is quickly exported through a shorter distance and a shorter path. The S-shaped bend not only increases the contact area between the coolant and the wall surface, making the heat exchange more sufficient, but also promotes the natural convection of the coolant. In addition, the package is a leadless package that eliminates bonding leads, removing heat dissipation obstacles, making the heat conduction smoother and more direct. The flow of the coolant accelerates the heat removal, greatly improving the heat dissipation efficiency and effectively solving the overheating problem of the chip during high-power operation in the on-state.

[0092] In the off-state of the device, the junction termination region can achieve efficient heat transfer and enhanced high electric field tolerance. In the N -Grooves with a certain width and spacing are distributed on the drift layer 42. The grooves are arranged in sequence from the inner side to the outer side of the chip. The grooves surrounding the source metal 26 are connected to form the in-chip grooved field limiting ring microchannel 31. When the chip withstands overvoltage, due to the concentration of the electric field in the terminal region, avalanche current or high leakage current is generated under high electric field, triggering local hot spots with high power density. The in-chip grooved field limiting ring microchannel 31 in the chip just constitutes a part of the coolant circulation path of the microchannel system, and can export the heat generated by the local hot spots through the microchannel system. At the same time, each groove is in N - The upper plane of the drift layer 42 is tightly surrounded by the terminal P + region 41, and the surrounding thickness is 0.5 - 1 μm. A grooved field limiting ring structure is formed at the junction terminal 30 in the SiC MOSFET chip 8. When the device operates in the blocking state at high voltage, peak electric fields are formed at the corners of multiple terminal P+ regions, and the concentrated electric field is distributed to each corner of the terminal P+ region, increasing the breakdown voltage of the terminal region and the tolerance to high electric fields. The groove widths corresponding to the microchannel chip inlet 28 and the microchannel chip outlet 29 are 5 - 20 μm, which are larger than the widths of other grooves, and the widths of other grooves are 0.5 - 3 μm. This makes the peak electric fields at the corners of the terminal P + regions corresponding to the microchannel chip inlet 28 and the microchannel chip outlet 29 the strongest. When the chip withstands overvoltage, the heat density generated by the local hot spots here is the highest, and the microchannels of the grooves here are wider and closer to the outlet and inlet of the microchannel, and can specifically export this part of the heat more quickly, ensuring the stable operation of the chip in a high-voltage environment. The grooves surrounding the gate metal 26 are filled with the SiO2 layer 40, which plays a role in enabling the coolant to flow smoothly through the grooved field limiting ring microchannels at the edge of the entire source region.

[0093] Paraffin is a phase change material with a melting point between 50 and 100 °C. When the device generates heat severely, the paraffin will melt into a coolant, and the microchannel system uses the flow of the liquid paraffin to carry away the heat. When the operating temperature of the device is low or the device is not working, the paraffin is solid, and can play a supporting role for the microchannels in the chip grooves and the substrate, preventing the material from collapsing and blocking the microchannels, especially the fine in-chip grooved field limiting ring microchannel 31.

[0094] The device structure has the ability to resist electromagnetic interference. The device package is a leadless package that cancels the bonding leads. The upper and lower edges of the corresponding molybdenum blocks in the source metal and the buffer layer are aligned and tightly connected. The upper and lower edges of the corresponding molybdenum blocks in the gate metal and the buffer layer are aligned and tightly connected. This enables the current to reach the source terminal and the gate terminal along the shortest path, reducing the values of parasitic inductance and parasitic resistance.

[0095] In addition, as Figures 23 - 25 shown, Figure 23Proportional example 1 is provided: Under overvoltage conditions, when the power of the SiC MOSFET chip is 0.19 W, the temperature distribution of the device under the condition of no heat dissipation packaging. Figure 24 Proportional example 2 is provided: Under overvoltage conditions, when the power of the SiC MOSFET chip is 5 W, the temperature distribution of the device under the existing silver sintered double-sided heat dissipation packaging technology. Figure 25 Under overvoltage conditions, when the power of the SiC MOSFET chip is 5 W and the liquid convection coefficient in the microchannel is 1000 W / (m²·K), the temperature distribution of a trench-type overvoltage-resistant and electromagnetic-interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure of the present invention is provided.

[0096] From Figure 26 As shown, the breakdown characteristic curves of the SiC MOSFET in proportional example 1 (SiC MOSFET under the condition of no heat dissipation packaging), proportional example 2 (SiC MOSFET under the existing silver sintered double-sided heat dissipation packaging technology), and the present invention.

[0097] In summary, by means of the above technical solutions of the present invention, by designing a trench-type overvoltage-resistant and electromagnetic-interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure, the stability and reliability of the SiC MOSFET under overvoltage conditions are effectively improved, the electromagnetic interference at high operating frequencies is reduced, and it can better adapt to various power electronic application scenarios; through the coupling packaging structure of the trench-type field limiting ring and the microchannel of the silicon nitride ceramic substrate, combined with the terminal area heat dissipation design, the heat dissipation efficiency of the SiC MOSFET when suffering from overvoltage impacts such as lightning strikes and switching overvoltages can be regulated, the overvoltage resistance of the device is significantly enhanced, the risk of performance degradation and device damage caused by overvoltage is greatly reduced, the heat generated by the device during overvoltage or normal operation can be quickly removed, the temperature is balanced, and the reliable and stable operation of the device is ensured. By using the trench-type overvoltage-resistant and electromagnetic-interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure without wire bonding, the parasitic inductance of the device packaging is effectively reduced, and the high-frequency harmonics generated by the parasitic parameters are effectively suppressed, thereby significantly reducing the electromagnetic interference and meeting the use requirements of high frequency, high voltage, and high reliability of power devices in the power system. At the same time, the leadless packaging without bonding leads also weakens the heat dissipation obstruction, the heat transfer is more smooth and direct, the heat dissipation efficiency is improved, and the heat dissipation and operation stability under complex working conditions are enhanced.

[0098] In the present invention, unless otherwise clearly specified or limited, terms such as "installation", "setting", "connection", "fixation", "swivel connection" and the like shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements or the interaction relationship between two elements. Unless otherwise clearly limited, for those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0099] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An overvoltage-resistant and electromagnetic interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure, characterized in that, It includes an upper copper-ceramic substrate, a buffer layer, an SiC MOSFET chip (8), a lower substrate nano-silver solder layer (9) and a lower copper-ceramic substrate, which are encapsulated in sequence from top to bottom; Among them, the SiC MOSFET chip (8) includes a microchannel chip inlet (28), a microchannel chip outlet (29), an in-chip trench field-limiting ring microchannel (31), a gate metal (26), a source metal (27) and a junction terminal (30); The junction terminal (30) surrounds the gate metal (26) and the source metal (27) in the center. The microchannel chip inlet (28) and the microchannel chip outlet (29) are located at the top of the junction terminal (30) close to the gate metal (26). The in-chip trench field-limiting ring microchannel (31) is located at the top inside the SiC MOSFET chip (8); The upper copper-ceramic substrate includes an upper Si3N4 layer (2), and the upper Si3N4 layer (2) is a flat cuboid; On one side of the bottom of the upper Si3N4 layer (2), a microchannel chip inlet connecting pipe (16) and a microchannel chip outlet connecting pipe (17) are provided; On both sides inside the upper Si3N4 layer (2), a first microchannel (33) and a second microchannel (34) are provided. On one side of the upper Si3N4 layer (2) away from the microchannel chip inlet connecting pipe (16), a microchannel inlet (32) and a microchannel outlet (35) are provided. The first microchannel (33) communicates with the microchannel inlet (32), and the second microchannel (34) communicates with the microchannel outlet (35).

2. The anti-overvoltage and anti-electromagnetic interference SiC MOSFET field limiting ring and microchannel interconnection structure according to claim 1, characterized in that, The upper copper-ceramic substrate further includes an upper substrate upper copper layer (1), an upper substrate lower copper layer (3), a source terminal (13) and a gate terminal (14); The buffer layer includes an upper nano-silver solder layer (4), a molybdenum block buffer layer (5), an epoxy resin filling layer (6), and a lower nano-silver solder layer (7); The lower copper-ceramic substrate includes a lower substrate upper copper layer (10), a lower Si3N4 layer (11), a lower substrate copper layer (12) and a drain terminal (15).

3. The anti-overvoltage and anti-electromagnetic interference SiC MOSFET field limiting ring and microchannel interconnection structure according to claim 1, characterized in that Both the first microchannel (33) and the second microchannel (34) are continuous S-shaped curved structures; The outermost edge of the S-shaped bending turn on one side close to the microchannel inlet (32) and the microchannel outlet (35) in the upper Si3N4 layer (2) is vertically aligned with the edge of the source metal (27).

4. An overvoltage-resistant and electromagnetic interference-resistant SiC MOSFET field limiting ring and microchannel interconnection structure according to claim 2, characterized in that, On one side of the upper substrate lower copper layer (3), a microchannel chip inlet connecting pipe via hole (18) and a microchannel chip outlet connecting pipe via hole (19) are provided; The gate terminal (14) is located above one side of the upper substrate lower copper layer (3) and between the microchannel chip inlet connecting pipe via hole (18) and the microchannel chip outlet connecting pipe via hole (19). The source terminal (13) is located at the bottom of the other side of the upper substrate lower copper layer (3); The gate terminal (14) is located below and in close connection with the upper Si3N4 layer (2), and there is no contact between the gate terminal (14) and the copper layer under the upper substrate (3), while the source terminal (13) is in close connection with the copper layer under the upper substrate (3).

5. The anti-overvoltage and anti-electromagnetic interference SiC MOSFET field limiting ring and microchannel interconnection structure according to claim 2, characterized in that, The upper nano silver solder layer (4) includes an upper gate metal corresponding area solder layer (20) directly above the gate metal (26) and an upper source metal corresponding area solder layer (21) directly above the source metal (27). The molybdenum block buffer layer (5) includes a gate metal corresponding area molybdenum pillar (22) directly above the gate metal (26) and a source metal corresponding area molybdenum pillar (23) directly above the source metal (27). The lower nano silver solder layer (7) includes a lower gate metal corresponding area solder layer (24) directly above the gate metal (26) and a lower source metal corresponding area solder layer (25) directly above the source metal (27). The epoxy resin filling layer (6) is located in the gap between the upper nano silver solder layer (4), the molybdenum block buffer layer (5), the lower nano silver solder layer (7) and the copper layer under the upper substrate (3), and the gap is tightly filled.

6. The anti-overvoltage and anti-electromagnetic interference SiC MOSFET field limiting ring and microchannel interconnection structure according to claim 5, wherein The source metal (27) is two L-shaped hexagons that are symmetric in shape and position. The gate metal (26) is located between the corners of the two source metals (27), and the source metal (27) and the gate metal (26) do not contact each other. The junction terminal (30) is a rectangular ring structure.

7. An overvoltage-resistant and electromagnetic-interference-resistant SiC MOSFET field-limiting ring and microchannel interconnection structure according to claim 2, characterized in that, The SiC MOSFET chip (8) further includes a drain metal (44), an N + -type 4H-SiC substrate (43), and an N - -drift layer (42) that are adjacent to each other in sequence from bottom to top. The N - -drift layer (42) is located below the junction terminal (30); The bottom of the junction terminal (30) is provided with a terminal P + Area (41), the N - The upper plane of the drift layer (42) is provided with a plurality of terminals P + The grooves are arranged in sequence from the inside to the outside of the junction terminal (30) in a rectangular ring shape, and each groove is in the N - The upper plane of the drift layer (42) is terminated by a terminal P + The region (41) is tightly surrounded, and the groove is filled with a SiO2 layer (40).

8. The anti-overvoltage and anti-electromagnetic interference SiC MOSFET field limiting ring and microchannel interconnection structure according to claim 7, characterized in that The said N - On the upper surface of the drift layer (42) and below the source metal (27), a terminal P-well region (45) and a P-well region (48) are distributed. The terminal P-well region (45) and the P-well region (48) are not adjacent. At the top of the terminal P-well region (45) on the side close to the edge of the source metal (27), a terminal source P + well region (46) is provided; An anode P region (49) and an anode N region (50) are provided at a portion of the junction terminal (30) away from the edge of the source metal (27), and the anode P region (49) and the anode N region (50) are surrounded by the P well region (48). + region (49) and anode N + region (50), and the anode P + region (49) and anode N + region (50) are surrounded by the P well region (48).

9. The anti-overvoltage and anti-electromagnetic interference SiC MOSFET field limiting ring and microchannel interconnection structure according to claim 8, characterized in that, The in-chip trench type field limiting ring microchannel (31) starts from the microchannel chip inlet (28), passes through the interconnected trenches, and reaches the microchannel chip outlet (29), forming a microchannel structure. The junction of the P-well region (48) and the upper surface of the N - drift layer (42) is a conductive channel, and a gate polysilicon (47) is disposed above the conductive channel; The part of the SiO2 layer (40) located above the N drift layer (42) inside the junction terminal (30) and outside the trench region, together with the trench, closes the in-chip trench-type field limiting ring microchannel (31). - The part of the SiO2 layer (40) located above the N drift layer (42) inside the junction terminal (30) and outside the trench region, together with the trench, closes the in-chip trench-type field limiting ring microchannel (31).

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