Integrated circuit device

Abstract

Integrated circuit devices and methods of manufacturing the same are provided. The integrated circuit device includes: a plurality of device isolation films spaced apart from each other; gaps among the plurality of device isolating films are filled with insulating films; a plurality of gate lines disposed over the gap filling insulating film; a plurality of source / drain regions including a first source / drain region and a second source / drain region, each of the plurality of source / drain regions being between the plurality of gate lines; a back contact provided under the first source / drain region, the back contact extending through the gap filling insulating film and electrically connected to the first source / drain region; and a gate protection film provided under the first source / drain region and in contact with the upper sidewall of the back surface contact. At least a portion of a sidewall of the gate protection film is surrounded by the gap-filling insulating film.

Description

Technical Field

[0001] The inventive concept relates to an integrated circuit device, and more particularly, to an integrated circuit device having a structure formed in a self-aligned manner. Background Art

[0002] As electronic products become compact and multifunctional and require high performance, integrated circuit devices require high capacity and high integration. Therefore, it is necessary to efficiently design a wiring structure to achieve high integration while ensuring the functions and operating speeds required for integrated circuit devices. Summary of the Invention

[0003] Aspects of the inventive concept provide an integrated circuit device having improved reliability.

[0004] Furthermore, the object of the inventive concept is not limited to the above object, and other objects not described herein will be clearly understood by those skilled in the art from the following description.

[0005] According to an aspect of the inventive concept, there is provided an integrated circuit device including: a plurality of device isolation films longitudinally extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a gap-fill insulating film positioned between the plurality of device isolation films; a plurality of gate lines provided on the gap-fill insulating film and longitudinally extending in the second horizontal direction; a plurality of source / drain regions including a first source / drain region and a second source / drain region, each of the plurality of source / drain regions being positioned between the plurality of gate lines; a back contact provided under the first source / drain region, the back contact extending through the gap-fill insulating film and electrically connected to the first source / drain region; and a gate protection film provided under the first source / drain region and contacting an upper sidewall of the back contact, wherein at least a portion of a sidewall of the gate protection film is surrounded by the gap-fill insulating film.

[0006] According to another aspect of the inventive concept, there is provided an integrated circuit device including: a plurality of device isolation films longitudinally extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a gap-fill insulating film positioned between the plurality of device isolation films; a plurality of gate lines disposed on the gap-fill insulating film and longitudinally extending in the second horizontal direction; a plurality of source / drain regions including a first source / drain region and a second source / drain region, each of the plurality of source / drain regions being positioned between the plurality of gate lines; a gate dielectric film positioned between the plurality of source / drain regions and the plurality of gate lines; a gate protective film covering a portion of a lower surface of the gate dielectric film adjacent to the first source / drain region; a gap-fill gate protective film covering a portion of the lower surface of the gate dielectric film adjacent to the second source / drain region; and a back contact contacting the gate protective film and electrically connected to the first source / drain region, wherein the gate protective film and the gap-fill gate protective film are disposed between the gap-fill insulating film and the plurality of source / drain regions.

[0007] According to another aspect of the inventive concept, there is provided an integrated circuit device including: a plurality of device isolation films longitudinally extending in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; a gap-fill insulating film positioned between two adjacent ones of the plurality of device isolation films; at least one nanosheet disposed on the gap-fill insulating film, spaced apart from an upper surface of the gap-fill insulating film in a vertical direction, and facing the upper surface of the gap-fill insulating film; a gate line disposed on the gap-fill insulating film to surround the at least one nanosheet and longitudinally extending in a second horizontal direction intersecting the first horizontal direction; a gate dielectric film surrounding the gate line and separating the at least one nanosheet from the gate line; a first source / drain region and a second source / drain region, each of the first source / drain region and the second source / drain region being disposed on the gap-fill insulating film, adjacent to the gate line, and contacting the at least one nanosheet; a back contact horizontally extending from a lower surface of the gap-fill insulating film in a vertical direction to a lower surface of the first source / drain region and covering a portion of the lower surface of the first source / drain region; a gate protective film positioned between the back contact and the gap-fill insulating film and covering another portion of the lower surface of the first source / drain region; and a source / drain contact provided on the second source / drain region and electrically connected to the second source / drain region, wherein the gap-fill insulating film includes a silicon oxide film and the gate protective film includes a silicon carbide film. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1is a diagram showing, as an example, a planar layout of a cell block of an integrated circuit device according to an embodiment;

[0010] Figure 2 is a diagram showing a planar layout of an integrated circuit device according to an embodiment;

[0011] Figure 3A is a cross-sectional view of the integrated circuit device taken along the line X1-X1' in Figure 2 ;

[0012] Figure 3B is a cross-sectional view of the integrated circuit device taken along the line Y1-Y1' in Figure 2 ;

[0013] Figure 3C is a cross-sectional view of the integrated circuit device taken along the line Y2-Y2' in Figure 2 ;

[0014] Figure 3D is Figure 3A an enlarged cross-sectional view of the region "EX2" of

[0015] Figure 4A is a diagram showing an integrated circuit device according to some embodiments;

[0016] Figure 4B is a diagram showing an integrated circuit device according to some embodiments;

[0017] Figure 4C is a diagram showing an integrated circuit device according to some embodiments;

[0018] Figure 4D is a diagram showing an integrated circuit device according to some embodiments;

[0019] Figure 4E is a diagram showing an integrated circuit device according to some embodiments;

[0020] Figure 5A is a diagram showing an integrated circuit device according to some embodiments;

[0021] Figure 5B is a diagram showing an integrated circuit device according to some embodiments;

[0022] Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10 , Figure 11A , Figure 11B , Figure 12 , Figure 13A ,Figure 13B , Figures 14 to 16 , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20 , Figure 21 , Figure 22A , Figure 22B , Figure 23A and Figure 23B are diagrams showing a method of manufacturing an integrated circuit device according to an embodiment in a process sequence; and

[0023] Specifically, Figure 6 , Figure 8A , Figure 9A , Figure 10 , Figure 11A , Figure 13A , Figures 14 to 16 , Figure 17A , Figure 18A , Figure 19A , Figure 20 , Figure 21 , Figure 22A and Figure 23A are diagrams showing a manufacturing process corresponding to a cross-section taken along the line X1-X1' of Figure 2 , Figure 7 , Figure 8B , Figure 9B , Figure 11B , Figure 12 , Figure 13B , Figure 17B , Figure 18B , Figure 19B , Figure 22B and Figure 23B are diagrams showing a manufacturing process corresponding to a cross-section taken along the line Y1-Y1' of Figure 2 . DETAILED DESCRIPTION

[0024] The advantages and features of the inventive concept and its implementation method will be elucidated by the following embodiments described in detail with reference to the accompanying drawings. However, the inventive concept may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Furthermore, the inventive concept is defined only by the scope of the claims. For clarity of description, the relative dimensions of layers and regions in the drawings may be exaggerated. Like reference numerals always refer to like elements.

[0025] When an element is referred to as being "connected to" or "coupled to" another element, the one element can be directly connected or coupled to the other element, or indirectly connected or coupled to the other element with intervening elements therebetween. On the other hand, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements.

[0026] The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] When an element or layer is referred to as being "on" another element or layer "above" or "over", the element or layer can be directly on the other element or layer, or there can also be intervening elements or layers therebetween. On the other hand, when an element is referred to as being "directly on" or "directly above", there are no intervening elements or layers.

[0028] Although terms such as first and second are used to describe various elements, components, and / or parts, these elements, components, and / or parts are not limited by these terms. These terms are only used to distinguish one element, component, or part from other elements, components, or parts. Thus, within the inventive concept, the first element, first component, or first part described below can also be referred to as the second element, second component, or second part.

[0029] The terms described herein are only for the purpose of describing embodiments and do not limit the inventive concept. In this specification, the singular forms also include the plural forms unless the context clearly dictates otherwise. The meanings of "comprising" and / or "including" used herein do not exclude the presence or addition of one or more other components, steps, operations, and / or elements other than the components, steps, operations, and / or elements mentioned.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. In addition, terms defined in commonly used dictionaries are not idealized or overly interpreted unless clearly and specifically defined. Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0031] Figure 1 is a diagram showing, as an example, a planar layout of a cell block 12 of an integrated circuit device 10 according to an embodiment.

[0032] Refer to Figure 1, the cell block 12 of the integrated circuit device 10 may include a plurality of logic cells LC including circuit patterns for forming various circuits. The plurality of logic cells LC may be arranged in a matrix form along a first horizontal direction X and a second horizontal direction Y inside the cell block 12. The second horizontal direction Y may intersect the first horizontal direction X, for example, may be perpendicular to the first horizontal direction X.

[0033] The plurality of logic cells LC may include circuit patterns having a layout designed according to placement and routing (PnR) technology to perform at least one logic function. The plurality of logic cells LC may perform various logic functions. In some embodiments, the plurality of logic cells LC may include a plurality of standard cells. In some embodiments, at least some of the plurality of logic cells LC may perform the same logic function. In some embodiments, at least some of the plurality of logic cells LC may perform different logic functions.

[0034] The plurality of logic cells LC may include various types of logic cells including a plurality of circuit elements. For example, each of the plurality of logic cells LC may include, but is not limited to, an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate and / or an XNOR gate, an inverter (INV), an adder (ADD), a buffer (BUF), a delay element (DLY), a filter (FIL), a multiplexer (MXT / MXIT), an OR / AND / inverter (OAI), an AND / OR (AO) gate, an AND / OR / inverter (AOI), a D flip-flop, a reset flip-flop, a master-slave flip-flop, a latch, or a combination thereof.

[0035] In the cell block 12, at least some of the plurality of logic cells LC forming a row RO1, RO2, RO3, RO4, RO5, or RO6 (or one of the first to sixth rows RO1, RO2, RO3, RO4, RO5, and RO6) in the first horizontal direction X have the same width. In addition, at least some of the plurality of logic cells LC forming a row RO1, RO2, RO3, RO4, RO5, or RO6 may have the same height. However, the inventive concept is not limited to Figure 1 the concept shown, and at least some of the plurality of logic cells LC forming a row RO1, RO2, RO3, RO4, RO5, or RO6 may have different widths and different heights.

[0036] The area of each of the multiple logic cells LC in the cell block 12 of the integrated circuit device 10 can be defined by a cell boundary CBD. A cell boundary contact region CBC can be provided between two logic cells LC adjacent to each other in a first horizontal direction X or a second horizontal direction Y among the multiple logic cells LC, and the cell boundaries CBD of the two logic cells LC are in contact with each other in the cell boundary contact region CBC. It will be understood that when an element is referred to as being "connected" or "coupled" to another element or "on" another element, it can be directly connected or coupled to the other element or directly on the other element, or there can be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element or as being "in contact" with another element or "contacting" another element, there are no intervening elements at the point of contact.

[0037] In some embodiments, among the multiple logic cells LC constituting a row RO1, RO2, RO3, RO4, RO5, or RO6, two logic cells LC adjacent to each other in the first horizontal direction X can be in contact with each other at the cell boundary contact region CBC without a separation distance therebetween. In some embodiments, among the multiple logic cells LC constituting a row RO1, RO2, RO3, RO4, RO5, or RO6, two logic cells LC adjacent to each other in the first horizontal direction X can be spaced apart from each other by a certain distance.

[0038] In some embodiments, among the multiple logic cells LC constituting a row RO1, RO2, RO3, RO4, RO5, or RO6, two adjacent logic cells LC can perform the same function. In this case, the two adjacent logic cells LC can have the same structure. In some embodiments, among the multiple logic cells LC constituting a row RO1, RO2, RO3, RO4, RO5, or RO6, two adjacent logic cells LC can perform different functions from each other.

[0039] In some embodiments, a logic cell LC selected from among the multiple logic cells LC in the cell block 12 of the integrated circuit device 10 and another logic cell LC adjacent to the selected logic cell LC in the second horizontal direction Y ( Figure 1 ) can have a symmetric structure with respect to the cell boundary contact region CBC therebetween. For example, the reference logic cell LC_R in the third row RO3 and the lower logic cell LC_L in the second row RO2 have a symmetric structure with respect to the cell boundary contact region CBC therebetween. In addition, the reference logic cell LC_R in the third row RO3 and the upper logic cell LC_H in the fourth row RO4 have a symmetric structure with respect to the cell boundary contact region CBC therebetween.

[0040] Figure 1It is shown that the cell block 12 includes six rows, such as the first to sixth rows RO1, RO2, RO3, RO4, RO5, and RO6, but this is only an example. The cell block 12 may include various numbers of rows selected as needed, and one row may include various numbers of logic units selected as needed.

[0041] One selected from among a plurality of ground lines VSS and a plurality of power supply lines VDD may be located between the first to sixth rows RO1, RO2, RO3, RO4, RO5, and RO6, and each of the first to sixth rows RO1, RO2, RO3, RO4, RO5, and RO6 includes a plurality of logic units LC arranged in a row in the first horizontal direction X. The plurality of ground lines VSS and the plurality of power supply lines VDD may each extend in the first horizontal direction X and may be alternately arranged while being spaced apart from each other in the second horizontal direction Y. Accordingly, the plurality of ground lines VSS and the plurality of power supply lines VDD may each overlap the cell boundary CBD of the logic unit LC in the vertical direction Z.

[0042] Figure 2 is a plan layout view showing an integrated circuit device 10 according to an embodiment. Specifically, Figure 2 is Figure 1 an enlarged view of the region "EX1". Figure 3A is a cross-sectional view of the integrated circuit device 10 taken along the Figure 2 line X1-X1' shown. Figure 3B is a cross-sectional view of the integrated circuit device 10 taken along the Figure 2 line Y1-Y1' shown. Figure 3C is a cross-sectional view of the integrated circuit device 10 taken along the Figure 2 line Y2-Y2' shown. Figure 3D is Figure 3A an enlarged cross-sectional view of the region "EX2".

[0043] Hereinafter, with reference to Figure 2 and Figures 3A to 3D an integrated circuit device 10 including a field effect transistor (FET) will be described. The FET has a gate-all-around structure, which includes an active region in the form of a nanowire or a nanosheet and a gate surrounding the active region. For example, the integrated circuit device 10 may include a multi-bridge channel FET (MBCFET) device. However, the inventive concept is not limited thereto, and the integrated circuit device 10 may include a planar FET device, a fin FET device, etc. The integrated circuit device 10 may include Figure 1 some of the plurality of logic units LC shown.

[0044] The integrated circuit device 10 may include a backside structure BSS and a frontside structure FSS disposed on the backside structure BSS. In some embodiments, the backside structure BSS may include a plurality of device isolation films 112, a plurality of gap-fill insulating films 192 each located between the plurality of device isolation films 112, a backside contact DBC, a gate protection film GP surrounding a part of an upper sidewall of the backside contact DBC, and a lower wiring film M2 and a lower insulating film 198 on a back surface 192B of the gap-fill insulating film 192. The gap-fill insulating film 192 may surround the backside contact DBC.

[0045] In some embodiments, the frontside structure FSS may be disposed on a front surface 192F of the gap-fill insulating film 192 and may include a plurality of nanosheet stacks NSS, a plurality of gate lines 160, source / drain regions 130 located between the plurality of gate lines 160, and an insulating liner 142 and an inter-gate insulating film 144 disposed above the source / drain regions 130.

[0046] The frontside structure FSS of the integrated circuit device 10 may include an active structure. For example, the active structure may have a fin shape, a nanowire shape, or a nanosheet shape. Figures 3A to 3D The active structure is shown to include the nanosheet stack NSS, but the inventive concept is not limited thereto.

[0047] At positions spaced apart from the front surface 192F of the gap-fill insulating film 192 in a vertical direction Z, each of the plurality of nanosheet stacks NSS may include at least one nanosheet facing the front surface 192F of the gap-fill insulating film 192. The term “nanosheet” used herein refers to a nanoscale sheet-shaped conductive structure having a direction substantially parallel to the direction of current flow. It should be understood that the nanosheet includes or may be a nanowire. Terms such as “same,” “equal,” “plane,” “parallel,” “perpendicular,” or “coplanar” as used herein encompass identity or approximate identity including, for example, deviations that may occur due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise.

[0048] Each of the plurality of nanosheet stacks NSS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 overlapping each other in the vertical direction Z. The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have different vertical distances (Z distances) from the front surface 192F of the gap-fill insulating film 192. Each of the plurality of gate lines 160 may surround the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 overlapping each other in the vertical direction Z in the nanosheet stack NSS.

[0049] Although Figure 2The planar shape (the shape in the plan view) of the nanosheet stack NSS is shown as being approximately quadrilateral, but the inventive concept is not limited thereto. The nanosheet stack NSS may have various planar shapes depending on the planar shape of each gate line 160. This example shows a configuration in which a plurality of nanosheet stacks NSS and a plurality of gate lines 160 are arranged on the gap-fill insulating film 192 and the plurality of nanosheet stacks NSS are arranged in rows on the gap-fill insulating film 192. However, the number of each of the nanosheet stacks NSS and the gate lines 160 provided on the gap-fill insulating film 192 is not particularly limited.

[0050] The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 in the nanosheet stack NSS may each be used as a channel region. In some embodiments, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may each have a thickness selected in the range from about 4 nm to about 6 nm, but the inventive concept is not limited thereto. Terms such as "about" or "substantially" may reflect quantities, dimensions, orientations, or layouts that vary only in a relatively small manner and / or in a manner that does not significantly change the operation, function, or structure of certain elements. For example, a range from "about 0.1 to about 1" may cover ranges such as a 0%-5% deviation around 0.1 and a 0% to 5% deviation around 1, especially if such deviations maintain the same effect as the listed range. Here, the thickness of each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 refers to the dimension in the vertical direction Z. In some embodiments, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have substantially the same thickness in the vertical direction Z. In some embodiments, at least some of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have different thicknesses in the vertical direction Z. In some embodiments, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 in the nanosheet stack NSS may each include a Si layer, a SiGe film, or a combination thereof.

[0051] As Figure 3A shown, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 in one nanosheet stack NSS may have the same or similar dimensions in the first horizontal direction X. In some embodiments, different from the example in Figure 3A , at least some of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 in one nanosheet stack NSS have different dimensions in the first horizontal direction X. In this example, a case where each of the plurality of nanosheet stacks NSS includes three nanosheets is shown, but the inventive concept is not limited to this example. For example, the nanosheet stack NSS may include at least one nanosheet, and the number of nanosheets constituting the nanosheet stack NSS is not particularly limited.

[0052] As shown Figure 3A As shown, a plurality of gate lines 160 may be stacked around a plurality of nanosheets NSS over the gap-fill insulating film 192 and extend longitudinally in a second horizontal direction Y. The plurality of gate lines 160 may extend parallel to each other. Each of the plurality of gate lines 160 may include a main gate portion 160M and a plurality of sub-gate portions 160S. The main gate portion 160M may cover the upper surface of the nanosheet stack NSS and extend longitudinally in the second horizontal direction Y. The plurality of sub-gate portions 160S may be integrally connected to the main gate portion 160M, for example, without a boundary therebetween, and are respectively disposed between the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3, and between the third nanosheet N3 and the gap-fill insulating film 192. In a vertical direction Z, the thickness of each of the plurality of sub-gate portions 160S may be less than the thickness of the main gate portion 160M.

[0053] Each of the plurality of gate lines 160 may include, or may be formed of, a metal, a metal nitride, a metal carbide film, or a combination thereof. The metal may be selected from the group consisting of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride may be selected from the group consisting of TiN and TaN. The metal carbide film may include, or may be formed of, TiAlC. However, the materials constituting the plurality of gate lines 160 are not limited to these examples.

[0054] A gate dielectric film 152 may be located between the nanosheet stack NSS and the gate lines 160. In some embodiments, the gate dielectric film 152 may have a stacked structure of an interfacial dielectric film and a high-k dielectric film. The interfacial dielectric film may include, or may be, a low-k dielectric material film having a permittivity of about 9 or less, such as a silicon oxide film, a silicon oxynitride film, or a combination thereof. In some embodiments, the interfacial dielectric film may be omitted. The high-k dielectric film may include, or may be, a material having a dielectric constant higher than that of a silicon oxide film or formed of the material. For example, the high-k dielectric film may have a dielectric constant of about 10 to about 25. The high-k dielectric film may include, or may be, a hafnium oxide film, but the inventive concept is not limited thereto.

[0055] Two sidewalls of each of the plurality of sub-gate portions 160S of the plurality of gate lines 160 may be spaced apart from the source / drain regions 130 with the gate dielectric film 152 therebetween. The gate dielectric film 152 may be located between the sub-gate portions 160S of the gate lines 160 and each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3, and between the sub-gate portions 160S of the gate lines 160 and the source / drain regions 130.

[0056] According to an embodiment, each of the gate dielectric film 152 and the gate line 160 may include a portion overlapping (e.g., vertically overlapping) with the plurality of nanosheet stacks NSS.

[0057] According to an embodiment, a plurality of transistors may be formed in a portion where the plurality of nanosheet stacks NSS, the gate line 160, and the gate dielectric film 152 overlap each other. According to an embodiment, the plurality of transistors may include p-channel metal oxide semiconductor (PMOS) transistors and n-channel metal oxide semiconductor (NMOS) transistors. For example, each of the plurality of transistors may include at least one nanosheet stack NSS, a gate dielectric film 152 and a gate line 160 surrounding the at least one nanosheet stack NSS, and a plurality of source / drain regions 130 facing the at least one nanosheet stack NSS in the first horizontal direction X.

[0058] In some embodiments, each of the plurality of nanosheet stacks NSS may include an undoped Si layer. In other embodiments, each of the plurality of nanosheet stacks NSS may include a doped Si layer. For example, when the plurality of nanosheet stacks NSS constitute a PMOS transistor or are included in a PMOS transistor, the plurality of nanosheet stacks NSS may each include a Si layer doped with a p-type dopant. In addition, when the plurality of nanosheet stacks NSS constitute an NMOS transistor or are included in an NMOS transistor, the plurality of nanosheet stacks NSS may each include a Si layer doped with an n-type dopant. The p-type dopant may be selected from the group consisting of boron (B) and gallium (Ga). The n-type dopant may be selected from the group consisting of phosphorus (P), arsenic (As), and antimony (Sb).

[0059] The upper surface of each of the gate dielectric film 152 and the gate line 160 may be covered by a capping insulating pattern 168. The capping insulating pattern 168 may include or may be a silicon nitride film or a silicon oxide film.

[0060] Two sidewalls of each of the gate line 160 and the capping insulating pattern 168 may be covered by an outer insulating spacer 118. The outer insulating spacer 118 may cover two sidewalls of the main gate portion 160M above the upper surface of the plurality of nanosheet stacks NSS. The outer insulating spacer 118 may be spaced apart from the gate line 160 with the gate dielectric film 152 therebetween.

[0061] As Figure 3B and Figure 3C shown, a plurality of recessed side insulating spacers 119 may be disposed on the upper surface of the device isolation film 112 to cover the sidewalls of the plurality of source / drain regions 130. In some embodiments, each of the plurality of recessed side insulating spacers 119 may be integrally connected to an adjacent outer insulating spacer 118, for example, without a boundary therebetween.

[0062] Each of the plurality of outer insulating spacers 118 and the plurality of recessed side insulating spacers 119 may include or be formed of silicon nitride, silicon oxide film, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. Each of the terms "SiCN", "SiBN", "SiON", "SiOCN", "SiBCN", and "SiOC" used herein indicates a material including the elements indicated by each term, and is not a chemical formula representing a stoichiometric relationship.

[0063] A metal silicide film 172 may be formed on the upper surface of each of the plurality of source / drain regions 130. The metal silicide film 172 may include a metal, and the metal includes Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide film 172 may include titanium silicide, but the inventive concept is not limited thereto.

[0064] The plurality of source / drain regions 130, the plurality of metal silicide films 172, and the plurality of outer insulating spacers 118 may be covered by an insulating liner 142. In some embodiments, the insulating liner 142 may be omitted. An inter-gate insulating film 144 may be disposed on the insulating liner 142. When the insulating liner 142 is omitted, the inter-gate insulating film 144 may be in contact with the plurality of source / drain regions 130.

[0065] The insulating liner 142 and the inter-gate insulating film 144 may be sequentially disposed on the plurality of source / drain regions 130 and the plurality of metal silicide films 172. The insulating liner 142 and the inter-gate insulating film 144 may constitute an insulating structure. In some embodiments, the insulating liner 142 may include or be formed of silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination thereof, but the inventive concept is not limited thereto. The inter-gate insulating film 144 may include or be formed of a silicon oxide film, but the inventive concept is not limited thereto.

[0066] As Figures 3A to 3CAs shown, each of the plurality of source / drain regions 130 may be formed as a multi-layer structure. In some embodiments, each of the plurality of source / drain regions 130 may include an upper source / drain region 132 and a lower source / drain region 134 below the upper source / drain region 132, or may be formed by the upper source / drain region 132 and the lower source / drain region 134 below the upper source / drain region 132. For example, the lower source / drain region 134 may be disposed below the upper source / drain region 132 and in contact with the upper source / drain region 132. In addition, an insulating spacer 142 and an inter-gate insulating film 144 may be sequentially disposed on the upper source / drain region 132. In some embodiments, each of the plurality of source / drain regions 130 may not include the upper source / drain region 132, but may include only the lower source / drain region 134 or may be formed only by the lower source / drain region 134. For example, each of the plurality of source / drain regions 130 may include a first semiconductor film 1342 and a second semiconductor film 1344 described below, or may be formed by the first semiconductor film 1342 and the second semiconductor film 1344 described below. For example, the insulating spacer 142 and the inter-gate insulating film 144 may be sequentially disposed on the lower source / drain region 134.

[0067] In some embodiments, the contact surfaces of the upper source / drain region 132 and the lower source / drain region 134 may be located between a plurality of device isolation films 112 spaced apart from each other in the second horizontal direction Y. For example, in a plan view, the contact surfaces of the upper source / drain region 132 and the lower source / drain region 134 may be located between the device isolation films 112. In certain embodiments, the contact surfaces of the upper source / drain region 132 and the lower source / drain region 134 may overlap the device isolation films 112 in the second horizontal direction Y. In some embodiments, the contact surfaces of the upper source / drain region 132 and the lower source / drain region 134 may be located between a plurality of recessed side insulating spacers 119 spaced apart from each other in the second horizontal direction Y (e.g., horizontally overlapping with a plurality of recessed side insulating spacers 119 spaced apart from each other in the second horizontal direction Y).

[0068] The lower source / drain region 134 may include a first semiconductor film 1342 and a second semiconductor film 1344. The first semiconductor film 1342 may conformally extend along the sidewalls and bottom of the second semiconductor film 1344. The first semiconductor film 1342 and the second semiconductor film 1344 may together contact the upper source / drain region 132. The first semiconductor film 1342 may include a portion between the second semiconductor film 1344 and the back contact DBC, and the second semiconductor film 1344 may be spaced apart from the back contact DBC with the portion of the first semiconductor film 1342 therebetween.

[0069] In some embodiments, the upper source / drain region 132 and the lower source / drain region 134 may each include a silicon film or a SiGe film. As used herein, the term "SiGe" refers to a material composed of the elements included in the term and does not represent a chemical formula indicating a stoichiometric relationship. For example, each of the upper source / drain region 132 and the lower source / drain region 134 may include a single-crystalline silicon film, a polycrystalline silicon film, an amorphous silicon film, a single-crystalline SiGe film, a polycrystalline SiGe film, or an amorphous SiGe film. For example, the upper source / drain region 132 may include or be formed of a silicon film. Further, in the lower source / drain region 134, the first semiconductor film 1342 may include or be a silicon film, and the second semiconductor film 1344 may include or be a SiGe film. In some embodiments, the upper source / drain region 132 may include or be formed of a SiGe film. In the lower source / drain region 134, both the first semiconductor film 1342 and the second semiconductor film 1344 may include or be SiGe films, but the ratio / percentage of Ge contained in the first semiconductor film 1342 and the second semiconductor film 1344 may be different from each other.

[0070] In some embodiments, the first group of the plurality of source / drain regions 130 may constitute a PMOS transistor. In this case, in some embodiments, each of the upper source / drain region 132 and the lower source / drain region 134 may include Si doped with a p-type dopant 1-x Ge x layer (where 0.0 < x ≤ 0.6).

[0071] In some embodiments, the content ratio or percentage of Ge in the upper source / drain region 132 may be greater than the content ratio or percentage of Ge in the lower source / drain region 134. In the lower source / drain region 134, the content ratio or percentage of Ge in the second semiconductor film 1344 may be greater than the content ratio or percentage of Ge in the first semiconductor film 1342. In some embodiments, the content ratio or atomic percentage of Ge in the first semiconductor film 1342 may be greater than about 0.0 at% and less than or equal to about 20 at%, for example, about 15 at% to about 30 at%. The content ratio or atomic percentage of Ge in the second semiconductor film 1344 may be from about 30 at% to about 60 at%, for example, about 40 at% to about 60 at%. However, the inventive concept is not limited to these examples. In some embodiments, the p-type dopant may include or be at least one selected from the group consisting of boron (B) and gallium (Ga), but the inventive concept is not limited thereto.

[0072] In some embodiments, a second group of the plurality of source / drain regions 130 may form NMOS transistors. In such a case, in some embodiments, each of the upper source / drain region 132 and the lower source / drain region 134 may include an Si layer doped with an n-type dopant, an undoped Si layer, or a combination thereof.

[0073] In some embodiments, the upper source / drain region 132 may include an Si layer doped with an n-type dopant, and the lower source / drain region 134 may include an Si layer doped with an n-type dopant, an undoped Si layer, or a combination thereof. In the lower source / drain region 134, the first semiconductor film 1342 may include or be formed of an undoped Si layer, and the second semiconductor film 1344 may include or be formed of an Si layer doped with an n-type dopant. In some embodiments, each of the upper source / drain region 132 and the lower source / drain region 134 may include an Si layer doped with an n-type dopant, and the content ratio or percentage of the n-type dopant in the upper source / drain region 132 may be greater than the content ratio or percentage of the n-type dopant in the lower source / drain region 134. In the lower source / drain region 134, each of the first semiconductor film 1342 and the second semiconductor film 1344 may include or be formed of an Si layer doped with an n-type dopant, and the content ratio or percentage of the n-type dopant in the second semiconductor film 1344 may be greater than the content ratio or percentage of the n-type dopant in the first semiconductor film 1342. The n-type dopant may include or may be at least one selected from the group consisting of phosphorus (P), arsenic (As), and antimony (Sb), but the inventive concept is not limited thereto.

[0074] In some embodiments, the plurality of source / drain regions 130 may include a first source / drain region 130a and a second source / drain region 130b. The first source / drain region 130a may be directly connected to the back contact DBC, and the second source / drain region 130b may be directly connected to the source / drain contact CA.

[0075] In some embodiments, the first source / drain region 130a and the second source / drain region 130b may be spaced apart from each other in a first horizontal direction X, with a nanosheet stack NSS therebetween. For example, the first source / drain region 130a may be used as a source region, and the second source / drain region 130b may be used as a drain region. In some embodiments, the first source / drain region 130a and the second source / drain region 130b may be as Figure 3AThe ones shown have the same shape, but the inventive concept is not limited thereto. The first source / drain region 130a and the second source / drain region 130b may have different shapes from each other. For example, the first source / drain region 130a and the second source / drain region 130b may have different horizontal widths or different vertical thicknesses from each other.

[0076] As Figure 3A shown, a plurality of gate lines 160 may be disposed above the front surface 192F of the gap-fill insulating film 192. The gap-fill insulating film 192 may cover / contact at least a part of the lowermost lower surface of the gate dielectric film 152. In addition, as Figure 2 shown, the gap-fill insulating film 192 may be located between a plurality of device isolation films 112 spaced apart from each other and extend longitudinally in the first horizontal direction X.

[0077] In some embodiments, the gap-fill insulating film 192 may include silicon nitride (SiN), silicon oxide film (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof, or be formed of silicon nitride (SiN), silicon oxide film (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof, but the inventive concept is not limited to these examples. Each of the terms "SiN", "SiO", "SiCN", "SiBN", "SiON", "SiOCN", "SiBCN", and "SiOC" used herein indicates a material including the elements shown by each term and is not a chemical formula representing a stoichiometric relationship. In some embodiments, the gap-fill insulating film 192 may include a low-k dielectric film or be formed of a low-k dielectric film. The low-k dielectric film may include fluorine-doped silicon oxide, organosilicate glass, carbon-doped oxide, porous silicon oxide, porous organosilicate glass, spin-on organic polymer dielectric, spin-on silicon-based polymer dielectric, or a combination thereof, or be formed of fluorine-doped silicon oxide, organosilicate glass, carbon-doped oxide, porous silicon oxide, porous organosilicate glass, spin-on organic polymer dielectric, spin-on silicon-based polymer dielectric, or a combination thereof, but the inventive concept is not limited to these examples.

[0078] In some embodiments, the back contact DBC may be disposed under a source / drain region 130 selected from among a plurality of source / drain regions 130. For example, the back contact DBC may be disposed under the first source / drain region 130a. The back contact DBC may extend, for example, in a vertical direction through the gap-fill insulating film 192 and contact the first source / drain region 130a. The figure shows that the upper surface of the back contact DBC is in the same plane as the lower surface of the gate dielectric film 152, but the shape of the back contact DBC is not limited to the shape shown in the figure. For example, the back contact DBC may extend further toward the first source / drain region 130a than shown in the figure, such that the back contact DBC overlaps the first source / drain region 130a in a first horizontal direction X and a second horizontal direction Y. In some embodiments, the back contact DBC may include or be formed of a back barrier film 194 and a back via 196.

[0079] In some embodiments, the back barrier film 194 may include or be formed of a metal or a metal nitride. For example, the back barrier film 194 may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, or be formed of Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but the inventive concept is not limited thereto. The back via 196 may include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, or be formed of molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, but the inventive concept is not limited thereto.

[0080] Although not shown, a metal silicide film may be located between the back barrier film 194 and the first source / drain region 130a. The metal silicide film may include a metal including Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. The metal silicide film may be formed by consuming a portion of the first source / drain region 130a.

[0081] As Figure 3AAs shown, the back contact DBC can be in contact with the gate protective film GP and the gap-fill insulating film 192 in the first horizontal direction X. For example, the gate protective film GP can cover the upper sidewall of the back contact DBC in the first horizontal direction X, and the gap-fill insulating film 192 can cover the lower sidewall of the back contact DBC in the first horizontal direction X. For example, in a cross-sectional view, the gate protective film GP can be surrounded by the source / drain region 130, the gate dielectric film 152, the gap-fill insulating film 192, and the back contact DBC. In addition, as Figure 3B shown, the back contact DBC can be in contact with the device isolation film 112 in the second horizontal direction Y. For example, the device isolation film 112 can cover the sidewall of the back contact DBC in the second horizontal direction Y.

[0082] In some embodiments, the horizontal width of the upper portion of the back contact DBC in the first horizontal direction X can be smaller than the horizontal width of the lower portion of the back contact DBC in the first horizontal direction X. For example, the horizontal width of the portion of the back contact DBC overlapping with the gate protective film GP in the first horizontal direction X can be smaller than the horizontal width of the portion of the back contact DBC overlapping with the gap-fill insulating film 192 in the first horizontal direction X.

[0083] In some embodiments, the gate protective film GP can cover / contact at least a portion of the lower surface of the lowermost end of the gate dielectric film 152. The portion of the lower surface of the gate dielectric film 152 covered by the gate protective film GP can be adjacent to the back contact DBC. In some embodiments, the gate protective film GP can isolate the first source / drain region 130a from the gap-fill insulating film 192. For example, the gap-fill insulating film 192 can be spaced apart from the first source / drain region 130a with the gate protective film GP therebetween.

[0084] In some embodiments, the back contact DBC can cover / contact a portion of the lower / bottom surface of the first source / drain region 130a, and the gate protective film GP can cover another portion of the lower / bottom surface of the first source / drain region 130a. For example, the horizontal width of the upper portion (e.g., the upper portion at the top) of the back contact DBC in the first horizontal direction X can be smaller than the horizontal width of the first source / drain region 130a in the first horizontal direction X. In some embodiments, the back contact DBC can completely cover the lower surface of the first source / drain region 130a, and the gate protective film GP can not cover / contact the lower surface of the first source / drain region 130a. For example, the horizontal width of the upper portion (e.g., the upper portion at the top) of the back contact DBC in the first horizontal direction X can be equal to or greater than the horizontal width of the first source / drain region 130a in the first horizontal direction X.

[0085] The gate protective film GP may include or may be the gap-fill gate protective film GPa (see Figure 21 ), which is the remaining part after the etching process for forming the back contact hole BCH (see Figure 22A ). The manufacturing process of the gate protective film GP is described in detail below with reference to Figure 21 and Figure 22A .

[0086] As Figure 3D shows, the upper surface of the gate protective film GP may be covered by the first source / drain region 130a and the gate dielectric film 152, and the sidewall GPS of the gate protective film GP opposite to the back contact DBC may be covered by the gap-fill insulating film 192. In some embodiments, the sidewall GPS of the gate protective film GP opposite to the back contact DBC may have a curved shape. For example, the sidewall GPS of the gate protective film GP opposite to the back contact DBC may not include a flat surface, but only include a curved surface. The sidewall GPS of the gate protective film GP opposite to the back contact DBC may have a convex shape, for example, a convex shape protruding in a direction away from the back contact DBC. The shape of the gate protective film GP is not limited to Figure 3A and Figure 3D shown, but may have various shapes. The shape of the gate protective film GP is described in detail below with reference to Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E .

[0087] The gate protective film GP may include a material having an etching selectivity with respect to the fin-type active region F1 (see Figure 7 ) described below or may be formed of the material. For example, the gate protective film GP may include a material having a higher bonding energy than the material constituting the fin-type active region F1 (see Figure 7 ), or may be formed of a material having a higher bonding energy than the material constituting the fin-type active region F1 (see Figure 7 ).

[0088] In some embodiments, the gate protective film GP may include SiGeC, SiGe, SiC, SiO, SiOC, SiOCN, SiOH, GeC, or a combination thereof. In some embodiments, the gate protective film GP may be made of SiGeC, SiGe, SiC, SiO, SiOC, SiOCN, SiOH, GeC, or a combination thereof. As used herein, each of "SiGeC", "SiGe", "SiC", "SiO", "SiOC", "SiOCN", "SiOH", "GeC" refers to a material including the elements indicated by each term and is not a chemical formula representing a stoichiometric relationship. In some embodiments, the gate protective film GP may be single-crystalline, polycrystalline, or amorphous. In some embodiments, the gate protective film GP may include a single-crystalline film formed by epitaxial growth.

[0089] For example, the gate protective film GP may include SiC or be formed of SiC, and the carbon (C) content in the gate protective film GP may be selected from about 3 at% to about 30 at% or from about 3 at% to about 25 at%. However, this is only an example, and the carbon (C) content in the gate protective film GP can be adjusted as necessary. In some embodiments, the gate protective film GP may include a SiGe film, and the ratio of Ge contained in the gate protective film GP may be greater than the ratio of Ge contained in the first semiconductor film 1342.

[0090] As Figure 2 shown, a pair of device isolation films 112 selected from among the plurality of device isolation films 112 may be spaced apart from each other with a gap-fill insulating film 192 therebetween. The plurality of device isolation films 112 may extend longitudinally in the first horizontal direction X and extend parallel to each other. The plurality of device isolation films 112 may be spaced apart from each other in the second horizontal direction Y. In some embodiments, each of the device isolation films 112 may include or may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. The back contact DBC may be surrounded by the gap-fill insulating film 192 in the first horizontal direction X and surrounded by the device isolation films 112 in the second horizontal direction Y.

[0091] As Figure 3B shown, the device isolation film 112 may cover the sidewalls of the back contact DBC. In some embodiments, the device isolation film 112 and the plurality of recessed side insulating spacers 119 may cover the lower portions of the sidewalls of the plurality of source / drain regions 130.

[0092] The source / drain contact CA may be disposed over a source / drain region 130 selected from among a plurality of source / drain regions 130. For example, the source / drain contact CA may be disposed over the second source / drain region 130b. Each source / drain contact CA may pass through the inter-gate insulating film 144 and the insulating spacer 142 and contact the metal silicide film 172. Each source / drain contact CA may be electrically connected to the second source / drain region 130b via the metal silicide film 172. As used herein, components described as "electrically connected" are configured such that an electrical signal can be transmitted from one component to another (although such an electrical signal may attenuate in strength as it is transmitted and may be selectively transmitted). Each source / drain contact CA may be spaced apart from the main gate portion 160M in a first horizontal direction X with an outer insulating spacer 118 therebetween.

[0093] The source / drain contact CA may include a conduction blocking pattern 174 and a contact plug 176 stacked in sequence over the second source / drain region 130b. The conduction blocking pattern 174 may contact the bottom surface and sidewalls of the contact plug 176 while surrounding the bottom surface and sidewalls of the contact plug 176. Each source / drain contact CA may extend longitudinally in a vertical direction Z and pass through the inter-gate insulating film 144 and the insulating spacer 142. The conduction blocking pattern 174 may be located between the metal silicide film 172 and the contact plug 176. The conduction blocking pattern 174 may have a surface contacting the metal silicide film 172 and a surface contacting the contact plug 176. In some embodiments, the conduction blocking pattern 174 may include or be formed of a metal or a metal nitride. For example, the conduction blocking pattern 174 may include or be formed of Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but the inventive concept is not limited thereto. The contact plug 176 may include or be formed of molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, but the inventive concept is not limited thereto.

[0094] The upper surfaces of each of the source / drain contact CA, the plurality of capping insulating patterns 168, and the inter-gate insulating film 144 may be covered by an upper insulating structure 180. The upper insulating structure 180 may include an etch stop film 182 and an interlayer insulating film 184 sequentially stacked on each of the source / drain contact CA, the plurality of capping insulating patterns 168, and the inter-gate insulating film 144. The etch stop film 182 may include a silicon carbide film (SiC), SiN, a silicon carbide film doped with nitrogen (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or a combination thereof, or may be formed of a silicon carbide film (SiC), a silicon carbide film doped with nitrogen (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or a combination thereof. The interlayer insulating film 184 may include or may be an oxide film, a nitride film, an ultra-low-k (ULK) film having an ultra-low dielectric constant K of about 2.2 to about 2.4, or a combination thereof. For example, the interlayer insulating film 184 may include or may be a tetraethyl orthosilicate (TEOS) film, a high density plasma (HDP) oxide film, a borophosphosilicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, a SiON film, a SiN film, a SiOC film, a SiCOH film, or a combination thereof, but the inventive concept is not limited thereto.

[0095] A source / drain via contact VA may be disposed on each source / drain contact CA. Each source / drain via contact VA may pass through the upper insulating structure 180 and contact the source / drain contact CA. Each source / drain via contact VA may be electrically connected to the second source / drain region 130b through the source / drain contact CA and the metal silicide film 172. The bottom surface of each source / drain via contact VA may contact the upper surface of the source / drain contact CA. Each source / drain via contact VA may include molybdenum (Mo) or tungsten (W), or may be formed of molybdenum (Mo) or tungsten (W), but the inventive concept is not limited thereto.

[0096] The upper surfaces of each of the upper insulating structure 180 and the source / drain via contact VA may be covered by an upper insulating film 186. The constituent materials of the upper insulating film 186 are the same as or substantially the same as those described above for the constituent materials of the interlayer insulating film 184.

[0097] The upper wiring layer M1 can pass through the upper insulating film 186 and be electrically connected to or in contact with the source / drain via contact VA located under the upper wiring layer M1. The upper wiring layer M1 can include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, or be formed of molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, but the inventive concept is not limited thereto.

[0098] The lower surfaces of each of the device isolation film 112, the gap-fill insulating film 192, and the back contact DBC can be covered by the lower insulating film 198. The constituent material of the lower insulating film 198 is the same as or substantially the same as those described above for the interlayer insulating film 184.

[0099] The lower wiring film M2 can pass through the lower insulating film 198 and be electrically connected to or in contact with the back contact DBC located on the upper portion of the lower wiring film M2. The lower wiring film M2 can include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, or be formed of molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof, but the inventive concept is not limited thereto.

[0100] According to an embodiment, the gate protection film GP covers the lower surface of the gate dielectric film 152 adjacent to the back contact DBC. Thus, during the process of forming the back contact DBC, the portion of the gate dielectric film 152 adjacent to the back contact DBC can be prevented from being etched, or the etching of the gate dielectric film 152 can be reduced during the process of forming the back contact DBC.

[0101] In addition, the gate protection film GP and the back contact DBC cover the lower surface of the first source / drain region 130a, and the gap-fill insulating film 192 is spaced apart from the first source / drain region 130a with the gate protection film GP and the back contact DBC therebetween. Thus, during the process of forming the back contact DBC, the first source / drain region 130a can be prevented from being etched, or the etching of the first source / drain region 130a can be reduced during the process of forming the back contact DBC.

[0102] Therefore, defects due to partial etching of the source / drain regions 130, the gate dielectric film 152, and the gate line 160 in the integrated circuit device can be prevented or reduced, thereby obtaining an integrated circuit device with improved reliability.

[0103] Figure 4A FIG. is a diagram showing an integrated circuit device 10a according to some embodiments. Figure 4A It shows the integrated circuit device 10a and Figure 3A The corresponding part of the region "EX2". In Figure 4A Among them, the same reference numerals as those in Figure 2 and Figures 3A to 3D are given to the same components, and their repeated descriptions are omitted. The integrated circuit device 10a is different from the integrated circuit device 10 described above with reference to Figure 2 and Figures 3A to 3D in that the integrated circuit device 10a includes a gate protection film GP1 instead of the gate protection film GP. Therefore, the following description focuses on the differences between them.

[0104] Referring to Figure 4A , the integrated circuit device 10a may include a gate protection film GP1. A part of the sidewall of the back contact DBC may be covered by the gate protection film GP1, and another part of the sidewall of the back contact DBC may be covered by the gap-fill insulating film 192. For example, the gate protection film GP1 may cover the upper sidewall of the back contact DBC, and the gap-fill insulating film 192 may cover the lower sidewall of the back contact DBC. The gate protection film GP1 may be surrounded by the first source / drain region 130a, the gate dielectric film 152, the gap-fill insulating film 192, and the back contact DBC.

[0105] In some embodiments, the gate protection film GP1 may cover at least a part of the lower surface of the lowermost end of the gate dielectric film 152. The part of the lower surface of the gate dielectric film 152 covered by the gate protection film GP1 may be adjacent to the back contact DBC. In some embodiments, the gate protection film GP1 may isolate the first source / drain region 130a from the gap-fill insulating film 192. For example, the gap-fill insulating film 192 may be spaced apart from the first source / drain region 130a with the gate protection film GP1 therebetween.

[0106] In some embodiments, the back contact DBC may cover a part of the lower surface of the first source / drain region 130a, and the gate protection film GP1 may cover another part of the lower surface of the first source / drain region 130a. For example, the horizontal width of the upper part of the back contact DBC in the first horizontal direction X may be smaller than the horizontal width of the first source / drain region 130a in the first horizontal direction X. In some embodiments, the back contact DBC may completely cover the lower surface of the first source / drain region 130a, and the gate protection film GP1 may not cover / contact the lower surface of the first source / drain region 130a. For example, the horizontal width of the upper part of the back contact DBC in the first horizontal direction X may be equal to or greater than the horizontal width of the first source / drain region 130a in the first horizontal direction X.

[0107] The gate protective film GP1 may include or may be the gap-fill gate protective film GPa (see Figure 21 ) that remains after the etching process for forming the back contact hole BCH (see Figure 22A ). The manufacturing process of the gate protective film GP1 is described in detail below with reference to Figure 21 and Figure 22A .

[0108] As Figure 4A shown, the upper surface of the gate protective film GP1 may be covered by the first source / drain region 130a and the gate dielectric film 152, and the sidewall GP1S of the gate protective film GP1 opposite to the back contact DBC may be covered by the gap-fill insulating film 192. In some embodiments, the sidewall GP1S of the gate protective film GP1 opposite to the back contact DBC may have a curved shape. For example, the sidewall GP1S of the gate protective film GP1 may include a combination of a flat surface and a curved surface. For example, the sidewall GP1S of the gate protective film GP1 may include, in a cross-sectional view, a combination of a flat surface extending from the sidewall of the back contact DBC in a direction intersecting the sidewall of the back contact DBC and a curved surface facing away from the sidewall of the back contact DBC. The sidewall GP1S of the gate protective film GP1 opposite to the back contact DBC may have a convex shape protruding in a direction away from the sidewall of the back contact DBC.

[0109] Figure 4B is a diagram showing an integrated circuit device 10b according to some embodiments. Figure 4B shows a part of the integrated circuit device 10b corresponding to the region “EX2” of Figure 3A . In Figure 4B , the same reference numerals as those in Figure 2 and Figures 3A to 3D are given to the same components, and their repeated descriptions are omitted. The integrated circuit device 10b is different from the integrated circuit device 10 described above with reference to Figure 2 and Figures 3A to 3D in that the integrated circuit device 10b includes a gate protective film GP2 instead of the gate protective film GP. Therefore, the following description focuses on the differences between them.

[0110] Refer to Figure 4B, the integrated circuit device 10b may include a gate protective film GP2. A part of the sidewall of the back contact DBC may be covered by the gate protective film GP2, and another part of the sidewall of the back contact DBC may be covered by the gap-fill insulating film 192. For example, the gate protective film GP2 may cover the upper sidewall of the back contact DBC, and the gap-fill insulating film 192 may cover the lower sidewall of the back contact DBC. The gate protective film GP2 may be surrounded by the first source / drain region 130a, the gate dielectric film 152, the gap-fill insulating film 192, and the back contact DBC.

[0111] In some embodiments, the gate protective film GP2 may cover / contact at least a part of the lower surface of the lowermost end of the gate dielectric film 152. The portion of the lower surface of the gate dielectric film 152 covered by the gate protective film GP2 may be adjacent to the back contact DBC.

[0112] In some embodiments, the back contact DBC may cover / contact a part of the lower surface of the first source / drain region 130a, and the gate protective film GP2 may cover / contact another part of the lower surface of the first source / drain region 130a. For example, the horizontal width of the upper portion of the back contact DBC in the first horizontal direction X may be smaller than the horizontal width of the first source / drain region 130a in the first horizontal direction X. In some embodiments, the back contact DBC may completely cover the lower surface of the first source / drain region 130a, and the gate protective film GP2 may not cover / contact the lower surface of the first source / drain region 130a. For example, the horizontal width of the upper portion of the back contact DBC in the first horizontal direction X may be equal to or greater than the horizontal width of the first source / drain region 130a in the first horizontal direction X.

[0113] The gate protective film GP2 may include or may be the remaining part of the gap-fill gate protective film GPa (see Figure 21 ) after the etching process for forming the back contact hole BCH (see Figure 22A ). The manufacturing process of the gate protective film GP2 is described in detail below with reference to Figure 21 and Figure 22A .

[0114] As Figure 4BAs shown, the upper surface of the gate protection film GP2 can be covered by the first source / drain region 130a and the gate dielectric film 152, and the sidewall GP2S of the gate protection film GP2 opposite to the backside contact DBC can be covered by the gap-fill insulating film 192. In some embodiments, the sidewall GP2S of the gate protection film GP2 opposite to the backside contact DBC can have a flat / plane surface. For example, the sidewall GP2S of the gate protection film GP2 can include only a flat / plane surface in a cross-sectional view. The sidewall GP2S of the gate protection film GP2 can include a flat / plane surface extending from the sidewall of the backside contact DBC in a direction intersecting the sidewall of the backside contact DBC. For example, the sidewall GP2S can include an inclined surface. The sidewall GP2S of the gate protection film GP2 opposite to the backside contact DBC can be away from the sidewall of the backside contact DBC in a direction from the bottom to the top of the sidewall GP2S. The top surface of the gate protection film GP2 can also be flat.

[0115] Figure 4C FIG. is a diagram showing an integrated circuit device 10c according to some embodiments. Figure 4C FIG. shows a part of the integrated circuit device 10c corresponding to the Figure 3A region "EX2". In Figure 4C , the same reference numerals as those in Figure 2 and Figures 3A to 3D are given to the same components, and their repeated descriptions are omitted. The integrated circuit device 10c is different from the integrated circuit device 10 described above with reference to Figure 2 and Figures 3A to 3D in that the integrated circuit device 10c includes a gate protection film GP3 instead of the gate protection film GP. Therefore, the following description focuses on the differences between them.

[0116] Referring to Figure 4C , the integrated circuit device 10c can include a gate protection film GP3. A part of the sidewall of the backside contact DBC can be covered by the gate protection film GP3, and another part of the sidewall of the backside contact DBC can be covered by the gap-fill insulating film 192. For example, the gate protection film GP3 can cover the upper sidewall of the backside contact DBC, and the gap-fill insulating film 192 can cover the lower sidewall of the backside contact DBC. The gate protection film GP3 can be surrounded by, or in contact with, the first source / drain region 130a, the gate dielectric film 152, the gap-fill insulating film 192, and the backside contact DBC.

[0117] In some embodiments, the gate protective film GP3 may cover at least a part of the lower surface of the lowermost end of the gate dielectric film 152. The portion of the lower surface of the gate dielectric film 152 covered by the gate protective film GP3 may be adjacent to the back contact DBC.

[0118] In some embodiments, the back contact DBC may cover a part of the lower surface of the first source / drain region 130a, and the gate protective film GP3 may cover another part of the lower surface of the first source / drain region 130a. For example, the horizontal width of the upper portion of the back contact DBC in the first horizontal direction X may be smaller than the horizontal width of the first source / drain region 130a in the first horizontal direction X. In some embodiments, the back contact DBC may completely cover the lower surface of the first source / drain region 130a, and the gate protective film GP3 may not cover (e.g., may not contact) the lower surface of the first source / drain region 130a. For example, the horizontal width of the upper portion of the back contact DBC in the first horizontal direction X may be equal to or greater than the horizontal width of the first source / drain region 130a in the first horizontal direction X.

[0119] The gate protective film GP3 may include or may be the remaining portion of the gap-fill gate protective film GPa (see Figure 21 ) after the etching process for forming the back contact hole BCH (see Figure 22A ). The manufacturing process of the gate protective film GP3 is described in detail below with reference to Figure 21 and Figure 22A .

[0120] As Figure 4C shown, the upper surface of the gate protective film GP3 may be covered by the first source / drain region 130a and the gate dielectric film 152, and the sidewall GP3S of the gate protective film GP3 opposite to the back contact DBC may be covered by the gap-fill insulating film 192. In some embodiments, the sidewall GP3S of the gate protective film GP3 opposite to the back contact DBC may have a sharp / angular shape, which has an acute angle in a cross-sectional view, for example. For example, the sidewall GP3S of the gate protective film GP3 opposite to the back contact DBC may include a vertex P. The sidewall GP3S of the gate protective film GP3 opposite to the back contact DBC may be away from the sidewall of the back contact DBC in the direction approaching the vertex P from the top and bottom of the gate protective film GP3.

[0121] Figure 4D is a diagram showing an integrated circuit device 10d according to some embodiments. Figure 4D shows a part of the integrated circuit device 10d corresponding to the region “EX2” of Figure 3A . In Figure 4D , the part corresponding to Figure 2 andFigures 3A to 3D Like reference numerals in the accompanying drawings denote like components, and their repeated description is omitted. The integrated circuit device 10d is different from the integrated circuit device 10 described above with reference to Figure 2 and Figures 3A to 3D in that the integrated circuit device 10d includes a gate protective film GP4 instead of the gate protective film GP. Therefore, the following description focuses on the differences between them.

[0122] Referring to Figure 4D , the integrated circuit device 10d may include a gate protective film GP4. A part of the sidewall of the back contact DBC may be covered by the gate protective film GP4, and another part of the sidewall of the back contact DBC may be covered by the gap-fill insulating film 192. For example, the gate protective film GP4 may cover / contact the upper sidewall of the back contact DBC, and the gap-fill insulating film 192 may cover / contact the lower sidewall of the back contact DBC. The gate protective film GP4 may be surrounded by, or in contact with, the first source / drain region 130a, the gate dielectric film 152, the gap-fill insulating film 192, and the back contact DBC.

[0123] In some embodiments, the gate protective film GP4 may cover / contact at least a part of the lower surface of the lowermost end of the gate dielectric film 152. The portion of the lower surface of the gate dielectric film 152 covered by the gate protective film GP4 may be adjacent to the back contact DBC.

[0124] In some embodiments, the back contact DBC may cover / contact a part of the lower surface of the first source / drain region 130a, and the gate protective film GP4 may cover / contact another part of the lower surface of the first source / drain region 130a. For example, the horizontal width of the upper portion of the back contact DBC in the first horizontal direction X may be smaller than the horizontal width of the first source / drain region 130a in the first horizontal direction X. In some embodiments, the back contact DBC may completely cover the lower surface of the first source / drain region 130a, and the gate protective film GP4 may not cover (e.g., may not contact) the lower surface of the first source / drain region 130a. For example, the horizontal width of the upper portion of the back contact DBC in the first horizontal direction X may be equal to or greater than the horizontal width of the first source / drain region 130a in the first horizontal direction X.

[0125] The gate protective film GP4 may include or may be the remaining part of the gap-fill gate protective film GPa (see Figure 21 ) after the etching process for forming the back contact hole BCH (see Figure 22A ). The manufacturing process of the gate protective film GP4 is described below with reference to Figure 21 andFigure 22A Detailed description.

[0126] As Figure 4D shown, the upper surface of the gate protection film GP4 can be covered by and / or in contact with the first source / drain region 130a and the gate dielectric film 152, and the sidewall GP4S of the gate protection film GP4 opposite to the back contact DBC can be covered by the gap-fill insulating film 192. In some embodiments, the sidewall GP4S of the gate protection film GP4 opposite to the back contact DBC can have a flat / plane surface. For example, the sidewall / surface GP4S of the gate protection film GP4 can include, for example, only a plurality of flat surfaces extending in different directions in a cross-sectional view. For example, the sidewall / surface GP4S of the gate protection film GP4 can include a first flat surface and a second flat surface. The first flat surface extends from the sidewall of the back contact DBC in a direction intersecting the sidewall of the back contact DBC, and the second flat surface faces away from the sidewall of the back contact DBC and extends in a direction intersecting the first flat surface. For example, the first flat surface can be a flat / plane surface extending in the first horizontal direction X, and the second flat surface can be a flat / plane surface extending in the vertical direction Z. The sidewall GP4S of the gate protection film GP4 opposite to the back contact DBC can be away from the sidewall of the back contact DBC in a direction moving from the bottom to the top of the sidewall GP4S opposite to the back contact DBC.

[0127] Figure 4E is a diagram showing an integrated circuit device 10e according to some embodiments. Figure 4E shows a portion of the integrated circuit device 10e corresponding to the Figure 3A region "EX2". In Figure 4E it, the same reference numerals as those in the Figure 2 and Figures 3A to 3D drawings are given to the same components, and their repeated descriptions are omitted. The integrated circuit device 10e is different from the integrated circuit device 10 described above with reference to Figure 2 and Figures 3A to 3D in that the integrated circuit device 10e includes a gate protection film GP5 instead of the gate protection film GP. Therefore, the following description focuses on the differences between them.

[0128] Referring to Figure 4E, the integrated circuit device 10e may include a gate protective film GP5. A part of the sidewall of the back contact DBC may be covered by the gate protective film GP5, and another part of the sidewall of the back contact DBC may be covered by the gap-fill insulating film 192. For example, the gate protective film GP5 may cover / contact the upper sidewall of the back contact DBC, and the gap-fill insulating film 192 may cover / contact the lower sidewall of the back contact DBC. The gate protective film GP5 may be surrounded by, or in contact with, the first source / drain region 130a, the gate dielectric film 152, the gap-fill insulating film 192, and the back contact DBC.

[0129] In some embodiments, the gate protective film GP5 may cover / contact at least a portion of the lower surface of the lowermost end of the gate dielectric film 152. The portion of the lower surface of the gate dielectric film 152 covered by the gate protective film GP5 may be adjacent to the back contact DBC.

[0130] In some embodiments, the back contact DBC may cover / contact a portion of the lower surface of the first source / drain region 130a, and the gate protective film GP5 may cover / contact another portion of the lower surface of the first source / drain region 130a. For example, the horizontal width of the upper portion of the back contact DBC in the first horizontal direction X may be less than the horizontal width of the first source / drain region 130a in the first horizontal direction X. In some embodiments, the back contact DBC may completely cover the lower surface of the first source / drain region 130a, and the gate protective film GP5 may not cover (e.g., may not contact) the lower surface of the first source / drain region 130a. For example, the horizontal width of the upper portion of the back contact DBC in the first horizontal direction X may be equal to or greater than the horizontal width of the first source / drain region 130a in the first horizontal direction X.

[0131] The gate protective film GP5 may include or may be the remaining portion of the gap-fill gate protective film GPa (see Figure 21 ) after the etching process for forming the back contact hole BCH (see Figure 22A ). The manufacturing process of the gate protective film GP5 is described in detail below with reference to Figure 21 and Figure 22A in detail.

[0132] As Figure 4EAs shown, the upper surface of the gate protection film GP5 can be covered by or in contact with the first source / drain region 130a and the gate dielectric film 152, and the sidewall GP5S of the gate protection film GP5 opposite to the back contact DBC can be covered by or in contact with the gap-fill insulating film 192. In some embodiments, the sidewall GP5S of the gate protection film GP5 opposite to the back contact DBC can have a flat surface. For example, the sidewall / surface GP5S of the gate protection film GP5 can include, for example, only a plurality of flat surfaces extending in different directions in a cross-sectional view. For example, the sidewall / surface GP5S of the gate protection film GP5 can include a first flat surface and a second flat surface. The first flat surface extends from the sidewall of the back contact DBC in a direction intersecting with the sidewall of the back contact DBC, and the second flat surface faces away from the sidewall of the back contact DBC and extends in a direction intersecting with the first flat surface. For example, the first flat surface can be a flat / plane surface diagonally extending between the first horizontal direction X and the vertical direction Z (e.g., between the first horizontal direction X, the second horizontal direction Y, and the vertical direction Z), and the second flat surface can be a flat / plane surface extending in the vertical direction Z. The sidewall GP5S of the gate protection film GP5 opposite to the back contact DBC can be away from the sidewall of the back contact DBC in a direction from the bottom to the top of the sidewall GP5S.

[0133] Similar to the integrated circuit device 10 described with reference to Figure 2 and Figures 3A to 3D the integrated circuit devices 10a, 10b, 10c, 10d, and 10e described with reference to Figures 4A to 4E include gate protection films GP1, GP2, GP3, GP4, and GP5. Therefore, during the process of forming the back contact DBC, defects in the integrated circuit device due to partial etching of the portion of the gate dielectric film 152 adjacent to the back contact DBC, the source / drain region 130, and the gate line 160 can be prevented or reduced, thereby obtaining an integrated circuit device with improved reliability.

[0134] Figure 5A FIG. is a diagram showing an integrated circuit device 20 according to some embodiments. Figure 5A FIG. is a cross-sectional view corresponding to the integrated circuit device 20 taken along the line X1-X1'. In Figure 2 , the same reference numerals as those in Figure 5A and Figure 2 and Figures 3A to 3D are assigned to the same components, and their repeated descriptions are omitted. The integrated circuit device 20 is the same as that described above with reference to Figure 2 and Figures 3A to 3DThe described integrated circuit device 10 is different in that the integrated circuit device 20 further includes a gap-fill gate protection film GPa. Therefore, the following description focuses on the differences between them.

[0135] As Figure 5A shown, each of the plurality of source / drain regions 130 may be located between a plurality of nanosheet stacks NSS spaced apart from each other in a first horizontal direction X.

[0136] A plurality of gate lines 160 may be disposed over a front surface 192F of the gap-fill insulating film 192. The gap-fill insulating film 192 may cover / contact at least a portion of a lower surface of a lowermost end of the gate dielectric film 152.

[0137] In some embodiments, a back contact DBC may be disposed under a source / drain region 130 selected from among the plurality of source / drain regions 130. For example, the back contact DBC may be disposed under a first source / drain region 130a. The back contact DBC may, for example, longitudinally extend vertically through the gap-fill insulating film 192 and contact the source / drain region 130.

[0138] In some embodiments, a gate protection film GP may be disposed under the first source / drain region 130a, and a gap-fill gate protection film GPa may be disposed under a second source / drain region 130b.

[0139] In some embodiments, the gate protection film GP may cover / contact at least a portion of a lower surface of a lowermost end of the gate dielectric film 152. A portion of the lower surface of the gate dielectric film 152 covered by the gate protection film GP may be adjacent to the back contact DBC.

[0140] In some embodiments, the back contact DBC may cover / contact a portion of a lower surface of the first source / drain region 130a, and the gate protection film GP may cover / contact another portion of the lower surface of the first source / drain region 130a. For example, a horizontal width of an upper portion of the back contact DBC in the first horizontal direction X may be less than a horizontal width of the first source / drain region 130a in the first horizontal direction X. In some embodiments, the back contact DBC may completely cover the lower surface of the first source / drain region 130a, and the gate protection film GP may not cover (e.g., may not contact) the lower surface of the first source / drain region 130a. For example, a horizontal width of an upper portion of the back contact DBC in the first horizontal direction X may be equal to or greater than a horizontal width of the first source / drain region 130a in the first horizontal direction X.

[0141] In some embodiments, the gap-fill gate protection film GPa may cover / contact at least a portion of the lower surface of the lowermost end of the gate dielectric film 152. The portion of the lower surface of the gate dielectric film 152 covered by the gap-fill gate protection film GPa may be adjacent to the second source / drain region 130b. The horizontal width of the gap-fill gate protection film GPa in the first horizontal direction X may be greater than the horizontal width of the second source / drain region 130b in the first horizontal direction X. In some embodiments, the gap-fill gate protection film GPa may isolate the second source / drain region 130b from the gap-fill insulating film 192. For example, the gap-fill insulating film 192 may be spaced apart from the second source / drain region 130b with the gap-fill gate protection film GPa therebetween.

[0142] The gate protection film GP may include or may be the remaining portion of the gap-fill gate protection film GPa after the etching process for forming the back contact hole BCH (see Figure 22A ). The manufacturing process of the gate protection film GP will be described in detail below with reference to Figure 21 and Figure 22A .

[0143] As Figure 5A shown, the upper surface of the gate protection film GP may be covered or contacted by the first source / drain region 130a and the gate dielectric film 152, the sidewall of the gate protection film GP opposite to the back contact DBC may be covered or contacted by the gap-fill insulating film 192. In some embodiments, the sidewall of the gate protection film GP may have a curved shape, which is opposite to the sidewall of the gate protection film GP contacting the back contact DBC. The sidewall of the gate protection film GP opposite to the back contact DBC may have a convex shape protruding in a direction away from the back contact DBC.

[0144] In addition, the upper surface of the gap-fill gate protection film GPa may be covered or contacted by the second source / drain region 130b and the gate dielectric film 152, the sidewall and the lower surface of the gap-fill gate protection film GPa may be covered or contacted by the gap-fill insulating film 192. In some embodiments, the sidewall of the gap-fill gate protection film GPa may have a curved shape. For example, the sidewall of the gap-fill gate protection film GPa may have a convex shape. However, the shape of the gap-fill gate protection film GPa is not limited to Figure 5A the shape shown, and may have various shapes. The gap-fill gate protection film GPa may have shapes respectively corresponding to those referred to in Figure 4A , Figure 4B , Figure 4C , Figure 4D andFigure 4E The shapes of the described gate protective films GP1, GP2, GP3, GP4, and GP5 are similar, so the descriptions of the gate protective films GP1, GP2, GP3, GP4, and GP5 can be applied to the gap-fill gate protective film GPa, unless otherwise indicated by the context.

[0145] In some embodiments, the gap-fill gate protective film GPa may include SiGe, SiGeC, SiC, SiO, SiOC, SiOCN, SiOH, GeC, or a combination thereof, or may be formed of SiGe, SiGeC, SiC, SiO, SiOC, SiOCN, SiOH, GeC, or a combination thereof. The gap-fill gate protective film GPa may include materials the same as or similar to the materials described for the Figures 3A to 3D constituent materials of the gate protective film GP, or may be formed of materials the same as or similar to the materials described for the Figures 3A to 3D constituent materials of the gate protective film GP. In some embodiments, the gap-fill gate protective film GPa may have a height of about 3 nanometers to about 6 nanometers in the vertical direction Z.

[0146] According to an embodiment, the gate protective film GP may cover / contact a portion of the lower surface of the gate dielectric film 152 adjacent to the first source / drain region 130a, and the gap-fill gate protective film GPa may cover / contact a portion of the lower surface of the gate dielectric film 152 adjacent to the second source / drain region 130b. Accordingly, during the process of forming the back contact DBC, the portion of the gate dielectric film 152 adjacent to the source / drain region 130 is prevented from being etched, or the etching of the gate dielectric film 152 adjacent to the source / drain region 130 may be reduced.

[0147] In addition, the gate protective film GP and the back contact DBC cover / contact the lower surface of the first source / drain region 130a, and the gap-fill gate protective film GPa covers / contact the lower surface of the second source / drain region 130b. Accordingly, during the process of forming the back contact DBC, the plurality of source / drain regions 130 are prevented from being etched, or the etching of the plurality of source / drain regions 130 may be reduced during the process of forming the back contact DBC. Accordingly, defects caused by partial etching of the plurality of source / drain regions 130, the gate dielectric film 152, and the plurality of gate lines 160 can be prevented or reduced, thereby obtaining an integrated circuit device with improved reliability.

[0148] Figure 5B is a diagram showing an integrated circuit device 30 according to some embodiments. Figure 5B is a cross-sectional view of the integrated circuit device 30 corresponding to a cross-section taken along the Figure 2 line X1-X1'. In Figure 5B it will be withFigure 2 , Figures 3A to 3D and Figure 5A the same reference numerals in the accompanying drawings as those in Figure 5A are assigned to the same components, and their repeated descriptions are omitted. The integrated circuit device 30 is different from the integrated circuit device 20 described above with reference to

[0149] in that the integrated circuit device 30 further includes a placeholder PH. Therefore, the following description focuses on the differences between them. Figure 5B As Figure 10 shown, the placeholder PH formed under the gap-fill gate protective film GPa can extend downward from the lower surface of the gap-fill gate protective film GPa and pass through the gap-fill insulating film 192. The placeholder PH can correspond to a structure formed by the remaining portion of the placeholder PH (see

[0150] ) formed under the gap-fill gate protective film GPa.

[0151] In some embodiments, the placeholder PH can include or be formed of a SiGe film. For example, the placeholder PH can include a single-crystalline SiGe film, a polycrystalline SiGe film, an amorphous SiGe film, or a combination thereof, or be formed of a single-crystalline SiGe film, a polycrystalline SiGe film, an amorphous SiGe film, or a combination thereof. Figure 7 ) and the fin-type active region F1 (see

[0152] Next, a method of manufacturing an integrated circuit device according to an embodiment will be described below.

[0153] Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10 , Figure 11A , Figure 11B , Figure 12 , Figure 13A , Figure 13B , Figures 14 to 16 , Figure 17A , Figure 17B ,Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20 , Figure 21 , Figure 22A , Figure 22B , Figure 23A and Figure 23B are diagrams showing a method of manufacturing an integrated circuit device according to an embodiment in a process sequence.

[0154] Specifically, Figure 6 , Figure 8A , Figure 9A , Figure 10 , Figure 11A , Figure 13A , Figures 14 to 16 , Figure 17A , Figure 18A , Figure 19A , Figure 20 , Figure 21 , Figure 22A and Figure 23A are diagrams showing the manufacturing process corresponding to the cross-section taken along the line X1-X1' of Figure 2 . Figure 7 , Figure 8B , Figure 9B , Figure 11B , Figure 12 , Figure 13B , Figure 17B , Figure 18B , Figure 19B , Figure 22B and ​ are diagrams showing the manufacturing process corresponding to the cross-section taken along the line Y1-Y1' of ​ .

[0155] In ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , Figure 19A , Figure 19B , Figure 20 , Figure 21 , Figure 22A , Figure 22B , Figure 23A andFigure 23B In Figure 2 and Figures 3A to 3D the same reference numerals are given to the same components / elements as those in the accompanying drawings, and their repeated description is omitted here.

[0156] Referring to Figure 6 , a plurality of sacrificial semiconductor layers 103 and a plurality of nanosheet semiconductor layers NS can be alternately stacked one layer at a time on a substrate 102. The substrate 102 can include an elemental semiconductor (such as Si and Ge) or a compound semiconductor (such as SiGe, SiC, GaAs, InAs, InGaAs, and InP), or be formed of the elemental semiconductor or the compound semiconductor. Each of the terms "SiGe", "SiC", "GaAs", "InAs", "InGaAs", and "InP" used herein indicates a material including the elements shown in each term and is not a chemical formula representing a stoichiometric relationship. For example, the substrate 102 can include or can be a bulk Si substrate.

[0157] The plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS can include or be formed of semiconductor materials having different etching rates from each other, so as to have a sufficiently high etching selectivity therebetween. In some embodiments, the plurality of nanosheet semiconductor layers NS can include or can be Si layers, and the plurality of sacrificial semiconductor layers 103 can include or can be SiGe film layers. In some embodiments, the Ge content in the plurality of sacrificial semiconductor layers 103 can be constant, for example, constant throughout the plurality of sacrificial semiconductor layers 103. The SiGe film constituting the plurality of sacrificial semiconductor layers 103 can have a constant Ge content, for example, constant throughout the SiGe film, and the Ge content can be selected in the range from about 5 at% to about 60 at% (for example, from about 10 at% to about 40 at%). The Ge content in the SiGe film constituting the plurality of sacrificial semiconductor layers 103 can be selected in various ways as necessary.

[0158] Referring to Figure 7 , the mask patterns MP1 are each formed on Figure 6On the structure shown, then a plurality of sacrificial semiconductor layers 103, a plurality of nanosheet semiconductor layers NS, and a substrate 102 are partially etched using a mask pattern MP1 as an etch mask. As a result, fin-type active regions F1 can be formed on the substrate 102. A plurality of trench regions T1 can be defined on the substrate 102 through the plurality of fin-type active regions F1. In some embodiments, each mask pattern MP1 can have a stacked structure of an oxide film pattern and a silicon nitride film pattern. The mask patterns MP1 can extend parallel to each other on the substrate 102 in a first horizontal direction X. The stacked structure of the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS can remain on the fin top surface FT of each fin-type active region F1.

[0159] Subsequently, a device isolation insulating film P112 can be formed on the obtained result. The device isolation insulating film P112 can have a thickness sufficient to fill the space of the plurality of trench regions T1 above the substrate 102. The device isolation insulating film P112 can include or can be a silicon oxide film.

[0160] To form the device isolation insulating film P112, a plasma enhanced chemical vapor deposition (PECVD) process, a high density plasma CVD (HDP CVD) process, an inductively coupled plasma CVD (ICP CVD) process, a capacitively coupled plasma CVD (CCP CVD) process, a flowable chemical vapor deposition (FCVD) process, a spin coating process, etc. can be used.

[0161] Referring to Figure 8A and Figure 8B , after planarizing Figure 7 the structure shown such that the upper surface of the mask pattern MP1 is exposed, the exposed mask pattern MP1 is removed, and a recess process is performed to remove a part of the device isolation insulating film P112. Thus, a device isolation film 112 can be formed. As a result, the plurality of sacrificial semiconductor layers 103 and the plurality of nanosheet semiconductor layers NS (see Figure 7 ) can protrude above the upper surface of the device isolation film 112.

[0162] To perform the recess process of the device isolation insulating film P112, a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process can be used. In addition, a wet etching process using NH4OH, tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), etc. as an etchant can be used. In addition, a dry etching process such as inductively coupled plasma (ICP), transformer coupled plasma (TCP), electron cyclotron resonance (ECR), and / or reactive ion etching (RIE) can be used. When performing the recess process for the device isolation insulating film P112 by using a dry etching process, a fluorine-containing gas (such as CF4), a chlorine-containing gas (such as Cl2), HBr, etc. can be used as an etching gas.

[0163] Multiple dummy gate structures DGS can be formed on a stacked structure of multiple sacrificial semiconductor layers 103 and multiple nanosheet semiconductor layers NS. Each of the multiple dummy gate structures DGS can extend longitudinally in a second horizontal direction Y. Each of the multiple dummy gate structures DGS can have a structure in which an oxide film D122, a dummy gate layer D124, and a capping layer D126 are sequentially stacked on a top surface of the stacked structure of the multiple sacrificial semiconductor layers 103 and the multiple nanosheet semiconductor layers NS. In some embodiments, the oxide film D122 can include or can be a film obtained by oxidizing a surface of the uppermost one of the multiple nanosheet semiconductor layers NS (see Figure 7 ). The dummy gate layer D124 can include or can be formed of polysilicon, and the capping layer D126 can include or can be a silicon nitride film.

[0164] Multiple outer insulating spacers 118 are formed to cover two sidewalls of each of the multiple dummy gate structures DGS, and then each of the multiple sacrificial semiconductor layers 103 and the multiple nanosheet semiconductor layers NS is partially etched using the multiple dummy gate structures DGS and the multiple outer insulating spacers 118 as an etching mask. Thus, the multiple nanosheet semiconductor layers NS are divided into multiple nanosheet stacks NSS, and each nanosheet stack NSS includes a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3. To etch a portion of each of the multiple sacrificial semiconductor layers 103 and the multiple nanosheet semiconductor layers NS, dry etching, wet etching, or a combination thereof can be used.

[0165] Subsequently, a first recess R1 can be formed by partially etching a fin-type active region F1, and the fin-type active region F1 is exposed by partially etching the multiple sacrificial semiconductor layers 103 and the multiple nanosheet semiconductor layers NS. To form the first recess R1, an etching process can be performed using dry etching, wet etching, or a combination thereof. After forming the first recess R1, multiple recess side insulating spacers 119 adjacent to the first recess R1 can be formed on the device isolation film 112.

[0166] In some embodiments, an etching process can be performed to form the first recess R1 such that a bottom of the first recess R1 is at the same level in a vertical direction Z as a bottom surface of a trench region T1 defining the fin-type active region F1. However, the embodiments are not limited thereto. The bottom of the first recess R1 can be at a level higher than a level of the bottom surface of the trench region T1 defining the fin-type active region F1, or at a level lower than a level of the bottom surface of the trench region T1 defining the fin-type active region F1.

[0167] Refer to Figure 9A and Figure 9B, a sacrificial insulating spacer 128 can be formed to extend along the sidewalls of the capping layer D126, the sidewalls of the plurality of outer insulating spacers 118, and the sidewalls of the plurality of nanosheet stacks NSS. The sacrificial insulating spacer 128 can extend to cover the upper surface of the fin-shaped active region F1 exposed in the structure shown in Figure 8A and Figure 8B .

[0168] For example, the sacrificial insulating spacer 128 can include or be formed of a silicon nitride film. The sacrificial insulating spacer 128 can be deposited using various methods such as PECVD process, HDP CVD process, ICP CVD process, CCP CVD process, FCVD process, and spin coating process.

[0169] Subsequently, a portion of the sacrificial insulating spacer 128 that extends along the inner wall of the first recess R1 can be removed, and a placeholder PH that fills the first recess R1 can be formed. In some embodiments, the placeholder PH can include or be formed of a SiGe film. For example, the placeholder PH can include a single crystal SiGe film, a polycrystalline SiGe film, an amorphous SiGe film, or a combination thereof, or be formed of a single crystal SiGe film, a polycrystalline SiGe film, an amorphous SiGe film, or a combination thereof.

[0170] In some embodiments, the placeholder PH can be deposited using raw materials containing elemental precursors by various methods such as PECVD process, HDP CVD process, ICP CVD process, CCP CVD process, and FCVD process. In some embodiments, to form the placeholder PH, a low-pressure CVD (LPCVD) process, a selective epitaxial growth (SEG) process, or a cyclic deposition etching (CDE) process can be performed using raw materials including elemental semiconductor precursors. The elemental semiconductor precursor can include or be a Si source containing elemental Si. Silane (SiH4), disilane (Si2H6), trisilane (Si3H8), dichlorosilane (SiH2Cl2), etc. can be used as the Si source, but the inventive concept is not limited thereto. In addition, the elemental semiconductor precursor can include or be a Ge source containing elemental Ge. Germane (GeH4), digermane (Ge2H6), trigermane (Ge3H8), tetragermane (Ge4H 10 ), dichlorogermane (GeH2Cl2), etc. can be used as the Ge source, but the inventive concept is not limited thereto. For example, the placeholder PH can be formed by epitaxially growing a SiGe film from the surface of the fin-shaped active region F1 exposed from the sidewalls and bottom of the first recess R1. In this case, the placeholder PH can include or be a single crystal SiGe film.

[0171] In some embodiments, the Ge content in the placeholder PH can be constant, e.g., constant throughout the placeholder PH. The SiGe film constituting the placeholder PH can have a constant Ge content, e.g., constant throughout the SiGe film, and the Ge content can be selected in the range from about 5 at% to about 60 at% (e.g., from about 10 at% to about 40 at%). However, the Ge content in the SiGe film constituting the placeholder PH can be selected in various ways within a range where the etching rates of the placeholder PH and the fin active region F1 are different from each other so as to have a sufficiently high etching selectivity between the placeholder PH and the fin active region F1.

[0172] In some embodiments, a plurality of first recesses R1 can be provided, and a plurality of placeholders PH filling the plurality of first recesses R1 can also be provided.

[0173] Subsequently, the upper portion of the placeholder PH can be partially and selectively etched to form a second recess R2. The selective etching process for partially and selectively etching the upper portion of the placeholder PH can be performed using a dry etching process, a wet etching process, or a combination thereof. The selective etching process can utilize the feature that the placeholder PH has a higher etching rate (e.g., high etching selectivity to the fin active region F1) than the fin active region F1. For example, in order to remove the placeholder PH, a wet etching process can be performed using an etchant in which HF, H2O2, and CH3COOH are mixed.

[0174] In some embodiments, the second recess R2 can have a height of 3 nanometers to about 6 nanometers in the vertical direction Z from the upper surface of the placeholder PH to the upper surface of the fin active region F1.

[0175] Referring to Figure 10 , a third recess R3 can be formed by partially recessing the fin active region F1 exposed on the sidewall of the second recess R2. To form the third recess R3, a dry etching process, a wet etching process, or a combination thereof can be used. The etching process for forming the third recess R3 can be performed in situ following the etching process for forming the second recess R2 described with reference to Figure 9A and Figure 9B . The etching process for forming the third recess R3 can utilize the feature that the fin active region F1 has a higher etching rate (e.g., high etching selectivity to the placeholder PH) than the placeholder PH.

[0176] In some embodiments, in order to form the gate protective films GP and GP1 having a curved shape as shown in Figure 3D and Figure 4A respectively, an isotropic etching process can be used to form the third recess R3. For example, the etching process can be performed using HCl, or the etching process can be performed using reactive ion etching (RIE).

[0177] In some embodiments, in order to form gate protective films GP2, GP3, GP4, and GP5 having sharp or angular shapes as shown in Figure 4B , Figure 4C , Figure 4D and Figure 4E respectively, an anisotropic etching process can be used to form a third recess R3. For example, when performing an etching process using KOH, NHOH4, or tetramethylammonium hydroxide (TMAH), the etching rate on the crystal plane (lattice plane) in a specific direction is different from the etching rate on the crystal plane (lattice plane) in another direction. Therefore, the third recess R3 can be formed to have a sharp or angular shape.

[0178] Subsequently, a gap-fill gate protective film GPa can be formed to fill the third recess R3. The gap-fill gate protective film GPa can include a material having an etching rate different from that of the fin-type active region F1, for example, a material having a sufficiently high etching selectivity to the fin-type active region F1. For example, the gap-fill gate protective film GPa can include a material having a higher bonding energy than the material constituting the fin-type active region F1, or can be formed of a material having a higher bonding energy than the material constituting the fin-type active region F1. The gap-fill gate protective film GPa can include a silicon oxide film, a silicon carbide film, SiOC, SiOCN, SiOH, GeC, or a combination thereof, or can be formed of a silicon oxide film, a silicon carbide film, SiOC, SiOCN, SiOH, GeC, or a combination thereof. The gap-fill gate protective film GPa can include a single crystal film, a polycrystalline film, or an amorphous film, or can be formed of a single crystal film, a polycrystalline film, or an amorphous film. For example, the gap-fill gate protective film GPa can include or can be a silicon carbide film, and the carbon content in the gap-fill gate protective film GPa can be about 10 at% to about 30 at% or about 5 at% to about 25 at%.

[0179] In some embodiments, the gap-fill gate protective film GPa can be deposited using raw materials containing elemental precursors by various methods such as PECVD process, HDP CVD process, ICP CVD process, CCP CVD process, and FCVD process. In some embodiments, in order to form the gap-fill gate protective film GPa, an LPCVD process, a SEG process, or a CDE process can be performed using raw materials including elemental semiconductor precursors. The elemental precursors can include or can be an Si source containing elemental Si, a C source containing elemental C, an N source containing elemental N, an N source containing OH, or a Ge source containing elemental Ge. For example, the gap-fill gate protective film GPa can be formed by epitaxially growing a silicon carbide film from the surface of the fin-type active region F1 exposed from a part of the inner wall of the third recess R3 and from the surface of the placeholder PH exposed from another part of the inner wall of the third recess R3.

[0180] In some embodiments, when a plurality of placeholders PH are provided in an integrated circuit device, a plurality of gap-fill gate protective films GPa may also be provided in the integrated circuit device.

[0181] Referring to Figure 11A and Figure 11B , a plurality of lower source / drain regions 134 may be formed after selectively removing the sacrificial insulating spacers 128. A liquid-phase or gas-phase etchant may be used to selectively remove the sacrificial insulating spacers 128. In some embodiments, a CH3COOH-based etchant (e.g., an etchant including a mixture of CH3COOH, HNO3, and HF or an etchant including a mixture of CH3COOH, H2O2, and HF) may be used to selectively remove the sacrificial insulating spacers 128, but the inventive concept is not limited to these examples.

[0182] Each of the plurality of lower source / drain regions 134 may include or may be formed of a first semiconductor film 1342 and a second semiconductor film 1344. Each of the first semiconductor film 1342 and the second semiconductor film 1344 may include or may be a single-crystal film, a polycrystalline film, or an amorphous film. Each of the first semiconductor film 1342 and the second semiconductor film 1344 may include or may be a Si film or a SiGe film. In some embodiments, the first semiconductor film 1342 may include or may be a Si film, and the second semiconductor film 1344 may include or may be a SiGe film. Further, in some embodiments, when each of the first semiconductor film 1342 and the second semiconductor film 1344 includes a SiGe film, the Ge content in the first semiconductor film 1342 may be less than the Ge content in the second semiconductor film 1344.

[0183] The first semiconductor film 1342 and the second semiconductor film 1344 may be sequentially deposited by various methods such as a PECVD process, an HDP CVD process, an ICP CVD process, a CCP CVD process, and an FCVD process using raw materials containing elemental precursors. For example, the first semiconductor film 1342 may be formed by epitaxially growing a Si film or a SiGe film from the surface of the fin-type active region F1, the surface of the gap-fill gate protective film GPa, and the sidewalls of the nanosheet stack NSS. Further, the second semiconductor film 1344 may be formed by epitaxially growing a SiGe film from the surface of the first semiconductor film 1342 and the sidewalls of the nanosheet stack NSS.

[0184] Referring to Figure 12 , it may be possible to Figure 11A and Figure 11BA plurality of upper source / drain regions 132 are formed on the structure shown, thereby forming a plurality of source / drain regions 130. The plurality of source / drain regions 130 may include a first source / drain region 130a and a second source / drain region 130b.

[0185] To form the plurality of upper source / drain regions 132, semiconductor material may be epitaxially grown from the exposed surfaces of the plurality of lower source / drain regions 134 in the Figure 11A and Figure 11B structure shown and the sidewalls of each of the first nanosheet N1, second nanosheet N2, and third nanosheet N3 in the nanosheet stack NSS.

[0186] Referring to Figure 13A and Figure 13B , an insulating liner 142 covering the Figure 12 structure shown is formed, and an inter-gate insulating film 144 is formed on the insulating liner 142. Subsequently, a portion of each of the insulating liner 142 and the inter-gate insulating film 144 may be etched to expose the upper surfaces of the plurality of capping layers D126. Then, the plurality of capping layers D126 are removed to expose the dummy gate layer D124, and the insulating liner 142 and the inter-gate insulating film 144 may be partially removed such that the upper surface of the inter-gate insulating film 144 and the upper surface of the dummy gate layer D124 are at approximately the same level.

[0187] Referring to Figure 14 , a gate space GS may be prepared by removing the dummy gate layer D124 and the oxide film D122 under the dummy gate layer D124 from the Figure 13A and Figure 13B structure shown, and the plurality of nanosheet stacks NSS may be exposed through the gate space GS. Subsequently, the plurality of sacrificial semiconductor layers 103 may be removed through the gate space GS. Thus, the gate space GS may extend to each of the space between the first nanosheet N1, second nanosheet N2, and third nanosheet N3 and the space between the upper surface of the fin-type active region F1 and the third nanosheet N3. In some embodiments, to selectively remove the plurality of sacrificial semiconductor layers 103, the first nanosheet N1, second nanosheet N2, and third nanosheet N3 may have an etching rate different from that of the plurality of sacrificial semiconductor layers 103, for example, characterized by having a high etching selectivity for the plurality of sacrificial semiconductor layers 103.

[0188] The plurality of sacrificial semiconductor layers 103 may be selectively removed using a liquid or a gaseous etchant. In some embodiments, a CH3COOH-based etchant (e.g., a mixture including CH3COOH, HNO3, and HF or an etchant formed from the mixture, or a mixture including CH3COOH, H2O2, and HF or an etchant formed from the mixture) may be used to selectively remove the plurality of sacrificial semiconductor layers 103, but the inventive concept is not limited to these examples.

[0189] Referring Figure 15 , a gate dielectric film 152 may be formed on the structure shown in Figure 14 to cover the exposed surfaces of each of the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fin-type active region F1. The gate dielectric film 152 may be formed using an atomic layer deposition (ALD) process.

[0190] Referring Figure 16 , a gate line 160 may be formed to fill the gate space GS (see Figure 15 ) from above the gate dielectric film 152 and cover the upper surface of the inter-gate insulating film 144. A capping insulating pattern 168 may be formed in the gate space GS to cover the upper surfaces of each of the gate line 160 and the gate dielectric film 152.

[0191] Referring Figure 17A and Figure 17B , a source / drain contact hole (not shown) may be formed in the structure shown in Figure 16 to pass through an insulating structure including the insulating liner 142 and the inter-gate insulating film 144 and expose the second source / drain region 130b. A portion of the second source / drain region 130b may be removed via the source / drain contact hole by an anisotropic etching process. Accordingly, the source / drain contact hole may extend a long distance in the vertical direction Z. Subsequently, a metal silicide film 172 may be formed on the second source / drain region 130b exposed at the bottom and the side surfaces of the source / drain contact hole. In some embodiments, in order to form the metal silicide film 172, a metal liner (not shown) is formed to conformally cover the exposed surface of the second source / drain region 130b, and then the metal liner is heat-treated. In addition, a process may be performed to cause a reaction between the second source / drain region 130b and the metal constituting the metal liner. After the metal silicide film 172 is formed, the remaining portion of the metal liner may be removed. During the process of forming the metal silicide film 172, a portion of the second source / drain region 130b may be consumed. In some embodiments, when the metal silicide film 172 includes or is a titanium silicide film, the metal liner may include or may be a Ti film.

[0192] Subsequently, a source / drain contact CA including a conduction barrier pattern 174 and a contact plug 176 may be formed on the metal silicide film 172.

[0193] Referring to Figure 18A and Figure 18B , an etch stop film 182 and an interlayer insulating film 184 may be sequentially formed on the structures shown in Figure 17A and Figure 17B to cover the upper surfaces of each of the gate insulating film 144, the source / drain contact CA, and the plurality of capping insulating patterns 168, thereby forming an upper insulating structure 180. Subsequently, a source / drain via contact VA may be formed to pass through the upper insulating structure 180 in the vertical direction Z and be electrically connected to or contact the source / drain contact CA.

[0194] Subsequently, an upper insulating film 186 may be formed to cover the upper insulating structure 180, and an upper wiring layer M1 may be formed through the upper insulating film 186 and be electrically connected to or contact the source / drain via contact VA.

[0195] Referring to Figure 19A and Figure 19B , the structures shown in Figure 18A and Figure 18B may be arranged such that the rear surface 102B of the substrate 102 faces upward and the front surface 102F of the substrate 102 faces downward. Subsequently, a chemical mechanical polishing process may be performed on the rear surface 102B of the substrate 102 to expose the placeholder PH.

[0196] Referring to Figure 20 , the fin-type active region F1 around the placeholder PH surrounding Figure 19A and Figure 19B may be selectively removed. To selectively remove the fin-type active region F1 around the placeholder PH, an etch rate of the spacer gate protection film GPa, the placeholder PH, and the gate dielectric film 152 may be different from that of the fin-type active region F1, for example, characterized by having a high etch selectivity for the fin-type active region F1. For example, to selectively remove the fin-type active region F1 around the exposed placeholder PH, an RIE process, a thermal etch process, or a wet etch process using a liquid or gas etchant may be performed. For example, an etchant including TMAH may be used, but the inventive concept is not limited thereto.

[0197] In addition, the gap-fill gate protection film GPa may include a material that not only has a higher bonding energy than the material constituting the fin-type active region F1 but also has a higher bonding energy than the material constituting the placeholder PH or the first source / drain region 130a (e.g., the first semiconductor film 1342 of the first source / drain region 130a). Therefore, during the selective removal process of the fin-type active region F1, the gap-fill gate protection film GPa may not be removed together.

[0198] For example, when the substrate 102 includes Si or is formed of Si, the placeholder PH or the first source / drain region 130a (e.g., the first semiconductor film 1342 of the first source / drain region 130a) includes SiGe or is formed of SiGe, the gap-fill gate protection film GPa includes a silicon carbide film or is formed of a silicon carbide film, and the bonding energy between Si and C constituting the gap-fill gate protection film GPa may be greater than the bonding energy between Si and Si constituting the substrate 102 and the bonding energy between Si and Ge constituting the placeholder PH or the first source / drain region 130a. Therefore, the gap-fill gate protection film GPa can prevent defects from occurring in the gate line 160 due to partial etching of the first source / drain region 130a during the selective removal process of the fin-type active region F1.

[0199] Refer to Figure 21 , a gap-fill insulating film 192 can be formed in the space formed by selectively removing the fin-type active region F1 (see Figure 19A ) to surround the exposed placeholder PH. To form the gap-fill insulating film 192, various methods such as PVD process, CVD process, or ALD process can be used.

[0200] Subsequently, a chemical mechanical polishing process can be performed on the upper surface of the gap-fill insulating film 192 to planarize the upper surface of the gap-fill insulating film 192.

[0201] Refer to Figure 22A and Figure 22B , an etching process can be performed to remove the placeholder PH, thereby forming a back contact hole BCH in the structure shown in Figure 21 . The etching process for removing the placeholder PH may include a selective etching process that utilizes the feature that the placeholder PH includes a material different from the material of the gap-fill insulating film 192. For example, RIE can be performed to remove the placeholder PH. The gap-fill gate protection film GPa (see Figure 21 ) can be exposed by removing the placeholder PH.

[0202] Subsequently, the central region of the gap-fill gate protective film GPa can be partially removed. In some embodiments, RIE can be performed to remove the central region of the gap-fill gate protective film GPa. The fourth recess R4 can be formed by removing the central region of the gap-fill gate protective film GPa and the placeholder PH, and the first source / drain region 130a can be exposed through the bottom surface of the fourth recess R4. After removing the central region of the gap-fill gate protective film GPa, a gate protective film GP including the remaining gap-fill gate protective film GPa or formed by the remaining gap-fill gate protective film GPa can be formed.

[0203] In some embodiments, in the case where there are multiple placeholders PH and multiple gap-fill gate protective films GPa, an etching process is performed on the multiple placeholders PH, and then RIE is performed on the gap-fill gate protective film GPa covering the first source / drain region 130a. However, in order to leave the gap-fill gate protective film GPa covering the second source / drain region 130b, RIE can be performed using a mask (not shown) that exposes the gap-fill gate protective film GPa covering the first source / drain region 130a. As a result, a Figure 5A structure including the gap-fill gate protective film GPa can be formed. For example, the mask can fill the space from which the placeholder PH on the gap-fill gate protective film GPa covering the second source / drain region 130b has been removed. In certain embodiments, after removing the mask, another layer can fill the space from which the placeholder PH on the gap-fill gate protective film GPa covering the second source / drain region 130b has been removed.

[0204] In some embodiments, in the case where there are multiple placeholders PH and multiple gap-fill gate protective films GPa, when an etching process is performed on the multiple placeholders PH, the etching process is performed on the placeholder PH on the first source / drain region 130a. However, in order to leave the placeholder PH on the second source / drain region 130b, the etching process can be performed using a mask (not shown) that exposes the placeholder PH on the first source / drain region 130a. As a result, a Figure 5B structure including the placeholder PH and the gap-fill gate protective film GPa can be formed.

[0205] Referring to Figure 23A and Figure 23B , a back contact DBC can be formed inside the fourth recess R4. The back contact DBC can include a back barrier film 194 and a back via 196. The back barrier film 194 can be formed to conformally extend along the inner wall of the fourth recess R4, and then the back via 196 can be formed on the back barrier film 194. The back barrier film 194 and the back via 196 can be deposited using CVD or ALD and / or can be deposited using various processes.

[0206] In some embodiments, although not shown in the drawings, a metal silicide film may be formed on the first source / drain region 130a exposed by the fourth recess R4. In some embodiments, to form the metal silicide film, a metal liner (not shown) is formed to conformally cover the exposed surface of the first source / drain region 130a, and then the metal liner is heat-treated. In addition, a process may be performed to cause a reaction between the first source / drain region 130a and the metal constituting the metal liner. After forming the metal silicide film, the remaining portion of the metal liner may be removed. During the process of forming the metal silicide film, a portion of the first source / drain region 130a may be consumed. In some embodiments, a backside barrier film 194 and a backside via 196 may be formed and heat-treated, and the metal silicide film may be formed by a reaction between the first source / drain region 130a and the metal constituting the backside barrier film 194.

[0207] Subsequently, a lower insulating film 198 may be formed to cover the backside contact DBC, the gap-fill insulating film 192, and the plurality of device isolation films 112. In addition, a lower wiring film M2 may be formed to pass through the lower insulating film 198 and electrically connect to and / or contact the backside contact DBC.

[0208] Although different drawings illustrate variations of the exemplary embodiments and different embodiments disclose different features from one another, these drawings and embodiments are not necessarily intended to be mutually exclusive of each other. Rather, when the relevant descriptions of the drawings and embodiments are considered as a whole, the features depicted in different drawings and / or described above in different embodiments may be combined with other features from other drawings / embodiments to produce additional variations of the embodiments. For example, the components and / or features of the above-described different embodiments may be combined interchangeably or additionally with the components and / or features of other embodiments to form additional embodiments, unless the context clearly indicates otherwise, and the present disclosure includes such additional embodiments.

[0209] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0210] This application claims priority to Korean Patent Application No. 10-2023-0178744, filed with the Korean Intellectual Property Office on December 11, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit device, comprising: a plurality of device isolation films extending longitudinally in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a gap-filling insulating film, located between the plurality of device isolation films; a plurality of gate lines disposed on the gap-filling insulating film and extending longitudinally in the second horizontal direction; a plurality of source / drain regions, including a first source / drain region and a second source / drain region, each of the plurality of source / drain regions being located between the plurality of gate lines; a backside contact provided below the first source / drain region, the backside contact extending through the gap-fill insulating film and electrically connected to the first source / drain region; as well as a gate protection film provided below the first source / drain region and in contact with an upper sidewall of the back contact, Wherein, at least a portion of the sidewall of the gate protection film is surrounded by the gap-filling insulating film.

2. The integrated circuit device according to claim 1, wherein: The gate protection film includes SiGe, SiGeC, SiO, SiC, SiOC, SiOCN, SiOH, GeC or a combination thereof.

3. The integrated circuit device according to claim 1, wherein: The gate protection film includes a silicon carbide film, and a carbon content in the gate protection film is about 3 at % to about 30 at %.

4. The integrated circuit device according to claim 1, wherein: Each of the first source / drain region and the second source / drain region includes: a first semiconductor film; and a second semiconductor film having side walls and a lower surface surrounded by the first semiconductor film, Here, each of the first semiconductor film and the second semiconductor film includes a Si film or a SiGe film.

5. The integrated circuit device according to claim 4, wherein: Each of the first semiconductor film and the second semiconductor film includes a SiGe film, The gate protection film includes a SiGe film, The ratio of Ge contained in the gate protection film is greater than the ratio of Ge contained in the first semiconductor film, and A ratio of Ge contained in the second semiconductor film is greater than the ratio of Ge contained in the first semiconductor film.

6. The integrated circuit device according to claim 1, wherein: The gate protection film covers a portion of the lower surface of the first source / drain region, and The back contact covers another portion of the lower surface of the first source / drain region.

7. The integrated circuit device according to claim 1, wherein: The gate protection film has a side wall opposite to the back contact, and The side wall of the gate protection film has a convex shape protruding in a direction away from the back contact.

8. The integrated circuit device according to claim 1, wherein: The gate protection film has a side wall opposite to the back contact, and The side wall of the gate protection film has a sharp shape having a vertical thickness that decreases in a direction away from the back contact.

9. The integrated circuit device according to claim 1, wherein: The gap-fill insulating film includes a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, and The gap-fill insulating film surrounds a side wall of the gate protection film.

10. The integrated circuit device according to claim 1, wherein: A portion of the back contact overlapping the gate protection film in the first horizontal direction has a horizontal width that decreases in a direction moving from a bottom to a top of the portion of the back contact.

11. The integrated circuit device according to claim 1 , further comprising a gate dielectric film between the plurality of source / drain regions and the plurality of gate lines, in, The gate protection film covers a portion of the gate dielectric film adjacent to the back contact.

12. The integrated circuit device according to claim 1, further comprising a gate dielectric film between the plurality of source / drain regions and the plurality of gate lines, in, The gate protection film is located between the gate dielectric film and the back contact, and The back contact is spaced apart from the gate dielectric film with the gate protection film therebetween.

13. An integrated circuit device comprising: a plurality of device isolation films extending longitudinally in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a gap-filling insulating film, located between the plurality of device isolation films; a plurality of gate lines disposed on the gap-filling insulating film and extending longitudinally in the second horizontal direction; a plurality of source / drain regions, including a first source / drain region and a second source / drain region, each of the plurality of source / drain regions being located between the plurality of gate lines; a gate dielectric film disposed between the plurality of source / drain regions and the plurality of gate lines; a gate protection film covering a portion of the lower surface of the gate dielectric film adjacent to the first source / drain region; a gap-filling gate protection film covering a portion of the lower surface of the gate dielectric film adjacent to the second source / drain region; as well as a back contact in contact with the gate protection film and electrically connected to the first source / drain region, Wherein, the gate protection film and the gap-filling gate protection film are arranged between the gap-filling insulating film and the plurality of source / drain regions.

14. The integrated circuit device according to claim 13, wherein: Each of the gate protection film and the gap-fill gate protection film includes SiGe, SiGeC, SiO, SiC, SiOC, SiOCN, SiOH, GeC, or a combination thereof.

15. The integrated circuit device according to claim 13, wherein: The gate protection film at least partially covers the lower surface of the first source / drain region, and The gap-filling gate protection film completely covers the lower surface of the second source / drain region.

16. The integrated circuit device according to claim 13, wherein: The sidewalls of the gate protection film and the sidewalls and lower surface of the gap-filling gate protection film are surrounded by the gap-filling insulating film, and The gap-fill insulating film includes a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

17. An integrated circuit device comprising: a plurality of device isolation films extending longitudinally in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; a gap-filling insulating film, located between two adjacent device isolation films among the plurality of device isolation films; at least one nanosheet disposed on the gap-filling insulating film, spaced apart from an upper surface of the gap-filling insulating film in a vertical direction, and facing the upper surface of the gap-filling insulating film; a gate line surrounding the at least one nanosheet over the gap-filling insulating film and extending longitudinally in the second horizontal direction intersecting the first horizontal direction; a gate dielectric film surrounding the gate line and separating the at least one nanosheet from the gate line; a first source / drain region and a second source / drain region, each of the first source / drain region and the second source / drain region being disposed above the gap-fill insulating film and adjacent to the gate line and in contact with the at least one nanosheet; a back contact extending in the vertical direction from the level of the lower surface of the gap-fill insulating film to the lower surface of the first source / drain region and covering a portion of the lower surface of the first source / drain region; a gate protection film located between the back contact and the gap-filling insulating film and covering another portion of the lower surface of the first source / drain region; as well as a source / drain contact provided over and electrically connected to the second source / drain region, Wherein, the gap filling insulating film comprises a silicon oxide film, and The gate protection film includes a silicon carbide film.

18. The integrated circuit device according to claim 17, wherein: The gate protection film includes carbon in an amount of about 3 at % to about 25 at %.

19. The integrated circuit device according to claim 17, wherein: The gate protection film has a side wall opposite to the back contact, and The side wall of the gate protection film has a curved shape.

20. The integrated circuit device according to claim 17, wherein: The gate protection film has a side wall opposite to the back contact, and The side wall of the gate protection film has a shape that is diagonally inclined between the first horizontal direction, the second horizontal direction, and the vertical direction.

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