Electronic device

Abstract

The invention provides an electronic device. The electronic device comprises a display layer; a cover layer disposed under the display layer; a circuit board connected to the display layer and disposed below the cover layer; and a capacitor disposed on the circuit board, in which the cap layer includes a first region overlapping the capacitor and a second region adjacent to the first region when viewed in a plane, and in which an opening is disposed in the first region.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0182876, filed with the Korean Intellectual Property Office on December 15, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Embodiments of the present disclosure described herein relate to an electronic device with improved reliability. Background art

[0004] Multimedia electronic devices, including televisions, mobile phones, tablet computers, navigation systems, game consoles, and the like, are equipped with a display device for presenting images. The display device may include an organic light - emitting display device. The organic light - emitting display device may include light - emitting elements that generate light through the recombination of electrons and holes. The organic light - emitting display device provides benefits such as a high response speed and low power consumption. Summary of the invention

[0005] Embodiments of the present disclosure provide an electronic device with improved reliability.

[0006] According to an embodiment of the present disclosure, there is provided an electronic device including: a display layer; a cover layer disposed under the display layer; a circuit board connected to the display layer and disposed under the cover layer; and a capacitor disposed on the circuit board, wherein, when viewed in a plane, the cover layer includes a first region overlapping the capacitor and a second region adjacent to the first region, and an opening is provided in the first region.

[0007] The electronic device further includes: a sensor layer disposed on the display layer and including a plurality of sensing electrodes; and a sensor driver configured to operate the sensor layer, wherein the sensor driver is disposed on the circuit board.

[0008] The sensor driver includes a charge pump, and the charge pump is electrically connected to the capacitor.

[0009] The cover layer includes a metal material.

[0010] Audible noise generated in the capacitor is diffusely reflected from the opening.

[0011] The opening includes a plurality of openings, wherein, when viewed in a plane, each of the plurality of openings extends in a first direction, and the plurality of openings are spaced apart from each other in a second direction intersecting the first direction.

[0012] The cover layer includes a sub - cover disposed within the opening.

[0013] The sub-cover includes a plurality of sub-covers, and among them, the plurality of sub-covers are arranged along a first direction and a second direction intersecting the first direction.

[0014] The circuit board is in contact with the cover layer.

[0015] The capacitor is spaced apart from the cover layer, and the circuit board is located between the capacitor and the cover layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] By referring to the drawings and describing the embodiments of the present disclosure in detail, the above and other features of the present disclosure will become apparent.

[0017] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0018] Figure 2 is a schematic cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0019] Figure 3 is a plan view showing a display layer and a circuit board according to an embodiment of the present disclosure.

[0020] Figure 4 is a top view of a sensor layer according to an embodiment of the present disclosure.

[0021] Figure 5 is a block diagram showing a sensor driver and a capacitor according to an embodiment of the present disclosure.

[0022] Figure 6 is a cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0023] Figure 7 is a plan view of a cover layer according to an embodiment of the present disclosure.

[0024] Figure 8A is a plan view of a cover layer according to an embodiment of the present disclosure.

[0025] Figure 8B is a plan view of a cover layer according to an embodiment of the present disclosure.

[0026] Figure 8C is a plan view of a cover layer according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] As used herein, when a component (or region, layer, part, etc.) is referred to as being "on", "connected to", or "coupled to" another component, it means that the component can be directly disposed on, connected to, or coupled to the other component, or a third component can be disposed between the two components.

[0028] Like reference numerals denote like components. In addition, in the drawings, the thickness, ratios, and dimensions of components are exaggerated for effective description of the technical content. The term "and / or" includes all possible combinations of associated components.

[0029] Terms such as first, second, etc. may be used to describe various components, but these terms are only used to distinguish one component from another. For example, the first component may be named the second component, and similarly, the second component may also be named the first component. Singular expressions include plural expressions unless the context clearly dictates otherwise.

[0030] In addition, terms such as "under", "below", "on", or "above" are used to describe the relationships of components shown in the drawings. These terms are relative concepts and are described with reference to the directions indicated in the drawings.

[0031] It should be understood that terms such as "including" or "having" specify the presence of the features, quantities, steps, operations, components, parts, or combinations thereof described in the specification, without precluding the possibility of adding or the presence of one or more other features, quantities, steps, operations, components, parts, or combinations thereof.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Additionally, terms defined in commonly used dictionaries should be interpreted in a manner consistent with their meanings in the relevant art and not in an overly formal sense unless expressly so defined herein.

[0033] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0034] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0035] Refer to Figure 1 , the electronic device 1000 may be a device that is activated in response to an electrical signal. For example, the electronic device 1000 may be a mobile phone (e.g., a straight-bar mobile phone or a foldable mobile phone), a laptop computer, a television, a tablet computer, a vehicle navigation system, a game console, or a wearable device, but is not limited thereto. Figure 1 As an example, the electronic device 1000 is shown as a mobile phone.

[0036] In the electronic device 1000, a display surface FS parallel to a first direction DR1 and a second direction DR2 intersecting the first direction DR1 may be defined. The display surface FS may include an active area DA and a peripheral area NDA. The electronic device 1000 may display an image IM via the active area DA. The peripheral area NDA may surround the active area DA. The image IM may not be displayed in the peripheral area NDA, but the present disclosure is not limited thereto.

[0037] The thickness direction of the electronic device 1000 may be parallel to a third direction DR3 intersecting the first direction DR1 and the second direction DR2. Accordingly, a front (or top) surface and a rear (or bottom) surface of components constituting the electronic device 1000 may be defined based on the third direction DR3.

[0038] Figure 2 is a schematic cross-sectional view of an electronic device according to an embodiment of the present disclosure.

[0039] Referring to Figure 2 , the electronic device 1000 may include a window WP, adhesive layers OCA1 and OCA2, an antireflection layer RPP, a sensor layer IS, a display layer DP, a protective layer PF, an embossed layer EB, a buffer layer CSH, a heat sink GP, and a cover layer CU.

[0040] The window WP may form a part of the appearance of the electronic device 1000. The window WP may protect internal components of the electronic device 1000 from external impacts and substantially provide the active area DA of the electronic device 1000. For example, the window WP may include a glass substrate, a sapphire substrate, or a plastic film. The window WP may have a multi-layer or single-layer structure. For example, the window WP may have a stacked structure of a plurality of plastic films bonded together with an adhesive, or a glass substrate and a plastic film bonded to each other with an adhesive.

[0041] The adhesive layer OCA1 may be disposed under the window WP. The window WP and the antireflection layer RPP may be bonded to each other through the adhesive layer OCA1. The adhesive layer OCA1 may include an adhesive or a cement. For example, the adhesive layer OCA1 may be an optically clear adhesive film, an optically clear adhesive resin, or a pressure-sensitive adhesive film.

[0042] The antireflection layer RPP may be disposed under the window WP. The antireflection layer RPP may reduce the reflectance of natural light (or sunlight) incident from above the window WP.

[0043] An antireflection layer RPP according to an embodiment of the present disclosure may include a phase retarder and a polarizer. The phase retarder may be of a film type or a liquid crystal coating type. The phase retarder may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may be of a film type or a liquid crystal coating type. The film type may include a stretched synthetic resin film, while the liquid crystal coating type may include liquid crystals arranged in a specific pattern. The phase retarder and the polarizer may also include a protective film. The phase retarder, the polarizer, or the protective film may be defined as a base layer of the antireflection layer RPP.

[0044] An adhesive layer OCA2 may be disposed under the antireflection layer RPP. The antireflection layer RPP and the sensor layer IS may be adhered to each other through the adhesive layer OCA2. The adhesive layer OCA2 may contain substantially the same material as the adhesive layer OCA1.

[0045] The sensor layer IS may obtain coordinate information from an external input. The sensor layer IS according to an embodiment of the present disclosure may be directly disposed on the surface of the display layer DP. For example, the sensor layer IS may be integrated with the display layer DP in an on-cell manner. The sensor layer IS may be manufactured together with the display layer DP through a continuous process. However, the present disclosure is not limited thereto, and the sensor layer IS may be manufactured through a separate process and then attached to the display layer DP. The sensor layer IS may include a touch panel.

[0046] The display layer DP may be disposed under the sensor layer IS. The display layer DP may be a component that actually creates an image. The display layer DP may be a light-emitting display layer, and is not particularly limited thereto. For example, the display layer DP may include an organic light-emitting display layer, a quantum dot display layer, a micro light-emitting diode (LED) display layer, or a nano LED display layer. The display layer DP may include a base layer SUB, a display circuit layer DP-CL, an image implementation layer DP-OLED, and a thin film encapsulation layer TFL.

[0047] A protective layer PF may be disposed under the display layer DP. The protective layer PF may protect the bottom surface of the display layer DP. The protective layer PF may contain polyethylene terephthalate (PET). However, the material of the protective layer PF is not particularly limited thereto.

[0048] An embossed layer EB may be disposed under the protective layer PF. The embossed layer EB may be colored. For example, the embossed layer EB may be black. The embossed layer EB may absorb light incident thereon. The embossed layer EB may be a layer having adhesive properties on both of its surfaces. The embossed layer EB may contain an adhesive or an adhesive agent. The protective layer PF and the buffer layer CSH may be bonded to each other through the embossed layer EB.

[0049] The buffer layer CSH can be disposed below the embossed layer EB. The buffer layer CSH can serve to release the pressure applied from the outside. The buffer layer CSH can include a sponge, foam, polyurethane resin, etc. The thickness of the buffer layer CSH can be greater than the thickness of the embossed layer EB.

[0050] The heat sink GP can be disposed below the buffer layer CSH. The heat sink GP can promote the dissipation of heat generated in the display layer DP. For example, the heat sink GP can be a graphite sheet. In one embodiment of the present disclosure, a film layer can be further disposed between the buffer layer CSH and the heat sink GP. The film layer can include polyimide (PI).

[0051] The cover layer CU can be disposed below the protective layer PF. The cover layer CU can be conductive. The cover layer CU can include a metallic material. For example, the cover layer CU can include copper (Cu). For example, the cover layer CU can be a copper strip (Cu strip). However, the present disclosure is not particularly limited thereto. A ground voltage can be applied to the cover layer CU. However, this is merely an example, and the cover layer CU can be floating.

[0052] Figure 3 is a plan view showing a display layer and a circuit board according to an embodiment of the present disclosure.

[0053] Reference Figure 2 and Figure 3 , the electronic device 1000 (see Figure 2 ) can further include a power pattern VDD, a data driver DIC, a circuit board CF, a sensor driver SIC, a capacitor CAP, and a connector CNT.

[0054] In the display layer DP, a display area DP-DA and a peripheral area DP-NDA adjacent to the display area DP-DA can be defined. The display area DP-DA can be an area for displaying an image. A plurality of pixels PX can be disposed in the display area DP-DA. The peripheral area DP-NDA can be an area where drive circuits, drive lines, etc. are disposed.

[0055] The display layer DP can include a base layer SUB, a plurality of pixels PX, a plurality of signal lines, a plurality of display pads P1 and P2, and a plurality of sensing pads PDT.

[0056] Each of the plurality of pixels PX can present one of the primary colors or one of the mixed colors. The primary colors can include red, green, or blue. The mixed colors can include various colors, such as white, yellow, cyan, or magenta. However, the color presented by each pixel PX is not limited thereto.

[0057] A plurality of signal lines may be provided on the base layer SUB. The plurality of signal lines may be connected to a plurality of pixels PX and transmit electrical signals to the plurality of pixels PX. The plurality of signal lines may include a plurality of scan lines GL, a plurality of data lines DL, a plurality of power lines PL, and a plurality of emission control lines EL. However, this is merely an example, and the configuration of the plurality of signal lines according to an embodiment of the present disclosure is not limited thereto. For example, the plurality of signal lines according to an embodiment of the present disclosure may further include an initialization voltage line.

[0058] The power pattern VDD may be provided in the peripheral region DP-NDA. The power pattern VDD may be connected to the plurality of power lines PL. Each of the plurality of pixels PX may receive the power supply voltage ELVDD provided by the power line PL.

[0059] A plurality of display pads P1 and P2 may be provided in the peripheral region DP-NDA. The plurality of display pads P1 and P2 may include a first display pad P1 and a second display pad P2. The first display pad P1 may include a plurality of first display pads P1. The plurality of first display pads P1 may be respectively connected to the plurality of data lines DL. The second display pad P2 may be connected to the power pattern VDD and electrically connected to the plurality of power lines PL. The display layer DP may provide electrical signals provided from the outside to the plurality of pixels PX through the plurality of display pads P1 and P2. In one example, in addition to the first display pad P1 and the second display pad P2, the plurality of display pads P1 and P2 may further include pads for receiving other electrical signals and are not limited to any one embodiment.

[0060] The data driver DIC may be mounted in the peripheral region DP-NDA. The data driver DIC may be a timing control circuit in the form of a chip. The data driver DIC may output a gray-scale voltage to the plurality of data lines DL in response to the frame data of the image data. The plurality of data lines DL may be respectively electrically connected to the plurality of first display pads P1 via the data driver DIC. However, this is merely an example, and the data driver DIC according to an embodiment of the present disclosure may be mounted on a film separated from the display layer DP. The data driver DIC may be electrically connected to the plurality of display pads P1 and P2 via the film.

[0061] A plurality of sensing pads PDT may be provided in the peripheral region DP-NDA. The plurality of sensing pads PDT may be respectively electrically connected to a plurality of sensing electrodes of the sensor layer IS. The plurality of sensing pads PDT may include a plurality of first sensing pads TD1 and a plurality of second sensing pads TD2.

[0062] The circuit board CF may be electrically connected to the plurality of display pads P1 and P2 and the plurality of sensing pads PDT.

[0063] The sensor driver SIC can be mounted on the circuit board CF. The sensor driver SIC can be electrically connected to a plurality of sensing pads PDT. The sensor driver SIC can operate the sensor layer IS.

[0064] The capacitor CAP can be mounted on the circuit board CF. The capacitor CAP can be electrically connected to the sensor driver SIC.

[0065] The first wiring L1 can be electrically connected to the data driver DIC. For example, the first wiring L1 can be connected to a plurality of display pads P1 and P2 and the connector CNT and be located between the plurality of display pads P1 and P2 and the connector CNT. The first wiring L1 can transmit and receive data signals. The data signals can be referred to as MIPI signals. The first wiring L1 can be disposed on the circuit board CF. The first wiring L1 can be referred to as a MIPI line.

[0066] The second wiring L2 can be electrically connected to the sensor layer IS and the sensor driver SIC and be located therebetween. For example, the second wiring L2 can be connected to a plurality of sensing pads PDT and the sensor driver SIC and be located between the plurality of sensing pads PDT and the sensor driver SIC. The second wiring L2 can transmit a touch emission signal TX and receive a touch reception signal RX. The second wiring L2 can be disposed on the circuit board CF.

[0067] The connector CNT can be electrically connected to each of the first wirings L1. The connector CNT can be disposed on the circuit board CF. The connector CNT can be connected to the main processor.

[0068] The main processor can include at least one of a central processing unit (CPU) and an application processor. The main processor can also include at least one of a graphics processing unit (GPU), a communication processor (CP), and an image signal processor (ISP). The main processor can also include a neural processing unit (NPU). The neural processing unit is a processor dedicated to processing artificial intelligence models, which can be created through machine learning. The artificial intelligence model can include multiple artificial neural network layers. The artificial neural network can be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), and a deep Q network, or a combination of two or more of the above, but not limited to the above examples. In addition to the hardware structure, the artificial intelligence model can additionally or alternatively include a software structure. At least two of the above processing units and processors can be implemented as a single integrated component (e.g., a single chip), or each can be implemented as an independent component (e.g., multiple chips).

[0069] The circuit board CF can be bent onto the rear surface of the display layer DP. In other words, the bottom surface of the display layer DP and the bottom surface of the circuit board CF can be arranged to face each other.

[0070] Figure 4 is a top view of a sensor layer according to an embodiment of the present disclosure.

[0071] Reference Figure 3 and Figure 4 and

[0072] The sensor layer IS may include an active region AR and a peripheral region NAR adjacent to the active region AR. The active region AR may be a region that is activated in response to an electrical signal. The active region AR may be a region that senses an input. The active region AR may overlap with the display region DP-DA of the display layer DP. The peripheral region NAR may overlap with the peripheral region DP-NDA of the display layer DP.

[0073] The base layer 201 may be an inorganic layer including one of silicon nitride, silicon oxynitride, and silicon oxide. Alternatively, the base layer 201 may be an organic layer including an epoxy resin, an acrylic resin, or an imide-based resin. The base layer 201 may be directly formed on the display layer DP. Alternatively, the base layer 201 may be bonded to the display layer DP through an adhesive member.

[0074] The plurality of sensing electrodes SP may include a plurality of first sensing electrodes TE1 and a plurality of second sensing electrodes TE2. The sensor layer IS may obtain information about an external input through a change in capacitance between the plurality of first sensing electrodes TE1 and the plurality of second sensing electrodes TE2.

[0075] Each of the plurality of first sensing electrodes TE1 may extend along a first direction DR1, and the plurality of first sensing electrodes TE1 may be arranged along a second direction DR2. Each of the plurality of first sensing electrodes TE1 may include a plurality of first portions SP1 and a plurality of second portions BSP1. Each of the plurality of second portions BSP1 may electrically connect two adjacent first portions SP1 to each other. The plurality of first portions SP1 and the plurality of second portions BSP1 may have a grid structure. The plurality of first portions SP1 may be referred to as a plurality of first sensing portions SP1. The plurality of second portions BSP1 may be referred to as a plurality of first connection portions BSP1.

[0076] Each of the plurality of second sensing electrodes TE2 may extend along a second direction DR2, and the plurality of second sensing electrodes TE2 may be arranged along a first direction DR1. Each of the plurality of second sensing electrodes TE2 may include a plurality of sensing patterns SP2 and a plurality of bridging patterns BSP2. Each of the plurality of bridging patterns BSP2 may electrically connect two adjacent sensing patterns SP2 to each other. The plurality of sensing patterns SP2 may have a grid structure. The plurality of sensing patterns SP2 may be referred to as a plurality of second sensing portions SP2. The plurality of bridging patterns BSP2 may be referred to as a plurality of second connection portions BSP2.

[0077] The plurality of second portions BSP1 may be provided on a layer different from the plurality of bridging patterns BSP2. The plurality of bridging patterns BSP2 may intersect the plurality of first sensing electrodes TE1 in an insulating manner. For example, the plurality of second portions BSP1 may intersect the plurality of bridging patterns BSP2 in an insulating manner.

[0078] The plurality of sensing lines TL1 and TL2 may include a plurality of first sensing lines TL1 and a plurality of second sensing lines TL2. The plurality of first sensing lines TL1 may be electrically connected to the plurality of first sensing electrodes TE1, respectively. The plurality of second sensing lines TL2 may be electrically connected to the plurality of second sensing electrodes TE2, respectively.

[0079] The plurality of first sensing lines TL1 may be electrically connected to the plurality of first sensing pads TD1 through contact holes, respectively. The plurality of second sensing lines TL2 may be electrically connected to the plurality of second sensing pads TD2 through contact holes, respectively.

[0080] Figure 5 is a block diagram showing a sensor driver and a capacitor according to an embodiment of the present disclosure.

[0081] Referring to Figure 3 and Figure 5 , the sensor driver SIC may include a charge pump CP. The charge pump CP may be electrically connected to the capacitor CAP.

[0082] The charge pump CP may increase or decrease the received voltage. The charge pump CP may convert a first voltage V1 received from a power supply circuit into a second voltage V2 that can be used by the sensor driver SIC.

[0083] The power supply circuit may include a power management integrated circuit (PMIC). The power supply circuit may generate a plurality of driving voltages to operate the display layer DP, the sensor layer IS, the data driver DIC, and the sensor driver SIC. For example, the plurality of driving voltages may include a gate high voltage, a gate low voltage, a first driving voltage (e.g., ELVSS voltage), a second driving voltage (e.g., ELVDD voltage), a first voltage V1 (e.g., a bias voltage), and an initialization voltage, but are not particularly limited to the above examples.

[0084] The first voltage V1 can be a DC voltage. The first voltage V1 can have a voltage level of approximately 3V (volts).

[0085] The second voltage V2 can swing to a predetermined voltage level. In other words, the second voltage V2 can fluctuate between the predetermined voltage levels. The second voltage V2 can swing between the first voltage level and a second voltage level having a voltage level higher than the first voltage level. For example, the first voltage level can be 3.3V, and the second voltage level can be 6V.

[0086] The capacitor CAP can be connected to the charge pump CP and the ground electrode GND and be located therebetween. The capacitor CAP can eliminate the noise generated by the charge pump CP. The capacitor CAP can be referred to as a stabilization capacitor.

[0087] The capacitor CAP can be repeatedly charged and discharged by the second voltage V2 generated by the charge pump CP. When the capacitor CAP is charged or discharged to the first voltage level and / or the second voltage level, the capacitor CAP may vibrate. This vibration of the capacitor CAP may generate audible noise.

[0088] Figure 6 is a cross-sectional view of an electronic device according to an embodiment of the present disclosure. In Figure 6 the description of, Figure 2 and Figure 5 the components described in are given the same reference numerals, and their description is omitted.

[0089] Referring to Figure 6 , a cover layer CU can be provided under the display layer DP. The cover layer CU can be in direct contact with the display layer DP. The circuit board CF can be electrically connected to the display layer DP. The circuit board CF can be bent from the display layer DP and provided under the cover layer CU. The circuit board CF can be in contact with the rear surface CU_S of the cover layer CU.

[0090] The capacitor CAP can be mounted on the circuit board CF. When the circuit board CF is bent, Figure 6 shows the capacitor CAP provided under the circuit board CF. Figure 6 Further shows the capacitor CAP provided under the display layer DP.

[0091] A plurality of openings OP can be defined in the cover layer CU. When viewed in a plane, the plurality of openings OP can overlap with the capacitor CAP. However, the capacitor CAP can also overlap with a part of the cover layer CU. The plurality of openings OP can overlap with the circuit board CF. The plurality of openings OP can be spaced apart from each other in a first direction DR1. An empty space can be defined in the cover layer CU through the plurality of openings OP.

[0092] According to the present disclosure, the audible noise NOS generated in the capacitor CAP can be diffusely reflected by a plurality of openings OP. The diffusely reflected audible noise NOS can be decomposed and reduced or eliminated. In other words, the transmission of the audible noise NOS to the window WP can be prevented or eliminated. Therefore, even when the user's ear contacts the window WP during a phone call, the user may not perceive the audible noise NOS. Thus, an electronic device 1000 with improved reliability can be provided.

[0093] In addition, according to the present disclosure, the cover layer CU can include a metallic material. The audible noise NOS transmitted into the plurality of openings OP can be easily reflected. In other words, the audible noise NOS can be diffusely reflected from the plurality of openings OP. This makes the audible noise NOS easy to be decomposed. The transmission of the audible noise NOS to the window WP can be reduced or eliminated. Therefore, an electronic device 1000 with improved reliability can be provided.

[0094] Figure 7 is a plan view of a cover layer according to an embodiment of the present disclosure.

[0095] Referring to Figure 6 and Figure 7 , a first region AR1 and a second region AR2 adjacent to the first region AR1 can be defined in the cover layer CU.

[0096] The first region AR1 can be a region that overlaps the capacitor CAP in a plane. The size of the first region AR1 can be defined based on the size of the capacitor CAP. A plurality of openings OP can be defined in the first region AR1.

[0097] When viewed in a plane, the plurality of openings OP can overlap the capacitor CAP.

[0098] The second region AR2 can surround the first region AR1. The first region AR1 and the second region AR2 can be integrally provided. The second region AR2 can be formed as a single plate without any separate openings.

[0099] When viewed in a plane, the plurality of openings OP can be arranged along a first direction DR1 and a second direction DR2.

[0100] According to the present disclosure, the audible noise NOS generated in the capacitor CAP can be diffusely reflected by a plurality of openings OP. This diffusely reflected audible noise NOS can be decomposed and then reduced or eliminated. In other words, the transmission of the audible noise NOS to the window WP can be prevented or eliminated. As a result, even when the user's ear contacts the window WP during a phone call, the user may not perceive the audible noise NOS. Thus, an electronic device 1000 with improved reliability can be provided.

[0101] Figure 8A is a plan view of a cover layer according to an embodiment of the present disclosure. In Figure 8A the description of, Figure 7 the components described in

[0102] are given the same reference numerals and their description is omitted. Figure 6 and Figure 8A , a plurality of openings OP-1 can be defined in the cover layer CU-1. A plurality of openings OP-1 can be defined in a first region AR1 of the cover layer CU-1.

[0103] When viewed in a plane, the plurality of openings OP-1 can overlap with the capacitor CAP.

[0104] When viewed in a plane, each of the plurality of openings OP-1 can extend in a first direction DR1. The plurality of openings OP-1 can be spaced apart from each other in a second direction DR2.

[0105] According to the present disclosure, the audible noise NOS generated in the capacitor CAP can be diffusely reflected by the plurality of openings OP-1. This diffusely reflected audible noise NOS can be decomposed and then reduced or eliminated. In other words, the transmission of the audible noise NOS to the window WP can be reduced or eliminated. As a result, even when the user's ear contacts the window WP during a phone call, the user may not perceive the audible noise NOS. Therefore, an electronic device 1000 with improved reliability can be provided.

[0106] Figure 8B is a plan view of a cover layer according to an embodiment of the present disclosure. In Figure 8B the description of, Figure 7 the components described in

[0107] Refer to Figure 6 and Figure 8B , a plurality of openings OP-2 can be defined in the cover layer CU-2. A plurality of openings OP-2 can be defined in a first region AR1 of the cover layer CU-2.

[0108] When viewed in a plane, the plurality of openings OP-2 can overlap with the capacitor CAP.

[0109] When viewed in a plane, each of the plurality of openings OP-2 can extend in a second direction DR2. The plurality of openings OP-2 can be spaced apart from each other in a first direction DR1.

[0110] According to the present disclosure, the audible noise NOS generated in the capacitor CAP can be diffusely reflected by a plurality of openings OP-2. This diffusely reflected audible noise NOS can be decomposed and then reduced or eliminated. In other words, the transmission of the audible noise NOS to the window WP can be reduced or eliminated. As a result, even when the user's ear is in contact with the window WP during a phone call, the user may not perceive the audible noise NOS. Therefore, an electronic device 1000 with improved reliability can be provided.

[0111] Figure 8C is a plan view of a cover layer according to an embodiment of the present disclosure. In Figure 8C the description of, Figure 7 the components described in are given the same reference numerals and their description is omitted.

[0112] Referring to Figure 6 and Figure 8C , an opening OP-3 can be defined in the cover layer CU-3. The opening OP-3 can be defined in a first region AR1 of the cover layer CU-3.

[0113] When viewed in a plane, the opening OP-3 can overlap with the capacitor CAP.

[0114] When viewed in a plane, the cover layer CU-3 can include a plurality of sub-covers CUP disposed within the opening OP-3. The plurality of sub-covers CUP can be arranged in the first region AR1. The plurality of sub-covers CUP can be arranged in a first direction DR1 and a second direction DR2.

[0115] According to the present disclosure, the audible noise NOS generated in the capacitor CAP can be diffusely reflected by the opening OP-3. This diffusely reflected audible noise NOS can be decomposed and then reduced or eliminated. In other words, the transmission of the audible noise NOS to the window WP can be reduced or eliminated. As a result, even when the user's ear is in contact with the window WP during a phone call, the user may not perceive the audible noise NOS. Therefore, an electronic device 1000 with improved reliability can be provided.

[0116] As described above, the audible noise generated by the capacitor can be diffusely reflected by a plurality of openings. The diffusely reflected audible noise can be decomposed and reduced or eliminated. In other words, the transmission of the audible noise to the window can be prevented or eliminated. As a result, even when the user's ear is in contact with the window during a phone call, the user may not perceive the audible noise. Therefore, an electronic device with improved reliability can be provided.

[0117] Although the present disclosure has been described with reference to embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. Electronic equipment, including: Display layer; A cover layer, disposed below the display layer; A circuit board connected to the display layer and arranged below the cover layer; as well as A capacitor is disposed on the circuit board. wherein, when viewed in a plane, the cover layer includes a first region overlapping the capacitor and a second region adjacent to the first region, and Wherein, an opening is arranged in the first area.

2. The electronic device according to claim 1, further comprising: a sensor layer, disposed on the display layer and comprising a plurality of sensing electrodes; as well as a sensor driver configured to operate the sensor layer, Wherein, the sensor driver is arranged on the circuit board.

3. The electronic device according to claim 2, wherein: The sensor driver includes a charge pump, and Wherein, the charge pump is electrically connected to the capacitor.

4. The electronic device according to claim 1, wherein: The cover layer includes a metal material.

5. The electronic device according to claim 1, wherein: Audible noise generated in the capacitor is diffusely reflected from the opening.

6. The electronic device according to claim 1, wherein: The opening comprises a plurality of openings, and Wherein, when viewed on the plane, each of the plurality of openings extends in a first direction, and the plurality of openings are spaced apart from each other in a second direction intersecting the first direction.

7. The electronic device according to claim 1, wherein: The cover layer includes a sub-cover disposed in the opening.

8. The electronic device according to claim 7, wherein: The sub-cover includes a plurality of sub-covers, and Wherein, the plurality of sub-covers are arranged along a first direction and a second direction intersecting with the first direction.

9. The electronic device according to claim 1, wherein: The circuit board is in contact with the cover layer.

10. The electronic device according to claim 1, wherein: The capacitor is spaced apart from the cover layer, and the circuit board is located between the capacitor and the cover layer.

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