Three-dimensional cross-field-effect self-aligned transistor with front and back power connections

Abstract

An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, an integrated circuit uses a cross field effect transistor (FET) having a first device, such as an n-type device, with a first channel facing a first direction and connected to a ground reference voltage level provided by a backside metal layer. The crossover FET also uses a second device, such as a p-type device, having a second channel facing a second direction orthogonal to the first direction and connected to a supply reference voltage level provided by the front side metal layer. A micro through silicon via (TSV) traverses the silicon substrate layer so as to be placed between the backside metal layer and a source region of the n-type device. The power connections reduce on-die area, reduce semiconductor fabrication complexity, which improves wafer yield, and reduce voltage drop, which improves performance.

Description

BACKGROUND OF THE INVENTION

[0001] Description of Related Technologies

[0002] As semiconductor manufacturing processes have advanced and the geometric dimensions on a die have decreased, semiconductor chips offer more functionality and performance. Although many advancements have been made, modern technology still presents design issues in processing and integrated circuit design that limit the potential benefits. For example, capacitive coupling, electromigration, short-channel effects such as at least leakage current, and process yield are some of the issues that affect device placement and signal routing across the entire die of a semiconductor chip. These issues have the potential to delay the completion of the design and impact the time to market. As each generation of semiconductor chips has evolved, voltage drop in modern integrated circuits has become an increasingly prominent design issue. Voltage drop is a decrease or ΔV in the voltage value at a node where the voltage value drops below a minimum threshold. For memories and latches without a restoration circuit, the stored value may be lost. Voltage drop constraints are not only an issue for portable computers and mobile communication devices, but also for high-performance desktop computers and server computers using superscalar microprocessors.

[0003] In addition, routing power signals across multiple metal layers to span a semiconductor chip increases the distance between the contacts for the power signals. This distance expands the floorplan. The floorplan of a semiconductor die is limited unless the semiconductor package size is increased. If the area for a die component does not exist in the layout, the component is not suitable for assembly on the same die. Therefore, significant redesigns are required, as well as possible movement or shifting of macroblocks in the floorplan. Such redesigns consume a significant amount of design time, thus delaying product release.

[0004] In view of the above, there is a need for methods and systems for efficiently routing power signals across a semiconductor die. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a schematic diagram of a cross-sectional view of a standard cell layout utilizing power connections routed in a front metal layer and a back metal layer.

[0006] Figure 2 is a general block diagram of a top view of a standard cell layout.

[0007] Figure 3 is a general block diagram of a top view of a standard cell layout.

[0008] Figure 4 is a general block diagram of a top view of a standard cell layout.

[0009] Figure 5A generalized block diagram of a top view of a standard cell layout utilizing power connections routed in a front metal layer and a back metal layer.

[0010] Figure 6 A generalized block diagram of a top view of a standard cell layout utilizing power connections routed in a front metal layer and a back metal layer.

[0011] Figure 7 A generalized block diagram of a top view of a standard cell layout utilizing power connections routed in a front metal layer and a back metal layer.

[0012] Figure 8 A generalized block diagram of a method for an integrated circuit layout for efficiently creating standard cells.

[0013] Figure 9 A generalized block diagram of an integrated circuit utilizing power connections routed in a front metal layer and a back metal layer.

[0014] Figure 10 A generalized block diagram showing a computing system having standard cells that utilize power connections routed in a front metal layer and a back metal layer.

[0015] While the present invention may have various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are described in detail herein. However, it should be understood that the drawings and the detailed description thereof are not intended to limit the present invention to the particular form disclosed, but on the contrary, the present invention is to cover all modifications, equivalents, and alternatives falling within the scope of the present invention as defined by the appended claims. Detailed Description

[0016] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, one of ordinary skill in the art should recognize that the present invention may be practiced without these specific details. In some instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the present invention. Additionally, it should be understood that for simplicity and clarity of illustration, the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements are enlarged relative to other elements.

[0017] Apparatuses and methods for efficiently routing power signals across a semiconductor die are envisioned. In various embodiments, an integrated circuit includes a backside power metal zero (or metal 0 or M1 or metal 0) rail located below a silicon substrate layer and any oxide layer for isolation. Through-silicon vias (TSVs) traverse the silicon substrate layer to be placed between the backside power M0 rail and the source region of an n-type device. A p-type device connects its source region to a power supply reference voltage level via a p-type source contact and a frontside power M0 rail. In some embodiments, the integrated circuit uses a cross-field effect transistor (FET) having a first device, such as an n-type device, with a first channel oriented in a first direction and connected to a ground reference voltage level provided by the backside M0 layer. The cross-FET also uses a second device, such as a p-type device, with a second channel oriented in a second direction orthogonal to the first direction and connected to a power supply reference voltage level provided by the frontside M0 layer. The power connections reduce the area on the die, lower the semiconductor manufacturing complexity, which increases the wafer yield, and reduce the voltage drop, which improves the performance. Further details of the integrated circuit and the power connections are provided in the following description of Figures 1 to 10 the integrated circuit and the power connections are provided in the following description of

[0018] Reference Figure 1 , a general block diagram of a cross-sectional view of a standard cell layout 100 illustrating power connections routed in a frontside metal layer and a backside metal layer. The standard cell layout 100 is for any of various types of Boolean gates and compound gates, which include transistors arranged in a specific manner for providing a data processing function or providing data storage. The standard cell layout 100 (or layout 100) uses a cross-FET having a first transistor, such as an n-type device 104, with a first channel oriented in a first direction and connected to a first voltage level reference provided by the backside metal layer. The cross-FET also uses a second transistor, such as a p-type device 102, with a second channel oriented in a second direction orthogonal to the first direction and connected to a second voltage level reference provided by the frontside metal layer. For ease of illustration, three-dimensional (3-D) diagrams of the p-type cross-FET and the n-type cross-FET are not shown here. However, 3-D diagrams are attached in ( Figure 2 of) the standard cell layout 200. Although the cross-sectional view shows each of the two transistors having metal gates oriented in the same direction, the actual placement of these transistors in the semiconductor layout includes orthogonal placement relative to each other.

[0019] The backside power metal zero (or metal 0 or M1 or metal 0) rail 110 is located below the silicon substrate layer and any oxide layer (not shown) for isolation. The micro through-silicon via (TSV) 120 traverses the silicon substrate layer so as to be placed between the backside power M0 rail 110 and the source region 130 of the n-type device 102. In some embodiments, the bottom transistor of the layout 100 is an n-type transistor as shown, wherein the source region 130 is connected to the ground reference voltage level via the micro TSV 120 and the backside power M0 rail 110. In such embodiments, the top transistor of the layout 100 is a p-type transistor as shown, wherein the source region 130 is connected to the power supply reference voltage level via the p-type source contact 180 and the frontside power M0 rail 190. In other embodiments, the n-type transistor and the p-type transistor are switched together with the type of voltage reference level connected to the backside power M0 rail 110 and the frontside power M0 rail 190.

[0020] Before continuing with the description of the materials of the layout 100, a description of the terms used to describe the circuits is provided herein. As used herein, a "cross-FET" is a cross-field effect transistor (FET, which is also referred to as an "XFET"). Additionally, as used herein, a "transistor" is also referred to as a "semiconductor device" or a "device". In some embodiments, the cross-FET is a vertically stacked gate-all-around (GAA) transistor, e.g., a top vertical GAA transistor (or GAA transistor) is formed vertically on top of the bottom GAA transistor with at least an isolation oxide layer between the two GAA transistors. Further, the top GAA transistor has one or more conductive channels, and the position of the one or more conductive channels is orthogonal to the one or more conductive channels of the bottom GAA transistor. Thus, the direction of current flow through the one or more top channels of the top GAA transistor is orthogonal to the direction of current flow through the one or more bottom channels of the bottom GAA transistor.

[0021] The doping polarity of the one or more top channels of the top GAA transistor is a polarity opposite to the doping polarity of the one or more bottom channels of the bottom GAA transistor. For example, in an embodiment, the top GAA transistor includes one or more p-type channels while the bottom GAA transistor includes one or more n-type channels. In another embodiment, the p-type and n-type polarities are opposite between the one or more channels of the top GAA transistor and the bottom GAA transistor. With the orthogonal orientation between the top GAA transistor and the bottom GAA transistor, both the top and bottom GAA transistors have the maximum mobility of their respective carriers based on their orientation.

[0022] The "micro-TSV" 120 is a through-silicon via that traverses through the silicon substrate layer from the backside power M0 rail 110 to the source region 130 and ends with physical contacts at each of the backside power M0 rail 110 and the source region 130. The distance between the backside power M0 rail 110 and the source region 130 defines the height or length of the micro-TSV 120, which traverses only the silicon substrate layer and any oxide layer above the backside power M0 rail 110. The micro-TSV 110 does not physically extend into the multiple insulating layers of the semiconductor die for routing multiple front-side metal layers. Similarly, the micro-TSV 110 does not physically extend into the multiple insulating layers of the semiconductor die for routing multiple back-side metal layers.

[0023] Although the orientation of the standard cell layout 100 (or layout 100) is shown with each of the backside power M0 rail 110 and the front-side power M0 rail 190 routed in the horizontal direction, other orientations are possible and contemplated. It should be understood that silicon wafers, integrated circuits, and semiconductor packages using the silicon substrate layer can be rotated and flipped. Accordingly, the materials and layers described will be rotated and flipped, and the orientation and direction will have different meanings. Thus, the terms "top", "bottom", "horizontal", "vertical", "above", and "below" can change as the layout 100 is rotated or flipped, and the use of these terms in the following description corresponds to the orientation shown in the layout 100.

[0024] As used herein, an "end" of a transistor is also referred to as a "region" of the transistor. For example, the source region is also referred to as the source end, the drain region is also referred to as the drain end, and the gate region is also referred to as the gate end. The source region and the drain region are typically formed in the same orientation (horizontal or vertical) as the corresponding gate metal of the same device. Examples of the source region and the drain region are trench silicide contacts. In some specific embodiments, the source region and the drain region include cobalt silicide (CoSi2). In other specific embodiments, the source region and the drain region include titanium silicide (TiSi2) or ruthenium (Ru).

[0025] For purposes of illustration, the multiple layers of circuitry for completing layout 100 are not shown. For example, at least the active regions, local interconnect layers, and upper metal layers (metal one through metal twelve or higher) and corresponding contacts are not shown. In the specific embodiment illustrated, p-type device 104 is vertically stacked on n-type device 102. However, as previously described, in other specific embodiments, the devices are switched with respect to the vertical stacking in layout 100. N-type device 102 includes at least an n-type gate 150 formed around an n-type channel 140. Similarly, p-type device 104 includes a p-type gate 170 formed around a p-type channel 180. Thus, the doping polarity of p-type channel 160 is a polarity opposite to that of n-type channel 104 of the bottom n-type device. In some specific embodiments, the channels are lateral nanowires, while in other specific embodiments, the channels are nanosheets.

[0026] The n-type channel 140 and n-type gate 150 are in an orthogonal direction with respect to the p-type channel 160 and p-type gate 170. In other words, the n-type channel 140 and n-type gate 150 are in a direction that is 90 degrees with respect to the direction of the p-type channel 160 and p-type gate 170. The direction of current flow through n-type channel 140 of n-type device 102 is orthogonal to the direction of current flow through p-type channel 160 of p-type device 104. Using the orthogonal orientation between the top p-type device 104 and the bottom n-type device 102, both devices have a maximum mobility of their respective charge carriers based on their orientation.

[0027] To transfer current from an off-chip power supply to p-type device 104, current flows from the off-chip power supply to multiple front-side metal layers to the front-side power M0 rail 190 to the source region 130 of p-type device 104. To transfer current from an off-chip ground reference to n-type device 102, current flows from the off-chip ground reference to one or more back-side metal layers to the back-side power M0 rail 110 to the source region 130 of n-type device 102. In some specific embodiments, a single thick back-side metal layer is used instead of multiple thick back-side metal layers to transfer the ground reference to reduce semiconductor manufacturing cost. The power connections shown in layout 100 reduce the die area, reduce semiconductor manufacturing complexity, which increases wafer yield, and reduce voltage drop, which improves performance.

[0028] Now turning to Figure 2 , a generalized block diagram of a top view of a standard cell layout 200 is shown. The previously described contacts (or vias), materials, and structures have the same numbers. Standard cell layout 200 (and Figures 3 to 7The layout 300 - 700) is for an inverter using cross FETs. Layout 200 is accompanied by a three - dimensional (3 - D) illustration of p - type and n - type cross FETs. It should be noted that the placement of the p - type cross FET and the n - type cross FET in the 3 - D illustration shows devices that are vertically aligned with each other. However, these devices are actually moved to a less vertical alignment, as will be shown in the semiconductor layout 200 - 700 of ( Figures 2 to 7 ), to allow for both front - side power connection and back - side power connection.

[0029] The top view of layout 300 is shown on the right side, and the cross - sectional view is shown on the left side. For this inverter, p - type devices are vertically stacked on n - type devices. However, in other embodiments, it is possible and contemplated to vertically stack n - type devices on p - type devices. Each device of the inverter uses gate - all - around (GAA) metal, which wraps one or more nanosheets in the gate region in a 360 - degree manner. The bottom n - type devices are fabricated on a first wafer. The top p - type devices are fabricated on a separate second wafer, and then the second wafer is bonded to the first wafer, as described later.

[0030] Here, in layout 200, the n - type nanosheets 140 are produced by the stacking of alternating layers, such as silicon - germanium semiconductor epitaxial growth layers alternating with silicon semiconductor epitaxial growth layers. The layers are etched to the size of the n - type nanosheets 140 using one of sidewall image transfer (SIT) process, extreme ultraviolet (EUV) lithography, directed self - assembly (DSA) patterning via chemical epitaxy, or self - aligned customization. In other specific implementations, the alternating layers are grown on top of a silicon - on - insulator (SOI) oxide layer, followed by an etching step. A given conductive layer of alternating silicon - germanium semiconductor epitaxial growth layers and silicon semiconductor epitaxial growth layers is selected to be retained for forming the gate region. Any semiconductor layer other than the selected layer is then removed. The n - type gate metal material 150 is deposited, and then the n - type gate metal 150 is polished by a chemical - mechanical planarization (CMP) step. In various specific implementations, titanium nitride (TiN) is used for the n - type gate metal 150. The n - type gate metal 150 is disposed around the n - type nanosheets 140 in a 360 - degree manner. An inter - layer dielectric (ILD) oxide layer is deposited around the gate region. Thereafter, n - type local interconnects 210 are formed. In some specific implementations, the n - type local interconnects 210 include tungsten, cobalt, ruthenium, or molybdenum.

[0031] Reference Figure 3 and Figure 4, a schematic block diagram showing a top view of a standard cell layout 300 and a standard cell layout 400. The previously described contacts (or vias), materials, and structures have the same numbers. In the standard cell layout 300, n-type TSV local interconnects 310 are formed in positions that will be later connected to the micro TSVs. In layout 400, contacts 410 are formed at specific positions of the n-type gate 150. The contacts 410 are used to connect the n-type gate 150 to the p-type gate.

[0032] Now turning to Figure 5 , a schematic block diagram showing a top view of a standard cell layout 500 (or layout 500). The previously described contacts (or vias), materials, and structures have the same numbers. In layout 500, p-type nanosheets 160 are generated in a manner similar to that of n-type nanosheets 140, but with different doping polarities. For the active regions of p-type devices, boron or gallium can be used for doping during the semiconductor manufacturing process. For the active regions of n-type devices, phosphorus or arsenic can be used for doping during the semiconductor manufacturing process. A p-type gate metal material 170 is deposited, and then the p-type gate metal 170 is polished by a CMP step. In various embodiments, titanium nitride (TiN) is used for the p-type gate metal 170. The p-type gate metal 170 is disposed around the p-type nanosheets 160 in a 360-degree manner. An interlayer dielectric (ILD) oxide layer is deposited around the gate region. Thereafter, p-type local interconnects 510 are formed. In some embodiments, the n-type local interconnects 210 include tungsten, cobalt, ruthenium, or molybdenum.

[0033] Now turning to Figure 6 and Figure 7 , a schematic block diagram showing a top view of a standard cell layout 600 (or layout 600) and a standard cell layout 700 (or layout 700). The previously described contacts (or vias), materials, and structures have the same numbers. In layout 600, contacts 610 and 620 are formed. The contact 610 is used to connect the p-type local interconnects 510 to the front-end M0 layer 190 that will be formed later. The contact 620 is used to connect the p-type gate 170 to the front-end M0 layer 190 that will be formed later. In layout 700, the front-end M0 layer 190 is formed to complete the connection of the cross-FET inverter. The nodes "IN" and "OUT" and the power connections "VDD" and "VSS" are marked on the layout 700 of the cross-FET inverter. The power connections shown in layout 700 reduce the area on the die, lower the semiconductor manufacturing complexity, which improves the wafer yield, and reduce the voltage drop, which improves the performance.

[0034] Now referring to Figure 8, shows a general block diagram of a method 800 for efficiently generating an integrated circuit layout of standard cells that utilize techniques to reduce voltage drop and reduce die area. For purposes of discussion, the steps in this particular implementation are shown in sequential order. However, in other particular implementations, some steps occur in a different order than shown, some steps are performed simultaneously, some steps are combined with other steps, and some steps are absent.

[0035] A semiconductor manufacturing process (or process) forms a first through-silicon via (TSV) (block 802) that traverses a silicon substrate layer to a back metal layer on a first node of an integrated circuit that receives a first voltage reference level. The process forms a first transistor having a first channel (block 804). The process forms a second transistor having a second channel on top of the first transistor in a vertical stack, with an orthogonal orientation between the first channel and the second channel (block 806). The process also places a cell, such as a standard cell, in the integrated circuit. In some particular implementations, each of the first transistor, the second transistor, and the transistors in the standard cell are formed as vertical gate-all-around (GAA) devices or other types of non-planar devices. In various particular implementations, the process uses a first doping polarity that is opposite to the doping polarity of the second channel for the first channel. For example, the first transistor is an n-type transistor having an n-type channel, and the second transistor is a p-type transistor having a p-type channel.

[0036] The processor routes the first voltage reference level to the first transistor via the back metal layer and the node (block 808). The process routes a second voltage reference level to the second transistor via the front metal layer (block 810). In some particular implementations, the first voltage reference level is a ground reference voltage level routed to the n-type transistor, and the second voltage reference level is a power reference voltage level routed to the p-type transistor. If no potential is applied to the input node of the integrated circuit (the "no" branch of conditional block 812), the integrated circuit waits to power up (block 814). However, if a potential is applied to the input node of the integrated circuit (the "yes" branch of conditional block 810), the integrated circuit transfers current from the input node to the output node through a given cell (block 816).

[0037] Reference Figure 9 , shows a general block diagram of an integrated circuit 900 having standard cells that utilize techniques to reduce voltage drop and reduce die area. Figure 9 The left side of shows a cross-sectional view of the integrated circuit 900 when it is formed. Figure 9A cross-sectional view of integrated circuit 900 after its formation is shown on the right side, which includes flipping these components. Starting from the cross-sectional view on the right side, the front metal layer 910 (or layer 910) includes multiple metal layers for routing data signals, control signals, and power reference voltage levels. Layer 910 contacts interconnects such as micro-bumps (not shown) placed in a semiconductor package including integrated circuit 900. The active device 920 processes various applications using source data with multiple front-end signals. In various embodiments, the active device 920 includes cross FETs formed using the techniques described previously for the standard cell layouts 100 - 700 for ( Figures 1 to 7 ). In an embodiment, layer 910 provides a power reference voltage level to the p-type devices of the p-type layer 922 of the active device 920. In other embodiments, the p-type layer 922 and the n-type layer 924 are switched, and layer 910 provides a ground reference voltage level to the n-type devices of the active device 920.

[0038] Layer 930 includes a back metal layer 934, which provides a ground reference voltage level to the n-type devices of the n-type layer 924 of the active device 920. In other embodiments, the p-type layer 922 and the n-type layer 924 are switched, and layer 930 provides a power reference voltage level to the p-type devices of the p-type layer 922 of the active device 920. Layer 930 also includes a copper layer 932. The copper layer 932 also dissipates heat energy from the active device 920. The copper barrier adhesion layer 940 (or layer 940) prevents copper from diffusing into the adjacent underlying silicon carrier wafer 950. The silicon carrier wafer 950 provides support and structure throughout the semiconductor manufacturing process. A heat sink is typically placed above the silicon carrier wafer 950. In another embodiment, the copper layer 932 is a single thick copper back layer with an oxide layer on the side opposite to the side in contact with the back metal layer 934. Additionally, the silicon carrier wafer 950 has a thin oxide layer. The thin thickness of the oxide layer of the silicon carrier wafer 950 reduces the resistance to heat transfer. The oxide layer of the copper layer 932 is joined to the oxide layer of the silicon carrier wafer 950.

[0039] Refer to Figure 10, a generalized block diagram of a computing system 1000 with standard cells is shown, and these standard cells utilize techniques to reduce voltage drop and reduce on-die area. The computing system 1000 includes a processor 1010 and a memory 1030. For the sake of illustration, interfaces such as a memory controller, a bus or communication fabric, one or more phase-locked loops (PLLs) and other clock generation circuits, a power management unit, etc. are not shown. It should be understood that in other specific implementations, the computing system 1000 includes one or more of other processors of the same type or different types as the processor 1010, one or more peripheral devices, a network interface, one or more other memory devices, etc. In some specific implementations, the functions of the computing system 1000 are integrated on a system-on-chip (SoC). In other specific implementations, the functions of the computing system 1000 are integrated on a peripheral device card inserted into a motherboard. The computing system 1000 is used in any of a variety of computing devices such as desktop computers, tablet computers, laptop computers, smartphones, smartwatches, game consoles, personal assistant devices, etc.

[0040] The processor 1010 includes hardware such as circuits. For example, the processor 1010 includes at least one integrated circuit 1020. The integrated circuit 1020 includes units 1022, and one or more of these units 1022 use a cross FET with a first transistor that has a first channel oriented in a first direction and connected to a first voltage level reference provided by a back metal layer. The cross FET also uses a second transistor that has a second channel oriented in a second direction orthogonal to the first direction and connected to a second voltage level reference provided by a front metal layer. The formation of the cross FETs of the units 1022 uses techniques performed for the standard cell layout 100 - 700 of ( Figures 1 to 7 and) the integrated circuit 900 of ( Figure 9 ).

[0041] In some specific implementations, the processor 1010 includes one or more processing units. In some specific implementations, each of the processing units includes one or more processor cores capable of general-purpose data processing and an associated cache memory subsystem. In such specific implementations, the processor 1010 is a central processing unit (CPU). In another specific implementation, the processing core is a computing unit, and each computing unit has a highly parallel data microarchitecture with multiple parallel execution lanes and an associated data storage buffer. In such specific implementations, the processor 1010 is a graphics processing unit (GPU), a digital signal processor (DSP), or others.

[0042] In some specific implementations, the memory 1030 includes one or more of a hard disk drive, a solid state disk, other types of flash memory, a portable solid state drive, a tape drive, and the like. The memory 1030 stores an operating system (OS) 1032, one or more applications represented by code 1034, and at least source data 1036. The memory 1030 is also capable of storing intermediate result data and final result data generated by the processor 1010 when executing a specific application of the code 1034. Although a single instance of the operating system 1032 and the code 1034 and the source data 1036 are shown, in other specific implementations, another quantity of these software components are stored in the memory 1030. The operating system 1032 includes instructions for initiating the startup of the processor 1010, allocating tasks to the hardware circuits, managing the resources of the computing system 1000, and hosting one or more virtual environments.

[0043] Each of the processor 1010 and the memory 1030 includes an interface unit for communicating with each other and any other hardware components included in the computing system 1000. The interface unit includes a queue for servicing memory requests and memory responses and control circuits for communicating with each other based on a specific communication protocol. The communication protocol determines various parameters, such as power supply voltage levels, power performance states that determine the operating power supply voltage and the operating clock frequency, data rates, one or more burst modes, and the like.

[0044] Note that one or more of the above specific implementations include software. In such specific implementations, program instructions for implementing the methods and / or mechanisms are transmitted or stored on a computer-readable medium. Many types of media configured to store program instructions are available and include hard disks, floppy disks, CD-ROMs, DVDs, flash memory, programmable ROM (PROM), random access memory (RAM), and various other forms of volatile or non-volatile storage devices. Generally, a computer-accessible storage medium includes any storage medium that can be accessed by a computer during use to provide instructions and / or data to the computer. For example, computer-accessible storage media include storage media such as magnetic or optical media, such as disks (fixed or removable), tapes, CD-ROMs or DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs, or Blu-ray. Storage media also includes volatile or non-volatile storage media such as RAM (e.g., synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low-power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (RDRAM), static RAM (SRAM), etc.), ROM accessible via a peripheral device interface (such as a universal serial bus (USB) interface, etc.), flash memory, non-volatile memory (e.g., flash memory). Storage media includes microelectromechanical systems (MEMS), and storage media accessible via communication media such as networks and / or wireless links.

[0045] Additionally, in various specific implementations, the program instructions include behavioral-level descriptions or register transfer level (RTL) descriptions of hardware functions in a high-level programming language (such as C) or a design language (HDL) (such as Verilog, VHDL, or a database format (such as the GDS II stream format (GDSII))). In some cases, the description is read by a synthesis tool that synthesizes the description to produce a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represents the functionality of the hardware including the system. The netlist is then placed and routed to produce a data set that describes the geometry to be applied to a mask. The mask is then used in various semiconductor manufacturing steps to produce a semiconductor circuit or circuit corresponding to the system. Alternatively, the instructions on the computer-accessible storage medium are the netlist (with or without the synthesis library) or the data set as desired. Additionally, the instructions are for the purpose of simulation by hardware-based type emulators from such vendors as and Mentor for such purposes.

[0046] Although the foregoing specific embodiments have been described in considerable detail, many variations and modifications will become apparent to those skilled in the art once the above disclosure is fully understood. It is intended that the following claims be interpreted to cover all such variations and modifications.

Claims

1. An integrated circuit, the integrated circuit comprising: A first transistor, the first transistor including a first channel oriented in a first direction; An oxide layer, the oxide layer adjacent to the first transistor; A second transistor, the second transistor adjacent to the oxide layer, wherein the second transistor includes a second channel, the second channel oriented in a direction orthogonal to the first direction; And A backside metal layer, the backside metal layer connected to each of a first power rail and the second transistor, the backside metal layer configured to route a first voltage reference level of the first power rail.

2. The integrated circuit according to claim 1, the integrated circuit further comprising a front metal layer connected to each of the second power rail and the first transistor, the front metal layer being configured to route a second voltage reference level of the second power rail.

3. The integrated circuit according to claim 2, wherein a first doping polarity of the first channel is a polarity opposite to a second doping polarity of the second channel.

4. The integrated circuit according to claim 2, wherein the first voltage reference level is different from the second voltage reference level.

5. The integrated circuit according to claim 2, the integrated circuit further comprising a through-silicon via (TSV) that traverses a silicon substrate layer between a source region of the second transistor and the back metal layer.

6. The integrated circuit according to claim 2, the integrated circuit further comprising a heat sink positioned closer to a plurality of back metal layers than a plurality of front metal layers.

7. The integrated circuit according to claim 6, the integrated circuit further comprising a copper barrier adhesive layer between the plurality of back metal layers and a carrier wafer.

8. A method, the method comprising: Form a first transistor in an integrated circuit having a first channel oriented in a first direction; Form an oxide layer adjacent to the first transistor in the integrated circuit; Form a second transistor adjacent to the oxide layer in the integrated circuit, wherein the second transistor includes a second channel, the second channel oriented in a direction orthogonal to the first direction; And Form a backside metal layer connected to each of a first power rail and the second transistor, the backside metal layer configured to route a first voltage reference level of the first power rail.

9. The method according to claim 8, the method further comprising forming a front metal layer connected to each of the second power rail and the first transistor, the front metal layer routing a second voltage reference level of the second power rail.

10. The method according to claim 9, the method further comprising forming the first channel having a first doping polarity that is a polarity opposite to a second doping polarity of the second channel.

11. The method according to claim 9, wherein the first voltage reference level is different from the second voltage reference level.

12. The method according to claim 9, the method further comprising forming a micro through-silicon via (TSV), the micro TSV passing through the silicon substrate layer between the source region of the second transistor and the back metal layer.

13. The method according to claim 9, the method further comprising forming a heat sink positioned closer to the plurality of back metal layers than the plurality of front metal layers.

14. The method according to claim 13, the method further comprising forming a copper barrier adhesive layer between the plurality of back metal layers and the carrier wafer.

15. A computing system, the computing system comprising: A memory, the memory configured to store instructions for one or more tasks and source data to be processed by the one or more tasks; An integrated circuit, the integrated circuit configured to execute the instructions of the one or more tasks using the source data, wherein the integrated circuit includes: A first transistor, the first transistor including a first channel oriented in a first direction; An oxide layer, the oxide layer adjacent to the first transistor; A second transistor, the second transistor adjacent to the oxide layer, wherein the second transistor includes a second channel, the second channel oriented in a direction orthogonal to the first direction; and A backside metal layer, the backside metal layer connected to each of a first power rail and the second transistor, the backside metal layer configured to route a first voltage reference level of the first power rail.

16. The computing system according to claim 15, wherein the integrated circuit further comprises a front metal layer, the front metal layer being connected to each of the second power rail and the first transistor, the front metal layer being configured to route a second voltage reference level of the second power rail.

17. The computing system according to claim 16, wherein a first doping polarity of the first channel is a polarity opposite to a second doping polarity of the second channel.

18. The computing system according to claim 16, wherein the first voltage reference level is different from the second voltage reference level.

19. The computing system according to claim 16, wherein the integrated circuit further comprises a micro through-silicon via (TSV) passing through the silicon substrate layer between the source region of the second transistor and the back metal layer.

20. The computing system according to claim 16, wherein the integrated circuit further comprises a heat sink positioned closer to the plurality of back metal layers than the plurality of front metal layers.

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