Voltage regulator with switching circuitry

Abstract

Described herein is a voltage regulator comprising: an error amplifier configured to provide an error signal based on a comparison of a reference voltage and a voltage at a voltage divider coupled to an output node of a voltage regulation circuit; a pass transistor configured to selectively pass a current from an input node to the output node based on the error signal; and switching circuitry configured to selectively couple one of a first voltage supply input and a second voltage supply input to the input node. The switching circuitry includes: a first branch including a first switch and a transistor coupled with the pass transistor in a cascode arrangement; and a second branch including a second switch.

Description

Technical Field

[0001] Embodiments of the subject matter described herein generally relate to regulators, including low dropout regulators having switching circuitry for voltage supply input selection. Background Art

[0002] Linear voltage regulators, such as low dropout (LDO) regulators, generate a regulated direct current (DC) output voltage from a received supply voltage. Specifically, LDO regulators are used in many applications because of their ability to linearly regulate the output voltage even when the supply voltage is very close to the output voltage. The noise generated by LDOs tends to be less and may be smaller than that of other types of regulators. Summary of the Invention

[0003] A brief overview of various exemplary embodiments is presented below. Some simplifications and omissions may be made in the following overview, which is intended to highlight and introduce some aspects of the various exemplary embodiments without limiting the scope. A detailed description of exemplary embodiments sufficient to allow one of ordinary skill in the art to make and use these concepts will follow in later sections.

[0004] In an example embodiment, a voltage regulation circuit includes: an error amplifier configured to provide an error signal based on a comparison of a reference voltage with a voltage at a voltage divider coupled to an output node of the voltage regulation circuit; a transfer transistor configured to selectively transfer current from an input node to the output node based on the error signal; and a switching circuitry configured to selectively couple one of a first voltage supply input and a second voltage supply input to the input node. The switching circuitry includes: a first branch coupled between the first voltage supply input and the input node, the first branch including a transistor coupled to the transfer transistor in a cascode arrangement; and a second branch coupled between the second voltage supply input and the input node.

[0005] In one or more embodiments, the voltage regulation circuit further includes: a charge pump having an input coupled to the output node, the charge pump configured to generate a charge pump voltage; and a cascode driver configured to receive the charge pump voltage and control an amount of current through the transistor of the first branch.

[0006] In one or more embodiments, the voltage regulation circuit further includes a first switch included in the first branch, a second switch included in the second branch, and one or more switch drivers coupled to the first switch and the second switch and configured to control the first switch and the second switch.

[0007] In one or more embodiments, the transistor of the first branch is a first nMOS power transistor having a first rated voltage, and the transfer transistor is a second nMOS power transistor having a second rated voltage less than the first rated voltage.

[0008] In one or more embodiments, when the output node is at zero volts and the first voltage supply input is selected, the transistor of the first branch is configured to dissipate most of the power in the voltage regulation circuit.

[0009] In one or more embodiments, when the output node is at zero volts and the second voltage supply input is selected, the transfer transistor is configured to dissipate most of the power in the voltage regulation circuit.

[0010] In one or more embodiments, the first voltage supply input is configured to receive a first voltage, the second voltage supply input is configured to receive a second voltage, and the first voltage is greater than the second voltage.

[0011] In one or more embodiments, the voltage regulation circuit further includes a current limiter circuit system coupled to the gate of the transfer transistor and configured to limit the current through the transfer transistor.

[0012] In an exemplary embodiment, a low dropout regulator includes: an output node; a voltage divider coupled to the output node; an error amplifier configured to generate an error signal based on a comparison of a reference voltage and the voltage at the voltage divider; a transfer transistor configured to receive the error signal from the error amplifier and selectively transfer current from an input node to the output node; and a switching circuit system including a first branch coupled between a first voltage supply input and the input node and a second branch coupled between a second voltage supply input and the input node, the first branch including a cascode transistor coupled to the transfer transistor in a cascode arrangement, and the second branch being coupled in parallel with the first branch.

[0013] In one or more embodiments, the low dropout regulator further includes: a charge pump having an input coupled to the output node, the charge pump being configured to generate a charge pump voltage; and a cascode driver configured to receive the charge pump voltage and control the amount of current through the cascode transistor.

[0014] In one or more embodiments, the cascode transistor is a first nMOS power transistor having a first rated voltage, and the transfer transistor is a second nMOS power transistor having a second rated voltage less than the first rated voltage.

[0015] In one or more embodiments, when the output node is shorted to ground and the first branch is active, the cascode transistor is configured to dissipate a first amount of power, and the transfer transistor is configured to dissipate a second amount of power that is less than the first amount of power.

[0016] In one or more embodiments, when the output node is shorted to zero volts and the second branch is active, the transfer transistor is configured to dissipate most of the power in the low dropout regulator.

[0017] In one or more embodiments, the first voltage supply input is configured to receive a first voltage, the second voltage supply input is configured to receive a second voltage, and the first voltage is greater than the second voltage.

[0018] In one or more embodiments, the low dropout regulator further includes a current limiter circuit system that is coupled to the gate of the transfer transistor and is configured to limit the current passing through the transfer transistor.

[0019] In an exemplary embodiment, a power management integrated circuit includes a battery, a direct current (DC)-DC converter coupled to the battery, and a voltage regulation circuit configured to generate a regulated output voltage at an output node. The voltage regulation circuit includes: a voltage divider coupled to the output node; an error amplifier configured to generate an error signal based on a comparison of a reference voltage and the voltage at the voltage divider; a transfer transistor configured to receive the error signal from the error amplifier and selectively transfer current from an input node to the output node based on the error signal; and a switch circuit system including a first branch coupled between the battery and the input node and a second branch coupled between the DC-DC converter and the input node, the first branch including a cascode transistor coupled to the transfer transistor in a cascode arrangement, and the second branch being coupled in parallel with the first branch.

[0020] In one or more embodiments, the power management integrated circuit further includes: a charge pump having an input coupled to the output node, the charge pump being configured to generate a charge pump voltage; and a cascode driver configured to receive the charge pump voltage and control the amount of current passing through the cascode transistor.

[0021] In one or more embodiments, the cascode transistor is a first nMOS power transistor having a first rated voltage, and the transfer transistor is a second nMOS power transistor having a second rated voltage that is less than the first rated voltage.

[0022] In one or more embodiments, when the output node is shorted to ground and the first branch is active, the cascode transistor is configured to dissipate a first amount of power, and the transfer transistor is configured to dissipate a second amount of power that is less than the first amount of power.

[0023] In one or more embodiments, when the output node is shorted to zero volts and the second branch is active, the transfer transistor is configured to dissipate most of the power in the low dropout regulator. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] A more complete understanding of the subject matter may be derived by considering the following figures, which are incorporated by reference into the detailed description and the claims, and in which like reference numerals throughout the figures refer to similar elements. The elements in the figures are shown for simplicity and clarity and are not necessarily drawn to scale. The figures are incorporated with the detailed description and form a part of the specification to further illustrate examples, embodiments, etc., and to explain various principles and advantages in accordance with the present disclosure, wherein:

[0025] Figure 1 is a block diagram of an illustrative low dropout (LDO) regulator coupled to a plurality of selectable voltage supply inputs, wherein the switching circuitry coupled to the voltage supply inputs includes a cascode high voltage input branch; and

[0026] Figure 2 is a block diagram of an illustrative system of a power management integrated circuit (PMIC) having an LDO regulator including Figure 1 ... DETAILED DESCRIPTION

[0027] The following detailed description is merely illustrative in nature and is not intended to limit embodiments of the subject matter or the application and uses of such embodiments. Further, there is no intention to be bound by any theory presented in the preceding background art or background or in the following detailed description.

[0028] For simplicity and clarity of illustration, the figures show general constructional manner, and descriptions and details of well-known features and techniques may be omitted so as not to unnecessarily obscure the present disclosure. Additionally, the elements in the figures are not necessarily drawn to scale. For example, the dimensions of some elements or regions in the figures may be exaggerated relative to other elements or regions to assist in improving understanding of the embodiments described herein.

[0029] The terms "first," "second," "third," "fourth," etc. (if any) in the description and claims may be used to distinguish similar elements and are not necessarily used to describe a particular sequential or temporal order. It should be understood that the terms so used may be interchangeable under appropriate circumstances such that the embodiments described herein (for example) can be operated in a sequence other than the sequence illustrated or otherwise described herein. Further, the terms "comprising," "having," and any variations thereof are intended to cover non-exclusive inclusion such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. As used herein, the term "coupled" is defined as connected directly or indirectly in an electrical or non-electrical manner. As used herein, the terms "substantially" and "substantially" mean sufficient to achieve the stated purpose in a practical manner, and minor deficiencies (if any) are not important for the stated purpose. As used herein, the words "exemplary" and "example" mean "serving as an example, instance, or illustration." Any embodiment described herein as exemplary or an example is not necessarily to be construed as preferred or advantageous over other embodiments. Further, certain terms may be used herein for reference purposes only and are thus not intended to be limiting.

[0030] Unless otherwise stated, directional references such as "top," "bottom," "left," "right," "above," "below," etc. are not intended to require any preferred orientation but are made for illustrative purposes with reference to the orientation of one or more of the corresponding figures.

[0031] The various embodiments described herein relate to voltage regulators, such as low dropout (LDO) regulators having multiple selectable voltage supply inputs, wherein the high voltage leg of the switching circuitry for selecting between the voltage supply inputs includes a first power transistor (sometimes referred to herein as a "cascode transistor"), and the first power transistor is in a cascode arrangement with a second power transistor (sometimes referred to herein as a "transfer transistor") of the voltage regulator. For example, the cascode transistor of an illustrative voltage regulator may have a higher rated voltage relative to the rated voltage of the transfer transistor, and during a scenario where the output of the regulator is shorted (e.g., shorted to 0V), the power dissipation through the cascode transistor may be greater than the power dissipation through the transfer transistor. In contrast, conventional voltage regulator methods may be arranged such that in the case of a short circuit, most of the power dissipation is concentrated in a single transfer transistor, resulting in an undesirably higher temperature at the transfer transistor than in the case where the power dissipation is distributed between two or more devices.

[0032] In one or more embodiments, an illustrative voltage regulator can include an error amplifier, a current limiter circuitry, and a pass transistor. The voltage regulator can be coupled to two or more alternative voltage supply inputs via a switching circuitry such that the error amplifier, the current limiter circuitry, and the pass transistor can be used with the multiple voltage supply inputs. In contrast, conventional voltage regulator approaches may require a corresponding error amplifier, current limiter, and pass transistor for each voltage supply input, which undesirably requires higher cost, greater footprint, and greater design complexity.

[0033] Figure 1 is a block diagram of a low dropout (LDO) regulator 100 (sometimes referred to as "linear regulator 100" or "voltage regulation circuit 100") having an input node 122 selectively coupled to multiple voltage supply inputs via a switching circuitry 116. The high voltage path (sometimes referred to as "high voltage branch") of the switching circuitry 116 can include a transistor 148 (sometimes referred to herein as "cascode transistor 148") coupled in a cascode arrangement with a transistor 106 (sometimes referred to herein as "pass transistor 106") of the LDO regulator 100. The cascode arrangement of the transistor 148 and the pass transistor 106 can provide suitable power dissipation in the LDO regulator 100 during a short circuit condition (i.e., shorted to ground, 0V, or another applicable reference potential) at, for example, the output node 126 of the LDO regulator 100, as further described below.

[0034] Although the switching circuitry 116 of the current example is described with reference to an LDO regulator, it should be understood that this is illustrative and non-limiting. For example, according to one or more other embodiments, the switching circuitry 116, particularly the cascode arrangement of its high voltage branch, can be used with other suitable voltage regulator arrangements.

[0035] As shown in the figure, the LDO regulator 100 may include an error amplifier 102, a charge pump 104, a transfer transistor 106, a transistor 108 (sometimes referred to herein as "sense transistor 108"), a current limiter circuit system 110, an output capacitor 114, a switching circuit system 116, a control circuit system 140, a switch driver 142, and a cascode driver 144. According to one or more embodiments, the error amplifier 102 may be a differential amplifier having a non-inverting input, an inverting input, and an output. The non-inverting input of the error amplifier 102 may be coupled to a reference node 138, at which a reference voltage VREF is provided (e.g., by a reference voltage supplier; not shown). In one or more embodiments, by way of non-limiting example, the reference voltage VREF may be between about 1V and about 1.2V. The inverting input of the error amplifier 102 may be coupled to a node 136 of a voltage divider 131, which includes a resistor 132 having a resistance R1 and a resistor 134 having a resistance R2, wherein the resistors 132 and 134 are coupled in series between the output node 126 of the LDO regulator 100 and ground or a reference node, and the node 136 is coupled between the resistors 132 and 134. The output of the error amplifier 102 may be coupled via a node 124 to the gates of the transfer transistor 106 and the sense transistor 108. The voltage signal output by the error amplifier 102 is sometimes referred to herein as an "error signal" and may control the amount of current allowed to pass through the transfer transistor 106 (i.e., from the drain terminal of the transfer transistor 106 to the source terminal of the transfer transistor 106; between the current-carrying terminals of the transfer transistor 106), thereby adjusting the voltage VOUT at the output node 126. That is, the transfer transistor 106 may selectively transfer current from the input node 122 to the output node 126 based on the error signal output by the error amplifier 102. The voltage VDIV at the node 136 of the voltage divider 131 may be a portion of the voltage VOUT, which is compared by the error amplifier 102 with the reference voltage VREF to determine the output voltage of the error amplifier 102. For example, VDIV may be equal to VOUT*(R2 / (R1 + R2)). In this way, the error amplifier 102 may regulate the voltage VOUT at the output node 126. It should be understood that herein, according to various embodiments, a "ground node" may refer to a node that receives or is connected to a ground voltage, a common voltage, or another suitable reference potential (e.g., 0V). Herein, the "gate terminal" or "base terminal" of a transistor may sometimes be referred to as a "control terminal", and the "drain terminal" and "source terminal" of a transistor may sometimes be referred to as "current-carrying terminals".

[0036] The sense transistor 108 can provide current sensing for the current limiter circuit system 110, where the current level through the sense transistor 108 corresponds to the current level through the transfer transistor 106. The current limiter circuit system 110 can limit the current through the transfer transistor 106 to a predefined current level (e.g., as a non-limiting example, 100 mA) based on the current through the sense transistor 108 by providing a feedback signal to node 124, the feedback signal adjusting the voltage at node 124 to limit the current allowed through the transfer transistor 106 and the sense transistor 108). The area ratio between the transfer transistor 106 and the sense transistor 108 can define the ratio of the current through the transfer transistor 106 to the current through the sense transistor 108).

[0037] The charge pump 104 can include an input coupled to the output node 126 and can be configured to generate and provide a voltage VCP (sometimes referred to herein as the "charge pump voltage") at the output node 128 based on the output voltage VOUT. For example, the charge pump 104 can provide the voltage VCP to various elements of the LDO regulator 100, such as the error amplifier 102 and the cascode driver 144, as non-limiting examples. In one or more embodiments, as a non-limiting example, the charge pump 104 is configured to generate a voltage VCP at a voltage level equal to or approximately equal to 10 V. In this document, unless otherwise specified, an example quantity referred to as "about" or "approximately" a given value is considered to be within + / - 10% of the given value.

[0038] The switch circuit system 116 can be controlled by the control circuit system 140 in conjunction with the switch driver 142 and the cascode driver 144 to selectively connect one of the high voltage supply input 118 and the medium voltage supply input 120 to the input node 122, a high supply voltage VHIGH being provided at the high voltage supply input 118 (e.g., by the battery of a system including the LDO regulator 100), and a medium supply voltage VMED being provided at the medium voltage supply input 120 (e.g., by a direct current (DC)-DC converter of a system including the LDO regulator 100). The input node 122 can be coupled to the drain terminal of the transfer transistor 106. The switch circuit system 116 can include: a high voltage branch coupled between the high voltage supply input 118 and the input node 122, where the high voltage branch includes a switch 146 and a transistor 148; and a medium voltage branch coupled between the medium voltage supply input 120 and the input node 122, where the medium voltage branch includes a switch 150. The medium voltage branch can be coupled in parallel with the high voltage branch.

[0039] The cascode driver 144 can receive control signals from the control circuitry 140. The output node 128 of the charge pump 104 can be coupled to the supply input of the cascode driver 144, and the voltage VCP can serve as the positive supply voltage for the cascode driver 144. The output of the cascode driver 144 can be coupled to the gate of the transistor 148 such that the cascode driver 144 controls the current passing through the transistor 148. For example, the cascode driver 144 can be selectively configured by the control circuitry 140 to place the transistor 148 in an "on" or "low impedance" state or in an "off" or "high impedance" state by adjusting the gate voltage provided by the cascode driver 144 to the gate terminal of the transistor 148.

[0040] The switch 146 in the high voltage leg of the switch circuitry 116 and the switch 150 in the medium voltage leg of the switch circuitry 116 can each be controlled by the switch driver 142. For example, the switch 146 can be controlled by a different switch driver than the switch driver used to control the switch 150, at least because the switch 146 must be able to handle a higher voltage than the switch 150. The control circuitry 140 can provide corresponding control signals for independently controlling each of the switch drivers (and the corresponding switches) in the switch driver 142.

[0041] As shown, the switches 146 and 150 can each include a body diode. These body diodes allow current to flow through the switches 146 and 150 even when they are open (off), and allow current to flow towards the node 122 provided that a low impedance path to the node 122 is available via the corresponding leg. For example, when VHIGH is greater than VMED and when there is a low impedance path between the high voltage supply input 118 and the node 122 (i.e., when the transistor 148 is on), the body diode of the switch 150 prevents reverse current from flowing into the medium voltage supply input 120. Herein, a switch or transistor is considered to be "closed", "on", or "activated" when a relatively low impedance path is provided between the input of the switch (excluding the body diode path) and the output of the switch such that current can flow between its input and its output. Herein, a switch or transistor is considered to be "open", "off", or "deactivated" when a relatively high impedance path is provided between the input of the switch or transistor and its output (excluding the body diode path) such that current flow therebetween is reduced or blocked.

[0042] The voltage VIN at node 122 can be set based on the highest voltage connected to node 122 via the switching circuitry 116 (e.g., for a configuration in which transistor 148 is effectively replaced by a simple short circuit). Given the cascode arrangement of transistor 148 and transfer transistor 106, when the high voltage supply input 118 is to be selected as the voltage supplier for the LDO regulator 100, the cascode driver 144 can be configured to provide a gate voltage to the gate terminal of transistor 148 sufficient to allow current conduction between the source and drain terminals of transistor 148, where VIN at node 122 is equal to the voltage output by the cascode driver 144 minus the gate-to-source voltage (VGS) of transistor 148. In this way, transistor 148 can limit the voltage VIN at node 122 (e.g., limited to a value of about 10V in this configuration). Continuing with the example, switch 146 can be closed by switch driver 142 to bypass the body transistor of switch 146 (thereby avoiding the associated voltage drop), and switch 150 can be held open by switch driver 142. In this configuration, the voltage at node 122 is greater than VMED, and the body diode of switch 150 prevents current from flowing from node 122 to the medium voltage supply input 120.

[0043] As another example in which the medium voltage supply input 120 is to be selected as the voltage supplier for the LDO regulator 100, the cascode driver 144 can be configured to provide a gate voltage to the gate terminal of transistor 148 sufficient to block or otherwise prevent current conduction between the source and drain terminals of transistor 148, such that the high voltage supply input 118 is effectively disconnected from node 122 (i.e., such that the high voltage branch of the switching circuitry 116 is “open”). Continuing with the example, switch 146 can be held open by switch driver 142 (where the current through the body diode of switch 146 is blocked by transistor 148), and switch 150 can be closed by switch driver 142 to bypass the body transistor of switch 150 (thereby avoiding the associated voltage drop). In this configuration, the voltage at node 122 is equal to or approximately equal to VMED.

[0044] It should be understood that the specific elements shown as being included in the switching circuitry 116 of the current example are illustrative and not restrictive. For example, in one or more other embodiments, alternatively, switches 146 and 150 can be implemented as diodes instead of switches. Although this embodiment will cause a corresponding voltage drop across the diodes in each branch of the switching circuitry 116, it has the advantage of lower cost (e.g., due to the omission of switches 146 and 150 and switch driver 142).

[0045] In one or more embodiments, transistor 148 and transfer transistor 106 can each be an n-type metal-oxide-semiconductor (nMOS) power transistor. In one or more embodiments, by way of non-limiting example, transistor 148 can have a rated drain-to-source voltage (VDS) of 90V or approximately 90V, and transfer transistor 106 can have a rated voltage of approximately 10V. High voltage supply input 118 can be connected to a voltage source (e.g., a battery) configured to supply a voltage VHIGH between 74V and 90V. Medium voltage supply 120 can be connected to a voltage source (e.g., a battery-powered DC-DC converter) configured to supply a voltage VMED between 3V and 7V. Transistor 148 can be configured such that when the high voltage branch is active (i.e., when cascode 148 is activated), the voltage drop across transistor 148 is greater than the voltage drop across transfer transistor 106, such that when the high voltage branch is active, the power dissipation in LDO regulator 100 is distributed between transistor 148 and transfer transistor 106, and such that the power dissipated by transistor 148 is greater than the power dissipated by transfer transistor 106.

[0046] By way of example, high voltage supply input 118 can receive a voltage VHIGH of approximately 50V, medium voltage supply input 120 can receive a voltage VMED of approximately 10V, and current limiter circuitry 110 can be configured to limit the current through transfer transistor 106 to 100mA. Continuing the example, in the case of a short circuit at output node 126 when the high voltage branch is active (e.g., VOUT is 0V, ground, or another suitable reference potential), LDO regulator 100 will dissipate 5W (i.e., 50V * 100mA) of power. In this scenario, the voltage VIN at node 122 is approximately 10V, such that the voltage drop across transistor 148 is approximately 50V - 10V = 40V, and the voltage drop across transfer transistor 106 is approximately 10V - 0V = 10V. Given a current limit of 100mA, the power dissipated by transistor 148 is approximately 40V * 100mA = 4W, and the power dissipated by transfer transistor 106 is approximately 10V * 100mA = 1W, such that transistor 148 dissipates most of the power via LDO regulator 100.

[0047] Continuing with the example, in the case of a short circuit occurring at output node 126 while the medium voltage branch is active, the LDO regulator 100 will dissipate 1 W (i.e., 10 V * 100 mA) of power. In this scenario, the voltage VIN at node 122 is approximately 10 V, such that the voltage drop across transfer transistor 106 is approximately 10 V - 0 V = 10 V. Given a current limit of 100 mA, the power dissipated by transfer transistor 106 is approximately 10 V * 100 mA = 1 W, such that transfer transistor 106 dissipates most of the power via LDO regulator 100.

[0048] For comparison, a conventional approach includes a first LDO regulator implemented for a high voltage supply configured to supply 50 V at a 100 mA current limit, and a separate second LDO regulator implemented for a medium voltage supply configured to supply 10 V at a 100 mA current limit. This arrangement would require the first transfer transistor of the first (high) voltage LDO regulator to sustain 50 V * 100 mA = 5 W of power, and would require the second transfer transistor of the second (medium) voltage LDO regulator to sustain 10 V * 100 mA = 1 W of power. In contrast, given the embodiment of LDO regulator 100, with VHIGH = 50 V, VMED = 10 V, and a current limit of 100 mA, transistor 148 will only need to sustain 4 W, and transfer transistor 106 will only need to sustain 1 W (as described above). This corresponds to a potential 20% reduction in the rated power (and thus device size) of transistor 148 of LDO regulator 100 compared to the first transfer transistor of the conventional approach in the above example, with equivalent temperature performance.

[0049] As shown, in LDO regulator 100, multiple optional voltage supply inputs 118 and 120 are coupled to a single feedback loop including error amplifier 102, transfer transistor 106, and current limiter circuitry 110. Conventional LDO regulators having multiple error amplifiers and multiple sets of current limiter circuitry (i.e., one / one set per voltage supply branch) each coupled to a respective optional voltage supply input require separate design, testing, and stabilization for each set of current limiter circuitry and each error amplifier. In contrast, LDO regulator 100 advantageously only requires testing, design, and stabilization of a single error amplifier 102 and a single current limiter circuitry 110.

[0050] In addition, the redesign of such a conventional LDO regulator having multiple error amplifiers and multiple sets of current limiter circuitry requires the redesign of each of the multiple LDOs and each of the multiple sets of current limiter circuitry. In contrast, in the case of a redesign being required, the LDO regulator 100 advantageously only requires the redesign of a single error amplifier 102 and a single current limiter circuitry 110. Additionally, the LDO regulator 100 can be reused for applications using the same voltage VMED and a higher voltage VHIGH without such a redesign.

[0051] Figure 2 An example of a system 200 is shown that includes a power management integrated circuit (PMIC) 202, a battery 204, and a system on a chip (SOC) 216. In the current example, the PMIC 202 includes Figure 1 an embodiment of the LDO regulator 100 as a voltage regulation circuit. In one or more embodiments, the system 200 is an automotive system and the SOC 216 is an automotive SOC. In the current example, reference is made to Figure 1 the LDO regulator 100, where like reference numerals are used to denote like elements.

[0052] The PMIC 202 may include a DC-DC converter 206, an LDO regulator 100, a converter driver 208, a memory 212, and control logic 214. The LDO regulator 100 may provide a regulated output voltage VOUT for powering one or more of the converter driver 208, the memory 212, and the control logic 214. The DC-DC converter 206 may receive a voltage VHIGH (e.g., as a non-limiting example, from about 12V to about 48V), and may generate a voltage VMED (e.g., as a non-limiting example, from about 6V to 10V) by stepping down the voltage VHIGH. The control logic 214 may communicate with the SOC 216 via an interface 230, and may control the DC-DC converter to amplify or reduce the voltage VMED based on instructions received from the SOC 216. In one or more embodiments, the memory 212 includes one-time programmable (OTP) memory, which may provide preset limits for voltage ranges and other parameters. For one or more embodiments where the system 200 is an automotive system, the preset limits of the OTP memory of the memory 212 may be stored by the manufacturer of the PMIC or by the manufacturer of the vehicle in which the system 200 is disposed.

[0053] The SOC 216 may include one or more processor cores 218, a computer-readable memory 220, one or more input / output (I / O) devices 222, one or more peripheral devices 224, and one or more subsystems 226, each of which may receive power from a corresponding DC-DC converter 228, where each of the DC-DC converters 228 is coupled to receive VMED from the DC-DC converter 206. The voltage VOUT generated by the LDO regulator 100 may be provided to a converter driver 231 configured to drive a corresponding one of the DC-DC converters 228.

[0054] Each of the processor cores 218 of the SOC 216 may include at least one central processing unit (CPU) and a local cache memory. In one or more embodiments, the memory 220 may be the system memory of the SOC 216 connected to the processor cores 218, the I / O devices 222, the peripheral devices 224, and / or the subsystems 226 via one or more interconnects or communication buses (not shown). The memory 220 may include computer-readable instructions for an operating system executable by the processor cores 218 and other software associated with tasks performed by the SOC 216.

[0055] As a non-limiting example, the I / O devices 222 may include I / O devices for applications provided by the SOC 216, such as a display, a touchscreen input device, and one or more network ports. As a non-limiting example, the peripheral devices 224 may include circuitry configured to perform flash memory management, power management, interconnect management, and physical layer tasks (e.g., universal serial bus (USB) functionality).

[0056] The system 200 may include sensors 232 (e.g., as a non-limiting example, an airflow sensor, a pressure sensor, a temperature sensor, a fuel sensor, a speed sensor, a voltage sensor, and / or a proximity sensor) receiving power from one or more of the DC-DC converters 228. The system 200 may include a motor driver 234 configured to drive one or more electric motors configured to convert electrical power into torque to rotate the wheels of a vehicle including the system 200. The motor driver 234 may receive power from one or more of the DC-DC converters 228.

[0057] In one or more embodiments, because the DC-DC converter 206 can be initially (e.g., at system 200 startup) powered by the LDO regulator 100 via the converter driver 208, the switching circuitry 116 can be initially configured to couple the output of the battery 204 to the input node (i.e., node 122) of the LDO regulator 100 to supply the voltage VHIGH. Subsequently, in response to determining that the DC-DC converter 206 has stabilized, the configuration of the switching circuitry 116 can be changed (e.g., by the control circuitry 140 and the cascode driver 144 turning off or otherwise ceasing conduction through the transistor 148) to couple the output of the DC-DC converter 206 to the input node of the LDO regulator 100 to supply the voltage VMED. In one or more embodiments, the output of the battery 204 can correspond to or can be coupled to the first voltage supply input (e.g., Figure 1 the high voltage supply input 118) of the LDO regulator 100. In one or more embodiments, the output of the DC-DC converter 206 can correspond to or can be coupled to the second voltage supply input (e.g., Figure 1 the medium voltage supply input 120) of the LDO regulator 100.

[0058] As described above, the switching circuitry 116 of the LDO regulator 100 can include cascode transistors coupled to the transfer transistor of the LDO regulator 100 in a cascode arrangement. The power dissipation in the LDO regulator 100 can be distributed among these transistors such that the LDO regulator 100 can better withstand adverse conditions, such as an unexpected short circuit from the output of the LDO regulator 100 to ground. Additionally, an LDO regulator 100 designed for a particular application can be simpler than a conventional regulator design, at least because the design of the LDO regulator 100 involves designing a single medium voltage error amplifier 102 (whereas a conventional regulator typically requires designing multiple error amplifiers, including a high voltage error amplifier to handle a high voltage supply), and involves designing a single set of current limiter circuitry 110 (whereas a conventional regulator typically requires a separate set of current protection circuitry for each voltage supply input). Compared to such conventional methods, using a single set of current limiter circuitry 110 and a single error amplifier 102 for multiple voltage supply inputs in the LDO regulator 100 can also achieve a beneficial reduction in the size and complexity of the LDO regulator 100.

[0059] The foregoing description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless stated otherwise explicitly, "connected" means that an element is directly joined to another element (or directly in communication with another element), and not necessarily in a mechanical manner. Similarly, unless stated otherwise explicitly, "coupled" means that an element is directly or indirectly joined to another element (or directly or indirectly in communication with another element), and not necessarily in a mechanical manner. Thus, although the schematic illustrations shown in the figures depict an exemplary arrangement of elements, additional intermediate elements, devices, features, or components may be present in one or more embodiments of the subject matter depicted. Further, unless otherwise noted, the term "amplifier" as used herein shall be understood to refer to a "power amplifier".

[0060] Although at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that a vast number of variations exist. It should also be understood that the (one or more) exemplary embodiments described herein are not intended to limit in any way the scope, applicability, or configuration of the claimed subject matter. Indeed, the foregoing detailed description will provide those skilled in the art with a convenient guide for implementing the described (one or more) embodiments. It should be understood that various changes may be made to the functionality and arrangement of the elements without departing from the scope defined by the claims, which scope includes known equivalents and foreseeable equivalents at the time of filing this patent application.

Claims

1. A voltage regulating circuit, characterized in that: include: an error amplifier configured to provide an error signal based on a comparison of a reference voltage and a voltage at a voltage divider coupled to an output node of the voltage regulation circuit; a pass transistor configured to selectively pass current from an input node to the output node based on the error signal; as well as a switching circuitry configured to selectively couple one of a first voltage supply input and a second voltage supply input to the input node, the switching circuitry comprising: a first branch coupled between the first voltage supply input and the input node, wherein the first branch includes a transistor coupled with the pass transistor in a cascode arrangement; as well as A second branch is coupled between the second voltage supply input and the input node.

2. The voltage regulating circuit according to claim 1, characterized in that: Also includes: a charge pump having an input coupled to the output node, wherein the charge pump is configured to generate a charge pump voltage; as well as A cascode driver is configured to receive the charge pump voltage and control an amount of current through the transistor of the first branch.

3. The voltage regulating circuit according to claim 2, characterized in that: Also includes: a first switch included in the first branch; a second switch included in the second branch; as well as One or more switch drivers coupled to the first switch and the second switch and configured to control the first switch and the second switch.

4. The voltage regulating circuit according to claim 2 or 3, characterized in that: The transistor of the first branch is a first nMOS power transistor having a first rated voltage, and the pass transistor is a second nMOS power transistor having a second rated voltage less than the first rated voltage.

5. The voltage regulating circuit according to claim 3 or 4, characterized in that: When the output node is at zero volts and the first voltage supply input is selected, the transistor of the first branch is configured to dissipate a majority of power in the voltage regulation circuit.

6. The voltage regulating circuit according to claim 5, characterized in that: When the output node is at zero volts and the second voltage supply input is selected, the pass transistor is configured to dissipate a majority of power in the voltage regulation circuit.

7. A voltage regulating circuit according to any preceding claim, characterised in that The first voltage supply input is configured to receive a first voltage, the second voltage supply input is configured to receive a second voltage, and the first voltage is greater than the second voltage.

8. A voltage regulating circuit according to any preceding claim, characterised in that Also includes: Current limiter circuitry is coupled to the gate of the pass transistor and is configured to limit current through the pass transistor.

9. A voltage regulating circuit according to any preceding claim, characterised in that The voltage regulation circuit is a low dropout LDO regulator.

10. A power management integrated circuit, characterized in that: include: Battery; a direct current (DC)-to-DC converter coupled to the battery; as well as A voltage regulating circuit as claimed in any preceding claim, wherein the first voltage supply input is the battery, and wherein the second voltage supply input is the DC-DC converter.

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