Low-power voltage regulator circuit based on low-voltage CMOS process devices

Abstract

The present invention relates to a low-power voltage regulator circuit based on a low-voltage CMOS process device. The circuit comprises: a bandgap reference for generating a reference voltage and applying the generated reference voltage to a voltage regulator; a voltage regulator for receiving the reference voltage and converting the received reference voltage into a target output voltage, wherein the voltage value of the target output voltage is greater than the voltage value of the reference voltage and the target output voltage is compatible with the highest voltage supported by the low-voltage CMOS process; and a load isolation circuit connected to the voltage regulator, applying the target output voltage to a connected load via the load isolation circuit, and isolating the connected load from the voltage regulator. While being compatible with advanced CMOS logic processes, the present invention can also meet the requirements of high-voltage operating scenarios such as 5V, achieving voltage resistance and level conversion functions with extremely low power consumption.

Description

Technical Field

[0001] The present invention relates to a voltage stabilizer circuit, in particular to a low-power voltage stabilizer circuit based on a low-voltage CMOS process device. Background Art

[0002] With the continuous upgrading of technology, in the current CMOS logic and radio frequency (RF) processes, 5V devices are gradually regarded as high-voltage devices. Foundries generally no longer provide corresponding 5V devices. For example, in CMOS RF processes below 55nm, the maximum supported devices are 3.3V. If 5V devices are required, the BCD (Bipolar-CMOS-DMOS) process is required. However, RF circuits require accurate device models. Therefore, the BCD process is not suitable for the research and development of RF chips.

[0003] Furthermore, in practical applications, chips are generally required to operate properly across a wide power supply voltage range. Therefore, in addition to the overall functional circuitry, an LDO (Low Dropout) regulator must be integrated within the chip to convert the high voltage of the external power supply to the low voltage required by other circuits. For low-voltage chips, the higher operating voltage of the LDO regulator makes it difficult for the LDO regulator to be controlled by other digital circuits within the chip. Therefore, once the chip is powered on, the LDO regulator must operate continuously, significantly increasing the chip's power consumption. In this case, reducing the chip's power consumption requires reducing the power consumption of the LDO regulator.

[0004] For working environments with higher working voltages, a common design solution is to use high-voltage devices, such as LDMOS devices. However, the use of high-voltage devices generally presents the following problems: In the CMOS process, multiple layers of additional masks are required when manufacturing high-voltage resistant devices, which greatly increases the chip area and results in higher power consumption.

[0005] Taking all factors into consideration, in actual application, the existing CMOS RF process conditions must also be compatible with working scenarios in specific 5V environments. Therefore, how to meet the requirements of high-voltage working scenarios such as 5V while effectively reducing power consumption is a technical problem that urgently needs to be solved. Summary of the Invention

[0006] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a low-power voltage regulator circuit based on low-voltage CMOS process devices. While being compatible with the continuously improving CMOS RF process, it can also meet the requirements of high-voltage working scenarios such as 5V, achieving both high-voltage operation and low power consumption.

[0007] According to the technical solution provided by the present invention, a low-power voltage regulator circuit based on a low-voltage CMOS process device is provided. The low-power voltage regulator circuit is manufactured based on a low-voltage CMOS logic process and can operate under a high-voltage power supply voltage. The low-power voltage regulator circuit includes:

[0008] A bandgap reference, used for generating a reference voltage and applying the generated reference voltage to a voltage regulator;

[0009] a voltage regulator receiving a reference voltage and converting the received reference voltage into a target output voltage, wherein a voltage value of the target output voltage is greater than a voltage value of the reference voltage and the target output voltage is adapted to a maximum voltage supported by a low-voltage CMOS process;

[0010] The load isolation circuit is connected to the voltage regulator, and applies the target output voltage to the connected load via the load isolation circuit, thereby isolating the connected load from the voltage regulator.

[0011] The high voltage power supply voltage is higher than the highest voltage supported by the low voltage CMOS logic process, and the voltage value of the high voltage power supply voltage is greater than the voltage value of the target output voltage;

[0012] The low-power voltage regulator circuit has no resistance device, and the bias current of the low-power voltage regulator circuit when working is at the nA level.

[0013] The bandgap reference includes a micro-current source, a linear negative temperature drift voltage generating circuit and a temperature drift compensation circuit connected in sequence, wherein:

[0014] The micro-current source generates a low-temperature drift reference current under a high-voltage power supply voltage, and loads the low-temperature drift reference current to a linear negative temperature drift voltage generating circuit;

[0015] The linear negative temperature drift voltage generating circuit generates a reference voltage that decreases linearly with temperature based on a low temperature drift reference current, and loads the reference voltage to the temperature drift compensation circuit;

[0016] The temperature drift compensation circuit is used to compensate for the temperature drift coefficient of the reference voltage to generate a reference voltage with low temperature drift after the temperature drift coefficient is compensated.

[0017] The micro-current source includes a current source matrix and a detection feedback control circuit adapted to be connected to the current source matrix, wherein:

[0018] The current source base generates a basic current at a high voltage supply voltage,

[0019] The detection feedback control circuit detects the basic current and performs feedback control on the current source matrix based on the detected basic current, so that the basic current generated by the current source matrix remains stable through feedback control, and a low-temperature drift reference current is formed based on the stable basic current.

[0020] The current source base includes a PMOS transistor M11 operating in a linear region and a basic current generating circuit adapted to be connected to the PMOS transistor M11, wherein:

[0021] The source terminal of the PMOS tube M11 is connected to the high voltage power supply voltage, the drain terminal of the PMOS tube M11 is connected to the basic current generating circuit, and the gate terminal of the PMOS tube M11 is connected to the output terminal of the detection feedback control circuit;

[0022] The detection feedback control circuit is further adaptively connected to the basic current generating circuit to obtain the basic current generated by the basic current generating circuit, and detects the obtained basic current and generates a feedback control voltage;

[0023] The detection feedback control circuit applies a feedback control voltage to the gate terminal of the PMOS transistor M11 to adjust the working state of the PMOS transistor M11 through the feedback control voltage, and keeps the basic current generated by the basic current generating circuit stable based on the working state of the PMOS transistor M11.

[0024] The detection feedback control circuit includes a feedback control main circuit and a voltage conversion branch, wherein:

[0025] The basic current generated by the basic current generating circuit is obtained through the feedback control main circuit, and the feedback control reference voltage corresponding to the basic current is generated through the voltage conversion branch.

[0026] The feedback control main circuit generates a feedback control voltage based on a feedback control reference voltage;

[0027] The feedback control main circuit includes a PMOS transistor M12, the source terminal of the PMOS transistor M12 is connected to the high-voltage power supply voltage, the gate terminal of the PMOS transistor M12 is adaptively connected to the basic current generation circuit, and the drain terminal of the PMOS transistor M12 is connected to the source terminal of the PMOS transistor M13 and the source terminal of the PMOS transistor M14;

[0028] The gate terminal of the PMOS tube M14 is connected to the voltage conversion branch.

[0029] The drain terminal of the PMOS transistor M14 is connected to the drain terminal of the NMOS transistor M16, the gate terminal of the NMOS transistor M16, the gate terminal of the NMOS transistor M15, the drain terminal of the NMOS transistor M15, the drain terminal of the PMOS transistor M13, and the gate terminal of the PMOS transistor M13 to form a feedback control output terminal connected to the gate terminal of the PMOS transistor M11, and is connected to the gate terminal of the PMOS transistor M11 through the feedback control output terminal;

[0030] The source terminal of the NMOS transistor M15 is connected to the drain terminal of the NMOS transistor M17, and the gate terminal of the NMOS transistor M17 is connected to the gate terminal of the NMOS transistor M18, the drain terminal of the NMOS transistor M18, and the source terminal of the NMOS transistor M16;

[0031] The source terminal of the NMOS transistor M17 is connected to the drain terminal of the NMOS transistor M19, and the gate terminal of the NMOS transistor M19 is connected to the gate terminal of the NMOS transistor M20, the drain terminal of the NMOS transistor M20, and the source terminal of the NMOS transistor M18;

[0032] The source terminal of the NMOS transistor M19 and the source terminal of the NMOS transistor M20 are both grounded.

[0033] The temperature drift compensation circuit includes a plurality of temperature drift compensation units connected in cascade, wherein:

[0034] Each level of temperature drift compensation unit can generate a voltage difference with the same temperature coefficient, so that the temperature drift coefficient of the reference voltage can be effectively compensated through multiple cascaded temperature drift compensation units.

[0035] The temperature drift compensation unit at least includes a temperature drift compensation PMOS current mirror unit and a temperature drift compensation NMOS differential pair tube unit, wherein:

[0036] The temperature drift compensation PMOS current mirror unit is connected to the high voltage power supply voltage and is adaptively connected to the temperature drift compensation NMOS differential pair tube unit;

[0037] The temperature drift compensation NMOS differential pair tube unit at least includes a temperature drift compensation NMOS differential input tube, a temperature drift compensation NMOS differential output tube and a temperature drift compensation NMOS control tube;

[0038] The drain terminals of the temperature drift compensation NMOS differential input tube and the temperature drift compensation NMOS differential output tube and the gate terminal of the temperature drift compensation NMOS differential output terminal are adaptively connected to the temperature drift compensation PMOS current mirror unit.

[0039] The source end of the temperature drift compensation NMOS differential input tube and the source end of the temperature drift compensation NMOS differential output tube are both connected to the drain end of the temperature drift compensation NMOS control tube, the source end of the temperature drift compensation NMOS control tube is grounded, and the gate terminal of the temperature drift compensation NMOS control tube is connected to the bias voltage VBN1;

[0040] When the temperature drift compensation units are cascaded, the gate terminal of the temperature drift compensation NMOS differential input tube is connected to the gate terminal of the temperature drift compensation NMOS differential output tube in the previous stage temperature drift compensation unit;

[0041] The gate end of the temperature drift compensation NMOS differential output end is connected to the temperature drift compensation NMOS differential input tube in the next stage temperature drift compensation unit, and outputs a zero temperature drift reference voltage through the gate end of the temperature drift compensation NMOS differential output tube in the last stage temperature drift compensation unit.

[0042] The voltage regulator includes an operational amplifier circuit, a voltage-stabilized bias current circuit, a voltage-stabilized current mirror circuit, and a voltage-stabilized conversion feedback circuit, wherein:

[0043] The first input terminal of the operational amplifier circuit receives a reference voltage, the second input terminal of the operational amplifier circuit is adaptively connected to the voltage stabilization conversion feedback circuit, and the voltage stabilization bias current circuit provides the operational amplifier bias current required for the operation of the operational amplifier circuit;

[0044] The output end of the operational amplifier circuit is connected to the voltage-stabilized conversion feedback circuit through a voltage-stabilized current mirror circuit, so as to load a voltage conversion reference current to the voltage-stabilized conversion feedback circuit through the voltage-stabilized current mirror circuit;

[0045] Based on the voltage conversion reference current, the voltage stabilizing conversion feedback circuit generates a target output voltage and loads a conversion sampling voltage to the second input terminal of the operational amplifier circuit, so that the operational amplifier circuit loads a stable voltage conversion reference current to the voltage stabilizing conversion feedback circuit through the voltage stabilizing current mirror circuit, and the target output voltage generated by the voltage stabilizing conversion feedback circuit remains stable.

[0046] The operational amplifier circuit includes a PMOS tube M56, wherein:

[0047] The gate terminal and source terminal of the PMOS transistor M56 are adaptively connected to the voltage-stabilizing bias current circuit. The drain terminal of the PMOS transistor M56 is connected to the source terminal of the PMOS transistor M57 and the source terminal of the PMOS transistor M58. The gate terminal of the PMOS transistor M57 forms the first input terminal of the operational amplifier circuit, and the gate terminal of the PMOS transistor M58 serves as the second input terminal of the operational amplifier circuit.

[0048] The drain terminal of the PMOS transistor M57 is connected to the drain terminal of the NMOS transistor M59, the gate terminal of the NMOS transistor M59, and the gate terminal of the NMOS transistor M60. The drain terminal of the NMOS transistor M60 is connected to the drain terminal of the PMOS transistor M58. The drain terminal of the NMOS transistor M60 and the drain terminal of the PMOS transistor M58 are connected to each other to form the output terminal of the operational amplifier circuit.

[0049] The source terminal of the NMOS transistor M59 and the source terminal of the NMOS transistor M60 are both grounded.

[0050] The voltage stabilization conversion feedback circuit includes a plurality of MOS impedance units connected in series, wherein:

[0051] The series-connected MOS units include at least one MOS impedance unit formed by an NMOS transistor group and at least one MOS impedance unit formed by a PMOS transistor group;

[0052] The voltage-stabilized current mirror circuit is adaptively connected to a MOS impedance unit formed by an NMOS tube group, and outputs a target output voltage through the MOS impedance unit;

[0053] The voltage stabilizing conversion feedback circuit is connected to the second input terminal of the operational amplifier circuit through a MOS impedance unit formed by a PMOS tube group;

[0054] When the MOS impedance unit is formed by the NMOS tube group, the NMOS tubes in the NMOS tube group are all configured in a diode connection state to form an NMOS-diode unit, and the NMOS-diode units are connected in series in sequence;

[0055] When the MOS impedance unit is formed by the PMOS tube group, the PMOS tubes in the PMOS tube group are all configured in a diode connection state to form a PMOS-diode unit, and the PMOS-diode units are connected in series in sequence;

[0056] The NMOS tubes in the NMOS tube group and the PMOS tubes in the PMOS tube group are both inverse ratio tubes, and both the NMOS tubes and the PMOS tubes are MOS tubes with longer conductive channels.

[0057] The present invention has the advantages of using a low-voltage CMOS process to manufacture the bandgap reference, voltage regulator, and load isolation circuit, and no resistor devices are used in the bandgap reference, voltage regulator, and load isolation circuit. This makes it compatible with existing CMOS RF processes and can reduce chip area and power consumption.

[0058] A bandgap reference is used to provide a reference voltage, and the voltage regulator generates a target power supply based on the reference voltage. The load isolation circuit can achieve isolation between the voltage regulator and the load. During operation, the bandgap reference, voltage regulator, and load isolation circuit can all operate under a high-voltage power supply voltage, and adapt the target output voltage to the highest voltage supported by the low-voltage CMOS process, thereby meeting high-voltage operating scenarios such as 5V. Without using resistor devices, the circuit design of the bandgap reference, voltage regulator, and load isolation circuit can make the bias current during operation at the nA level, which can effectively reduce the power consumption of the voltage regulator circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 The figure is a circuit block diagram of an embodiment of a low-power voltage regulator circuit of the present invention.

[0060] Figure 2 This is a circuit diagram of an embodiment of the bandgap reference of the present invention.

[0061] Figure 3 This is a circuit diagram of an embodiment of a voltage stabilizer of the present invention. DETAILED DESCRIPTION

[0062] The present invention will be further described below with reference to specific drawings and embodiments.

[0063] In order to meet the requirements of high-voltage operating scenarios such as 5V and effectively reduce power consumption while being compatible with existing CMOS logic and radio frequency processes, the present invention provides a low-power voltage regulator circuit based on low-voltage CMOS process devices. Specifically, the low-power voltage regulator circuit is prepared based on a low-voltage CMOS logic process and can operate under a high-voltage power supply voltage. The low-power voltage regulator circuit includes:

[0064] A bandgap reference, used for generating a reference voltage and applying the generated reference voltage to a voltage regulator;

[0065] a voltage regulator receiving a reference voltage and converting the received reference voltage into a target output voltage, wherein a voltage value of the target output voltage is greater than a voltage value of the reference voltage and the target output voltage is adapted to a maximum voltage supported by a low-voltage CMOS process;

[0066] The load isolation circuit is connected to the voltage regulator, and applies the target output voltage to the connected load via the load isolation circuit, thereby isolating the connected load from the voltage regulator.

[0067] It should be noted that the low-power voltage-stabilizing circuit of the present invention can be prepared using the existing CMOS logic process, that is, the low-power voltage-stabilizing circuit of the present invention can be compatible with the existing CMOS RF process (CMOS logic and radio frequency process) during preparation. Specifically, while being compatible with the existing CMOS RF process, the method of preparing the low-power voltage-stabilizing circuit can be consistent with the existing technology. As can be seen from the background technology description, the CMOS RF process is a low-voltage logic development process. With the continuous upgrading of the current process, the maximum voltage supported by the CMOSRF process generally does not exceed 3.3V. Therefore, the low-power voltage-stabilizing circuit of the present invention can operate under a high-voltage power supply voltage, specifically referring to a voltage value of the high-voltage power supply voltage that is higher than the maximum voltage supported by the low-voltage CMOS process. For example, the voltage value of the high-voltage power supply voltage can be the 5V mentioned above. Figure 1 、 Figure 2 and Figure 3 middle, V DD That is the high voltage power supply voltage, that is Figures 1 to 3 Voltage in V DDSpecifically, when the low-power voltage regulator circuit can work under the high-voltage power supply voltage, that is, the low-power voltage regulator circuit of the present invention can meet the requirements of the 5V high-voltage working scenario.

[0068] Figure 1 An embodiment of the low-power voltage regulator circuit of the present invention is shown in the figure. As can be seen from the figure, the low-power voltage regulator circuit of the present invention may include at least a bandgap reference, a voltage regulator and a load isolation circuit. It should be understood that the bandgap reference, the voltage regulator and the load isolation circuit should all be prepared using a low-voltage CMOS RF process. Specifically, when operating under a high-voltage power supply voltage, the bandgap reference can generate a reference voltage, and the voltage regulator can convert the reference voltage into a target output voltage. Generally, the voltage value of the reference voltage is lower than the target output voltage, and the target output voltage should be compatible with the maximum voltage supported by the low-voltage CMOS process. Among them, the target output voltage is compatible with the maximum voltage supported by the low-voltage CMOS process, which specifically means that the target output voltage is not higher than the maximum voltage supported by the low-voltage CMOS RF process. As can be seen from the above description, when the maximum voltage supported by the low-voltage CMOS process can be 3.3V, at this time, the target output voltage should not exceed 3.3V.

[0069] From the above description, it can be seen that the voltage value of the high voltage power supply voltage can be 5V, and the voltage value of the target output voltage can be 3.3V. Therefore, in general, the voltage value of the high voltage power supply voltage is greater than the voltage value of the target output voltage.

[0070] It can be seen from the above description that when resistor devices are used, the chip / circuit area will be large and the power consumption will increase. Therefore, in order to achieve the purpose of low power consumption, in one embodiment of the present invention, there is no resistor device in the low-power regulator circuit, and the bias current of the low-power regulator circuit during operation is at the nA level.

[0071] It is understandable that the low power consumption voltage stabilizing circuit of the present invention does not contain any resistor device, that is, the low power consumption voltage stabilizing circuit is designed without using any resistor device. In this case, there is no resistor device in the bandgap reference, the voltage regulator, and the load isolation circuit.

[0072] In addition, in order to further reduce power consumption, the bias current of the low-power regulator circuit can be made into nA level when it is working. Since the working circuit of the low-power regulator circuit is small, the regulator responds slowly to load changes. Therefore, in order to prevent the influence of load changes on the regulator, the present invention can load the target output voltage to the load connected to the load isolation circuit through the load isolation circuit, and the regulator and the load can be isolated through the load isolation circuit.

[0073] Figure 1FIG1 shows an embodiment of the load isolation circuit of the present invention. In the figure, the load isolation circuit includes an NMOS transistor MN1. At this time, the gate terminal of the NMOS transistor MN1 is connected to the output terminal of the regulator, and the drain terminal of the NMOS transistor MN1 is connected to the voltage regulator. V DD Connect, the source terminal of NMOS tube MN1 is connected to the load, Figure 1 In the example, the low-voltage output voltage outputted by the source terminal of NMOS transistor MN1 is the target output voltage mentioned above. It is understood that the load isolation circuit can also adopt other forms, specifically those that can meet the operating current of the nanoampere level and avoid the impact of load conversion on the voltage regulator. Examples are not given here one by one.

[0074] In one embodiment of the present invention, the bandgap reference includes a micro-current source, a linear negative temperature drift voltage generating circuit, and a temperature drift compensation circuit connected in sequence, wherein:

[0075] The micro-current source generates a low-temperature drift reference current under a high-voltage power supply voltage, and loads the low-temperature drift reference current to a linear negative temperature drift voltage generating circuit;

[0076] The linear negative temperature drift voltage generating circuit generates a reference voltage that decreases linearly with temperature based on a low temperature drift reference current, and loads the reference voltage to the temperature drift compensation circuit;

[0077] The temperature drift compensation circuit is used to compensate for the temperature drift coefficient of the reference voltage to generate a reference voltage with low temperature drift after the temperature drift coefficient is compensated.

[0078] In order to generate a reference voltage under a high-voltage power supply voltage, in one embodiment of the present invention, the bandgap reference may include a micro-current source, a linear negative temperature drift voltage generating circuit, and a temperature drift compensation circuit connected in sequence, wherein a low-temperature drift reference current can be generated by the micro-current source. The generated low-temperature drift reference current specifically means that the current is less affected by the external high-voltage power supply voltage and temperature changes; the low-temperature drift reference current can be converted into a reference voltage that decreases linearly with temperature by the linear negative temperature drift voltage generating circuit. The reference voltage decreases linearly with temperature, specifically means that when the temperature rises, the reference voltage decreases linearly.

[0079] Since the reference voltage has a negative temperature characteristic, in order to obtain a reference voltage with low temperature drift, the present invention can use a temperature compensation circuit to compensate the temperature coefficient of the reference voltage, so that a reference voltage with low temperature drift can be generated after the temperature coefficient compensation. The generation of a reference voltage with low temperature drift specifically means that the reference voltage is less affected by the external high voltage power supply voltage and temperature, thereby providing a stable reference voltage for the voltage regulator.

[0080] In one embodiment of the present invention, the micro-current source includes a current source substrate and a detection feedback control circuit adapted to be connected to the current source substrate, wherein:

[0081] The current source base generates a basic current at a high voltage supply voltage,

[0082] The detection feedback control circuit detects the basic current and performs feedback control on the current source matrix based on the detected basic current, so that the basic current generated by the current source matrix remains stable through feedback control, and a low-temperature drift reference current is formed based on the stable basic current.

[0083] To generate a low-temperature drift reference current, a microcurrent source may include a current source substrate and a detection feedback control circuit. The current source substrate may be used to generate a base current. The detection feedback control circuit may provide feedback control over the base current generated by the current source substrate, thereby maintaining a stable base current generated by the current source substrate. This stable base current may then be used to generate a low-temperature drift reference current. As can be seen from the above description, maintaining a stable base current specifically means that the base current is less affected by the external high-voltage power supply voltage and temperature.

[0084] In one embodiment of the present invention, the current source substrate includes a PMOS transistor M11 operating in a linear region and a basic current generating circuit adaptively connected to the PMOS transistor M11, wherein:

[0085] The source terminal of the PMOS tube M11 is connected to the high voltage power supply voltage, the drain terminal of the PMOS tube M11 is connected to the basic current generating circuit, and the gate terminal of the PMOS tube M11 is connected to the output terminal of the detection feedback control circuit;

[0086] The detection feedback control circuit is further adaptively connected to the basic current generating circuit to obtain the basic current generated by the basic current generating circuit, and detects the obtained basic current and generates a feedback control voltage;

[0087] The detection feedback control circuit applies a feedback control voltage to the gate terminal of the PMOS transistor M11 to adjust the working state of the PMOS transistor M11 through the feedback control voltage, and keeps the basic current generated by the basic current generating circuit stable based on the working state of the PMOS transistor M11.

[0088] Figure 2 An embodiment of the bandgap reference of the present invention is shown in FIG. Figure 2As can be seen from the embodiment shown in the figure, the current source substrate should include at least a PMOS transistor M11 and a basic current generating circuit. In order to meet the low-temperature drift reference current generated by the micro-current source, the PMOS transistor M11 should be operated in the linear region, that is, the PMOS transistor M11 can be used as a linear resistor. The method of configuring the PMOS transistor M11 to operate in the linear region can be consistent with the existing technology and will not be repeated here. The basic current generating circuit can generate a basic current. During feedback control, the feedback control circuit should obtain the basic current and generate a feedback control voltage based on the basic current. The feedback control voltage is used to adjust the operating state of the PMOS transistor M11, thereby maintaining the basic current generated by the basic current generating circuit.

[0089] Figure 2 An embodiment of a basic current generating circuit is shown in FIG. As can be seen from the figure, the basic current generating circuit includes an NMOS transistor M1, an NMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, a PMOS transistor M5, a PMOS transistor M6, a PMOS transistor M7, a PMOS transistor M8, a PMOS transistor M9, and a PMOS transistor M10, wherein:

[0090] The source terminal voltage of PMOS tube M9 V DD The gate electrode of the PMOS transistor M9 and the gate terminal of the PMOS transistor M10 are both connected to the detection feedback control circuit, the source terminal of the PMOS transistor M10 is connected to the drain terminal of the PMOS transistor M11, and in addition, the gate terminal of the PMOS transistor M9 and the gate terminal of the PMOS transistor M10 are also connected to the drain terminal of the PMOS transistor M9 and the source terminal of the PMOS transistor M7, and the drain terminal of the PMOS transistor M10 is connected to the source terminal of the PMOS transistor M8;

[0091] The gate terminal of the PMOS transistor M7 is connected to the gate terminal of the PMOS transistor M8, the drain terminal of the PMOS transistor M7, and the source terminal of the PMOS transistor M5. The gate terminal of the PMOS transistor M5 is connected to the drain terminal of the PMOS transistor M5 and the drain terminal of the NMOS transistor M3. The drain terminal of the PMOS transistor M8 is connected to the source terminal of the PMOS transistor M6. The gate terminal of the PMOS transistor M6 is connected to the drain terminal of the PMOS transistor M6, the gate terminal of the NMOS transistor M3, the gate terminal of the NMOS transistor M4, and the drain terminal of the NMOS transistor M4.

[0092] The source terminal of the NMOS transistor M4 is connected to the gate terminal of the NMOS transistor M1, the drain terminal of the NMOS transistor M2, and the gate terminal of the NMOS transistor M2. The source terminal of the NMOS transistor M1 and the source terminal of the NMOS transistor M2 are both grounded. The gate terminal of the NMOS transistor M1 and the gate terminal of the NMOS transistor M2 both receive a bias voltage VBN1. The gate terminal of the NMOS transistor M3 and the gate terminal of the NMOS transistor M4 both receive a bias voltage VBN2.

[0093] It should be noted that bias voltages VBN1 and VBN2 can be generated using existing bias circuits. NMOS transistors M1 and M2 form a current mirror, NMOS transistors M3 and M4 form a current mirror, PMOS transistors M5 and M6 form a diode connection, PMOS transistors M7 and M8 form a current mirror, and PMOS transistors M9 and M10 also form a current mirror. Specifically, during operation, NMOS transistors M2 to M4 and PMOS transistors M5 to M8 can all generate a voltage drop, that is, they can all achieve voltage division, thereby preventing overvoltage from breaking down the MOS transistors used in the low-power voltage-stabilizing circuit of the present invention. In addition, the current source matrix can also adopt other forms, specifically based on the ability to achieve the above-mentioned basic current generation and stabilize the basic current through feedback control. Examples are not given here one by one.

[0094] In one embodiment of the present invention, the detection feedback control circuit includes a feedback control main circuit and a voltage conversion branch, wherein:

[0095] The basic current generated by the basic current generating circuit is obtained through the feedback control main circuit, and the feedback control reference voltage corresponding to the basic current is generated through the voltage conversion branch.

[0096] The feedback control main circuit generates a feedback control voltage based on a feedback control reference voltage;

[0097] The feedback control main circuit includes a PMOS transistor M12, the source terminal of the PMOS transistor M12 is connected to the high-voltage power supply voltage, the gate terminal of the PMOS transistor M12 is adaptively connected to the basic current generation circuit, and the drain terminal of the PMOS transistor M12 is connected to the source terminal of the PMOS transistor M13 and the source terminal of the PMOS transistor M14;

[0098] The gate terminal of the PMOS tube M14 is connected to the voltage conversion branch.

[0099] The drain terminal of the PMOS transistor M14 is connected to the drain terminal of the NMOS transistor M16, the gate terminal of the NMOS transistor M16, the gate terminal of the NMOS transistor M15, the drain terminal of the NMOS transistor M15, the drain terminal of the PMOS transistor M13, and the gate terminal of the PMOS transistor M13 to form a feedback control output terminal connected to the gate terminal of the PMOS transistor M11, and is connected to the gate terminal of the PMOS transistor M11 through the feedback control output terminal;

[0100] The source terminal of the NMOS transistor M15 is connected to the drain terminal of the NMOS transistor M17, and the gate terminal of the NMOS transistor M17 is connected to the gate terminal of the NMOS transistor M18, the drain terminal of the NMOS transistor M18, and the source terminal of the NMOS transistor M16;

[0101] The source terminal of the NMOS transistor M17 is connected to the drain terminal of the NMOS transistor M19, and the gate terminal of the NMOS transistor M19 is connected to the gate terminal of the NMOS transistor M20, the drain terminal of the NMOS transistor M20, and the source terminal of the NMOS transistor M18;

[0102] The source terminal of the NMOS transistor M19 and the source terminal of the NMOS transistor M20 are both grounded.

[0103] Figure 2 An embodiment of the detection feedback control circuit is shown in FIG. Figure 2 It can be seen that when the gate terminal of the PMOS transistor M12 is adaptively connected to the basic current generating circuit, it specifically means that at least the gate terminal of the PMOS transistor M12 is connected to the gate terminal of the PMOS transistor M9 and the gate terminal of the PMOS transistor M10.

[0104] Figure 2 An embodiment of a voltage conversion branch is also shown in FIG. As can be seen from the figure, the voltage conversion branch may include a PMOS tube M23, an NMOS tube M21, and an NMOS tube M21, wherein the source terminal of the PMOS tube M23 is connected to the voltage V DD The gate terminal of the PMOS transistor M23, the drain terminal of the PMOS transistor M23, and the drain terminal of the NMOS transistor M22 are all connected to the gate terminal of the PMOS transistor M14. The source terminal of the NMOS transistor M22 is connected to the drain terminal of the NMOS transistor M21. The source terminal of the NMOS transistor M21 is grounded. The gate terminal of the NMOS transistor M22 is connected to the bias voltage VBN2, and the gate terminal of the NMOS transistor M21 is connected to the bias voltage VBN1. Specifically, when the NMOS transistor M21 is turned on at the bias voltage VBN1 and the NMOS transistor M22 is turned on at the bias voltage VBN2, a feedback control reference voltage corresponding to the basic current can be generated by the PMOS transistor M23.

[0105] In a specific implementation, NMOS transistors M19 and M20 form a current mirror, and NMOS transistors M17 and M18 also form a current mirror. Furthermore, PMOS transistors M13 and M14 form a differential pair. Generally, PMOS transistors M13 and M14 should be of different sizes. This means that an asymmetric differential pair can be formed based on the PMOS transistors M13 and M14. Consequently, when the feedback control main circuit is connected to the gate terminal of PMOS transistor M11, a negative feedback connection can be formed. Based on the asymmetric differential pair, a feedback control voltage can be generated based on a feedback control reference voltage. Furthermore, during operation, a voltage drop can be generated across PMOS transistors M15, M16, NMOS transistors M17, and M18, thereby achieving voltage division and withstand voltage protection.

[0106] Furthermore, Figure 2 An embodiment of a linear negative temperature drift voltage generating circuit is also shown. As shown in the figure, the linear negative temperature drift voltage generating circuit may include a PMOS transistor M24, a PMOS transistor M25, a PMOS transistor M26, a PMOS transistor M27 and a PNP transistor Q1, wherein:

[0107] The source terminal voltage of PMOS tube M24 V DD The gate terminal of the PMOS transistor M24 should be connected to at least the gate terminal of the PMOS transistor M9 and the gate terminal of the PMOS transistor M10, the drain terminal of the PMOS transistor M24 should be connected to the source terminal of the PMOS transistor M25, the gate terminal and the drain terminal of the PMOS transistor M25 should be connected to the source terminal of the PMOS transistor M26, and the gate terminal and the drain terminal of the PMOS transistor M26 should be connected to the source terminal of the PMOS transistor M27;

[0108] The gate terminal and the drain terminal of the PMOS transistor M27 are connected to the emitter terminal of the PNP transistor Q1 to form a linear negative temperature drift voltage output terminal. The base terminal and the collector terminal of the PNP transistor Q1 are both grounded.

[0109] Specifically, a reference voltage can be loaded into the temperature drift compensation circuit via the linear negative temperature drift voltage output terminal. For the aforementioned linear negative temperature drift voltage generation circuit, the PMOS transistor M24 can form a current mirror with the PMOS transistor M9 and the PMOS transistor M10 to mirror the generated low-temperature drift reference circuit to the linear negative temperature drift voltage generation circuit. The PMOS transistors M25, M26, and M27 are all in a diode connection mode. A large voltage drop can be generated through the PMOS transistors M25 to M27 to prevent overvoltage from breaking down the MOS transistors within the low-power voltage regulator of the present invention. Furthermore, the voltage drop across the PMOS transistors M25 to M27 can generate a reference voltage that decreases linearly with temperature at the emitter end of the PNP transistor Q1.

[0110] In one embodiment of the present invention, the temperature drift compensation circuit includes a plurality of temperature drift compensation units connected in cascade, wherein:

[0111] Each level of temperature drift compensation unit can generate a voltage difference with the same temperature coefficient, so that the temperature drift coefficient of the reference voltage can be effectively compensated through multiple cascaded temperature drift compensation units.

[0112] The temperature drift compensation unit at least includes a temperature drift compensation PMOS current mirror unit and a temperature drift compensation NMOS differential pair tube unit, wherein:

[0113] The temperature drift compensation PMOS current mirror unit is connected to the high voltage power supply voltage and is adaptively connected to the temperature drift compensation NMOS differential pair tube unit;

[0114] The temperature drift compensation NMOS differential pair tube unit at least includes a temperature drift compensation NMOS differential input tube, a temperature drift compensation NMOS differential output tube and a temperature drift compensation NMOS control tube;

[0115] The drain terminals of the temperature drift compensation NMOS differential input tube and the temperature drift compensation NMOS differential output tube and the gate terminal of the temperature drift compensation NMOS differential output terminal are adaptively connected to the temperature drift compensation PMOS current mirror unit.

[0116] The source end of the temperature drift compensation NMOS differential input tube and the source end of the temperature drift compensation NMOS differential output tube are both connected to the drain end of the temperature drift compensation NMOS control tube, the source end of the temperature drift compensation NMOS control tube is grounded, and the gate terminal of the temperature drift compensation NMOS control tube is connected to the bias voltage VBN1;

[0117] When the temperature drift compensation units are cascaded, the gate terminal of the temperature drift compensation NMOS differential input tube is connected to the gate terminal of the temperature drift compensation NMOS differential output tube in the previous stage temperature drift compensation unit;

[0118] The gate end of the temperature drift compensation NMOS differential output end is connected to the temperature drift compensation NMOS differential input tube in the next stage temperature drift compensation unit, and outputs a zero temperature drift reference voltage through the gate end of the temperature drift compensation NMOS differential output tube in the last stage temperature drift compensation unit.

[0119] In order to compensate for the temperature drift coefficient of the reference voltage, the temperature drift compensation circuit may include multiple temperature drift compensation units, and the multiple temperature drift compensation units are connected in a cascade manner, wherein each level of temperature compensation unit can generate a voltage difference with the same temperature coefficient, the temperature coefficient of the generated voltage difference is opposite to the temperature coefficient of the reference voltage, and the difference in the voltage difference generated by each level of temperature compensation unit is equal. Therefore, in a specific implementation, the number of temperature drift compensation units in a cascade state in the temperature drift compensation circuit can be determined according to the temperature coefficient of the reference voltage, that is, the number of temperature drift compensation units in a cascade state should be based on the ability to effectively compensate for the temperature drift coefficient of the reference voltage, wherein effectively compensating for the temperature drift coefficient of the reference voltage specifically refers to the ability to generate a reference voltage with low temperature drift, such as a reference voltage with low temperature drift can be a reference voltage with zero temperature drift.

[0120] In a specific implementation, when the temperature drift compensation unit is connected in cascade, the temperature drift compensation unit in the temperature drift compensation circuit preferably adopts the same circuit form. Specifically, the temperature drift compensation unit may include a temperature drift compensation PMOS current mirror unit and a temperature drift compensation NMOS differential pair tube unit, wherein the temperature drift compensation PMOS current mirror unit is connected to the high voltage power supply voltage and is adaptively connected to the temperature drift compensation NMOS differential pair tube unit.

[0121] It can be understood that after multiple temperature drift compensation units are cascaded, there are first-stage temperature drift compensation units and last-stage temperature drift compensation units, wherein the first-stage temperature drift compensation unit is the temperature drift compensation unit connected to the linear negative temperature drift voltage generating circuit, the last-stage temperature drift compensation unit is the temperature drift compensation unit that outputs the reference voltage, and the temperature drift compensation units of other stages are cascaded correspondingly to the temperature drift compensation units of the previous stage and the temperature drift compensation units of the next stage.

[0122] Figure 2 An embodiment of a temperature drift compensation circuit is shown in FIG. , and it can be seen from the figure that Figure 2 The temperature drift compensation circuit includes at least the first-stage temperature drift compensation unit, the second-stage temperature drift compensation unit and the last-stage temperature drift compensation unit. Figure 2 The temperature drift compensation unit is described in detail. Specifically,

[0123] For the first-stage temperature drift compensation unit, the temperature drift compensation PMOS current mirror unit includes at least PMOS tube M31, PMOS tube M32, PMOS tube M33 and PMOS tube M34, NMOS tube M29 forms a temperature drift compensation NMOS differential input tube, NMOS tube M30 forms a temperature drift compensation NMOS differential output tube, and NMOS tube M28 forms a temperature drift compensation NMOS control tube, wherein,

[0124] The source terminals of the PMOS tube M33 and the PMOS tube M34 are both connected to the voltage V DD The gate terminal of the PMOS transistor M33 is connected to the gate terminal of the PMOS transistor M34, the drain terminal of the PMOS transistor M33, and the source terminal of the PMOS transistor M31. The drain terminal of the PMOS transistor M34 is connected to the source terminal of the PMOS transistor M32. The gate terminal of the PMOS transistor M31 is connected to the drain terminal of the PMOS transistor M31 and the drain terminal of the NMOS transistor M29. The gate terminal of the NMOS transistor M29 is connected to the linear negative temperature drift voltage output terminal. The source terminal of the NMOS transistor M29 is connected to the drain terminal of the NMOS transistor M28.

[0125] The gate terminal of the PMOS transistor M32 is connected to the drain terminal of the PMOS transistor M32, the drain terminal of the NMOS transistor M30, and the gate terminal of the NMOS transistor M30. The source terminal of the NMOS transistor M30 is connected to the drain terminal of the NMOS transistor M28. The gate terminal of the NMOS transistor M30 is also connected to the gate terminal of the NMOS transistor M37 in the second-stage temperature drift compensation unit. The source terminal of the NMOS transistor M28 is grounded.

[0126] For the second-stage temperature drift compensation unit, the temperature drift compensation PMOS current mirror unit includes at least PMOS tube M38, PMOS tube M39, PMOS tube M40 and PMOS tube M41, NMOS tube M37 forms a temperature drift compensation NMOS differential input tube, NMOS tube M36 forms a temperature drift compensation NMOS differential output tube, and NMOS tube M35 forms a temperature drift compensation NMOS control tube, wherein,

[0127] The source terminals of the PMOS transistor M40 and the PMOS transistor M41 are both connected to the voltage V DD The gate terminal of the PMOS transistor M40 is connected to the gate terminal of the PMOS transistor M41, the drain terminal of the PMOS transistor M40, and the source terminal of the PMOS transistor M39. The drain terminal of the PMOS transistor M41 is connected to the source terminal of the PMOS transistor M38. The gate terminal of the PMOS transistor M39 is connected to the drain terminal of the PMOS transistor M39 and the drain terminal of the NMOS transistor M37. The gate terminal of the NMOS transistor M37 is connected to at least the gate terminal of the NMOS transistor M30. The source terminal of the NMOS transistor M37 is connected to the drain terminal of the NMOS transistor M35.

[0128] The gate terminal of the PMOS transistor M38 is connected to the drain terminal of the PMOS transistor M38, the drain terminal of the NMOS transistor M36, and the gate terminal of the NMOS transistor M36. The source terminal of the NMOS transistor M36 is connected to the drain terminal of the NMOS transistor M35. The gate terminal of the NMOS transistor M36 is also connected to the gate terminal of the temperature drift compensation NMOS differential input transistor in the third-stage temperature drift compensation unit. The source terminal of the NMOS transistor M35 is grounded.

[0129] For the temperature drift compensation unit of the last stage, the temperature drift compensation PMOS current mirror unit includes at least PMOS tube M45, PMOS tube M46, PMOS tube M47 and PMOS tube M48, NMOS tube M44 forms a temperature drift compensation NMOS differential input tube, NMOS tube M43 forms a temperature drift compensation NMOS differential output tube, and NMOS tube M42 forms a temperature drift compensation NMOS control tube, wherein,

[0130] The source terminals of the PMOS tube M47 and the PMOS tube M48 are both connected to the voltage V DDThe gate terminal of the PMOS transistor M47 is connected to the gate terminal of the PMOS transistor M48, the drain terminal of the PMOS transistor M47, and the source terminal of the PMOS transistor M46. The drain terminal of the PMOS transistor M48 is connected to the source terminal of the PMOS transistor M45. The gate terminal of the PMOS transistor M46 is connected to the drain terminal of the PMOS transistor M46 and the drain terminal of the NMOS transistor M44. The gate terminal of the NMOS transistor M44 is connected to the gate terminal of the temperature drift compensation NMOS differential output transistor in the previous stage temperature drift compensation unit. The source terminal of the NMOS transistor M44 is connected to the drain terminal of the NMOS transistor M42.

[0131] The gate terminal of the PMOS transistor M45 is connected to the drain terminal of the PMOS transistor M45, the drain terminal of the NMOS transistor M43, and the gate terminal of the NMOS transistor M43. The source terminal of the NMOS transistor M43 is connected to the drain terminal of the NMOS transistor M42. The source terminal of the NMOS transistor M42 is grounded. The gate terminal of the NMOS transistor M43 also serves as the output terminal of the entire temperature drift compensation circuit. That is, a zero temperature drift reference voltage can be output through the gate terminal of the NMOS transistor M43. Figure 2 The VOUT1 in the figure is the reference voltage with zero temperature drift.

[0132] It can be understood that when the temperature drift compensation circuit has only three cascaded temperature drift compensation units, the temperature drift compensation unit of the third stage is the temperature drift compensation unit of the last stage. At this time, the gate terminal of the NMOS tube M44 should be connected to the gate terminal of the NMOS tube M36. In other cases, please refer to the above description, and no examples will be given here one by one.

[0133] In one embodiment of the present invention, the voltage regulator includes an operational amplifier circuit, a voltage-regulated bias current circuit, a voltage-regulated current mirror circuit, and a voltage-regulated conversion feedback circuit, wherein:

[0134] The first input terminal of the operational amplifier circuit receives a reference voltage, the second input terminal of the operational amplifier circuit is adaptively connected to the voltage stabilization conversion feedback circuit, and the voltage stabilization bias current circuit provides the operational amplifier bias current required for the operation of the operational amplifier circuit;

[0135] The output end of the operational amplifier circuit is connected to the voltage-stabilized conversion feedback circuit through a voltage-stabilized current mirror circuit, so as to load a voltage conversion reference current to the voltage-stabilized conversion feedback circuit through the voltage-stabilized current mirror circuit;

[0136] Based on the voltage conversion reference current, the voltage stabilizing conversion feedback circuit generates a target output voltage and loads a conversion sampling voltage to the second input terminal of the operational amplifier circuit, so that the operational amplifier circuit loads a stable voltage conversion reference current to the voltage stabilizing conversion feedback circuit through the voltage stabilizing current mirror circuit, and the target output voltage generated by the voltage stabilizing conversion feedback circuit remains stable.

[0137] In order to generate a target output voltage based on a reference voltage, the voltage regulator of the present invention may include an operational amplifier circuit, a voltage-regulated bias current circuit, a voltage-regulated current mirror circuit, and a voltage-regulated conversion feedback circuit. The voltage-regulated bias current circuit can provide the operational amplifier circuit with the operational amplifier bias circuit required for operation. The operational amplifier circuit can receive the reference voltage and the conversion sampling voltage loaded by the voltage-regulated conversion feedback circuit. Based on the reference voltage and the conversion sampling voltage, the operational amplifier circuit can generate an error amplification voltage. The error amplification voltage can be the difference between the reference voltage and the conversion sampling voltage. That is, the operational amplifier circuit is now operating in a comparator state.

[0138] The error amplifier circuit output by the operational amplifier circuit can generate a voltage conversion reference current through the voltage-stabilized current mirror circuit, and the generated voltage conversion reference current is loaded into the voltage-stabilized conversion feedback circuit, so that the voltage-stabilized conversion feedback circuit can output the target output voltage. Of course, the voltage-stabilized conversion feedback circuit can also obtain the conversion sampling voltage at the same time. It can be understood that the conversion sampling voltage is the sampling value after sampling the target output voltage, and the conversion sampling voltage is proportional to the target output voltage. That is, the state of the target output voltage can be represented by the conversion sampling voltage.

[0139] In one embodiment of the present invention, the operational amplifier circuit includes a PMOS transistor M56, wherein:

[0140] The gate terminal and source terminal of the PMOS transistor M56 are adaptively connected to the voltage-stabilizing bias current circuit. The drain terminal of the PMOS transistor M56 is connected to the source terminal of the PMOS transistor M57 and the source terminal of the PMOS transistor M58. The gate terminal of the PMOS transistor M57 forms the first input terminal of the operational amplifier circuit, and the gate terminal of the PMOS transistor M58 serves as the second input terminal of the operational amplifier circuit.

[0141] The drain terminal of the PMOS transistor M57 is connected to the drain terminal of the NMOS transistor M59, the gate terminal of the NMOS transistor M59, and the gate terminal of the NMOS transistor M60. The drain terminal of the NMOS transistor M60 is connected to the drain terminal of the PMOS transistor M58. The drain terminal of the NMOS transistor M60 and the drain terminal of the PMOS transistor M58 are connected to each other to form the output terminal of the operational amplifier circuit.

[0142] The source terminal of the NMOS transistor M59 and the source terminal of the NMOS transistor M60 are both grounded.

[0143] Figure 3An embodiment of an operational amplifier circuit is shown in FIG. As can be seen from the figure, the operational amplifier circuit may include a PMOS transistor M56, a PMOS transistor M57, a PMOS transistor M58, an NMOS transistor M59, and an NMOS transistor M60. As can be seen from the above description, a reference voltage is applied to the gate terminal of the PMOS transistor M57, and a conversion sampling voltage is applied to the gate terminal of the PMOS transistor M58. Thereafter, the reference voltage and the conversion sampling voltage can be compared, and an error amplified voltage is output from the output terminal of the operational amplifier circuit.

[0144] Figure 3 An embodiment of a voltage-stabilized bias current circuit is also shown in FIG. In the figure, the voltage-stabilized bias current circuit includes an NMOS transistor M49, an NMOS transistor M50, a PMOS transistor M51, a PMOS transistor M52, a PMOS transistor M53, a PMOS transistor M54, and a PMOS transistor M55, wherein:

[0145] The drain terminal of the NMOS transistor M49 is connected to the gate terminal of the NMOS transistor M49 and the gate terminal of the NMOS transistor M50, and a bias reference current is received through the drain terminal of the NMOS transistor M49. The source terminal of the NMOS transistor M49 and the source terminal of the NMOS transistor M50 are both grounded.

[0146] The drain terminal of the NMOS transistor M50 is connected to the drain terminal of the PMOS transistor M51 and the gate terminal of the PMOS transistor M51. The source terminal of the PMOS transistor M51 is connected to the drain terminal of the PMOS transistor M52 and the gate terminal of the PMOS transistor M52. The source terminal of the PMOS transistor M52 is connected to the drain terminal of the PMOS transistor M53, the gate terminal of the PMOS transistor M53, and the gate terminal of the PMOS transistor M56.

[0147] The source terminals of the PMOS tube M53 and the PMOS tube M56 are connected to the drain terminal and the gate terminal of the PMOS tube M55. The source terminal of the PMOS tube M55 is connected to the drain terminal and the gate terminal of the PMOS tube M54. The source terminal of the PMOS tube M54 is connected to the voltage V DD .

[0148] Figure 3In the figure, Current Bias is the bias reference current loaded to the drain end of the NMOS transistor M49. The NMOS transistor M49 and the NMOS transistor M50 form a current mirror. The PMOS transistors M51, M52, M54, and M55 are all in a diode connection state. The PMOS transistors M53 and M56 form a current mirror, thereby providing an operational amplifier bias current for the operational amplifier circuit. The operational amplifier bias current can be generated by processing the bias reference current by the voltage-stabilized bias current circuit. That is, the operational amplifier bias current can be determined by the operating parameters of the voltage-stabilized bias current circuit, and the specific operation requirement of the operational amplifier circuit shall prevail.

[0149] Figure 3 An embodiment of a voltage-stabilized current mirror circuit is also shown. As shown in the figure, the voltage-stabilized current mirror circuit includes an NMOS transistor M61, a PMOS transistor M62, a PMOS transistor M63, a PMOS transistor M64, and a PMOS transistor M65, wherein:

[0150] The gate terminal of the NMOS transistor M61 is connected to the drain terminal of the NMOS transistor M60 and the drain terminal of the PMOS transistor M58. The source terminal of the NMOS transistor M61 is grounded. The drain terminal of the NMOS transistor M61 is connected to the drain terminal of the PMOS transistor M62 and the gate terminal of the PMOS transistor M62. The source terminal of the PMOS transistor M62 is connected to the drain terminal of the PMOS transistor M63 and the gate terminal of the PMOS transistor M63.

[0151] The source terminal of the PMOS tube M63 is connected to the drain terminal of the PMOS tube M64, the gate terminal of the PMOS tube M64 and the gate terminal of the PMOS tube M65. The source terminal of the PMOS tube M64 and the source terminal of the PMOS tube M65 are both connected to the voltage V DD .

[0152] As can be seen from the voltage-stabilized current mirror circuit shown in the figure, secondary amplification can be achieved through the NMOS transistor M61. The PMOS transistors M62 and M63 are in a diode connection state to provide impedance. The PMOS transistors M64 and M65 are connected to form a current mirror, thereby loading a voltage conversion reference current into the voltage-stabilized conversion feedback circuit. That is, the voltage-stabilized conversion feedback circuit serves as an active load of the voltage-stabilized current mirror circuit.

[0153] In one embodiment of the present invention, the voltage stabilization conversion feedback circuit includes a plurality of MOS impedance units connected in series, wherein:

[0154] The series-connected MOS units include at least one MOS impedance unit formed by an NMOS transistor group and at least one MOS impedance unit formed by a PMOS transistor group;

[0155] The voltage-stabilized current mirror circuit is adaptively connected to a MOS impedance unit formed by an NMOS tube group, and outputs a target output voltage through the MOS impedance unit;

[0156] The voltage stabilizing conversion feedback circuit is connected to the second input terminal of the operational amplifier circuit through a MOS impedance unit formed by a PMOS tube group;

[0157] When the MOS impedance unit is formed by the NMOS tube group, the NMOS tubes in the NMOS tube group are all configured in a diode connection state to form an NMOS-diode unit, and the NMOS-diode units are connected in series in sequence;

[0158] When the MOS impedance unit is formed by the PMOS tube group, the PMOS tubes in the PMOS tube group are all configured in a diode connection state to form a PMOS-diode unit, and the PMOS-diode units are connected in series in sequence;

[0159] The NMOS tubes in the NMOS tube group and the PMOS tubes in the PMOS tube group are both inverse ratio tubes, and both the NMOS tubes and the PMOS tubes are MOS tubes with longer conductive channels.

[0160] In order to achieve the aforementioned voltage conversion and voltage feedback without using resistors, the voltage-stabilizing conversion feedback circuit of the present invention may employ multiple MOS impedance units connected in series, wherein a MOS impedance unit is an impedance formed by a MOS transistor. In a specific implementation, the voltage-stabilizing conversion feedback circuit may include at least one MOS impedance unit formed by an NMOS transistor group and at least one MOS impedance unit formed by a PMOS transistor group, wherein the NMOS transistor group includes at least two NMOS transistors, and the PMOS transistor group includes at least two PMOS transistors. The number of NMOS transistors in the NMOS transistor group and the number of PMOS transistors in the PMOS transistor group may be selected as needed to form the desired MOS impedance.

[0161] When a MOS impedance unit is formed by an NMOS transistor group, all NMOS transistors within the NMOS transistor group are configured in a diode-connected state. Therefore, each NMOS transistor within the NMOS transistor group can form an NMOS-diode unit. When there are two or more NMOS transistors within the NMOS transistor group, the NMOS-diode units formed are sequentially connected in series to form a MOS impedance unit. Similarly, when a MOS impedance unit is formed by a PMOS transistor group, all PMOS transistors within the PMOS transistor group are configured in a diode-connected state. Therefore, each PMOS transistor within the PMOS transistor group can form a PMOS-diode unit. When there are two or more PMOS transistors within the PMOS transistor group, the PMOS-diode units formed are sequentially connected in series to form a MOS impedance unit. It should be noted that when configuring the MOS transistors in the diode-connected state, the gate terminal of the current MOS transistor can be connected to the drain terminal of the current MOS transistor. The specific method for configuring the diode-connected state can be selected as needed.

[0162] In order to provide the required impedance without using resistors and to ensure that the bias current of the low-power voltage-stabilizing circuit of the present invention during operation is in the nA range, in one embodiment of the present invention, the NMOS transistors in the NMOS transistor group and the PMOS transistors in the PMOS transistor group are both inverse-ratio transistors, and both the NMOS transistors and the PMOS transistors are MOS transistors with longer conductive channels. That is, the NMOS transistors and the PMOS transistors are inverse-ratio transistors, and the NMOS transistors and the PMOS transistors with longer conductive channels should be able to provide sufficiently large impedance capabilities, thereby reducing the bias current during operation.

[0163] Figure 3 In the illustrated embodiment of the voltage regulator, the voltage stabilization conversion feedback circuit includes a MOS impedance unit formed by an NMOS tube group and two MOS impedance units composed of PMOS tubes, wherein the three MOS impedance units are connected in series in sequence. The MOS impedance unit formed by the NMOS tube group is connected to the voltage stabilization current mirror circuit, and the MOS impedance unit formed by the NMOS tube group can output the target output voltage. The first MOS impedance unit formed by the PMOS tube group is connected to the operational amplifier circuit to load the conversion sampling voltage to the operational amplifier circuit.

[0164] Figure 3 In the MOS impedance unit composed of NMOS transistors, the NMOS transistors M66 and M67 are included. The drain terminal of the NMOS transistor M66 is connected to the drain terminal of the PMOS transistor M65 and the gate terminal of the NMOS transistor M66, forming a regulated output terminal of the voltage regulator. The target output voltage can be outputted through the regulated output terminal. The source terminal of the NMOS transistor M66 is connected to the drain terminal of the NMOS transistor M67 and the gate terminal of the NMOS transistor M67.

[0165] Figure 3 In the embodiment, the PMOS transistor M68 and the PMOS transistor M69 form a PMOS transistor group, and the PMOS transistor M70 and the PMOS transistor M71 form a PMOS transistor group. Specifically, the source terminal of the PMOS transistor M68 is connected to the source terminal of the NMOS transistor M67, the gate terminal of the PMOS transistor M68 is connected to the drain terminal of the PMOS transistor M68 and the source terminal of the PMOS transistor M69, and the gate terminal of the PMOS transistor M69 is connected to the drain terminal of the PMOS transistor M69 and the source terminal of the PMOS transistor M70. After being connected to each other, a feedback sampling node is formed, and the feedback sampling node is connected to the gate terminal of the PMOS transistor M58.

[0166] The gate terminal of the PMOS transistor M70 is connected to the drain terminal of the PMOS transistor M70 and the source terminal of the PMOS transistor M71 . The gate terminal of the PMOS transistor M71 and the drain terminal of the PMOS transistor M71 are both grounded.

[0167] In specific implementation, the voltage stabilization conversion feedback circuit may also adopt other forms, specifically based on being able to achieve voltage conversion and provide the required impedance to ensure that the bias current of the low power voltage stabilization circuit is at the nA level when working.

Claims

1. A low-power voltage regulator circuit based on a low-voltage CMOS process device, characterized in that: The low-power voltage regulator circuit is prepared based on a low-voltage CMOS logic process, and the low-power voltage regulator circuit can operate under a high-voltage power supply voltage, wherein the low-power voltage regulator circuit includes: A bandgap reference, used for generating a reference voltage and applying the generated reference voltage to a voltage regulator; a voltage regulator receiving a reference voltage and converting the received reference voltage into a target output voltage, wherein a voltage value of the target output voltage is greater than a voltage value of the reference voltage and the target output voltage is adapted to a maximum voltage supported by a low-voltage CMOS process; A load isolation circuit is connected to the voltage regulator, applies the target output voltage to the connected load via the load isolation circuit, and isolates the connected load from the voltage regulator; The high voltage power supply voltage is higher than the highest voltage supported by the low voltage CMOS logic process, and the voltage value of the high voltage power supply voltage is greater than the voltage value of the target output voltage; The low-power voltage regulator circuit has no resistance device, and the bias current of the low-power voltage regulator circuit when working is at the nA level; The bandgap reference includes a micro-current source, a linear negative temperature drift voltage generating circuit and a temperature drift compensation circuit connected in sequence, wherein: The micro-current source generates a low-temperature drift reference current under a high-voltage power supply voltage, and loads the low-temperature drift reference current to a linear negative temperature drift voltage generating circuit; The linear negative temperature drift voltage generating circuit generates a reference voltage that decreases linearly with temperature based on a low temperature drift reference current, and loads the reference voltage to the temperature drift compensation circuit; A temperature drift compensation circuit is used to compensate for the temperature drift coefficient of the reference voltage to generate a reference voltage with low temperature drift after the temperature drift coefficient is compensated; The micro-current source includes a current source matrix and a detection feedback control circuit adapted to be connected to the current source matrix, wherein: The current source base generates a basic current at a high voltage supply voltage, The detection feedback control circuit detects the basic current and performs feedback control on the current source matrix based on the detected basic current, so that the basic current generated by the current source matrix remains stable through the feedback control, and a low-temperature drift reference current is formed based on the stable basic current; The current source base includes a PMOS transistor M11 operating in a linear region and a basic current generating circuit adapted to be connected to the PMOS transistor M11, wherein: The source terminal of the PMOS tube M11 is connected to the high voltage power supply voltage, the drain terminal of the PMOS tube M11 is connected to the basic current generating circuit, and the gate terminal of the PMOS tube M11 is connected to the output terminal of the detection feedback control circuit; The detection feedback control circuit is further adaptively connected to the basic current generating circuit to obtain the basic current generated by the basic current generating circuit, and detects the obtained basic current and generates a feedback control voltage; The detection feedback control circuit applies a feedback control voltage to the gate terminal of the PMOS transistor M11, so as to adjust the working state of the PMOS transistor M11 through the feedback control voltage, and keep the basic current generated by the basic current generating circuit stable based on the working state of the PMOS transistor M11; The voltage regulator includes an operational amplifier circuit, a voltage-stabilized bias current circuit, a voltage-stabilized current mirror circuit, and a voltage-stabilized conversion feedback circuit, wherein: The first input terminal of the operational amplifier circuit receives a reference voltage, the second input terminal of the operational amplifier circuit is adaptively connected to the voltage stabilization conversion feedback circuit, and the voltage stabilization bias current circuit provides the operational amplifier bias current required for the operation of the operational amplifier circuit; The output end of the operational amplifier circuit is connected to the voltage-stabilized conversion feedback circuit through a voltage-stabilized current mirror circuit, so as to load a voltage conversion reference current to the voltage-stabilized conversion feedback circuit through the voltage-stabilized current mirror circuit; Based on the voltage conversion reference current, the voltage stabilizing conversion feedback circuit generates a target output voltage and loads a conversion sampling voltage to the second input terminal of the operational amplifier circuit, so that the operational amplifier circuit loads a stable voltage conversion reference current to the voltage stabilizing conversion feedback circuit through the voltage stabilizing current mirror circuit, and the target output voltage generated by the voltage stabilizing conversion feedback circuit remains stable.

2. The low-power voltage regulator circuit based on a low-voltage CMOS process device according to claim 1, characterized in that: The detection feedback control circuit includes a feedback control main circuit and a voltage conversion branch, wherein: The basic current generated by the basic current generating circuit is obtained through the feedback control main circuit, and the feedback control reference voltage corresponding to the basic current is generated through the voltage conversion branch. The feedback control main circuit generates a feedback control voltage based on a feedback control reference voltage; The feedback control main circuit includes a PMOS transistor M12, the source terminal of the PMOS transistor M12 is connected to the high-voltage power supply voltage, the gate terminal of the PMOS transistor M12 is adaptively connected to the basic current generation circuit, and the drain terminal of the PMOS transistor M12 is connected to the source terminal of the PMOS transistor M13 and the source terminal of the PMOS transistor M14; The gate terminal of the PMOS tube M14 is connected to the voltage conversion branch. The drain terminal of the PMOS transistor M14 is connected to the drain terminal of the NMOS transistor M16, the gate terminal of the NMOS transistor M16, the gate terminal of the NMOS transistor M15, the drain terminal of the NMOS transistor M15, the drain terminal of the PMOS transistor M13, and the gate terminal of the PMOS transistor M13 to form a feedback control output terminal connected to the gate terminal of the PMOS transistor M11, and is connected to the gate terminal of the PMOS transistor M11 through the feedback control output terminal; The source terminal of the NMOS transistor M15 is connected to the drain terminal of the NMOS transistor M17, and the gate terminal of the NMOS transistor M17 is connected to the gate terminal of the NMOS transistor M18, the drain terminal of the NMOS transistor M18, and the source terminal of the NMOS transistor M16; The source terminal of the NMOS transistor M17 is connected to the drain terminal of the NMOS transistor M19, and the gate terminal of the NMOS transistor M19 is connected to the gate terminal of the NMOS transistor M20, the drain terminal of the NMOS transistor M20, and the source terminal of the NMOS transistor M18; The source terminal of the NMOS transistor M19 and the source terminal of the NMOS transistor M20 are both grounded.

3. The low-power voltage regulator circuit based on a low-voltage CMOS process device according to claim 1, characterized in that: The temperature drift compensation circuit includes a plurality of temperature drift compensation units connected in cascade, wherein: Each level of temperature drift compensation unit can generate a voltage difference with the same temperature coefficient, so that the temperature drift coefficient of the reference voltage can be effectively compensated through multiple cascaded temperature drift compensation units. The temperature drift compensation unit at least includes a temperature drift compensation PMOS current mirror unit and a temperature drift compensation NMOS differential pair tube unit, wherein: The temperature drift compensation PMOS current mirror unit is connected to the high voltage power supply voltage and is adaptively connected to the temperature drift compensation NMOS differential pair tube unit; The temperature drift compensation NMOS differential pair tube unit at least includes a temperature drift compensation NMOS differential input tube, a temperature drift compensation NMOS differential output tube and a temperature drift compensation NMOS control tube; The drain terminals of the temperature drift compensation NMOS differential input tube and the temperature drift compensation NMOS differential output tube and the gate terminal of the temperature drift compensation NMOS differential output terminal are adaptively connected to the temperature drift compensation PMOS current mirror unit. The source end of the temperature drift compensation NMOS differential input tube and the source end of the temperature drift compensation NMOS differential output tube are both connected to the drain end of the temperature drift compensation NMOS control tube, the source end of the temperature drift compensation NMOS control tube is grounded, and the gate terminal of the temperature drift compensation NMOS control tube is connected to the bias voltage VBN1; When the temperature drift compensation units are cascaded, the gate terminal of the temperature drift compensation NMOS differential input tube is connected to the gate terminal of the temperature drift compensation NMOS differential output tube in the previous stage temperature drift compensation unit; The gate end of the temperature drift compensation NMOS differential output end is connected to the temperature drift compensation NMOS differential input tube in the next stage temperature drift compensation unit, and outputs a zero temperature drift reference voltage through the gate end of the temperature drift compensation NMOS differential output tube in the last stage temperature drift compensation unit.

4. The low-power voltage regulator circuit based on a low-voltage CMOS process device according to claim 1, characterized in that: The operational amplifier circuit includes a PMOS tube M56, wherein: The gate terminal and source terminal of the PMOS transistor M56 are adaptively connected to the voltage-stabilizing bias current circuit. The drain terminal of the PMOS transistor M56 is connected to the source terminal of the PMOS transistor M57 and the source terminal of the PMOS transistor M58. The gate terminal of the PMOS transistor M57 forms the first input terminal of the operational amplifier circuit, and the gate terminal of the PMOS transistor M58 serves as the second input terminal of the operational amplifier circuit. The drain terminal of the PMOS transistor M57 is connected to the drain terminal of the NMOS transistor M59, the gate terminal of the NMOS transistor M59, and the gate terminal of the NMOS transistor M60. The drain terminal of the NMOS transistor M60 is connected to the drain terminal of the PMOS transistor M58. The drain terminal of the NMOS transistor M60 and the drain terminal of the PMOS transistor M58 are connected to each other to form the output terminal of the operational amplifier circuit. The source terminal of the NMOS transistor M59 and the source terminal of the NMOS transistor M60 are both grounded.

5. The low-power voltage regulator circuit based on a low-voltage CMOS process device according to claim 1, characterized in that: The voltage stabilization conversion feedback circuit includes a plurality of MOS impedance units connected in series, wherein: The series-connected MOS units include at least one MOS impedance unit formed by an NMOS transistor group and at least one MOS impedance unit formed by a PMOS transistor group; The voltage-stabilized current mirror circuit is adaptively connected to a MOS impedance unit formed by an NMOS tube group, and outputs a target output voltage through the MOS impedance unit; The voltage stabilizing conversion feedback circuit is connected to the second input terminal of the operational amplifier circuit through a MOS impedance unit formed by a PMOS tube group; When the MOS impedance unit is formed by the NMOS tube group, the NMOS tubes in the NMOS tube group are all configured in a diode connection state to form an NMOS-diode unit, and the NMOS-diode units are connected in series in sequence; When the MOS impedance unit is formed by the PMOS tube group, the PMOS tubes in the PMOS tube group are all configured in a diode connection state to form a PMOS-diode unit, and the PMOS-diode units are connected in series in sequence; The NMOS tubes in the NMOS tube group and the PMOS tubes in the PMOS tube group are both inverse ratio tubes, and both the NMOS tubes and the PMOS tubes are MOS tubes with longer conductive channels.

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