Clock signal generation system and clock signal generation method

Abstract

The invention discloses a clock signal generation system and a clock signal generation method. The clock signal generation system comprises a plurality of clock units; the clock unit comprises a synchronous generation circuit and a frequency divider, the synchronous generation circuit generates a corresponding synchronous output signal based on a clock input signal, a synchronous input signal and a delay control value, and the frequency divider generates a clock output signal based on the clock input signal, the synchronous output signal and a frequency division control value. According to the clock signal generation system and the clock signal generation method provided by the invention, the high-level duration time of the synchronous output signal can be adjusted by adjusting the delay control value, so that when the frequency divider generates the clock output signal based on the clock input signal, the synchronous output signal and the frequency division control value, the frequency division control value can be adjusted; the change of the high level duration of the synchronous output signal causes the change of the phase difference between the clock output signals, so that the phase synchronization or adjustable phase difference between the clock output signals is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a clock signal generation system and a clock signal generation method. Background Art

[0002] Clock synchronization and clock buffer chips with multiple outputs are widely used in fields such as phased array radars, electronic countermeasures, and communication base stations. The following Figure 1 is a schematic diagram of a 14-output clock buffer: CLKIN is the input clock, generally with a relatively high frequency, which can reach GHz frequency. CLKOUT0 to CLKOUT13 are 14 clock outputs, and the output frequency is the division frequency of CLKIN. RFSYNCIN is the input synchronization signal, which is used to synchronize the phases of the 14 outputs. The phases of the 14 outputs can be set to be exactly the same, or they can be a repeatable fixed phase difference, and the phase difference is usually an integer multiple of the input clock period. The division ratios of CLKOUT0 to CLKOUT13 can be the same or different. When the division ratios are different, the first rising edges after synchronization need to be aligned.

[0003] As Figure 2 shown, taking the output clock signals CLKOUT0, CLKOUT1, and CLKOUT2 as examples, after CLKOUT0 and CLKOUT1 are synchronized, a repeatable fixed phase difference is generated, while the phases of CLKOUT0 and CLKOUT2 are exactly the same after synchronization.

[0004] Among them, the frequency divider of the clock buffer will introduce phase uncertainty. Figure 3 is a schematic diagram of a frequency divider with a division ratio of D; for a frequency divider with a division ratio of D, there are D possible phases for the output clock signal Output. This phase uncertainty mainly comes from two aspects: one is that the frequency divider may start dividing at different edges; the other is that different initial states when the frequency divider starts working will result in different phases. Figure 4 is an input-output waveform diagram of a divide-by-4 frequency divider. It can be seen that there are four phases of 0°, 90°, 180°, and 270° between the output clock signal Output and the input clock signal Input Clock.

[0005] In systems such as phased arrays, MIMO, and multi-channel ADC sampling, a clock chip is required to provide multiple phasesynchronized clock signals. In order to eliminate the phase uncertainty introduced by the above frequency divider, a reset method can be adopted. First, the internal voltage state of the frequency divider is reset to a fixed value, and then, at the same moment, the reset signal is released simultaneously, so that different frequency dividers start working at the same moment, that is, multi-output phase synchronization can be achieved. The clock edge of the reset signal and the input clock needs to meet the requirements of the sampling setup and hold time of the frequency divider.

[0006] When there are multiple dividers in a chip that need to be synchronized, when the system is powered on, the POR circuit (Power-On Reset circuit) will generate a rising or falling edge, and the output signal of the POR circuit can be used as the synchronization signal SYNC.

[0007] If there is a need for multi-chip synchronization, since the power-on times of different chips and the output moments of the POR circuits cannot be guaranteed to be the same, the POR circuit cannot be used for synchronization; at this time, an external synchronization signal SYNC is required to trigger multiple chips simultaneously. As Figure 5 shown, the input clocks of the two chips are the same, and the synchronization signal SYNC is input to Chip 1 and Chip 2 simultaneously, making the clock output phases of Chip 1 and Chip 2 synchronized.

[0008] However, in some cases, the traces and environments of Chip 1 and Chip 2 on the PCB board may be different. At this time, the output phase delay between them needs to be adjusted appropriately to compensate for the environmental error.

[0009] The information disclosed in this background section is only intended to enhance the overall understanding of the present invention and should not be regarded as an admission or any form of suggestion that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Invention

[0010] The object of the present invention is to provide a clock signal generation system and a clock signal generation method, which can synchronize or adjust the phase delay of multiple clock output signals output.

[0011] To achieve the above object, the technical solution provided by a specific embodiment of the present invention is as follows: A clock signal generation system, comprising: a plurality of clock units; each of the clock units includes a synchronization generation circuit and a divider, the clock input terminals of each of the synchronization generation circuits and the clock input terminals of the dividers are all used to receive a clock input signal, the reset terminals of each of the synchronization generation circuits are all used to receive a synchronization input signal, the delay control terminals of each of the synchronization generation circuits are used to receive their respective delay control values, the reset terminals of each of the dividers are connected to the output terminals of the corresponding synchronization generation circuits, the frequency division control terminals of each of the dividers are used to receive their respective frequency division control values, each of the synchronization generation circuits generates a corresponding synchronization output signal based on the clock input signal, the synchronization input signal and the delay control value, and each of the dividers generates a clock output signal based on the clock input signal, the synchronization output signal and the frequency division control value.

[0012] In one or more embodiments of the present invention, the synchronization generation circuit includes a counter, a first flip-flop, and a second flip-flop; a clock input terminal of the counter is configured to receive a clock input signal, a reset terminal of the counter is configured to receive a synchronization input signal, a delay control terminal of the counter is configured to receive a delay control value, clock input terminals of the first flip-flop and the second flip-flop are connected to an output terminal of the counter, a D input terminal of the first flip-flop is configured to receive a power supply voltage signal, and a D input terminal of the second flip-flop is connected to a Q output terminal of the first flip-flop.

[0013] In one or more embodiments of the present invention, the synchronization generation circuit further includes an OR gate, a first input terminal of the OR gate is configured to receive a synchronization input signal, a second input terminal of the OR gate is connected to a QB output terminal of the second flip-flop, and an output terminal of the OR gate is connected to a reset terminal of a frequency divider.

[0014] In one or more embodiments of the present invention, the synchronization input signal is a pulse signal and a high-level duration of the synchronization input signal is greater than a clock period of the clock input signal.

[0015] In one or more embodiments of the present invention, the clock unit further includes a delay register configured to configure a delay control value; and / or the clock unit further includes a frequency division register configured to configure a frequency division control value.

[0016] The present invention also discloses a method for generating a clock signal, including: using the synchronization input signal as a reset signal of the synchronization generation circuit, and controlling the synchronization generation circuit to output a synchronization output signal in cooperation with the clock input signal, and simultaneously controlling the synchronization generation circuit by a delay control value to perform delay adjustment on the synchronization output signal; using the synchronization output signal output by the synchronization generation circuit as a reset signal of the frequency divider, and controlling the frequency divider to output a clock output signal in cooperation with the clock input signal, and simultaneously adjusting a frequency division ratio of the frequency divider by a frequency division control value.

[0017] In one or more embodiments of the present invention, the synchronization input signal is a pulse signal and a high-level duration of the synchronization input signal is greater than a clock period of the clock input signal.

[0018] In one or more embodiments of the present invention, the using the synchronization input signal as a reset signal of the synchronization generation circuit, and controlling the synchronization generation circuit to output a synchronization output signal in cooperation with the clock input signal, and simultaneously controlling the synchronization generation circuit by a delay control value to perform delay adjustment on the synchronization output signal includes: Reset the counter within a preset time by synchronizing the input signal with the clock input signal, and control the frequency of the output signal of the counter after reset by the delay control value; Use the output signal of the counter as the sampling clock signal for the first flip-flop and the second flip-flop; Sample the power supply voltage signal through the first flip-flop based on the output signal after the counter is reset; Sample the signal output by the first flip-flop through the second flip-flop based on the output signal after the counter is reset.

[0019] In one or more embodiments of the present invention, perform an OR logic operation on the output signal of the second flip-flop and the synchronization input signal through an OR gate to generate a synchronization output signal.

[0020] In one or more embodiments of the present invention, configure the delay control value through a delay register; and / or Configure the frequency division control value through a frequency division register.

[0021] Compared with the prior art, the clock signal generation system and the clock signal generation method of the present invention generate corresponding synchronization output signals through a synchronization generation circuit based on a clock input signal and a synchronization input signal. At the same time, by adjusting the delay control value, the duration of the high level of the synchronization output signal can be adjusted. Subsequently, when the frequency divider generates a clock output signal based on the clock input signal, the synchronization output signal, and the frequency division control value, due to the change in the duration of the high level of the synchronization output signal, the phase difference between the clock output signals changes, achieving the purpose of phase synchronization or adjustable phase difference between the clock output signals. Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0023] Figure 1 Schematic diagram of a 14-channel output clock buffer in the prior art.

[0024] Figure 2 Partial output waveform diagram of a 14-channel output clock buffer in the prior art.

[0025] Figure 3 Schematic diagram of a frequency divider with a frequency division ratio of D in the prior art.

[0026] Figure 4It is the input / output waveform diagram of a divide-by-4 frequency divider in the prior art.

[0027] Figure 5 It is the clock circuit diagram composed of two chips in the prior art.

[0028] Figure 6 It is the circuit schematic diagram of the clock signal generation system in an embodiment of the present invention.

[0029] Figure 7 It is the circuit schematic diagram of the synchronization generation circuit in an embodiment of the present invention.

[0030] Figure 8 It is the waveform diagram of the synchronization generation circuit in an embodiment of the present invention.

[0031] Figure 9 It is the partial waveform diagram of the clock signal generation system in an embodiment of the present invention. Detailed implementation manners

[0032] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0033] "Coupled", "connected", or "linked" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include a connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through circuits or components such as switches and follower circuits. Additionally, in the invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity, or order between these technical features.

[0034] In the detailed description of the specification, reference is made to the accompanying drawings that form a part of it, where the same reference numerals always represent the same components, and which are shown by way of exemplary embodiments that can be implemented. It should be understood that other embodiments can be utilized without departing from the scope of the present application, and structural or logical changes can be made. Therefore, the following detailed description should not be regarded as restrictive.

[0035] The various operations in the specification may be described, in turn, as a number of discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of the description should not be construed as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0036] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0037] Various components and devices may be referred to or shown herein in the singular (e.g., "MOS transistor", "transistor", "switch", etc.), but this is merely for ease of discussion, and any element referred to in the singular may include a plurality of such elements in accordance with the teachings herein.

[0038] The specification describes the use of the phrases "in one embodiment", "in other embodiments", or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "comprising", "including", "having", etc., used with respect to the embodiments of this application are synonymous.

[0039] As Figure 6 shown, a clock signal generation system in an embodiment of the present invention includes: a plurality of clock units, each clock unit may be considered as a separate clock chip or different groups within the same chip, and all clock units generate a set of clock output signals.

[0040] Each clock unit includes a synchronization generation circuit 10 and a frequency divider 20. The clock input terminals of the respective synchronization generation circuits 10 and the clock input terminals of the frequency dividers 20 are all used to receive a clock input signal CKIN. The reset terminals of the respective synchronization generation circuits 10 are all used to receive a synchronization input signal SYNC. The delay control terminals of the respective synchronization generation circuits 10 are used to receive their respective delay control values RG_DLY. The reset terminals of the respective frequency dividers 20 are connected to the output terminals of the corresponding synchronization generation circuits 10. The frequency division control terminals of the respective frequency dividers 20 are used to receive their respective frequency division control values RG_DIV. Each synchronization generation circuit 10 generates a corresponding synchronization output signal based on the clock input signal CKIN, the synchronization input signal SYNC, and its respective delay control value RG_DLY. Each frequency divider 20 generates a corresponding clock output signal based on the clock input signal CKIN, the synchronization output signal, and its respective frequency division control value RG_DIV.

[0041] Figure 6Shown is a clock signal generation system composed of 14 clock units CELL0 to CELL13. Correspondingly, there are 14 synchronization generation circuits 10 and 14 frequency dividers 20. The 14 synchronization generation circuits 10 respectively receive 14 delay control values RG_DLY0<12:0> to RG_DLY13<12:0>. The 14 synchronization generation circuits 10 respectively output 14 synchronization output signals SYNC_OUT0 to SYNC_OUT13. The 14 frequency dividers 20 respectively receive 14 frequency division control values RG_DIV0<12:0> to RG_DIV13<12:0>. The 14 frequency dividers 20 respectively output 14 clock output signals CKOUT0 to CKOUT13. In other embodiments, the number of clock units can be increased or decreased as needed.

[0042] The 14 delay control values RG_DLY0<12:0> to RG_DLY13<12:0> are respectively configured by the corresponding 14 13-bit delay registers. Each delay register can be set to the same value or different values. In other embodiments, the delay register can also be a delay register with other bit numbers.

[0043] The 14 frequency division control values RG_DIV0<12:0> to RG_DIV13<12:0> are respectively configured by the corresponding 14 13-bit frequency division registers. The frequency division control value determines the frequency division ratio of the frequency division register. Each frequency division register can be set to the same value or different values. For example, when the frequency division control value is configured as 0000000001000 (binary), the frequency division ratio is 8 (decimal). In one embodiment, the frequency division register can be an SPI bus configuration register or an I2C bus configuration register, etc. In other embodiments, the frequency division register can also be a frequency division register with other bit numbers.

[0044] The values set in the delay register and the frequency division register can control a certain clock output signal to generate different phase differences and different output frequencies (different configurations of the frequency division register) relative to the clock output signals of other channels, or generate different phase differences and the same output frequency (the same configuration of the frequency division register). For example, if the frequency division control value RG_DIV0<12:0> and the frequency division control value RG_DIV5<12:0> are both set to 5, and the delay control value RG_DLY0<12:0> and the delay control value RG_DLY5<12:0> are respectively set to 2 and 3, then there will be an error in the delay accuracy between the clock output signal CKOUT0 and the clock output signal CKOUT5. This delay accuracy is usually the period of the clock input signal CKIN, and the frequencies of the clock output signal CKOUT0 and the clock output signal CKOUT5 are the same.

[0045] Such as Figure 7As shown, the structure of the synchronization generation circuit 10 of the first clock unit CELL0 is used as an example for illustration. The synchronization generation circuit 10 includes a counter COUNTER, a first flip-flop DFF1, a second flip-flop DFF2, and an OR gate OR.

[0046] The clock input terminal of the counter COUNTER is used to receive a clock input signal CKIN. The reset terminal RST of the counter COUNTER is used to receive a synchronization input signal SYNC (the synchronization input signal SYNC serves as the reset signal of the counter COUNTER). The delay control terminal DLY of the counter COUNTER is used to receive a delay control value RG_DLY0<12:0>. The clock input terminals of the first flip-flop DFF1 and the second flip-flop DFF2 are connected to the output terminal of the counter COUNTER to receive the output signal CKI of the counter COUNTER. The D input terminal of the first flip-flop DFF1 is used to receive a power supply voltage signal VDD, and the power supply voltage signal VDD is a high-potential signal. The D input terminal of the second flip-flop DFF2 is connected to the Q output terminal of the first flip-flop DFF1. The first input terminal of the OR gate OR is used to receive the synchronization input signal SYNC. The second input terminal of the OR gate OR is connected to the QB output terminal of the second flip-flop DFF2 to receive the output signal SYNC_DLY of the second flip-flop DFF2. The output terminal of the OR gate OR is connected to the reset terminal of the frequency divider 20, and the output terminal of the OR gate OR generates a synchronization output signal SYNC_OUT0.

[0047] In addition, when it is necessary to make the phase of the clock output signals output by two or more clock units exactly the same, the path formed by the counter COUNTER, the first flip-flop DFF1, and the second flip-flop DFF2 in the corresponding clock unit can be turned off, so that the synchronization generation circuit 10 outputs a synchronization output signal that is the same as the synchronization input signal SYNC. Conversely, when it is necessary to have a certain phase difference between the clock output signals output by two or more clock units, the path formed by the counter COUNTER, the first flip-flop DFF1, and the second flip-flop DFF2 in the corresponding clock unit is turned on. In other embodiments, if it is not considered necessary to keep the phase of the clock output signals output by the corresponding clock units consistent, the OR gate OR can be not provided.

[0048] As Figure 8 described, the clock input signal CKIN is a high-frequency clock signal, and the synchronization input signal SYNC is a pulse signal and the duration of the effective level (high level) of the synchronization input signal SYNC is much longer than the clock period of the clock input signal CKIN.

[0049] When the synchronous input signal SYNC changes from low level to high level, the counter COUNTER is in the reset state and its output signal CKI is pulled low; when the synchronous input signal SYNC changes from high level to low level, the reset of the counter COUNTER is released and it starts to work normally. At this time, the output signal CKI starts to output normally at the next rising edge of the clock input signal CKIN after the synchronous input signal SYNC changes from high level to low level. The frequency of the normally output output signal CKI is the waveform after the clock input signal CKIN is divided by frequency, that is, the period T CKI =N*T CKIN , where, T CKIN is the clock period of the clock input signal CKIN, and the division ratio N is determined by the delay control value RG_DLY<12:0> configured by the delay register.

[0050] The waveform of the output signal SYNC_DLY of the second flip-flop DFF2 is high level when the synchronous input signal SYNC is in the high level state. When the synchronous input signal SYNC switches from high level to low level, the first flip-flop DFF1 starts to sample the power supply voltage signal VDD through the output signal CKI, and the second flip-flop DFF2 starts to sample the output signal generated by the Q output terminal of the first flip-flop DFF1 through the output signal CKI. After two consecutive rising edges of the output signal CKI, the output signal SYNC_DLY of the second flip-flop DFF2 is pulled low. After the synchronous input signal SYNC and the output signal SYNC_DLY of the second flip-flop DFF2 pass through the OR gate OR, the final synchronous output signal SYNC_OUT0 is output. Compared with the synchronous input signal SYNC, the duration of the high level of the synchronous output signal SYNC_OUT0 is extended by N Ts CKIN cycles.

[0051] In one embodiment, the frequency divider 20 can be formed by cascading multiple divide-by-2 / 3 frequency division units or composed of a P-S counter (pulse swallowing counter).

[0052] Combined Figure 6 , as Figure 9 shown, taking the clock unit CELL0 and the clock unit CELL5 as examples, the clock input signal CKIN is a GHz clock signal, the input synchronous input signal SYNC is a pulse signal, and the duration of the high level of the pulse waveform is much longer than the clock period of the clock input signal CKIN. After the synchronous input signal SYNC passes through the synchronous generation circuit 10 of the clock unit CELL0, the synchronous output signal SYNC_OUT0 is generated. The duration of the high level of the synchronous output signal SYNC_OUT0 is extended by 2 Ts relative to the synchronous input signal SYNC CKINThe period (the delay control value RG_DLY0<12:0> is configured to 2, obtaining an extension of 2 T CKIN cycles); after the synchronization input signal SYNC passes through the synchronization generation circuit 10 of the clock unit CELL5, a synchronization output signal SYNC_OUT5 is generated. The high-level duration of the synchronization output signal SYNC_OUT5 is extended by 3 T CKIN cycles (the delay control value RG_DLY0<12:0> is configured to 3, obtaining an extension of 3 T CKIN cycles).

[0053] Since both the frequency division control value RG_DIV0<12:0> and the frequency division control value RG_DIV5<12:0> are 5, that is, the clock output signal CKOUT0 and the clock output signal CKOUT5 are both clock signals that are the 5-frequency division of the clock input signal CKIN.

[0054] Before the high-level pulse of the synchronization input signal SYNC arrives, the phases of the clock output signal CKOUT0 and the clock output signal CKOUT5 are out of sync. When the synchronization input signal SYNC switches from low level to high level, both the clock output signal CKOUT0 and the clock output signal CKOUT5 are pulled low to the low level and are in the reset state. After the synchronization output signal SYNC_OUT0 switches from high level to low level, the frequency divider 20 of the clock unit CELL0 starts to work normally. Next, when the first rising edge of the clock input signal CKIN appears, it triggers the generation of the first rising edge of the clock output signal CKOUT0; similarly, after the synchronization output signal SYNC_OUT5 switches from high level to low level, the frequency divider 20 of the clock unit CELL5 starts to work normally. Next, when the first rising edge of the clock input signal CKIN appears, it triggers the generation of the first rising edge of the clock output signal CKOUT5. At this time, a repeatable fixed phase difference is generated between the clock output signal CKOUT0 and the clock output signal CKOUT5, and this phase difference is equal to a delay accuracy, that is, one T CKIN cycle.

[0055] Combined with Figures 6 to 9 , the present invention also discloses a method for generating a clock signal, including: By using the synchronization input signal SYNC as the reset signal of the synchronization generation circuit 10 of each clock unit, and cooperating with the clock input signal CKIN to control the synchronization generation circuit 10 to output a synchronization output signal, and at the same time using a delay control value to control the synchronization generation circuit 10 to adjust the delay of the synchronization output signal, the delay control value is configured by a delay register. In one embodiment, the synchronization input signal SYNC is a pulse signal and the duration of the high level of the synchronization input signal SYNC is much longer than the clock period of the clock input signal CKIN.

[0056] Multiple synchronization generation circuits 10 output a group of synchronization output signals SYNC_OUT0~SYNC_OUTn, and the duration of the high level of each synchronization output signal relative to the synchronization input signal SYNC is controlled by the corresponding delay control value.

[0057] The synchronization output signal output by the synchronization generation circuit 10 of each clock unit cooperates with the clock input signal CKIN to control the frequency divider 20 of the corresponding clock unit to output a clock output signal, and the frequency division ratio of the frequency divider 20 is adjusted by a frequency division control value, and the frequency division control value is configured by a frequency division register.

[0058] Multiple frequency dividers 20 output a group of clock output signals CKOUT0~CKOUTn, and the phase difference between the clock output signals is determined by the duration of the high level of the corresponding synchronization output signal relative to the synchronization input signal SYNC and the frequency division control value.

[0059] Furthermore, in combination with the specific circuit of a single synchronization generation circuit 10, the above "by using the synchronization input signal SYNC as the reset signal of the synchronization generation circuit, and cooperating with the clock input signal CKIN to control the synchronization generation circuit 10 to output a synchronization output signal, and at the same time using a delay control value to control the synchronization generation circuit 10 to adjust the delay of the synchronization output signal" includes: The synchronization input signal SYNC cooperates with the clock input signal CKIN to reset the counter COUNTER within a preset time, and the frequency of the output signal CKI of the counter COUNTER after the reset is controlled by the delay control value (that is, the frequency division ratio of the counter COUNTER is controlled by the delay control value RG_DLY).

[0060] The output signal CKI of the counter COUNTER is used as the sampling clock signal of the first flip-flop DFF1 and the second flip-flop DFF2.

[0061] The first flip-flop DFF1 samples the power supply voltage signal VDD based on the output signal CKI after the counter COUNTER is reset; The signal output by the first flip-flop DFF1 is sampled by the second flip-flop DFF2 based on the output signal CKI after the counter COUNTER is reset.

[0062] The OR gate OR performs an OR logic operation on the output signal SYNC_DLY of the second flip-flop DFF2 and the synchronous input signal SYNC to generate a synchronous output signal.

[0063] As can be seen from the above, by cooperating the first flip-flop DFF1 and the second flip-flop DFF2 with the counter COUNTER, and by setting the frequency division ratio of the counter COUNTER, the high-level duration of the finally output synchronous output signal can be extended based on the synchronous input signal SYNC. The extended time of each synchronous output signal is different, which also determines the phase difference between subsequent clock output signals. Therefore, the phase difference between each clock output signal can be adjusted by adjusting the delay control value.

[0064] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be construed as limiting the claimed invention.

[0065] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A clock signal generation system, characterized in that, Comprising: Multiple clock units; The clock unit includes a synchronization generation circuit and a frequency divider. The clock input terminals of each synchronization generation circuit and the clock input terminal of the frequency divider are all used to receive a clock input signal. The reset terminals of each synchronization generation circuit are all used to receive a synchronization input signal. The delay control terminals of each synchronization generation circuit are used to receive their respective delay control values. The reset terminals of each frequency divider are connected to the output terminals of the corresponding synchronization generation circuit. The frequency division control terminals of each frequency divider are used to receive their respective frequency division control values. Each synchronization generation circuit generates a corresponding synchronization output signal based on the clock input signal, the synchronization input signal, and the delay control value. Each frequency divider generates a clock output signal based on the clock input signal, the synchronization output signal, and the frequency division control value.

2. The clock signal generation system according to claim 1, characterized in that, The synchronization generation circuit includes a counter, a first flip-flop, and a second flip-flop. The clock input terminal of the counter is used to receive a clock input signal. The reset terminal of the counter is used to receive a synchronization input signal. The delay control terminal of the counter is used to receive a delay control value. The clock input terminals of the first flip-flop and the second flip-flop are connected to the output terminal of the counter. The D input terminal of the first flip-flop is used to receive a power supply voltage signal. The D input terminal of the second flip-flop is connected to the Q output terminal of the first flip-flop.

3. The clock signal generation system according to claim 2, characterized in that, The synchronization generation circuit further includes an OR gate. The first input terminal of the OR gate is used to receive a synchronization input signal. The second input terminal of the OR gate is connected to the QB output terminal of the second flip-flop. The output terminal of the OR gate is connected to the reset terminal of the frequency divider.

4. The clock signal generation system according to claim 1, characterized in that, The synchronization input signal is a pulse signal and the high-level duration of the synchronization input signal is greater than the clock cycle of the clock input signal.

5. The clock signal generation system according to claim 1, characterized in that, The clock unit further includes a delay register for configuring the delay control value; and / or The clock unit further includes a frequency division register for configuring the frequency division control value.

6. A clock signal generation method, characterized in that, Comprising: By using the synchronization input signal as the reset signal of the synchronization generation circuit and cooperating with the clock input signal to control the synchronization generation circuit to output a synchronization output signal, and at the same time using the delay control value to control the synchronization generation circuit to adjust the delay of the synchronization output signal; By using the synchronization output signal output by the synchronization generation circuit as the reset signal of the frequency divider and cooperating with the clock input signal to control the frequency divider to output a clock output signal, and at the same time using the frequency division control value to adjust the frequency division ratio of the frequency divider.

7. The clock signal generation method according to claim 6, characterized in that, The synchronization input signal is a pulse signal and the high-level duration of the synchronization input signal is greater than the clock cycle of the clock input signal.

8. The clock signal generation method according to claim 6, characterized in that, The method of using the synchronization input signal as the reset signal of the synchronization generation circuit and cooperating with the clock input signal to control the synchronization generation circuit to output a synchronization output signal, and at the same time using the delay control value to control the synchronization generation circuit to adjust the delay of the synchronization output signal includes: Resetting the counter within a preset time by the synchronization input signal cooperating with the clock input signal, and controlling the frequency of the signal output by the counter after reset by the delay control value; Using the output signal of the counter as the sampling clock signal of the first flip-flop and the second flip-flop; Sample the power supply voltage signal by a first trigger based on the output signal after the counter is reset; Sample the signal output by the first trigger by a second trigger based on the output signal after the counter is reset.

9. The clock signal generation method according to claim 8, characterized in that, Perform an OR logic operation on the output signal of the second trigger and the synchronous input signal through an OR gate to generate a synchronous output signal.

10. The clock signal generation method according to claim 6, characterized in that, Configure the delay control value through a delay register; and / or Configure the frequency division control value through a frequency division register.

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