Clock signal generation system and clock signal generation method

Abstract

The present invention discloses a clock signal generation system and a clock signal generation method. The clock signal generation system includes: multiple clock units; the clock units include a synchronization generation circuit and a frequency divider, the synchronization generation circuit generates a corresponding synchronization output signal based on a clock input signal, a synchronization input signal, and a delay control value, and the frequency divider generates a clock output signal based on the clock input signal, the synchronization output signal, and the frequency division control value. The clock signal generation system and the clock signal generation method of the present invention can adjust the high-level duration of the synchronization output signal by adjusting the delay control value. Then, when the frequency divider generates the clock output signal based on the clock input signal, the synchronization output signal, and the frequency division control value, the change in the high-level duration of the synchronization output signal causes a change in the phase difference between the clock output signals, thereby achieving phase synchronization or adjustable phase difference between the clock output signals.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a clock signal generating system and a clock signal generating method. Background Art

[0002] Multi-channel output clock synchronization and clock buffer chips are widely used in phased array radar, electronic countermeasures, communication base stations and other fields. Figure 1 Schematic diagram of a 14-output clock buffer: CLKIN is the input clock, typically at a high frequency, reaching GHz. CLKOUT0 through CLKOUT13 are the 14 clock outputs, each with a frequency divided by CLKIN. RFSYNCIN is the input synchronization signal, used to synchronize the phases of the 14 outputs. The 14 outputs can be set to completely aligned or with a repeatable fixed phase difference, typically an integer multiple of the input clock period. The division ratios of CLKOUT0 through CLKOUT13 can be the same or different. For different division ratios, the first rising edge after synchronization must be aligned.

[0003] like Figure 2 As shown, taking the output clock signals CLKOUT0, CLKOUT1 and CLKOUT2 as an example, after CLKOUT0 is synchronized with CLKOUT1, a repeatable fixed phase difference is generated, and after CLKOUT0 is synchronized with CLKOUT2, the phases are completely consistent.

[0004] Among them, the clock buffer's frequency divider introduces phase uncertainty. Figure 3 The following diagram shows a frequency divider with a division ratio of D. A frequency divider with a division ratio of D has D possible phases for the output clock signal. This phase uncertainty arises from two main sources: first, the frequency divider may start dividing at different edges; second, different initial states of the frequency divider can lead to different phases. Figure 4 The following is an input and output waveform diagram of a divide-by-4 frequency divider. It can be seen that there are four phases between the output clock signal Output and the input clock signal Input Clock: 0°, 90°, 180°, and 270°.

[0005] In systems such as phased arrays, MIMO, and multi-channel ADC sampling, clock chips are required to provide multiple phase-synchronized clock signals. To eliminate the phase uncertainty introduced by the aforementioned frequency dividers, a reset method can be used. First, the internal voltage state of the frequency divider is reset to a fixed value. Then, the reset signal is released simultaneously, allowing different frequency dividers to start operating at the same time, thus achieving multi-channel output phase synchronization. The clock edges of the reset signal and the input clock must meet the setup and hold time requirements of the frequency divider sampling.

[0006] For example, if there is a multi-channel frequency divider that needs to be synchronized inside a chip, when the system is powered on, the POR circuit (power-on reset circuit) will send a rising or falling edge. The output signal of the POR circuit can be used as the synchronization signal SYNC.

[0007] If there is a need for multi-chip synchronization, the POR circuit cannot be used for synchronization because the power-on time and POR circuit output time of different chips cannot be guaranteed to be consistent. In this case, an external synchronization signal SYNC is required to trigger multiple chips at the same time. Figure 5 As shown, the two chips have the same input clock, and the synchronization signal SYNC is input to chip 1 and chip 2 at the same time, so that the clock output phases of chip 1 and chip 2 are synchronized.

[0008] However, in some cases, the routing and environment of chip 1 and chip 2 on the PCB may be different. In this case, the output phase delay between them needs to be appropriately adjusted to compensate for the environmental error.

[0009] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the Invention

[0010] An object of the present invention is to provide a clock signal generating system and a clock signal generating method, which can synchronize or adjust the phase delay of multiple clock output signals.

[0011] In order to achieve the above-mentioned purpose, a technical solution provided by a specific embodiment of the present invention is as follows: A clock signal generating system includes: multiple clock units; the clock units include a synchronization generating circuit and a frequency divider, the clock input end of each synchronization generating circuit and the clock input end of the frequency divider are both used to receive a clock input signal, the reset end of each synchronization generating circuit is used to receive a synchronization input signal, the delay control end of each synchronization generating circuit is used to receive a respective delay control value, the reset end of each frequency divider is connected to the output end of the corresponding synchronization generating circuit, the frequency division control end of each frequency divider is used to receive a respective frequency division control value, each synchronization generating circuit generates a corresponding synchronization output signal based on the clock input signal, the synchronization input signal and the delay control value, and each frequency divider generates a clock output signal based on the clock input signal, the synchronization output signal and the frequency division control value.

[0012] In one or more embodiments of the present invention, the synchronization generation circuit includes a counter, a first trigger, and a second trigger; the clock input terminal of the counter is used to receive a clock input signal, the reset terminal of the counter is used to receive a synchronization input signal, the delay control terminal of the counter is used to receive a delay control value, the clock input terminal of the first trigger and the clock input terminal of the second trigger are connected to the output terminal of the counter, the D input terminal of the first trigger is used to receive a power supply voltage signal, and the D input terminal of the second trigger is connected to the Q output terminal of the first trigger.

[0013] In one or more embodiments of the present invention, the synchronization generation circuit also includes an OR gate, wherein the first input terminal of the OR gate is used to receive a synchronization input signal, the second input terminal of the OR gate is connected to the QB output terminal of the second trigger, and the output terminal of the OR gate is connected to the reset terminal of the divider.

[0014] In one or more embodiments of the present invention, the synchronization input signal is a pulse signal and the high level duration of the synchronization input signal is greater than the clock period of the clock input signal.

[0015] In one or more embodiments of the present invention, the clock unit further includes a delay register, and the delay register is used to configure the delay control value; and / or

[0016] The clock unit further includes a frequency division register, and the frequency division register is used to configure a frequency division control value.

[0017] The present invention also discloses a clock signal generating method, comprising:

[0018] By using the synchronous input signal as the reset signal of the synchronous generation circuit and cooperating with the clock input signal to control the synchronous generation circuit to output the synchronous output signal, and at the same time controlling the synchronous generation circuit through the delay control value to adjust the delay of the synchronous output signal;

[0019] The synchronous output signal output by the synchronous generating circuit is used as the reset signal of the frequency divider, and the frequency divider is controlled to output the clock output signal in conjunction with the clock input signal, and the frequency division ratio of the frequency divider is adjusted by the frequency division control value.

[0020] In one or more embodiments of the present invention, the synchronization input signal is a pulse signal and the high level duration of the synchronization input signal is greater than the clock period of the clock input signal.

[0021] In one or more embodiments of the present invention, the method of using the synchronization input signal as a reset signal of the synchronization generating circuit and controlling the synchronization generating circuit to output the synchronization output signal in conjunction with the clock input signal, and controlling the synchronization generating circuit by the delay control value to adjust the delay of the synchronization output signal includes:

[0022] The counter is reset within a preset time by using a synchronous input signal in conjunction with a clock input signal, and the frequency of the output signal of the counter after reset is controlled by a delay control value;

[0023] Using the output signal of the counter as a sampling clock signal for the first flip-flop and the second flip-flop;

[0024] Sampling the power supply voltage signal based on the output signal of the reset counter by the first trigger;

[0025] The signal output by the first flip-flop is sampled by the second flip-flop based on the output signal after the counter is reset.

[0026] In one or more embodiments of the present invention, an OR logic operation is performed on the output signal of the second flip-flop and the synchronous input signal through an OR gate to generate a synchronous output signal.

[0027] In one or more embodiments of the present invention, the delay control value is configured via a delay register; and / or

[0028] The frequency division control value is configured through the frequency division register.

[0029] Compared with the prior art, the clock signal generating system and the clock signal generating method of the present invention generate corresponding synchronous output signals based on the clock input signal and the synchronous input signal through the synchronous generating circuit, and at the same time, the high-level duration of the synchronous output signal can be adjusted by adjusting the delay control value. Then, when the divider generates the clock output signal based on the clock input signal, the synchronous output signal and the frequency division control value, the change in the high-level duration of the synchronous output signal causes the phase difference between each clock output signal to change, thereby achieving the purpose of phase synchronization or adjustable phase difference between each clock output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 Schematic diagram of a 14-output clock buffer in the prior art.

[0032] Figure 2 This is a partial output waveform diagram of a 14-output clock buffer in the prior art.

[0033] Figure 3 Schematic diagram of a frequency divider with a frequency division ratio of D in the prior art.

[0034] Figure 4 4 is an input and output waveform diagram of a divide-by-4 frequency divider in the prior art.

[0035] Figure 5 This is a clock circuit diagram composed of two chips in the prior art.

[0036] Figure 6 FIG. 4 is a circuit diagram of a clock signal generating system according to an embodiment of the present invention.

[0037] Figure 7 FIG. 4 is a circuit schematic diagram of a synchronization generating circuit in an embodiment of the present invention.

[0038] Figure 8 FIG. 1 is a waveform diagram of a synchronization generating circuit in an embodiment of the present invention.

[0039] Figure 9 FIG. 1 is a partial waveform diagram of a clock signal generating system in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0041] The terms "coupled," "connected," or "connected" as used in this specification encompass both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrically conductive medium, which may have parasitic inductance or capacitance. An indirect connection may also include a connection through other active or passive devices, such as switches, follower circuits, or other circuits or components, to achieve the same or similar functional objectives. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another and do not necessarily require or imply a specific relationship, quantity, or order between these technical features.

[0042] In the detailed description of the specification, reference is made to the accompanying drawings forming a part hereof, wherein like reference numerals designate like parts throughout, and wherein exemplary embodiments that may be implemented are shown by way of example. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present application. Therefore, the following detailed description should not be construed in a limiting sense.

[0043] The various operations in the specification may be described as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0044] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0045] Various components and devices may be referred to or shown in the singular form in this document (for example, "MOS tube", "transistor", "switch", etc.), but this is only for convenience of discussion, and any element referred to in the singular form may include multiple such elements according to the teachings of this document.

[0046] The specification uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," which can each refer to one or more of the same or different embodiments. In addition, the terms "including," "comprising," "having," etc. used in relation to the embodiments of this application are synonymous.

[0047] like Figure 6 As shown, a clock signal generating system in one embodiment of the present invention includes: multiple clock units, each clock unit can be considered as a separate clock chip or a different group within the same chip, and all clock units generate a set of clock output signals.

[0048] Each clock unit includes a synchronization generating circuit 10 and a frequency divider 20. The clock input end of each synchronization generating circuit 10 and the clock input end of the frequency divider 20 are both used to receive the clock input signal CKIN. The reset end of each synchronization generating circuit 10 is both used to receive the synchronization input signal SYNC. The delay control end of each synchronization generating circuit 10 is used to receive its own delay control value RG_DLY. The reset end of each frequency divider 20 is connected to the output end of the corresponding synchronization generating circuit 10. The frequency division control end of each frequency divider 20 is used to receive its own frequency division control value RG_DIV. Each synchronization generating circuit 10 generates a corresponding synchronization output signal based on the clock input signal CKIN, the synchronization input signal SYNC and its own delay control value RG_DLY. Each frequency divider 20 generates a corresponding clock output signal based on the clock input signal CKIN, the synchronization output signal and its own frequency division control value RG_DIV.

[0049] Figure 6 The illustrated clock signal generation system comprises 14 clock cells CELL0 through CELL13, correspondingly comprising 14 synchronization generation circuits 10 and 14 frequency dividers 20. The 14 synchronization generation circuits 10 receive 14 delay control values ​​RG_DLY0<12:0> through RG_DLY13<12:0>, respectively, and output 14 synchronization output signals SYNC_OUT0 through SYNC_OUT13, respectively. The 14 frequency dividers 20 receive 14 division control values ​​RG_DIV0<12:0> through RG_DIV13<12:0>, respectively, and output 14 clock output signals CKOUT0 through CKOUT13, respectively. In other embodiments, the number of clock cells may be increased or decreased as needed.

[0050] The 14 delay control values ​​RG_DLY0<12:0> to RG_DLY13<12:0> are configured by corresponding 14 13-bit delay registers. Each delay register can be set to the same value or different values. In other embodiments, the delay registers can also be delay registers of other bit numbers.

[0051] The 14 frequency division control values ​​RG_DIV0<12:0> to RG_DIV13<12:0> are configured by corresponding 14 13-bit frequency division registers. The frequency division control values ​​determine the division ratio of the frequency division registers. Each frequency division register can be set to the same value or different values. For example, when the frequency division control value is configured to 0000000001000 (binary), the division ratio is 8 (decimal). In one embodiment, the frequency division registers can be SPI bus configuration registers or I2C bus configuration registers. In other embodiments, the frequency division registers can also be frequency division registers with other bit numbers.

[0052] The values ​​set in the delay register and the frequency divider register can control the clock output signal of one channel to produce a different phase difference and output frequency relative to the clock output signals of other channels (different frequency divider register configurations), or to produce different phase differences and the same output frequency (same frequency divider register configurations). For example, if the frequency divider control values ​​RG_DIV0<12:0> and RG_DIV5<12:0> are both set to 5, and the delay control values ​​RG_DLY0<12:0> and RG_DLY5<12:0> are set to 2 and 3, respectively, there will be a delay accuracy error between the clock output signals CKOUT0 and CKOUT5. This delay accuracy is generally equal to the period of the clock input signal CKIN, and the frequency of the clock output signals CKOUT0 and CKOUT5 will be the same.

[0053] like Figure 7 As shown, the structure of the synchronization generating circuit 10 of the first clock unit CELL0 is taken as an example for description. The synchronization generating circuit 10 includes a counter COUNTER, a first flip-flop DFF1, a second flip-flop DFF2 and an OR gate OR.

[0054] A clock input terminal of the counter COUNTER is used to receive a clock input signal CKIN. A reset terminal RST of the counter COUNTER is used to receive a synchronization input signal SYNC (the synchronization input signal SYNC serves as a reset signal of the counter COUNTER). A delay control terminal DLY of the counter COUNTER is used to receive a delay control value RG_DLY0<12:0>. A clock input terminal of a first flip-flop DFF1 and a clock input terminal of a second flip-flop DFF2 are connected to an output terminal of the counter COUNTER to receive an output signal CKI of the counter COUNTER. A D input terminal of the first flip-flop DFF1 is used to receive a power supply voltage signal VDD, which is a high-level signal. A D input terminal of the second flip-flop DFF2 is connected to a Q output terminal of the first flip-flop DFF1. A first input terminal of an OR gate OR is used to receive the synchronization input signal SYNC. A second input terminal of the OR gate OR is connected to a QB output terminal of the second flip-flop DFF2 to receive an output signal SYNC_DLY of the second flip-flop DFF2. An output terminal of the OR gate OR is connected to a reset terminal of a frequency divider 20. The output terminal of the OR gate OR generates a synchronization output signal SYNC_OUT0.

[0055] In addition, when the phases of the clock output signals output by two or more clock units need to be completely consistent, the path formed by the counter COUNTER, the first flip-flop DFF1, and the second flip-flop DFF2 in the corresponding clock units can be turned off, so that the synchronization generating circuit 10 outputs a synchronization output signal that is identical to the synchronization input signal SYNC. Conversely, when the clock output signals output by two or more clock units need to have a certain phase difference, the path formed by the counter COUNTER, the first flip-flop DFF1, and the second flip-flop DFF2 in the corresponding clock units can be turned on. In other embodiments, if it is not necessary to maintain the phases of the clock output signals output by the corresponding clock units, the OR gate can be omitted.

[0056] like Figure 8 As described above, the clock input signal CKIN is a high-frequency clock signal, the synchronization input signal SYNC is a pulse signal, and the effective level (high level) duration of the synchronization input signal SYNC is much longer than the clock cycle of the clock input signal CKIN.

[0057] When the synchronous input signal SYNC changes from low level to high level, the counter COUNTER is in reset state and its output signal CKI is pulled low; when the synchronous input signal SYNC changes from high level to low level, the reset of the counter COUNTER is released and it starts to work normally. At this time, the output signal CKI is normally output at the next rising edge of the clock input signal CKIN after the synchronous input signal SYNC changes from high level to low level. The frequency of the normally output output signal CKI is the waveform after the frequency division of the clock input signal CKIN, that is, the period T of the output signal CKI. CKI =N*T CKIN , where T CKIN is the clock period of the clock input signal CKIN. The division ratio N is determined by the delay control value RG_DLY<12:0> configured in the delay register.

[0058] The waveform of the output signal SYNC_DLY of the second flip-flop DFF2 is high when the synchronization input signal SYNC is in a high state. When the synchronization input signal SYNC switches from a high level to a low level, the first flip-flop DFF1 starts sampling the power supply voltage signal VDD through the output signal CKI, and the second flip-flop DFF2 starts sampling the output signal generated by the Q output terminal of the first flip-flop DFF1 through the output signal CKI. After two consecutive rising edges of the output signal CKI, the output signal SYNC_DLY of the second flip-flop DFF2 is pulled to a low level. After the synchronization input signal SYNC and the output signal SYNC_DLY of the second flip-flop DFF2 pass through the OR gate, the final synchronization output signal SYNC_OUT0 is output. Compared with the synchronization input signal SYNC, the duration of the high level of the synchronization output signal SYNC_OUT0 is extended by N T CKIN cycle.

[0059] In one embodiment, the frequency divider 20 may be formed by cascading a plurality of divide-by-2 / 3 frequency division units or by a PS counter (pulse swallowing counter).

[0060] Combine Figure 6 ,like Figure 9 As shown, taking the clock unit CELL0 and the clock unit CELL5 as an example, the clock input signal CKIN is a GHz clock signal, the input synchronization input signal SYNC is a pulse signal, and the high level duration of the pulse waveform is much longer than the clock period of the clock input signal CKIN. After the synchronization input signal SYNC passes through the synchronization generating circuit 10 of the clock unit CELL0, the synchronization output signal SYNC_OUT0 is generated. The high level duration of the synchronization output signal SYNC_OUT0 is extended by 2 T compared with the synchronization input signal SYNC. CKIN cycles (delay control value RG_DLY0<12:0> is configured as 2, and 2 T CKIN The synchronous input signal SYNC generates a synchronous output signal SYNC_OUT5 after passing through the synchronous generating circuit 10 of the clock unit CELL5. The high level duration of the synchronous output signal SYNC_OUT5 is extended by 3 T relative to the synchronous input signal SYNC. CKIN cycles (delay control value RG_DLY0<12:0> is configured as 3, and 3 T CKIN extension of the cycle).

[0061] Since the frequency division control value RG_DIV0<12:0> and the frequency division control value RG_DIV5<12:0> are both 5, the clock output signal CKOUT0 and the clock output signal CKOUT5 are both clock signals obtained by dividing the clock input signal CKIN by 5.

[0062] Before the arrival of the high-level pulse of the synchronization input signal SYNC, the phases of the clock output signal CKOUT0 and the clock output signal CKOUT5 are in an asynchronous state. When the synchronization input signal SYNC switches from a low level to a high level, the clock output signal CKOUT0 and the clock output signal CKOUT5 are both pulled down to a low level and are in a reset state. After the synchronization output signal SYNC_OUT0 switches from a high level to a low level, the frequency divider 20 of the clock unit CELL0 starts to work normally. Next, when the first rising edge of the clock input signal CKIN appears, it triggers the generation of the first rising edge of the clock output signal CKOUT0; similarly, after the synchronization output signal SYNC_OUT5 switches from a high level to a low level, the frequency divider 20 of the clock unit CELL5 starts to work normally. Next, when the first rising edge of the clock input signal CKIN appears, it triggers the generation of the first rising edge of the clock output signal CKOUT5. At this time, the clock output signal CKOUT0 and the clock output signal CKOUT5 generate a repeatable fixed phase difference, which is equal to a delay accuracy, that is, a T CKIN cycle.

[0063] Combine Figures 6 to 9 The present invention also discloses a clock signal generating method, comprising:

[0064] The synchronization input signal SYNC is used as a reset signal for the synchronization generation circuit 10 of each clock unit, and is coordinated with the clock input signal CKIN to control the synchronization generation circuit 10 to output a synchronization output signal. Furthermore, the synchronization generation circuit 10 is controlled by a delay control value to adjust the delay of the synchronization output signal. The delay control value is configured via a delay register. In one embodiment, the synchronization input signal SYNC is a pulse signal, and the duration of the high level of the synchronization input signal SYNC is much longer than the clock period of the clock input signal CKIN.

[0065] The plurality of synchronization generating circuits 10 output a set of synchronization output signals SYNC_OUT0 ˜SYNC_OUTn. The high level duration of each synchronization output signal relative to the synchronization input signal SYNC is controlled by a corresponding delay control value.

[0066] The synchronous output signal output by the synchronous generating circuit 10 of each clock unit cooperates with the clock input signal CKIN to control the corresponding clock unit's divider 20 to output the clock output signal, and the dividing ratio of the divider 20 is adjusted by the dividing control value, and the dividing control value is configured by the dividing register.

[0067] The frequency dividers 20 output a set of clock output signals CKOUT0 -CKOUTn. The phase difference between the clock output signals is determined by the high level duration of the corresponding synchronous output signals relative to the synchronous input signal SYNC and the frequency division control value.

[0068] Furthermore, in combination with the specific circuit of a single synchronization generating circuit 10, the above-mentioned “using the synchronization input signal SYNC as the reset signal of the synchronization generating circuit and cooperating with the clock input signal CKIN to control the synchronization generating circuit 10 to output the synchronization output signal, and controlling the synchronization generating circuit 10 by the delay control value to adjust the delay of the synchronization output signal” includes:

[0069] The counter COUNTER is reset within a preset time by the synchronous input signal SYNC and the clock input signal CKIN, and the frequency of the output signal CKI of the counter COUNTER is controlled by the delay control value after the reset (ie, the frequency division ratio of the counter COUNTER is controlled by the delay control value RG_DLY).

[0070] The output signal CKI of the counter COUNTER is used as a sampling clock signal of the first flip-flop DFF1 and the second flip-flop DFF2.

[0071] The power supply voltage signal VDD is sampled by the first flip-flop DFF1 based on the output signal CKI after the counter COUNTER is reset;

[0072] The signal output by the first flip-flop DFF1 is sampled by the second flip-flop DFF2 based on the output signal CKI after the counter COUNTER is reset.

[0073] An OR logic operation is performed on the output signal SYNC_DLY of the second flip-flop DFF2 and the synchronous input signal SYNC through an OR gate OR to generate a synchronous output signal.

[0074] As can be seen from the above, by cooperating with the counter COUNTER through the first trigger DFF1 and the second trigger DFF2, and by setting the division ratio of the counter COUNTER, the high-level duration of the final output synchronous output signal can be extended on the basis of the synchronous input signal SYNC. The extension time of each synchronous output signal is different, which also determines the phase difference between the subsequent clock output signals. Therefore, the phase difference between the clock output signals can be adjusted by adjusting the delay control value.

[0075] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0076] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A clock signal generating system, characterized in that: include: Multiple clock units; The clock unit includes a synchronization generating circuit and a frequency divider. The clock input end of each synchronization generating circuit and the clock input end of the frequency divider are both used to receive a clock input signal. The reset end of each synchronization generating circuit is both used to receive a synchronization input signal. The delay control end of each synchronization generating circuit is used to receive a respective delay control value. The reset end of each frequency divider is connected to the output end of the corresponding synchronization generating circuit. The frequency division control end of each frequency divider is used to receive a respective frequency division control value. Each synchronization generating circuit generates a corresponding synchronization output signal based on the clock input signal, the synchronization input signal and the delay control value. Each frequency divider generates a clock output signal based on the clock input signal, the synchronization output signal and the frequency division control value. The synchronization generating circuit includes a counter, a first trigger and a second trigger. The clock input end of the counter is used to receive the clock input signal, the reset end of the counter is used to receive the synchronization input signal, the delay control end of the counter is used to receive the delay control value, the clock input end of the first trigger and the clock input end of the second trigger are connected to the output end of the counter, the D input end of the first trigger is used to receive a power supply voltage signal, and the D input end of the second trigger is connected to the Q output end of the first trigger.

2. The clock signal generating system according to claim 1, wherein: The synchronization generating circuit further includes an OR gate, wherein the first input end of the OR gate is used to receive a synchronization input signal, the second input end of the OR gate is connected to the QB output end of the second trigger, and the output end of the OR gate is connected to the reset end of the frequency divider.

3. The clock signal generating system according to claim 1, wherein: The synchronous input signal is a pulse signal, and the high level duration of the synchronous input signal is greater than the clock period of the clock input signal.

4. The clock signal generating system according to claim 1, wherein: The clock unit further includes a delay register, wherein the delay register is used to configure a delay control value; and / or The clock unit further includes a frequency division register, and the frequency division register is used to configure a frequency division control value.

5. A clock signal generating method, based on the clock signal generating system according to any one of claims 1 to 4, characterized in that: The clock signal generating method comprises: By using the synchronous input signal as the reset signal of the synchronous generation circuit and cooperating with the clock input signal to control the synchronous generation circuit to output the synchronous output signal, and at the same time controlling the synchronous generation circuit through the delay control value to adjust the delay of the synchronous output signal; The synchronous output signal output by the synchronous generating circuit is used as the reset signal of the frequency divider, and the frequency divider is controlled to output the clock output signal in conjunction with the clock input signal, and the frequency division ratio of the frequency divider is adjusted by the frequency division control value.

6. The clock signal generating method according to claim 5, wherein: The synchronous input signal is a pulse signal, and the high level duration of the synchronous input signal is greater than the clock period of the clock input signal.

7. The clock signal generating method according to claim 5, wherein: The method of using the synchronization input signal as a reset signal of the synchronization generating circuit and cooperating with the clock input signal to control the synchronization generating circuit to output the synchronization output signal, and controlling the synchronization generating circuit by a delay control value to adjust the delay of the synchronization output signal comprises: The counter is reset within a preset time by using a synchronous input signal in conjunction with a clock input signal, and the frequency of the output signal of the counter after reset is controlled by a delay control value; Using the output signal of the counter as a sampling clock signal for the first flip-flop and the second flip-flop; Sampling the power supply voltage signal based on the output signal of the reset counter by the first trigger; The signal output by the first flip-flop is sampled by the second flip-flop based on the output signal after the counter is reset.

8. The clock signal generating method according to claim 7, wherein: An OR logic operation is performed on the output signal of the second trigger and the synchronous input signal through an OR gate to generate a synchronous output signal.

9. The clock signal generating method according to claim 5, wherein: Configuring the delay control value via the delay register; and / or The frequency division control value is configured through the frequency division register.

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