Debugging mode switching method and device, electronic equipment and storage medium
By generating a new protocol and adjusting the mode switching protocol of the downloader, the problem of false triggering during mode switching in the prior art is solved, and a more stable communication process is achieved.
Patent Information
- Application Number
- CN202510278333.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-10
- Publication Date
- 2025-06-20
AI Technical Summary
In the prior art, when switching the downloader mode, the number of TMSC pulses is small during the TCKC high level, which is prone to incorrect triggering and affecting normal communication.
A new protocol (second protocol) is generated, which includes a second number of detection intervals in the first clock state and a third number of detection intervals in the second clock state, and the second number is greater than the first number, and mode switching is performed by adjusting the protocol.
It effectively avoids mistriggering during mode switching and ensures that the communication is carried out normally.
Smart Images
Figure CN120179485A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of downloaders, and in particular, to a method, device, electronic device, and storage medium for switching a debugging mode. Background Art
[0002] A downloader is a device used to write program code or firmware into non-volatile memories such as microcontrollers, FPGAs, and EPROMs. A downloader is also known as a programmer or burner, and its basic functions include data transmission, programming, and verification. Downloaders have different download modes, such as two-wire mode and four-wire mode, and the main difference lies in the number and functions of the download channels they use.
[0003] In the prior art, when switching the mode of a downloader, two signals, TCKC and TMSC, are mainly used. During the high level of TCKC, three TMSC pulses are continuously sent, and the switch from CJTAG to JTAG can be completed, that is, the switch from two-wire to four-wire mode. During the period when TCKC maintains a high level, the number of TMSC pulses is small, which is likely to cause false triggering during normal communication. Summary of the Invention
[0004] In view of this, the purpose of the present application is to provide a method, device, electronic device, and storage medium for switching a debugging mode to overcome the problems in the prior art.
[0005] In a first aspect, an embodiment of the present application provides a method for switching a debugging mode, which acts on a downloader to be debugged; the downloader to be debugged switches modes based on a first protocol; wherein, the first protocol includes a first number of detection intervals in a first clock state; the method includes: Generating a second protocol according to actual service requirements; wherein, the second protocol includes a second number of detection intervals in a first clock state and a third number of detection intervals in a second clock state; wherein, the second number is greater than the first number; Adjusting the mode of the downloader to be debugged based on the second protocol, so that the downloader to be debugged communicates and works in the adjusted mode.
[0006] In some technical solutions of the present application, the above-mentioned first protocol includes: a first clock signal and a first data signal; the second protocol includes a second clock signal and a second data signal; The generating a second protocol according to actual service requirements; wherein, the second protocol includes a second number of detection intervals in a first clock state and a third number of detection intervals in a second clock state; wherein, the second number is greater than the first number; includes: Using the first clock signal as the second data signal; Use the first data signal as the second clock signal; wherein, the second clock signal is used to sample the second data signal.
[0007] In some technical solutions of the present application, the above first clock state is a high level state, and the second clock state is a low level state; The second clock signal samples the second data signal in the following manner: When the second data signal is in a high level state, perform data acquisition on the second data signal for a first number of times to obtain a first acquisition result; When the second data signal is in a low level state, perform data acquisition on the second data signal for a third number of times to obtain a second acquisition result.
[0008] In some technical solutions of the present application, the above-mentioned to-be-debugged downloader is connected to a state machine; the method further includes: Send the second protocol to the state machine and receive the reset signal sent by the state machine; After the first acquisition result and the second acquisition result are confirmed to be correct, perform mode adjustment according to the reset signal.
[0009] In some technical solutions of the present application, the above-mentioned after the first acquisition result and the second acquisition result are confirmed to be correct, perform mode adjustment according to the reset signal, including: After the first acquisition result and the second acquisition result are confirmed to be correct, and when the reset signal switches from a low level to a high level, perform mode adjustment.
[0010] In some technical solutions of the present application, the above-mentioned perform mode adjustment on the to-be-debugged downloader based on the second protocol so that the to-be-debugged downloader communicates in the adjusted mode, including: Based on the second protocol, adjust the to-be-debugged downloader from a two-wire mode to a four-wire mode so that the to-be-debugged downloader communicates in the four-wire mode.
[0011] In a second aspect, an embodiment of the present application provides a method for switching a debugging mode, which acts on a state machine. The state machine is connected to a to-be-debugged downloader, and the to-be-debugged downloader performs mode switching based on a first protocol; wherein, the first protocol includes a first number of detection intervals in a first clock state; the method includes: Receive the second protocol sent by the downloader to be debugged; wherein, the second protocol is obtained in the following manner: generate the second protocol according to actual service requirements; wherein, the second protocol includes a second number of detection intervals in the first clock state and a third number of detection intervals in the second clock state; wherein, the second number is greater than the first number; Generate a reset signal according to the second protocol, and send the reset signal to the downloader to be debugged, so that the downloader to be debugged performs mode adjustment based on the second protocol and the reset signal, and communicates in the adjusted mode.
[0012] In a third aspect, an embodiment of the present application provides a device for switching the debugging mode, which acts on the downloader to be debugged; the downloader to be debugged switches modes based on the first protocol; wherein, the first protocol includes a first number of detection intervals in the first clock state; the device includes: A generation module, configured to generate a second protocol according to actual service requirements; wherein, the second protocol includes a second number of detection intervals in the first clock state and a third number of detection intervals in the second clock state; wherein, the second number is greater than the first number; An adjustment module, configured to adjust the mode of the downloader to be debugged based on the second protocol, so that the downloader to be debugged communicates in the adjusted mode.
[0013] In a fourth aspect, an embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the computer program, the steps of the above method for switching the debugging mode are implemented.
[0014] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is run by a processor, the steps of the above method for switching the debugging mode are executed.
[0015] The technical solution provided by the embodiment of the present application may include the following beneficial effects: The method of the present application acts on the downloader to be debugged; the downloader to be debugged switches modes based on the first protocol; wherein, the first protocol includes a first number of detection intervals in the first clock state; specifically: generate a second protocol according to actual service requirements; wherein, the second protocol includes a second number of detection intervals in the first clock state and a third number of detection intervals in the second clock state; wherein, the second number is greater than the first number; adjust the mode of the downloader to be debugged based on the second protocol, so that the downloader to be debugged communicates in the adjusted mode.
[0016] This application adjusts the original protocol in the downloader to be debugged, generates a new protocol according to the actual business requirements, adjusts the mode based on the new protocol, and confirms the adjustment process multiple times, effectively avoiding mis-triggering.
[0017] To make the above objects, features, and advantages of this application more obvious and understandable, the following provides preferred embodiments in conjunction with the accompanying drawings and describes them in detail as follows. Brief Description of the Drawings
[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the following briefly introduces the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other relevant drawings can be obtained based on these drawings.
[0019] Figure 1 Shows a schematic flowchart of a method for switching debugging modes provided by an embodiment of this application; Figure 2 Shows a schematic diagram of a first protocol provided by an embodiment of this application; Figure 3 Shows a schematic diagram of a second protocol provided by an embodiment of this application; Figure 4 Shows a schematic diagram of a state machine provided by an embodiment of this application; Figure 5 Shows a schematic diagram of a device for switching debugging modes provided by an embodiment of this application; Figure 6 Shows a schematic structural diagram of an electronic device provided by an embodiment of this application. Detailed Embodiments
[0020] To make the objects, technical solutions, and advantages of the embodiments of this application clearer, the following will clearly and completely describe the technical solutions in the embodiments of this application in conjunction with the drawings in the embodiments of this application. It should be understood that the drawings in this application only serve the purpose of illustration and description and are not used to limit the protection scope of this application. Additionally, it should be understood that the schematic drawings are not drawn to actual scale. The flowcharts used in this application show the operations implemented according to some embodiments of this application. It should be understood that the operations in the flowchart may not be implemented in sequence, and steps without logical context relationships may be reversed or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart or remove one or more operations from the flowchart under the guidance of the content of this application.
[0021] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all embodiments. The components of the embodiments of the present application usually described and illustrated in the accompanying drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but merely represents the selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.
[0022] It should be noted that the term "including" will be used in the embodiments of the present application to indicate the existence of the features stated thereafter, but does not exclude adding other features.
[0023] A downloader is a device used to write program code or firmware into non-volatile memories such as microcontrollers, FPGAs, and EPROMs. The downloader is also known as a programmer or burner, and its basic functions include data transfer, programming, and verification. The downloader has different download modes, such as two-wire mode and four-wire mode, and the main difference lies in the number of download channels used and their functions.
[0024] In the prior art, when switching the mode of the downloader, two signals, TCKC and TMSC, are mainly used. During the high level of TCKC, three consecutive TMSC pulses are sent to complete the switch from CJTAG to JTAG, that is, from 2-wire to 4-wire mode. During the period when TCKC maintains a high level, the number of TMSC pulses is small, which is likely to cause false triggering during normal communication.
[0025] Based on this, the embodiments of the present application provide a method, device, electronic device, and storage medium for switching debug modes, which will be described below through embodiments.
[0026] Figure 1 The flowchart of a method for switching debug modes provided by the embodiments of the present application is shown. Among them, this method acts on the downloader to be debugged; the downloader to be debugged switches modes based on the first protocol; among them, the first protocol includes a first number of detection intervals in the first clock state; it includes steps S101 - S102; specifically: S101. Generate a second protocol according to the actual business requirements; among them, the second protocol includes a second number of detection intervals in the first clock state and a third number of detection intervals in the second clock state; among them, the second number is greater than the first number; S102. Adjust the mode of the downloader to be debugged based on the second protocol, so that the downloader to be debugged communicates and works in the adjusted mode.
[0027] This application adjusts the original protocol in the downloader to be debugged, generates a new protocol according to actual business requirements, adjusts the mode based on the new protocol, and confirms the adjustment process multiple times to effectively avoid mis-triggering.
[0028] The following will detail some embodiments of this application. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.
[0029] The method for switching the debug mode in this application mainly involves a state machine and a downloader to be debugged. The downloader to be debugged is a system that satisfies the three characteristics of a finite state machine, including states, events, and actions. The states of the downloader to be debugged include loading, downloading, pausing, completion, or failure, etc. These states trigger state transitions through events, and actions are optional. A state machine is a directed graph composed of a set of states and a set of corresponding actions, and the state machine runs by responding to a series of actions.
[0030] Before executing the method in this application on the downloader to be debugged, the downloader to be debugged switches modes through the existing first protocol; wherein, the first protocol includes: a first clock signal and a first data signal, and the first protocol includes a first number of detection intervals in the first clock state. Specifically, the modes of the downloader to be debugged here include a two-wire mode and a four-wire mode. The downloader to be debugged can switch from the two-wire mode to the four-wire mode based on the first protocol.
[0031] Specifically, the first protocol is as Figure 2 shown, including a first clock signal: the TCKC signal and a first data signal: the TMSC signal. Among them, TCKC includes a high-level state and a low-level state, and TMSC has three consecutive pulses, and all these three pulses are in the high-level state of TCKC. During these three pulses, the downloader to be debugged can switch from the two-wire mode (CJTAG) to the four-wire mode (JTAG).
[0032] When the embodiment of this application switches the mode of the downloader to be debugged, it is necessary to first adjust the protocol of the downloader to be debugged: adjust the original first protocol in the downloader to be debugged to a new second protocol. Among them, the second protocol includes a second number of detection intervals in the first clock state and a third number of detection intervals in the second clock state; wherein, the second number is greater than the first number. The adjustment of the first protocol here includes improving on the basis of the original first protocol, or deleting the original first protocol and reconfiguring the second protocol, or after configuring the second protocol, using the second protocol to overwrite the first protocol, etc.
[0033] When generating the second protocol, the embodiments of the present application are based on actual business requirements. For example, when the actual business requirements are strict, the generated second quantity and third quantity are larger; when the actual business requirements are relaxed, the generated second quantity and third quantity are smaller. It should be noted that the smaller second quantity is still larger than the first quantity.
[0034] Specifically, the second protocol in the embodiments of the present application includes a second clock signal, a second data signal, and a reset signal. Among them, the reset signal is generated by the state machine after the debugging downloader configures the second protocol and sends the second protocol to the state machine. The second clock signal is the first data signal, and the second data signal is the first clock signal. The second clock signal is used to sample the second data signal. The second clock signal is used to sample the second data signal.
[0035] Furthermore, the second clock signal samples the second data signal in the following manner: when the second data signal is in the high-level state, data is collected a first number of times for the second data signal to obtain a first collection result; when the second data signal is in the low-level state, data is collected a third number of times for the second data signal to obtain a second collection result. After obtaining the first collection result and the second collection result, a correctness judgment is made on the first collection result and the second collection result: determine whether a mode switch is actually required. After determining that both the first collection result and the second collection result require a mode switch, a mode switch is performed at a preset moment. Here, the preset moment is determined by the reset signal. The reset signal includes a high-level state and a low-level state. The specific mode switch moment is the moment when the reset signal switches from the low level to the high level.
[0036] The specific switching process is as Figure 3 and Figure 4 shown. The debugging module switches from the 2-wire mode to the 4-wire mode following the protocol as follows. Through the design of the state machine, it can be ensured that the switching logic will not be accidentally triggered during normal communication, and at the same time, it can also be ensured that the mode switch can be successfully completed during the switching process.
[0037] Use TMS as the trigger event to be treated as a clock, and then sample TCK. TCK (Test Clock) is the test clock signal used to synchronize operations on the JTAG interface. It samples and updates data at the rising or falling edge of each clock cycle to achieve synchronous data transmission on the JTAG interface. TCK provides a basic clock signal for TAP (Test Access Port) operations, and all operations are driven by this clock signal. TMS (Test Mode Select) is the test mode select signal used to control the transition of the JTAG state machine. By inputting different values for TMS at each TCK clock cycle, the state of the JTAG state machine can be changed, thus selecting different test or operation modes. The level change of the TMS signal determines whether the state of the state machine changes. For example, in the Test-Logic-Reset state, as long as TMS remains high and lasts for 5 TCK clocks, the state machine will definitely return to the Test-Logic-Reset state.
[0038] To ensure the stability of the state machine design: IDLE state, the default state when the debug module is powered on. CHECK state, the state for detecting before switching to the debug mode. RESET state, the debug mode generates a soft reset signal in the 2-wire mode, and an asynchronous reset operation is performed at this time. END state, the asynchronous reset ends, and the debug module is in the 4-wire mode at this time.
[0039] 1. IDLE: The default state when powered on is IDLE. When it is detected that TCK is 1 at the rising edge of TMS, it enters the CHECK state. Otherwise, it remains in the IDLE state all the time. During IDLE, the value of soft_rstn is equal to 1.
[0040] 2. CHECK: During the CHECK state, when it is detected that TCK is 1 at the rising edge of TMS, CNT is incremented until CNT counts up to 3 and then jumps to the RESET state. Otherwise, it remains in the CHECK state all the time. When it is detected that TCK is 0 at the rising edge of TMS, it jumps to the IDLE state.
[0041] During the CHECK state, the value of soft_rstn is equal to 1.
[0042] 3. RESET: During the RESET state, the value of soft_rstn is equal to 0. When it is detected that TCK is 0, the state machine jumps to the END state. Otherwise, the state machine remains in the RESET state all the time.
[0043] 4. END: The state machine jumps to the IDLE state, and the value of soft_rstn is equal to 1.
[0044] Figure 5The figure shows a schematic structural diagram of a device for switching a debugging mode provided by an embodiment of the present application, which acts on a downloader to be debugged; the downloader to be debugged switches modes based on a first protocol; wherein, the first protocol includes a first number of detection intervals in a first clock state; the device includes: A generation module, configured to generate a second protocol according to actual service requirements; wherein, the second protocol includes a second number of detection intervals in a first clock state and a third number of detection intervals in a second clock state; wherein, the second number is greater than the first number; An adjustment module, configured to adjust the mode of the downloader to be debugged based on the second protocol, so that the downloader to be debugged communicates and works in the adjusted model.
[0045] The first protocol includes: a first clock signal and a first data signal; the second protocol includes a second clock signal and a second data signal; The generating a second protocol according to actual service requirements; wherein, the second protocol includes a second number of detection intervals in a first clock state and a third number of detection intervals in a second clock state; wherein, the second number is greater than the first number; includes: Taking the first clock signal as the second data signal; Taking the first data signal as the second clock signal; wherein, the second clock signal is used to sample the second data signal.
[0046] The first clock state is a high level state, and the second clock state is a low level state; The second clock signal samples the second data signal in the following manner: When the second data signal is in a high level state, performing data acquisition on the second data signal for a first number of times to obtain a first acquisition result; When the second data signal is in a low level state, performing data acquisition on the second data signal for a third number of times to obtain a second acquisition result.
[0047] The downloader to be debugged is connected to a state machine; the method further includes: Sending the second protocol to the state machine and receiving a reset signal sent by the state machine; After confirming that the first acquisition result and the second acquisition result are correct, performing mode adjustment according to the reset signal.
[0048] The performing mode adjustment according to the reset signal after confirming that the first acquisition result and the second acquisition result are correct includes: After the first acquisition result and the second acquisition result are confirmed to be correct, and when the reset signal switches from low level to high level, mode adjustment is performed.
[0049] Performing mode adjustment on the to-be-debugged downloader based on the second protocol so that the to-be-debugged downloader communicates in the adjusted mode, including: Adjusting the to-be-debugged downloader from a two-wire mode to a four-wire mode based on the second protocol so that the to-be-debugged downloader communicates in the four-wire mode.
[0050] As Figure 6 shown, an embodiment of the present application provides an electronic device for executing the method of switching the debugging mode in the present application. The device includes a memory, a processor, a bus, and a computer program stored on the memory and executable on the processor. Wherein, when the above-mentioned processor executes the above-mentioned computer program, the steps of the above-mentioned method of switching the debugging mode are implemented.
[0051] Specifically, the above-mentioned memory and processor can be general memory and processor, and no specific limitation is made here. When the processor runs the computer program stored in the memory, it can execute the above-mentioned method of switching the debugging mode.
[0052] Corresponding to the method of switching the debugging mode in the present application, an embodiment of the present application further provides a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is run by a processor, the steps of the above-mentioned method of switching the debugging mode are executed.
[0053] Specifically, the storage medium can be a general storage medium, such as a mobile disk, a hard disk, etc. When the computer program on the storage medium is run, it can execute the above-mentioned method of switching the debugging mode.
[0054] In the embodiments provided by the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. The system embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there can be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point, the displayed or discussed coupling or direct coupling or communication connection between each other can be through some communication interfaces. The indirect coupling or communication connection of the system or unit can be in an electrical, mechanical or other form.
[0055] The unit described as a separation component may or may not be physically separated. The component shown as a unit may or may not be a physical unit, and it may be located in one place or distributed across multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0056] In addition, each functional unit in the embodiments provided in this application can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit.
[0057] If the described function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.
[0058] It should be noted that: similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and cannot be understood as indicating or implying relative importance.
[0059] Finally, it should be noted that: the above-described embodiments are only specific implementation manners of this application, used to illustrate the technical solution of this application, rather than limiting it. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: any person skilled in the art within the technical scope disclosed in this application can still modify the technical solutions described in the foregoing embodiments, or can easily think of changes, or perform equivalent replacements on some of the technical features; and these modifications, changes, or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.
Claims
1. A method for switching a debugging mode, characterized in that: Acting on a downloader to be debugged; the downloader to be debugged switches modes based on a first protocol; wherein the first protocol includes a first number of detection intervals in a first clock state; the method includes: Generate a second protocol according to actual business needs; wherein the second protocol includes a second number of detection intervals in the first clock state and a third number of detection intervals in the second clock state; wherein the second number is greater than the first number; The mode of the downloader to be debugged is adjusted based on the second protocol, so that the downloader to be debugged performs communication work in the adjusted mode.
2. The method according to claim 1, characterized in that The first protocol includes: a first clock signal and a first data signal; the second protocol includes a second clock signal and a second data signal; The generating of a second protocol according to actual business requirements; wherein the second protocol comprises a second number of detection intervals in a first clock state and a third number of detection intervals in a second clock state; wherein the second number is greater than the first number; comprising: Using the first clock signal as the second data signal; The first data signal is used as the second clock signal; wherein the second clock signal is used to sample the second data signal.
3. The method according to claim 2, characterized in that The first clock state is a high level state, and the second clock state is a low level state; The second clock signal samples the second data signal in the following manner: When the second data signal is in a high level state, performing data collection on the second data signal a first number of times to obtain a first collection result; When the second data signal is in a low level state, data collection is performed a third number of times on the second data signal to obtain a second collection result.
4. The method according to claim 3, characterized in that The downloader to be debugged is connected to a state machine; the method further includes: Sending the second protocol to the state machine, and receiving a reset signal sent by the state machine; After the first acquisition result and the second acquisition result are confirmed to be correct, the mode is adjusted according to the reset signal.
5. The method according to claim 4, characterized in that After the first acquisition result and the second acquisition result are confirmed to be correct, performing mode adjustment according to the reset signal includes: After the first acquisition result and the second acquisition result are confirmed to be correct, and when the reset signal is switched from a low level to a high level, the mode adjustment is performed.
6. The method according to claim 1, characterized in that The step of adjusting the mode of the downloader to be debugged based on the second protocol so that the downloader to be debugged performs communication work in the adjusted mode includes: The downloader to be debugged is adjusted from the two-wire mode to the four-wire mode based on the second protocol, so that the downloader to be debugged performs communication in the four-wire mode.
7. A method for switching a debugging mode, characterized in that: Acting on a state machine, the state machine is connected to a downloader to be debugged, and the downloader to be debugged performs mode switching based on a first protocol; wherein the first protocol includes a first number of detection intervals in a first clock state; the method includes: Receive a second protocol sent by the downloader to be debugged; wherein the second protocol is obtained by: generating the second protocol according to actual business needs; wherein the second protocol includes a second number of detection intervals in a first clock state and a third number of detection intervals in a second clock state; wherein the second number is greater than the first number; A reset signal is generated according to the second protocol, and the reset signal is sent to the downloader to be debugged, so that the downloader to be debugged performs mode adjustment based on the second protocol and the reset signal, and performs communication work in the adjusted model.
8. A device for switching a debugging mode, characterized in that: Acting on a downloader to be debugged; the downloader to be debugged switches modes based on a first protocol; wherein the first protocol includes a first number of detection intervals in a first clock state; the device includes: A generating module, configured to generate a second protocol according to actual business requirements; wherein the second protocol includes a second number of detection intervals in a first clock state and a third number of detection intervals in a second clock state; wherein the second number is greater than the first number; The adjustment module is used to adjust the mode of the downloader to be debugged based on the second protocol, so that the downloader to be debugged can communicate in the adjusted mode.
9. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the steps of the method for switching the debugging mode as described in any one of claims 1 to 7 are performed.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for switching the debugging mode as claimed in any one of claims 1 to 7 are executed.