Server power-on timeout monitoring system, method, medium, device and program product

Abstract

The present application discloses a server power-on timeout monitoring system, method, medium, device and program product, which relates to the field of computer technology, including a first controller that performs power-on timeout monitoring on different components according to the power-on sequence of different components in the server, obtains power-on timeout monitoring results of different components, and transmits the power-on timeout monitoring results to a second controller, which then performs abnormal analysis on the power-on timeout monitoring results to obtain abnormal analysis results. Since the power-on time of different components is inconsistent, segmented monitoring can accurately capture the specific power-on timeout conditions of different components, thereby improving the accuracy of power-on timeout monitoring on the server. Therefore, the technical problem of low accuracy of power-on timeout monitoring on the server can be solved, achieving the technical effect of improving the accuracy of power-on timeout monitoring on the server.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a server power-on timeout monitoring system, method, medium, device, and program product. Background Art

[0002] During the server power-on process, power-on timeouts may occur, which can affect the normal operation of the server. Therefore, it is necessary to monitor server power-on timeouts.

[0003] In the related technologies of server power-on timeout monitoring, the entire power-on time of the server is usually monitored. Since different components in the server are powered on in stages, the power-on times of different components are inconsistent, resulting in low accuracy of the server power-on timeout monitoring. Summary of the Invention

[0004] The present application provides a server power-on timeout monitoring system, method, medium, device and program product to at least solve the problem of low accuracy of server power-on timeout monitoring in related technologies.

[0005] The present application provides a server power-on timeout monitoring system, comprising: a first controller, a second controller;

[0006] The first controller is connected to the second controller;

[0007] The first controller performs power-on timeout monitoring on different components in sections according to the power-on sequence of different components in the server, obtains power-on timeout monitoring results of different components, and transmits the power-on timeout monitoring results to the second controller;

[0008] The second controller performs an abnormality analysis on the power-on timeout monitoring result to obtain an abnormality analysis result.

[0009] The present application also provides a server power-on timeout monitoring method, comprising:

[0010] Using the first controller to perform power-on timeout monitoring on different components in the server in sections according to the power-on sequence of different components, and obtain power-on timeout monitoring results of different components;

[0011] transmitting the power-on timeout monitoring result to the second controller using the first controller;

[0012] The second controller is used to perform abnormal analysis on the power-on timeout monitoring result to obtain an abnormal analysis result.

[0013] The present application also provides a server power-on timeout monitoring device, comprising:

[0014] The monitoring unit is configured to use the first controller to perform power-on timeout monitoring on different components in sections according to the power-on sequence of different components in the server, and obtain power-on timeout monitoring results of different components;

[0015] a transmission unit, configured to transmit a power-on timeout monitoring result to a second controller using the first controller;

[0016] The analyzing unit is used to use the second controller to perform abnormal analysis on the power-on timeout monitoring result to obtain an abnormal analysis result.

[0017] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned server power-on timeout monitoring methods when executing the computer program.

[0018] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned server power-on timeout monitoring methods are implemented.

[0019] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned server power-on timeout monitoring methods when executed by a processor.

[0020] Through this application, the first controller monitors the power-on timeouts of different components in the server according to the power-on order of the different components, obtains the power-on timeout monitoring results of the different components, and transmits the power-on timeout monitoring results to the second controller. The second controller then performs an exception analysis on the power-on timeout monitoring results to obtain an exception analysis result. Because the power-on times of different components are inconsistent, segmented monitoring can accurately capture the specific power-on timeout situations of different components, thereby improving the accuracy of the server's power-on timeout monitoring. Therefore, the technical problem of low accuracy of the server's power-on timeout monitoring can be solved, achieving the technical effect of improving the accuracy of the server's power-on timeout monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 A schematic diagram of the structure of a server power-on timeout monitoring system provided in an embodiment of the present application;

[0023] Figure 2A schematic diagram of the structure of another server power-on timeout monitoring system provided in an embodiment of the present application;

[0024] Figure 3 A schematic diagram of the connection relationship between different components provided in an embodiment of the present application;

[0025] Figure 4 A flowchart of the entire process of server power-on timeout monitoring provided in an embodiment of the present application;

[0026] Figure 5 A flow chart of a method for monitoring server power-on timeout provided in an embodiment of the present application;

[0027] Figure 6 This is a structural diagram of a server power-on timeout monitoring device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0030] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0031] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the server power-on timeout monitoring method depends, the specific application environment architecture or specific hardware architecture is described herein.

[0032] An embodiment of the present application provides a server power-on timeout monitoring system. The server power-on timeout monitoring system is described in detail in conjunction with the execution process of the server power-on timeout monitoring system.

[0033] Figure 1A schematic diagram of the structure of a server power-on timeout monitoring system provided in an embodiment of the present application is shown as follows: Figure 1 As shown, the server power-on timeout monitoring system includes: a first controller and a second controller.

[0034] The first controller is connected to the second controller.

[0035] The first controller can be a Complex Programmable Logic Device (CPLD), and the second controller can be a Baseboard Management Controller (BMC). However, it should be clear that this statement is not intended to limit the first controller to only a CPLD and the second controller to only a BMC. The first and second controllers can also be other components with control functions.

[0036] The first and second controllers can be connected via a universal hardware interface. The server's motherboard has a reserved interface slot, and each controller is equipped with a matching interface. By plugging each controller into the corresponding slot on the motherboard, they are physically connected. This interface connection method provides high data transmission rates, ensuring timely and accurate transmission of monitoring data between the two controllers.

[0037] The first controller performs power-on timeout monitoring on different components in sections according to the power-on sequence of different components in the server, obtains power-on timeout monitoring results of different components, and transmits the power-on timeout monitoring results to the second controller.

[0038] The power-on sequence refers to the order in which different components within a server receive power during the startup process. For example, the key power supply module on the motherboard is typically powered on first. Once it stabilizes, subsequent components such as expansion boards are powered on. Each component completes the power-on process in this predetermined order to ensure the entire server boots up properly. These components include, but are not limited to, voltage regulators, switch boards, and graphics processing unit (GPU) boards. The voltage regulator module regulates the voltage of various components within the server.

[0039] Segmented monitoring divides the entire power-on process into multiple phases. Each phase corresponds to a specific component, with independent timers and power-on timeout thresholds set for monitoring. The power-on timeout monitoring result is the first controller's assessment of the component power-on time during each monitoring phase, based on pre-set power-on time thresholds. If a component's power-on time exceeds the corresponding set power-on time threshold, it is considered to have timed out; otherwise, it is considered to have not timed out. The power-on timeout monitoring result contains information on the power-on status of each monitored component.

[0040] In order to facilitate a better understanding of the power-on timeout monitoring results, the detailed data of the power-on timeout monitoring results provided in the embodiment of the present application are as follows:

[0041] Table 1

[0042]

[0043] The hardware components in the server are powered on according to a preset power-on sequence. The first controller monitors the power-on process of each component one by one according to the preset power-on sequence. For each component, the first controller sets a predetermined power-on time limit (e.g., 5 seconds, 10 seconds, etc.). After a component begins powering on, the first controller monitors its power-on status in real time and records the start time. If a component fails to complete the power-on process within the specified time limit, the first controller determines a power-on timeout and generates a power-on timeout monitoring result for that component. The first controller compiles the power-on timeout monitoring results for each component and transmits them to the second controller via the communication interface.

[0044] By accurately monitoring the power-on process of each component, it is possible to promptly detect and respond to problems that may arise during the power-on process, such as hardware failures and incorrect power-on sequences, to prevent system startup failures.

[0045] The second controller performs an abnormality analysis on the power-on timeout monitoring result to obtain an abnormality analysis result.

[0046] Exception analysis involves the second controller analyzing received power-on timeout monitoring results, identifying possible causes of the anomaly, and generating a corresponding solution or report. Through exception analysis, the second controller can determine the severity of the problem and take appropriate measures, such as issuing an alarm, logging, or triggering automated processing. The exception analysis result is the data output by the second controller after analyzing the power-on timeout monitoring results. It typically includes the judgment basis during the analysis process, the anomaly type, the anomaly location, and the recommended treatment.

[0047] The second controller analyzes the received power-on timeout monitoring results one by one, identifying the cause of each component's timeout. This analysis process includes determining whether the timeout occurred in a specific component; determining whether the power-on failure was caused by a hardware fault; determining whether the timeout was caused by an unstable power supply, an incorrect power-on sequence, or external environmental factors. Based on the anomaly analysis results, the second controller identifies different types of anomalies, such as hardware failure, system configuration error, and unstable power supply. The system handles each anomaly differently. After anomaly analysis, the second controller generates an anomaly analysis result, including the anomaly type and cause analysis; potentially affected hardware components; and recommended remedial measures, such as restarting, replacing hardware, or adjusting power configuration. Based on the anomaly analysis result, the second controller can trigger appropriate response actions, such as issuing an alarm, logging, notifying the administrator, or performing recovery actions (such as power cycling or hardware recovery) according to predefined automated policies. All anomaly analysis processes and results are recorded in a log, and a report is generated for system administrators and maintenance personnel to review and analyze.

[0048] By analyzing the abnormality of the power-on timeout monitoring results, the second controller can quickly identify possible faults or abnormal conditions in the system, avoiding the time and cost of manual troubleshooting and improving fault diagnosis efficiency.

[0049] Through this application, the first controller monitors the power-on timeouts of different components in the server according to the power-on order of the different components, obtains the power-on timeout monitoring results of the different components, and transmits the power-on timeout monitoring results to the second controller. The second controller then performs an exception analysis on the power-on timeout monitoring results to obtain an exception analysis result. Because the power-on times of different components are inconsistent, segmented monitoring can accurately capture the specific power-on timeout situations of different components, thereby improving the accuracy of the server's power-on timeout monitoring. Therefore, the technical problem of low accuracy of the server's power-on timeout monitoring can be solved, achieving the technical effect of improving the accuracy of the server's power-on timeout monitoring.

[0050] In some embodiments, please refer to Figure 1 The first controller includes: a first monitoring module, a second monitoring module and a third monitoring module.

[0051] The first monitoring module monitors the power-on time of at least two first voltage regulating modules of the mainboard in different components when the first controller triggers the power-on.

[0052] The first monitoring module is specifically responsible for monitoring the power-up time of the first voltage regulator module on the motherboard. It integrates a timer, signal receiving and transmitting units, and a logic judgment unit. It can accurately capture key signals during the power-up process and accurately measure and determine the power-up time.

[0053] A triggered boot occurs when a user activates a server using a physical button (such as the power button on the server's front panel) or a software command (such as a power-on command sent through remote management software). This triggers the primary controller to awaken and begin powering on and initializing the server's internal components according to a pre-set sequence, gradually transitioning the server from a powered-off state to normal operation.

[0054] The first voltage regulator module is a key power supply component installed on the server motherboard. Its primary function is to convert the input power voltage into a stable voltage suitable for the operation of various components on the motherboard. Typically, a motherboard is equipped with at least two first voltage regulator modules to meet the power and voltage requirements of different components, ensuring that the motherboard can provide reliable and stable power support to each chip during power-up. First voltage regulator modules include but are not limited to a 3.3 volt voltage regulator (P3V3 VR) and a 12 volt voltage regulator (P12V VR).

[0055] Power-up time monitoring involves the first monitoring module using its internal timer to monitor in real time the time it takes for the first voltage regulator module to power up and stabilize its supply. By comparing this time with a preset time threshold, the module determines whether the power-up time is within a normal range, allowing for the timely detection of any abnormal delays that may occur during the power-up process.

[0056] On the server motherboard, the first monitoring module is connected to the motherboard's first controller via a high-speed signal line to ensure real-time reception of the power-on trigger signal. The first monitoring module is also connected to the control signal lines and power signal lines of each first voltage regulator module to accurately monitor signal changes and timing during the power-up process. For example, the first monitoring module's signal receiving port is connected to the enable signal line of the first voltage regulator module to monitor the power-on startup signal; its power monitoring port is connected to the output of the voltage regulator module to detect the stable power supply completion signal.

[0057] The first monitoring module runs a dedicated monitoring program that pre-stores the normal power-on duration threshold and related signal characteristic parameters for the first voltage regulator module. When the motherboard's first controller triggers a power-on trigger, the first monitoring module is immediately activated, and its internal timer begins counting. Simultaneously, the monitoring program monitors the first voltage regulator module's enable signal and power supply output signal in real time. For example, when the first voltage regulator module's enable signal reaches a high level (indicating power-on), the timer starts. When the power supply output voltage stabilizes within a preset operating voltage range (e.g., 1.2V ± 0.05V), the timer stops, and the module's power-on time is determined. This time is then compared with a preset duration threshold to determine whether a timeout has occurred. The monitoring results (including power-on time, timeout status, and other information) are recorded in a local storage unit for subsequent processing and transmission.

[0058] By using a dedicated first monitoring module to monitor the power-on time of at least two first voltage regulation modules on the mainboard respectively, the power-on time of each module can be accurately measured, avoiding the time measurement error caused by the simultaneous power-on of multiple modules in the traditional overall monitoring method.

[0059] The second monitoring module monitors the power-on time of the expansion boards in different components when the first controller triggers the power-on.

[0060] The second monitoring module is specifically responsible for monitoring the power-up time of the expansion board in the server. It has independent timing and signal detection capabilities. When the first controller triggers the power-up, it can accurately record the entire process from the beginning to the completion of the expansion board power-up and determine whether this time is within the normal range.

[0061] Expansion boards are daughterboards that connect to the mainboard via interfaces and provide specific server functionality expansion (such as computing acceleration and storage expansion). These boards include, but are not limited to, switch boards and GPU boards. Power-on time monitoring involves the second monitoring module using its internal timer to monitor the time it takes for an expansion board to power up and stabilize its power supply. By comparing this time with a preset time threshold, the module determines whether the expansion board's power-on time is within the normal range, allowing for timely detection of any abnormal delays during the power-on process.

[0062] Within the server, the second monitoring module is connected to the first controller via a dedicated signal line to ensure real-time reception of the power-on trigger signal. The second monitoring module is also connected to the expansion board's power management unit and signal interface to accurately monitor signal changes and timing during the expansion board's power-up process. For example, the second monitoring module's signal receiving port is connected to the expansion board's enable signal line to monitor the power-on start signal, while its power monitoring port is connected to the expansion board's power output to detect the stable power supply completion signal. The second monitoring module runs a dedicated monitoring program that pre-stores the expansion board's normal power-on duration threshold and related signal characteristic parameters. When the first controller triggers the power-on trigger, the second monitoring module is immediately activated, and its internal timer begins counting. Simultaneously, the monitoring program monitors the expansion board's enable signal and power output signal in real time. For example, when the expansion board's enable signal reaches a high level (indicating the start of power-up), the timer starts. When the voltage at the power output stabilizes within the preset operating voltage range (e.g., 5V±0.1V), the timer stops, thus determining the expansion board's power-on time. This time is compared with the preset time threshold to determine whether it has timed out, and the monitoring results (including power-on time, whether it has timed out, etc.) are recorded in the local storage unit for subsequent processing and transmission.

[0063] By independently monitoring the power-on time of the expansion board through the second monitoring module, the power-on time of the expansion board can be accurately measured, avoiding the time measurement error caused by the simultaneous power-on of multiple components in the traditional overall monitoring method.

[0064] When the first controller receives a first power-ready signal sent by an expansion board in a different component, the third monitoring module monitors the power-on time of at least two second voltage regulation modules of the mainboard; the power-on time interval between the first voltage regulation module and the second voltage regulation module is greater than a preset interval threshold.

[0065] The third monitoring module is specifically responsible for monitoring the power-up time of the second voltage regulator module on the motherboard. It has independent timing and signal detection capabilities. Upon receiving a specific signal, it can accurately record the entire process from the start of the second voltage regulator module's power-up to the completion of stable power supply, and determine whether this time is within the normal range.

[0066] The first power-ready signal is sent to the first controller after the expansion board completes its power-up process and stabilizes its power supply. This signal indicates that the expansion board is ready and its power supply is stable, providing a basis for subsequent component power-up operations. The first power-ready signal is typically a specific level signal (such as a high level) or a data signal, transmitted via a preset communication protocol. The first power-ready signal can be a Field-Programmable Gate Array Ready (FPGA_READY) signal.

[0067] The second voltage regulator module is another key power supply component installed on the server motherboard. Its primary function is to convert the input power voltage into a stable voltage suitable for the operation of various components on the motherboard. The second voltage regulator module is powered on later than the first voltage regulator module. Second voltage regulator modules include, but are not limited to, the Central Processing Unit Voltage Regulator (CPU VR) and the Dual-Inline-Memory-Modules Voltage Regulator (DIMM VR). The power-on interval refers to the time difference between the start of powering on the first voltage regulator module and the start of powering on the second voltage regulator module.

[0068] Inside the server, the third monitoring module is connected to the first controller via a signal line to ensure real-time reception of the first power-ready signal. Simultaneously, the third monitoring module is connected to the control and power signal lines of the second voltage regulator module on the mainboard to accurately monitor signal changes and timing during the power-up process. For example, the third monitoring module's signal receiving port is connected to the enable signal line of the second voltage regulator module to monitor the power-on startup signal; its power monitoring port is connected to the output of the voltage regulator module to detect the stable power supply completion signal.

[0069] The third monitoring module runs a dedicated monitoring program that pre-stores the normal power-on duration threshold and related signal characteristic parameters for the second voltage regulator module. When the first controller receives the first power-ready signal from the expansion board, the third monitoring module is immediately activated, and its internal timer begins counting. Simultaneously, the monitoring program monitors the enable signal and power output signal of the second voltage regulator module in real time. For example, when the enable signal of the second voltage regulator module reaches a high level (indicating power-on), the timer starts. When the voltage at the power output stabilizes within a preset operating voltage range (e.g., 3.3V ± 0.1V), the timer stops, and the module's power-on time is determined. This time is then compared with the preset duration threshold to determine whether a timeout has occurred. The monitoring results (including power-on time, timeout status, and other information) are recorded in a local storage unit for subsequent processing and transmission.

[0070] Independent power-on time monitoring of the second voltage regulation module can accurately measure its power-on time, avoiding the time measurement error caused by the simultaneous power-on of multiple modules in the traditional overall monitoring method.

[0071] In some embodiments, please refer to Figure 1 The first monitoring module includes: a first timer; when the first controller triggers the power-on, the first controller controls the first timer to start timing; if the first controller receives a second power-ready signal sent by the target first voltage regulation module, the first controller controls the first timer to end timing, and obtains a first timing duration from the start to the end of the first timer; the target first voltage regulation module is the first voltage regulation module with the latest power-on time among the at least two first voltage regulation modules; if the first controller determines that the first timing duration is less than the first preset duration threshold, the first controller determines that the power-on of the at least two first voltage regulation modules has not timed out; the first controller determines the state of the at least two first voltage regulation modules as the first power-on non-timeout state.

[0072] The first timer is a hardware counter or software clock integrated into the first monitoring module, used to accurately measure the power-up time of the first voltage regulator module. The target first voltage regulator module is the voltage regulator module that powers on last among the multiple first voltage regulator modules, sorted by power-up time. The second power-good signal is a signal sent by the target first voltage regulator module to notify the system that the voltage regulator module has completed powering up. The second power-good signal can be a power-on completion (PWRGD) signal.

[0073] The first timing duration refers to the time interval from when the first controller triggers the power-on and the first timer starts timing, to when the second power-ready signal sent by the target first voltage regulation module is received and the first timer stops timing. This time interval reflects the total power-on time of all first voltage regulation modules. The first preset duration threshold is a pre-set time threshold used to determine whether the power-on time of the first voltage regulation module is normal. If the first timing duration is less than the first preset duration threshold, it is considered that the power-on time of the first voltage regulation module is within the normal range; if it exceeds the first preset duration threshold, it is considered that the power-on time has timed out.

[0074] The first power-on non-timeout state is when the first controller determines that the first timing duration is less than a first preset duration threshold, and determines the states of at least two first voltage regulation modules as the first power-on non-timeout state. This indicates that the power-on time of the first voltage regulation modules is within a normal range and no timeout issue has occurred.

[0075] On the server motherboard, the first monitoring module is connected to the first controller via signal lines to ensure real-time reception of the power-on trigger signal and the second power-ready signal. The first monitoring module is also connected to the control signal line and power signal line of the first voltage regulator module to accurately monitor signal changes and timing during the power-up process. For example, the first monitoring module's signal receiving port is connected to the enable signal line of the first voltage regulator module to monitor the power-on startup signal; its power monitoring port is connected to the output of the first voltage regulator module to detect the stable power supply completion signal.

[0076] The first monitoring module runs a dedicated monitoring program that pre-stores the normal power-on duration threshold and related signal characteristic parameters for the first voltage regulator module. When the first controller triggers power-on, it sends a start signal to the first monitoring module. Upon receiving this signal, the first monitoring module controls the first timer to start timing. Simultaneously, the monitoring program monitors the enable signal and power output signal of the target first voltage regulator module in real time. For example, when the enable signal of the target first voltage regulator module reaches a high level (indicating power-on), the timer starts. When the voltage at the power output stabilizes within a preset operating voltage range (e.g., 1.2V±0.05V), the target first voltage regulator module sends a second power-ready signal. Upon receiving this signal, the first monitoring module controls the first timer to stop timing and obtain a first timed duration. This timed duration is then compared with a preset first timed duration threshold to determine whether the module has timed out. If the first timed duration is less than the first preset timed duration threshold, the first controller determines that the power-on of the first voltage regulator module has not timed out and sets the module's status to the first power-on non-timed-out state.

[0077] The first timer in the first monitoring module precisely measures the power-on time of the target first voltage regulator module, accurately determining whether its power-on time is within a normal range. This precise monitoring method avoids the time measurement errors caused by the simultaneous power-on of multiple modules in traditional integrated monitoring methods, thereby improving monitoring accuracy and reliability.

[0078] In some embodiments, the server power-on timeout monitoring system also includes: if the first controller does not receive the second power-ready signal within the first target time, the first controller determines that at least one of the at least two first voltage regulation modules has a power-on timeout; the first target time is the time interval after the first timer starts timing and the first preset time threshold is exceeded.

[0079] The first target time is a time point after the first timer starts counting and after the first preset time threshold is reached. This time point is used to determine whether the voltage regulation module can complete the power-on process within the predetermined time.

[0080] The first controller is connected to the first voltage regulator module via a signal line to ensure real-time reception of the second power-ready signal. The first controller also integrates a first timer for measuring power-up time. When the first controller triggers a power-up, it starts the first timer. During the operation of the first timer, the first controller continuously monitors for the second power-ready signal from the target first voltage regulator module. If the signal is not received within a first target time (i.e., a first preset duration threshold after the first timer starts), the controller determines that at least one of the two first voltage regulator modules has experienced a power-up timeout. The specific process is as follows: After receiving the power-up signal, the first controller controls the first timer to start and begin recording time. During this timer, the first controller monitors the second power-ready signal in real time. If the signal is still not detected after the first target time, the controller determines that a first voltage regulator module has experienced a power-up timeout. The timeout determination result is recorded in the first controller's storage unit for subsequent processing and analysis.

[0081] It can quickly locate the voltage regulation module with power-on timeout, provide maintenance personnel with clear fault information, shorten troubleshooting time, and improve maintenance efficiency.

[0082] In some embodiments, the server power-on timeout monitoring system also includes: when the first controller determines that at least one first voltage regulation module among at least two first voltage regulation modules has power-on timed out, the first controller obtains the first state value of the enable signal corresponding to each of the at least two first voltage regulation modules, and obtains the second state value of the second power-ready signal corresponding to each of the at least two first voltage regulation modules; the first controller determines the state of the first voltage regulation module corresponding to the first state value being the first preset state value and the second state value being the second preset state value as the first power-on timeout state; the power-on timeout monitoring result includes the first power-on timeout state or the first power-on non-timeout state.

[0083] The enable (ENABLE) signal is a control signal (usually high level valid) sent by the first controller to the first voltage regulation module, which is used to start the power supply function of the first voltage regulation module. The first state value represents the level state of the enable signal, such as high level (1) is valid and low level (0) is invalid. The second state value represents the level state of the power ready signal, such as high level (1) is ready and low level (0) is not ready. The first preset state value is the expected valid state of the enable signal (such as 1, that is, high level is valid). The second preset state value is the expected invalid state of the power ready signal (such as 0, that is, low level is not ready). The first power-on timeout state is a state identifier that marks a first voltage regulation module as a timeout fault module when the enable signal of a first voltage regulation module is valid but the power is not ready.

[0084] The first controller is connected to the first voltage regulation module through a signal line to ensure that the enable signal and the second power-ready signal can be monitored in real time. The first controller is equipped with a signal monitoring and processing unit for analyzing and processing the acquired signal status values. When the first controller determines that at least one of the at least two first voltage regulation modules has a power-on timeout, a further status value acquisition process is triggered. The first controller reads the current status values of the enable signal and the second power-ready signal corresponding to each first voltage regulation module respectively. For each first voltage regulation module, the first controller checks whether its enable signal is in the first preset status value and whether the second power-ready signal is in the second preset status value. If both conditions are met at the same time, the module is marked as being in the first power-on timeout state, and this status information is integrated into the power-on timeout monitoring result; if not, it is marked as the first power-on non-timeout state, and is also included in the monitoring result.

[0085] By acquiring and analyzing the status values of the enable signal and the second power-ready signal, the first controller can accurately determine which specific first voltage regulation modules have power-on timeout problems, providing maintenance personnel with clear fault location information, shortening troubleshooting time, and improving maintenance efficiency.

[0086] In some embodiments, the server power-on timeout monitoring system also includes: the first controller obtains the target model of the first processor in the expansion board; the first controller searches for the target second preset time threshold corresponding to the target model based on a pre-established mapping relationship between the model and the second preset time threshold; the first controller determines the target second preset time threshold as the preset time threshold of the second monitoring module.

[0087] The first processor is the core processor on the expansion board, responsible for executing the expansion board's primary functions. For example, the first processor could be the GPU on a GPU board. The target model is the specific hardware model of the first processor, used to uniquely identify the processor type and specifications. The second preset duration threshold is the maximum power-up time allowed for the expansion board (e.g., 500ms). Different processor models correspond to different thresholds (determined by differences in hardware initialization time). The model-to-threshold mapping relationship is a pre-existing table or database that associates processor models with their corresponding power-up timeout thresholds.

[0088] The first controller is connected to the first processor on the expansion board via a high-speed communication interface to ensure that the model information of the processor can be reliably obtained. When the server is turned on, the first controller performs the following operations: the first controller sends a query instruction to the expansion board via a preset communication protocol to read the model information of the first processor. For example, the stored model information is obtained by reading the model identifier in the processor's register or through the electrically erasable programmable read-only memory on the expansion board. After successfully obtaining the target model, the first controller searches in a pre-established mapping relationship table. The mapping relationship table can be a two-dimensional array or a hash table, in which the key is the processor model and the value is the corresponding second preset duration threshold. The search process can be implemented by a simple array traversal or hash search algorithm to quickly locate the threshold corresponding to the target model. After finding the target second preset duration threshold, the first controller sends it to the second monitoring module and sets it as the preset duration threshold of the module for subsequent power-on time monitoring of the expansion board.

[0089] Different processor models may have different timing characteristics during the power-up process. By setting a specific second preset duration threshold for each model, you can more accurately determine whether the expansion board's power-up time is normal, avoiding false or missed detections caused by using a unified threshold.

[0090] In some embodiments, please refer to Figure 1The second monitoring module includes: a second timer; when the first controller triggers the power-on, the first controller controls the second timer to start timing; if the first controller receives a first power-ready signal, the first controller controls the second timer to end timing, and obtains a second timing duration from the start to the end of the second timer; if the first controller determines that the second timing duration is less than the target second preset duration threshold, it is determined that the expansion board power-on has not timed out; and the state of the expansion board is determined to be the second power-on non-timeout state.

[0091] The second monitoring module refers to a hardware module used to monitor the power-on process of the expansion board, and is specifically responsible for timing and judging whether the expansion board has completed the startup task within the predetermined time. The second timer is a timer component used to record the duration of the power-on process. The target second preset time threshold is the preset maximum time, and the target second preset time threshold refers to the maximum allowable power-on time determined based on the hardware configuration such as the processor model of the expansion board. If the power-on process is not completed within the time, it is judged to be normal, otherwise it may indicate that there is a fault in the power-on process. The second power-on non-timeout state refers to the state of the expansion board during the power-on process, indicating that the power-on time of the expansion board does not exceed the predetermined time threshold, that is, the expansion board can complete the startup within the specified time.

[0092] When the first controller triggers the power-on, the second timer of the second monitoring module starts timing. The first controller sends a start signal to the second timer to start the timing task. During the startup process, the first controller monitors the first power-ready signal from the server power system to confirm whether the power supply is ready. Once the first power-ready signal is received, the first controller controls the second timer to stop timing, obtains the time from the start to the end of the timing, and obtains the second timing duration. The first controller compares the obtained second timing duration with the target second preset duration threshold. If the second timing duration is less than the target second preset duration threshold, it means that the expansion board has completed the startup task within the specified time; otherwise, it means that the power-on process of the expansion board has timed out. If the second timing duration is less than the target second preset duration threshold, the first controller determines the status of the expansion board as "second power-on non-timeout state", that is, the expansion board is successfully started and has not timed out.

[0093] The first controller can promptly detect the power-on timeout of the expansion board, and can take further measures according to the timeout situation, such as issuing an alarm or adjusting the configuration, to avoid the system being in an unstable state for a long time and reduce the risk of failure.

[0094] In some embodiments, the server power-on timeout monitoring system also includes: if the first controller does not receive the first power-ready signal within the second target time, it is determined that the expansion board has powered on and has timed out; the second target time is the time after the second timer starts timing and is separated by a second preset time threshold of the target; the first controller determines the state of the expansion board as a second power-on timeout state; the power-on timeout monitoring result includes the second power-on timeout state or the second power-on non-timeout state.

[0095] The second target time is the time point corresponding to the target second preset duration threshold from the start of the second timer. The second target time is a key time node for determining whether the expansion board power-on timeout has occurred. If the first power-ready signal is not received before this time point, it can be determined that an abnormal power-on timeout has occurred on the expansion board. For example, if the target second preset duration threshold is 3000 milliseconds, then the second target time is 3000 milliseconds after the second timer starts.

[0096] The second power-on timeout status is an abnormal state detected when the first controller does not receive the first power-ready signal within the second target time. This second power-on timeout status is recorded and identified within the first controller for subsequent exception handling and system diagnosis. It also forms part of the power-on timeout monitoring results, providing important support for troubleshooting and maintenance of the entire server system.

[0097] When the first controller triggers the power-on operation, the second timer immediately starts counting. Simultaneously, the first controller uses a dedicated signal monitoring pin to monitor the first power-ready signal sent by the expansion board in real time. This monitoring process is continuous, and the controller continuously scans the voltage level on the signal line to determine whether the expected ready signal appears. During the timing process, once the second timer reaches the second target time (i.e., the time point after the start of timing has passed the target second preset duration threshold), the first controller immediately determines: If the first power-ready signal is still not detected at this time, it is determined that the expansion board has timed out from power-on. At this point, the first controller marks the power-on status of the expansion board as "second power-on timeout status" in the internal status register or corresponding status storage area, and stores and records this status information in the power-on timeout monitoring results for subsequent system processing and analysis.

[0098] By explicitly setting the second target time and the target second preset duration threshold, it is possible to accurately determine whether a timeout anomaly occurs during the expansion board power-up process. This avoids the uncertainty and potential risks of system startup delays caused by excessive waiting times, helps promptly identify possible hardware faults (such as power supply component failures or power supply line problems) or software initialization anomalies during the expansion board power-up process, and improves the server system's ability to identify and respond to expansion board power-up anomalies.

[0099] In some embodiments, please refer to Figure 1 The third monitoring module includes: a third timer; when the first controller receives a first power-ready signal sent by the expansion board, the first controller controls the third timer to start timing; if the first controller receives a reset signal sent by the second processor of the mainboard, the first controller controls the third timer to end timing, and obtains a third timing duration from the start to the end of the third timer; if the first controller determines that the third timing duration is less than a third preset duration threshold, the first controller determines that the power-on of at least two second voltage regulation modules has not timed out; the first controller determines the status of the at least two second voltage regulation modules as the third power-on non-timeout state.

[0100] The third monitoring module is used to monitor the power-on process of the voltage regulation module, especially the timeout detection related to the power-on duration. The third monitoring module can accurately record the time from the voltage regulation module receiving the power signal to completing the power-on process. The third timer is used to record the time from the first controller receiving the first power-ready signal from the expansion board to the reception of the reset signal. The third timer helps monitor whether the power startup process meets the specified duration. The reset signal is a signal sent by the second processor of the mainboard, usually indicating that the system has completed initialization or reset. For the voltage regulation module, the reset signal means that the power-on process has been completed.

[0101] The third timing duration is the length of time recorded by the third timer, which represents the time from the start of timing by the first controller to the receipt of the reset signal. This duration is used to determine whether the voltage regulation module completes the power-on process within the predetermined time. The third preset duration threshold is a set upper limit of time, which is used to determine whether the voltage regulation module completes the power-on process within the specified time. If the third timing duration is less than the threshold, it indicates that the power-on process is normal. The third power-on non-timeout state is a normal state identifier determined by the first controller for the power-on state of the second voltage regulation module when the third timing duration is less than the third preset duration threshold. This state information will be stored in the internal state storage area of the first controller, and can subsequently be used as the data basis for the entire server power-on timeout monitoring system to summarize and analyze the power-on status of each component, and is used to indicate that the power-on process of the second voltage regulation module is completed smoothly and normally without abnormal delays or failures, thereby providing a guarantee for the stable startup and operation of the server.

[0102] When the first controller detects the first power-ready signal from the expansion board, it immediately sends a command to the third monitoring module via its internal control logic circuit, triggering the third timer to begin timing. At this point, the counter within the third timer, driven by the system clock signal, begins counting cumulatively, recording the elapsed time in real time from that moment, preparing for subsequent measurement of the power-on duration of the second voltage regulator module. While the second voltage regulator module continues to power on, the first controller monitors the reset signal sent by the second processor on the mainboard in real time. Specifically, the signal detection pin of the first controller continuously scans the signal line connected to the second processor to determine whether the level or pulse state on the signal line changes. Upon detecting the reset signal, the first controller quickly sends an end-time command to the third timer. Upon receiving this command, the third timer immediately stops timing and saves the current counter value (i.e., the third timer duration) to a pre-assigned storage unit for subsequent processing. After obtaining the third timer duration recorded by the third timer, the first controller retrieves a pre-set third preset time threshold from internal memory and performs a comparison operation on the two using the processor's arithmetic logic unit. If the third timed duration is less than the third preset duration threshold, the first controller determines, based on a preset logic rule, that the second voltage regulator module has not timed out from powering on. At this point, the first controller updates the power-on status of the second voltage regulator module to the "third power-on non-timeout state" in its internal status register or corresponding status storage area. This allows the entire monitoring system to subsequently summarize and process the power-on status of each component, providing accurate data support for server startup process control and anomaly detection.

[0103] By using a third timer to accurately time the entire power-on process of the second voltage regulation module from receiving the first power-ready signal to sending the reset signal, the actual time consumption of the module can be accurately measured, avoiding the monitoring error caused by the traditional overall monitoring method due to the lack of component segmentation, and effectively improving the monitoring accuracy of the power-on process of the second voltage regulation module, so that it can better adapt to the actual power-on time characteristics of different modules in different environments, helping to timely discover potential power-on abnormalities and ensure the stability and reliability of the server motherboard power supply system.

[0104] In some embodiments, the server power-on timeout monitoring system also includes: if the first controller does not receive a reset signal within a third target time, the first controller determines that at least one of the at least two second voltage regulation modules has a power-on timeout; the third target time is the time interval of a third preset time threshold after the third timer starts timing.

[0105] The third target time refers to the point in time corresponding to the third preset duration threshold after the third timer starts. It is the key time point for determining whether the second voltage regulator module has timed out from powering on. For example, if the third preset duration threshold is set to 2000 milliseconds, the third target time is the 2000th millisecond after the third timer starts. The third preset duration threshold: A time threshold pre-set based on the normal power-on characteristics of the second voltage regulator module, taking into account factors such as the hardware circuit characteristics, power supply requirements, and the interoperability time with other motherboard components of the second voltage regulator module. This threshold, determined through extensive experimental testing and analysis of actual application scenarios, serves as a criterion for determining whether the power-on time of the second voltage regulator module exceeds the normal range. Units are generally milliseconds or seconds. For example, for a certain model of second voltage regulator module, the third preset duration threshold may be 1800 milliseconds. Third power-on timeout state: When the first controller does not receive a reset signal within the third target time, it determines that at least one of the two second voltage regulator modules has timed out from powering on and marks the corresponding state as the third power-on timeout state. This status information will be recorded and identified within the first controller for subsequent exception handling and system diagnosis. It will also serve as part of the power-on timeout monitoring results, providing an important basis for troubleshooting and maintenance of the entire server system.

[0106] When the first controller receives the first power-ready signal sent by the expansion board, the third timer starts timing. The first controller monitors the reset signal sent by the second processor on the mainboard in real time through a dedicated signal monitoring pin, and continuously scans the signal line connected to the second processor to determine whether the signal state has changed. When the third timer reaches the third target time (that is, the time point after the third timer starts timing and passes the third preset time threshold), if the first controller still does not detect the reset signal, it is determined that there is a power-on timeout in at least two second voltage regulation modules. At this time, the first controller marks the power-on state of the corresponding second voltage regulation module as the third power-on timeout state in the internal state storage area, and records this state information as part of the power-on timeout monitoring result.

[0107] By explicitly setting the third target time and the third preset duration threshold, it is possible to accurately determine whether a timeout anomaly occurs during the power-up process of the second voltage regulator module. This helps promptly identify potential hardware faults (such as voltage regulation circuit failures or power management chip anomalies) or software initialization issues in the second voltage regulator module. This improves the server system's ability to identify power-up anomalies in key motherboard power supply components, thus preventing server startup failures or unstable operation caused by power supply anomalies.

[0108] In some embodiments, the server power-on timeout monitoring system also includes: when the first controller determines that at least one second voltage regulation module among at least two second voltage regulation modules has power-on timed out, the first controller obtains the third state value of the enable signal corresponding to each of the at least two second voltage regulation modules, and obtains the fourth state value of the third power-ready signal corresponding to each of the at least two second voltage regulation modules; the first controller determines the state of the second voltage regulation module corresponding to the third state value being the third preset state value and the fourth state value being the fourth preset state value as the third power-on timeout state; the power-on timeout monitoring result includes the third power-on timeout state or the third power-on non-timeout state.

[0109] The third state value refers to the state value of the enable signal at a specific moment, generally represented by binary "0" or "1". For example, "1" indicates that the enable signal is in the active state, and "0" indicates that the enable signal is in the off state. The first controller can understand whether the second voltage regulation module has received the power-on instruction by reading this state value. The third power-ready signal is a signal sent by the second voltage regulation module after completing its own power-on process and reaching a stable power supply state, which is used to inform the first controller that its power state is ready. This signal is also a digital signal. For example, a high level indicates that the power is ready, and a low level indicates that the power is not ready. It is transmitted to the first controller through a dedicated signal line to facilitate the first controller to monitor the power-on process of the second voltage regulation module. The third power-ready signal can be a PWRGD signal.

[0110] The fourth state value refers to the state of the third power-ready signal at a specific moment, also represented by a binary value of "0" or "1." For example, "1" indicates that the second voltage regulator module has successfully powered on and is providing stable power, while "0" indicates that the power-on process has not yet been completed or a failure has occurred. By monitoring this state value, the first controller can determine the power-on result of the second voltage regulator module. The third preset state value is a predefined expected state value of the enable signal, indicating that the second voltage regulator module should be in a standard state of power-on activation. For example, during a normal power-on process, the third preset state value is set to "1," meaning that the second voltage regulator module should have received the enable signal and begun powering up. The fourth preset state value is a predefined expected state value of the third power-ready signal, indicating that the second voltage regulator module has successfully powered on and reached a standard state of stable power supply. For example, a fourth preset state value of "1" indicates that the second voltage regulator module has completed power-on and is providing normal power. These preset state values are determined during the server system design phase based on the logical relationships of the hardware circuits and normal operating requirements, and serve as a basis for determining whether the second voltage regulator module has powered on normally.

[0111] When the first controller determines that one of at least two second voltage regulation modules has experienced a power-on timeout, it immediately initiates further monitoring of these second voltage regulation modules. The first controller, through its internal signal monitoring circuit, reads the third state value of the enable signal and the fourth state value of the third power-ready signal corresponding to each second voltage regulation module. Specifically, the first controller sends a monitoring request to the enable signal line and the third power-ready signal line of each second voltage regulation module, obtains the current signal state, and stores these state values in an internal temporary register. After obtaining the third and fourth state values of each second voltage regulation module, the first controller compares them one by one with pre-stored third and fourth preset state values. For each second voltage regulation module, if its third state value is equal to the third preset state value and its fourth state value is equal to the fourth preset state value, the module is determined to be in the third power-on timeout state. Otherwise, the module is considered to be in another abnormal state or in a power-on non-timeout state. Finally, the first controller aggregates these determination results to form a detailed power-on timeout monitoring result, which includes specific power-on status information of each second voltage regulation module for subsequent system fault diagnosis and processing.

[0112] By acquiring and analyzing the status of the enable signal and the third power-ready signal of the second voltage regulator module, the specific second voltage regulator module experiencing the power-on timeout can be accurately located. This avoids blindly troubleshooting all second voltage regulator modules, improves the efficiency and accuracy of fault diagnosis, and provides a clear direction for subsequent repair and replacement work.

[0113] In some embodiments, the server power-on timeout monitoring system also includes: if the second controller parses out that the power-on timeout monitoring result contains a first power-on timeout state, the second controller determines that the first voltage regulation module corresponding to the first state value being the first preset state value and the second state value being the second preset state value has an abnormality; the second controller determines that the first voltage regulation module corresponding to the first state value being the first preset state value and the second state value being the second preset state value has an abnormality as an abnormal analysis result.

[0114] The second controller receives power-on timeout monitoring results from the first controller in real time via a preset communication interface (such as an Ethernet interface or a serial communication interface). Upon receiving the data, the second controller uses a pre-programmed parsing program to parse the monitoring results according to preset data formats and encoding rules, extracting the power-on status information of each component contained therein, specifically focusing on whether any records related to the first power-on timeout status exist. When the second controller detects the presence of the first power-on timeout status in the monitoring results, it further extracts the first and second status values of the corresponding first voltage regulation module from the monitoring results. These status values are then compared one by one with the pre-stored first and second preset status values. Specifically, the first and second preset status values are read from internally stored configuration parameters, and then a conditional statement in the program is used to compare the actual status value with the preset values. If both the first and second status values of a first voltage regulation module are found to be equal, an abnormality is determined for that first voltage regulation module. At this point, the second controller records the abnormality in the abnormality analysis results. The record includes the abnormal component type (the first voltage regulator module), the specific module identifier (such as the module's location number in the server or the circuit connection identifier), and the abnormality manifestation (such as a power-on timeout and the enable signal and power-ready signal meeting a preset abnormal state combination). Finally, the abnormality analysis results can be organized and stored in a preset format for subsequent query and analysis.

[0115] Through in-depth analysis of power-on timeout monitoring results, the first voltage regulator module experiencing a power-on timeout issue can be accurately identified, and further status value comparison can be used to determine the specific abnormality. This precise location capability avoids the need for large-scale, blind troubleshooting of numerous server components, improving the efficiency and accuracy of fault diagnosis, shortening system repair time, and enhancing server availability and reliability.

[0116] In some embodiments, the server power-on timeout monitoring system further includes: if the second controller parses the power-on timeout monitoring result and finds that it includes a second power-on timeout state, it is determined that there is an abnormality in the expansion board; the second controller determines the abnormality in the expansion board as an abnormality parsing result.

[0117] The second controller receives power-on timeout monitoring results from the first controller in real time via a pre-defined communication interface (such as an Ethernet interface). Upon receiving the monitoring results, it uses a pre-programmed parsing program to parse the data according to a pre-defined data format, extracting the power-on status information of each component and focusing on whether there are records of the second power-on timeout state. If the second controller detects the second power-on timeout state in the monitoring results, it directly determines that an expansion board has an abnormality based on pre-defined analysis logic. At this point, the second controller creates a new abnormality record in its internal abnormality logging module, recording the abnormality of the expansion board, including the time of occurrence, identification information of the expansion board (such as slot location, hardware identification), and the type of abnormality (power-on timeout). The second controller records the determined expansion board abnormality as the abnormality analysis result and reports the result to the system management platform or stores it in a local log file according to the pre-defined reporting mechanism. Simultaneously, the second controller alerts system administrators or maintenance personnel to the abnormal expansion board status through indicators, audible alarms, or pop-up warning prompts on the user interface.

[0118] The second controller accurately analyzes power-on timeout monitoring results to quickly determine whether an expansion board has experienced a power-on timeout anomaly. This eliminates the tedious process of manually checking each server component one by one, improves the efficiency and accuracy of fault diagnosis, shortens system repair time, and enhances the overall availability and reliability of the server system.

[0119] In some embodiments, the server power-on timeout monitoring system also includes: if the second controller parses out that the power-on timeout monitoring result includes a third power-on timeout state, the second controller determines that the third state value is the third preset state value and the fourth state value is the fourth preset state value, and there is an abnormality in the second voltage regulation module corresponding to the fourth preset state value; the second controller determines that the third state value is the third preset state value and the fourth state value is the fourth preset state value, and there is an abnormality in the second voltage regulation module corresponding to the fourth preset state value as an abnormal analysis result.

[0120] The second controller receives power-on timeout monitoring results from the first controller in real time via a preset communication interface (such as an Ethernet interface or a serial communication interface). Upon receiving the data, the second controller uses a pre-programmed parsing program to parse the monitoring results according to preset data formats and encoding rules, extracting the power-on status information of each component contained therein, specifically focusing on whether there are any records related to the third power-on timeout status. When the second controller detects the presence of the third power-on timeout status in the monitoring results, it further extracts the third and fourth status values of the corresponding second voltage regulation module from the monitoring results. These status values are then compared one by one with pre-stored third and fourth preset status values. Specifically, the third and fourth preset status values are read from internally stored configuration parameters, and then a conditional statement in the program is used to match the actual status values with the preset values. If the third and fourth status values of a second voltage regulation module are found to be equal to both the third and fourth preset status values, an abnormality is determined for that second voltage regulation module. At this point, the second controller records the abnormality in the abnormality analysis results. The record includes the abnormal component type (the second voltage regulator module), the specific module identifier (such as the module's location number in the server or the circuit connection identifier), and the abnormality manifestation (such as a power-on timeout and the enable signal and the third power-ready signal meeting a predetermined abnormal state combination). Finally, the abnormality analysis results can be organized and stored in a predetermined format for subsequent query and analysis.

[0121] By recording and presenting anomaly analysis results in a clear and concise manner, system administrators and maintenance personnel can intuitively understand anomalies that occur during server power-on. These anomaly analysis results can serve as a guide for maintenance work, helping maintenance personnel quickly enter the repair process, reducing fault diagnosis time and improving repair efficiency and quality. They also provide valuable data support for subsequent system optimization and improvement.

[0122] In order to better understand the server power-on timeout monitoring system, Figure 2 As shown, Figure 2This is a structural diagram of another server power-on timeout monitoring system provided in an embodiment of the present application. According to the timing relationship between the mainboard, the switch board, and the GPU board, as well as the power-on time between the three boards, three power-on timeout monitoring modules are set in the mainboard CPLD; the first power-on timeout monitoring module (i.e., the first monitoring module) is used to implement the power-on timeout monitoring function of the P3V3 VR and P12V VR on the mainboard. Since the power-on speed of the above two VRs is relatively fast, the power-on timeout time set by this module is relatively short; the second power-on timeout monitoring module (i.e., the second monitoring module) is used to implement the power-on timeout monitoring function of the FPGA_READY signal on the switch board and the GPU board. As mentioned above, the alternating current (Alternating Current) of GPUs from different manufacturers is different. Current (AC) after power-on, the time it takes to send out the FPGA_READY signal varies greatly. Therefore, in order to ensure the versatility of the server head, the power-on timeout of this module needs to be set according to the longest power-on time of the GPU to ensure that when the server head is equipped with GPUs from different manufacturers, there is no possibility of false power-on timeout alarms due to the power-on timeout being set too short. Therefore, the power-on timeout set by the second power-on timeout monitoring module is longer; the third power-on timeout monitoring module (i.e., the third monitoring module) is used to implement the power-on timeout monitoring function of the CPU VR and DIMM VR on the motherboard, as well as the power-on timeout monitoring function of the GPU board. The power-on speed of the CPU VR and DIMM VR is faster. Although the GPU board generates the FPGA_READY signal slowly after AC, after generating the signal and receiving the power-on signal sent by the switch board, the VR on the GPU board powers on faster. Therefore, the power-on timeout set by the third power-on timeout monitoring module is shorter. However, it should be clear that Figure 2 This is only a structural diagram of a server power-on timeout monitoring system provided in this application, and does not limit the server power-on timeout monitoring system to only Figure 2 The structure shown in the figure can also be used as the server power-on timeout monitoring system.

[0123] When the motherboard CPLD detects a valid start or end signal from the power-on timeout monitoring module, it starts or ends the corresponding power-on timeout monitoring module's timer. If the timer reaches the set timeout limit after starting and does not stop, the CPLD records the relevant exception information in the Inter-Integrated Circuit (I2C) register and triggers an abnormal interrupt. By pulling the general-purpose input / output (GPIO) low, the BMC is informed of the current motherboard abnormal interrupt. The BMC reads the CPLD register through I2C and analyzes the specific cause of the power-on timeout.

[0124] In order to better understand the connection relationship between different components in the server, such as Figure 3 As shown, Figure 3 This is a structural diagram of the connection relationship between different components provided in an embodiment of the present application. The mainboard CPLD communicates with the switch board CPLD through the GPIO interface to realize the interactive functions of signals such as the switch board power-on signal, the switch board power-on completion signal (SW_PWRGD), the FPGA_READY signal, and the reset signal; the mainboard CPLD realizes the interactive functions of the sleep type 3 signal (Sleep Type 3 Signal, SLP_S3), the sleep type 4 signal (Sleep Type 4 Signal, SLP_S4), the reference clock ready (Reference Clock READY, Reference Clock READY) REFCLK_READY signal, the central processing unit power-on completion (Central Processing Unit Power Good, CPU_PWRGD) signal, and the reset (PLTRST) signal between the mainboard CPLD and the CPU through the GPIO; the mainboard CPLD realizes the interactive functions of the dual-inline-memory module power good fault (Dual-Inline-Memory-ModulesPWRGD) between the mainboard CPLD and the dual-inline-memory-modules (DIMMs) through the GPIO. The motherboard CPLD uses GPIO to transmit interrupt signals to the BMC and also transmits register data to the BMC through I2C. The motherboard CPLD uses GPIO to interact with the motherboard VR chip, including controlling the enable signal (ENABLE) of the voltage regulator (VR) chip and receiving the reset (PWRGD) signal output by the VR chip.

[0125] In order to better understand the entire process of server power-on timeout monitoring, Figure 4 As shown, Figure 4A flow chart of the entire process of server power-on timeout monitoring provided by an embodiment of the present application. After the server is connected to the alternating current (AC) power supply, the standby (STBY) power of each board will be powered on quickly. According to the power-on timing requirements, after the mainboard CPLD collects the response signal SLP_S3 and the response signal SLP_S4 sent by the CPU, on the one hand, it will push up the enable signal of the mainboard P12V VR to power on the mainboard P12V, and on the other hand, it will send a power-on signal to the switch board CPLD, and at the same time, it will start the timing of the first power-on timeout monitoring module and the second power-on timeout monitoring module of the mainboard; after the mainboard CPLD receives the PWRGD signal of P12VVR, it will then push up the enable signal of the mainboard P3V3 VR to power on the mainboard P3V3. When the mainboard CPLD receives the PWRGD signal of P3V3 VR, the mainboard CPLD will wait for the FPGA_READY signal sent by the switch board CPLD, and at the same time, it will generate a timing end flag for the timer of the first power-on timeout monitoring module. If the timer timing time is less than 5 seconds, it is determined that P12V If the VR and P3V3 VR power-on does not time out, and the timing exceeds 5 seconds without receiving the timing end mark, the CPLD will lock the value of the current timing state machine and determine whether there is a power-on timeout of P12V VR or P3V3 VR. The specific power-on timeout caused by which voltage needs to be determined based on the ENABLE signal and PWRGD signal of P12V VR and P3V3 VR in the timing state machine when the timer counts to 5s. The judgment principle is: if the ENABLE signal of P12V VR is high and the PWRGD signal of P12V VR is low at this time, then it is determined that P12V power-on timed out; if the ENABLE signal of P3V3 VR is high and the PWRGD of P3V3 VR is low at this time, then it is determined that P3V3 power-on timed out. When a power-on timeout exception occurs, the CPLD will inform the BMC of this status. However, it should be clear that this statement is not intended to limit the entire process of power-on timeout monitoring on the server. Figure 4 The process shown can also be used to implement the entire process of server power-on timeout monitoring through other processes.

[0126] After the mainboard CPLD receives the FPGA_READY signal from the switch board, it continues to push up the enable signals of the CPU and DIMM-related VRs. It also starts the timing of the third power-on timeout monitoring module on the mainboard. Finally, it generates a timeout flag for the timer of the second power-on timeout monitoring module. If the timer counts less than 12 minutes, it is determined that the FPGA_READY signals on the switch board and GPU board have not timed out. If the timer counts for more than 12 minutes without receiving the timeout flag, the CPLD locks the value of the current timing state machine and determines that the FPGA_READY signals on the switch board and GPU board have timed out.

[0127] After the VR of the CPU and DIMM on the motherboard is powered on, the CPLD will receive the PWRGD signal of the corresponding VR. After the CPU is powered on, it will output a clock signal. After the clock is stable, the CPU will send a REFCLK_READY signal to the CPLD. After receiving the signal, the motherboard CPLD will wait for the SW_PWRGD signal sent by the switch board CPLD. After receiving the above signal, the motherboard CPLD will send a CPU_PWRGD signal to the CPU, indicating that the CPU is powered on and ready. After receiving this signal, the CPU will send a PLTRST system reset indication signal. After receiving the PLTRST signal, the CPLD will generate a reset signal to the CPU, PCIe devices, etc. on the motherboard, as well as the switch board CPLD. At the same time, after the PLTRST signal is generated, it indicates that all devices on the motherboard have been powered on. At this time, the motherboard CPLD will generate a timeout flag for the timer of the third power-on timeout monitoring module. If the timer timing is less than 10 seconds, it is determined that the CPU VR and DIMM on the motherboard are powered on. If the VR and GPU boards are powered on without timing out and the timing exceeds 10 seconds without receiving a timing end flag, the CPLD will lock the value of the current timing state machine and determine that a power-on timeout has occurred. The specific judgment logic is consistent with the judgment principle of the first power-on timeout monitoring module mentioned above.

[0128] By rationally dividing different power-on timeout monitoring areas and setting different power-on timeout periods, the function of segmented power-on timeout monitoring of the server is realized; the requirements of matching the server head (mainboard + switch board) with different GPUs are met; and the accuracy of power-on timeout monitoring and the timeliness of reporting after power-on timeout anomalies are improved.

[0129] According to the embodiment of the present application, the present application also proposes a server power-on timeout monitoring method, such as Figure 5 As shown, Figure 5 This is a flow chart of a server power-on timeout monitoring method provided in an embodiment of the present application. The method is applied to a server power-on timeout monitoring system. The method includes the following steps:

[0130] Step 101 : Using a first controller, according to the power-on sequence of different components in a server, perform power-on timeout monitoring on different components in sections to obtain power-on timeout monitoring results of different components.

[0131] Step 102: Utilize the first controller to transmit the power-on timeout monitoring result to the second controller.

[0132] Step 103: Utilize the second controller to perform abnormal analysis on the power-on timeout monitoring result to obtain an abnormal analysis result.

[0133] Through this application, the first controller monitors the power-on timeouts of different components in the server according to the power-on order of the different components, obtains the power-on timeout monitoring results of the different components, and transmits the power-on timeout monitoring results to the second controller. The second controller then performs an exception analysis on the power-on timeout monitoring results to obtain an exception analysis result. Because the power-on times of different components are inconsistent, segmented monitoring can accurately capture the specific power-on timeout situations of different components, thereby improving the accuracy of the server's power-on timeout monitoring. Therefore, the technical problem of low accuracy of the server's power-on timeout monitoring can be solved, achieving the technical effect of improving the accuracy of the server's power-on timeout monitoring.

[0134] As a refinement of step 101, the first controller includes a first monitoring module, a second monitoring module and a third monitoring module. When using the first controller to perform segmented power-on timeout monitoring on different components according to the power-on sequence of different components in the server, it can be implemented in but not limited to the following ways, including: using the first monitoring module to monitor the power-on time of at least two first voltage regulation modules of the mainboard in different components when the first controller triggers power-on; using the second monitoring module to monitor the power-on time of expansion boards in different components when the first controller triggers power-on; using the third monitoring module to monitor the power-on time of at least two second voltage regulation modules of the mainboard when the first controller receives a first power-ready signal sent by the expansion boards in different components; the power-on time interval between the first voltage regulation module and the second voltage regulation module is greater than a preset interval threshold.

[0135] Since the embodiments of the server power-on timeout monitoring method correspond to the embodiments of the server power-on timeout monitoring system, the embodiments of the server power-on timeout monitoring method can be found in the description of the embodiments of the server power-on timeout monitoring system, and will not be repeated here. The embodiments of the server power-on timeout monitoring method have the same beneficial effects as the aforementioned server power-on timeout monitoring system.

[0136] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0137] The embodiment of the present application also provides a server power-on timeout monitoring device, Figure 6 A schematic diagram of the structure of a server power-on timeout monitoring device provided in an embodiment of the present application is shown as follows: Figure 6 Shown, including:

[0138] The monitoring unit 21 is configured to use the first controller to perform power-on timeout monitoring on different components in sections according to the power-on sequence of different components in the server, and obtain power-on timeout monitoring results for different components;

[0139] The transmission unit 22 is used to transmit the power-on timeout monitoring result to the second controller using the first controller;

[0140] The analyzing unit 23 is configured to use the second controller to perform abnormal analysis on the power-on timeout monitoring result to obtain an abnormal analysis result.

[0141] Through this application, the first controller monitors the power-on timeouts of different components in the server according to the power-on order of the different components, obtains the power-on timeout monitoring results of the different components, and transmits the power-on timeout monitoring results to the second controller. The second controller then performs an exception analysis on the power-on timeout monitoring results to obtain an exception analysis result. Because the power-on times of different components are inconsistent, segmented monitoring can accurately capture the specific power-on timeout situations of different components, thereby improving the accuracy of the server's power-on timeout monitoring. Therefore, the technical problem of low accuracy of the server's power-on timeout monitoring can be solved, achieving the technical effect of improving the accuracy of the server's power-on timeout monitoring.

[0142] For the description of the features in the embodiment corresponding to the server power-on timeout monitoring device, please refer to the relevant description of the embodiment corresponding to the server power-on timeout monitoring system, which will not be repeated here.

[0143] An embodiment of the present application further provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps of any of the above-mentioned server power-on timeout monitoring method embodiments.

[0144] An embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned server power-on timeout monitoring method embodiments when running.

[0145] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0146] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned server power-on timeout monitoring method embodiments are implemented.

[0147] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps in any of the above-mentioned server power-on timeout monitoring method embodiments.

[0148] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0149] The above describes in detail the server power-on timeout monitoring system, method, medium, device, and program product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core concept of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and such improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A server power-on timeout monitoring system, characterized in that: include: a first controller, a second controller; The first controller is connected to the second controller; The first controller performs power-on timeout monitoring on different components in the server in sections according to the power-on sequence of the different components, obtains power-on timeout monitoring results of the different components, and transmits the power-on timeout monitoring results to the second controller; The second controller performs an abnormality analysis on the power-on timeout monitoring result to obtain an abnormality analysis result; Wherein, the first controller includes: a first monitoring module, a second monitoring module and a third monitoring module; The first monitoring module monitors the power-on time of at least two first voltage regulating modules of the mainboard in the different components when the first controller triggers the power-on; The second monitoring module monitors the power-on time of the expansion boards in the different components when the first controller triggers the power-on; The third monitoring module monitors the power-on time of at least two second voltage regulating modules of the mainboard when the first controller receives a first power-ready signal sent by an expansion board among the different components; the power-on time interval between the first voltage regulating module and the second voltage regulating module is greater than a preset interval threshold, the power-on sequence of the second voltage regulating module is later than that of the first voltage regulating module, and the first power-ready signal is a signal sent by the expansion board to the first controller after completing its own power-on process; Wherein, the first controller determines whether the power-on of the at least two first voltage regulating modules has timed out according to the total power-on time of the at least two first voltage regulating modules; Wherein, the first controller determines whether the expansion board is powered on for a timeout according to the total power-on time of the expansion board; The first controller determines whether power-on of the at least two second voltage regulating modules has timed out according to the total power-on time of the at least two second voltage regulating modules.

2. The server power-on timeout monitoring system according to claim 1, characterized in that: The first monitoring module includes: a first timer; When the first controller triggers the power on, the first controller controls the first timer to start timing; If the first controller receives a second power-ready signal sent by a target first voltage regulating module, the first controller controls the first timer to end timing and obtains a first timing duration from the start to the end of the first timer; the target first voltage regulating module is the first voltage regulating module with the latest power-on time among the at least two first voltage regulating modules; If the first controller determines that the first timing duration is less than a first preset duration threshold, the first controller determines that the power-on of the at least two first voltage regulating modules has not timed out; The first controller determines the states of the at least two first voltage regulating modules as a first power-on non-timeout state.

3. The server power-on timeout monitoring system according to claim 2, characterized in that: The server power-on timeout monitoring system further includes: If the first controller does not receive the second power-ready signal within the first target time, the first controller determines that at least one of the at least two first voltage regulation modules has power-on timed out; the first target time is the time interval after the first timer starts timing and the first preset time threshold.

4. The server power-on timeout monitoring system according to claim 3, characterized in that: The server power-on timeout monitoring system further includes: When the first controller determines that at least one of the at least two first voltage regulating modules has a power-on timeout, the first controller obtains a first state value of an enable signal corresponding to each of the at least two first voltage regulating modules, and obtains a second state value of a second power-ready signal corresponding to each of the at least two first voltage regulating modules; The first controller determines the state of the first voltage regulation module corresponding to the first state value being a first preset state value and the second state value being a second preset state value as a first power-on timeout state; the power-on timeout monitoring result includes the first power-on timeout state or the first power-on non-timeout state.

5. The server power-on timeout monitoring system according to claim 1, characterized in that: The server power-on timeout monitoring system further includes: The first controller obtains a target model of the first processor in the expansion board; The first controller searches for a target second preset time threshold corresponding to the target model according to a pre-established mapping relationship between the model and the second preset time threshold; The first controller determines the target second preset time threshold as the preset time threshold of the second monitoring module.

6. The server power-on timeout monitoring system according to claim 5, characterized in that: The second monitoring module includes: a second timer; When the first controller triggers the power on, the first controller controls the second timer to start timing; If the first controller receives the first power-ready signal, the first controller controls the second timer to end timing, and obtains a second timing duration from the start to the end of the second timer; If the first controller determines that the second timing duration is less than the target second preset duration threshold, it is determined that the expansion board power-on has not timed out; The state of the expansion board is determined to be a second power-on non-timeout state.

7. The server power-on timeout monitoring system according to claim 6, characterized in that: The server power-on timeout monitoring system further includes: If the first controller does not receive the first power-ready signal within the second target time, it is determined that the expansion board is powered on for timeout; the second target time is the time interval between the second timer starting to count and the target second preset time threshold; The first controller determines the state of the expansion board as a second power-on timeout state; and the power-on timeout monitoring result includes the second power-on timeout state or the second power-on non-timeout state.

8. The server power-on timeout monitoring system according to claim 1, characterized in that: The third monitoring module includes: a third timer; When the first controller receives the first power-ready signal sent by the expansion board, the first controller controls the third timer to start timing; If the first controller receives a reset signal sent by the second processor of the mainboard, the first controller controls the third timer to end timing, and obtains a third timing duration from the start to the end of the third timer; If the first controller determines that the third timing duration is less than a third preset duration threshold, the first controller determines that the power-on of the at least two second voltage regulating modules has not timed out; The first controller determines the states of the at least two second voltage regulating modules as a third power-on non-timeout state.

9. The server power-on timeout monitoring system according to claim 8, characterized in that: The server power-on timeout monitoring system further includes: If the first controller does not receive the reset signal within the third target time, the first controller determines that at least one of the at least two second voltage regulation modules has timed out from power-on; the third target time is the time interval between the start of the third timer and the third preset time threshold.

10. The server power-on timeout monitoring system according to claim 9, characterized in that: The server power-on timeout monitoring system further includes: When the first controller determines that at least one of the at least two second voltage regulating modules has a power-on timeout, the first controller obtains a third state value of an enable signal corresponding to each of the at least two second voltage regulating modules, and obtains a fourth state value of a third power-ready signal corresponding to each of the at least two second voltage regulating modules; The first controller determines the state of the second voltage regulation module corresponding to the third state value being the third preset state value and the fourth state value being the fourth preset state value as the third power-on timeout state; the power-on timeout monitoring result includes the third power-on timeout state or the third power-on non-timeout state.

11. The server power-on timeout monitoring system according to claim 4, characterized in that: The server power-on timeout monitoring system further includes: If the second controller parses the power-on timeout monitoring result to include the first power-on timeout state, the second controller determines that the first state value is a first preset state value and the second state value is a second preset state value, and a first voltage regulation module corresponding to the first state value is abnormal; The second controller determines that an abnormality exists in the first voltage regulation module corresponding to the first state value being a first preset state value and the second state value being a second preset state value as the abnormality analysis result.

12. The server power-on timeout monitoring system according to claim 7, characterized in that: The server power-on timeout monitoring system further includes: If the second controller parses the power-on timeout monitoring result and finds that the second power-on timeout status is included, it is determined that an abnormality exists in the expansion board; The second controller determines that an abnormality exists in the expansion board as the abnormality analysis result.

13. The server power-on timeout monitoring system according to claim 10, characterized in that: The server power-on timeout monitoring system further includes: If the second controller parses the power-on timeout monitoring result and finds that the third power-on timeout state is included in the second controller, the second controller determines that the third state value is a third preset state value and the fourth state value is a fourth preset state value, and an abnormality exists in the second voltage regulation module corresponding to the second controller; The second controller determines that an abnormality exists in the second voltage regulation module corresponding to the third state value being a third preset state value and the fourth state value being a fourth preset state value as the abnormality analysis result.

14. A server power-on timeout monitoring method, characterized in that: include: Using the first controller, according to the power-on sequence of different components in the server, the different components are segmented to perform power-on timeout monitoring on the different components to obtain power-on timeout monitoring results of the different components; transmitting the power-on timeout monitoring result to the second controller using the first controller; performing an abnormality analysis on the power-on timeout monitoring result using the second controller to obtain an abnormality analysis result; The first controller includes a first monitoring module, a second monitoring module, and a third monitoring module. The first controller is used to monitor the power-on timeout of different components in the server in sections according to the power-on sequence of the different components, including: Using the first monitoring module to monitor the power-on time of at least two first voltage regulating modules of the mainboard in the different components when the first controller triggers the power-on; using the second monitoring module to monitor the power-on time of the expansion boards in the different components when the first controller triggers the power-on; The third monitoring module is used to monitor the power-on time of at least two second voltage regulating modules of the mainboard when the first controller receives a first power-ready signal sent by an expansion board in the different components; the power-on time interval between the first voltage regulating module and the second voltage regulating module is greater than a preset interval threshold; the second voltage regulating module is powered on later than the first voltage regulating module, and the first power-ready signal is a signal sent by the expansion board to the first controller after completing its own power-on process; wherein, using the first controller to determine whether the power-on of the at least two first voltage regulating modules has timed out according to the total power-on time of the at least two first voltage regulating modules; wherein, using the first controller to determine whether the expansion board is powered on for a timeout according to the total power-on time of the expansion board; Wherein, the first controller is used to determine whether the power-on of the at least two second voltage regulating modules has timed out according to the total power-on time of the at least two second voltage regulating modules.

15. A server power-on timeout monitoring device, characterized in that: include: a monitoring unit configured to, using the first controller, perform power-on timeout monitoring on different components in the server in sections according to the power-on sequence of the different components, and obtain power-on timeout monitoring results of the different components; a transmission unit, configured to transmit the power-on timeout monitoring result to a second controller using the first controller; an analysis unit, configured to perform an abnormality analysis on the power-on timeout monitoring result using the second controller to obtain an abnormality analysis result; The first controller includes a first monitoring module, a second monitoring module and a third monitoring module, and the monitoring unit is further configured to: Using the first monitoring module to monitor the power-on time of at least two first voltage regulating modules of the mainboard in the different components when the first controller triggers the power-on; using the second monitoring module to monitor the power-on time of the expansion boards in the different components when the first controller triggers the power-on; The third monitoring module is used to monitor the power-on time of at least two second voltage regulating modules of the mainboard when the first controller receives a first power-ready signal sent by an expansion board in the different components; the power-on time interval between the first voltage regulating module and the second voltage regulating module is greater than a preset interval threshold; the second voltage regulating module is powered on later than the first voltage regulating module, and the first power-ready signal is a signal sent by the expansion board to the first controller after completing its own power-on process; The monitoring unit is further configured to, using the first controller, determine whether power-on of the at least two first voltage regulating modules has timed out based on the total power-on time of the at least two first voltage regulating modules; The monitoring unit is further configured to determine, using the first controller and based on the total power-on time of the expansion board, whether the expansion board is powered on for a timeout; The monitoring unit is further configured to determine, using the first controller, whether power-on of the at least two second voltage regulating modules has timed out based on the total power-on time of the at least two second voltage regulating modules.

16. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the server power-on timeout monitoring method as claimed in any one of claim 14 when executing the computer program.

17. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the server power-on timeout monitoring method according to any one of claim 14 are implemented.

18. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for monitoring power-on timeout on a server as claimed in any one of claim 14 are implemented.

Images