Clock domain crossing path checking method and device and related device

Abstract

The embodiment of the invention provides a clock domain crossing path checking method and device and a related device.The method comprises the steps that a clock domain crossing path set designed by a chip is obtained, and each clock domain crossing path in the clock domain crossing path set comprises a source clock domain and a target clock domain which are different in clock domain; the source clock domain and the target clock domain of each cross-clock-domain path are subjected to clock domain constraint, equivalent synchronous time sequence paths are obtained, and the source clock domain and the target clock domain of each equivalent synchronous time sequence path are from the same clock domain under the clock domain constraint; performing time sequence analysis on the equivalent synchronous time sequence path to obtain path delay information; and checking the corresponding cross-clock-domain path based on the path delay information of the equivalent synchronous time sequence path to obtain a check result of the cross-clock-domain path. According to the technical scheme provided by the embodiment of the invention, the path comprehensiveness and completeness when the time sequence analysis is carried out on the clock domain crossing path can be improved, and the time sequence analysis accuracy of the clock domain crossing path is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of digital chip design and verification, and specifically to a method, device and related devices for checking cross-clock domain paths. Background Art

[0002] With the continuous improvement of the integration level of chip design, there are more and more functional modules inside the chip design, and these functional modules may need to work in different clock domains. A path used to implement information interaction between functional modules located in different clock domains is called a cross-clock domain (Clock Domain Crossing, CDC) path. Therefore, the check of CDC paths is an important verification link in the chip design process.

[0003] In the RTL (Register Transfer Level) design stage of the chip, the check of CDC paths can detect cross-clock problems that cannot be found in functional timing simulation in advance, thereby reducing the risk of chip design failure. Therefore, how to provide technical solutions to improve the comprehensiveness and completeness of paths during the timing analysis of cross-clock domain paths in chip design and improve the accuracy of timing analysis of cross-clock domain paths has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0004] In view of this, the embodiments of the present invention provide a method, device and related devices for checking cross-clock domain paths, which improve the comprehensiveness and completeness of paths during the timing analysis of cross-clock domain paths in chip design and improve the performance of chip design.

[0005] To achieve the above object, the embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, the embodiments of the present invention provide a method for checking cross-clock domain paths, including:

[0007] Obtain a set of cross-clock domain paths of the chip design, where each cross-clock domain path in the set of cross-clock domain paths includes a source clock domain and a destination clock domain with different clock domains;

[0008] Perform clock domain constraints on the source clock domain and the destination clock domain of each cross-clock domain path to obtain equivalent synchronous timing paths, so that the source clock domain and the destination clock domain of each equivalent synchronous timing path behave as coming from the same clock domain under clock domain constraints;

[0009] Perform timing analysis on the equivalent synchronous timing paths to obtain path delay information;

[0010] Check the cross-clock domain path corresponding to it based on the path delay information of the equivalent synchronous timing path, and obtain the check result of the cross-clock domain path.

[0011] In a second aspect, an embodiment of the present invention provides a cross-clock domain path checking device, including:

[0012] A cross-clock domain path set acquisition module, configured to acquire a cross-clock domain path set of a chip design, where each cross-clock domain path in the cross-clock domain path set includes a source clock domain and a destination clock domain with different clock domains;

[0013] A clock domain constraint module, configured to perform clock domain constraints on the source clock domain and the destination clock domain of each cross-clock domain path to obtain an equivalent synchronous timing path, so that the source clock domain and the destination clock domain of each equivalent synchronous timing path appear to come from the same clock domain under clock domain constraints;

[0014] A timing analysis module, configured to perform timing analysis on the equivalent synchronous timing path to obtain path delay information;

[0015] A check result determination module, configured to check the cross-clock domain path corresponding to it based on the path delay information of the equivalent synchronous timing path, and obtain the check result of the cross-clock domain path.

[0016] In a third aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor, where the memory stores a program, and the processor calls the program stored in the memory to execute the cross-clock domain path checking method as described in the first aspect.

[0017] In a fourth aspect, an embodiment of the present invention provides a storage medium, where the storage medium stores a program, and when the program is executed, it implements the cross-clock domain path checking method as described in the first aspect

[0018] In a fifth aspect, an embodiment of the present invention provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the cross-clock domain path checking method as described in the first aspect.

[0019] A method for checking cross - clock - domain paths provided by an embodiment of the present invention includes: obtaining a set of cross - clock - domain paths in a chip design, where each cross - clock - domain path in the set of cross - clock - domain paths includes a source clock domain and a destination clock domain with different clock domains; performing clock - domain constraints on the source clock domain and the destination clock domain of each cross - clock - domain path to obtain equivalent synchronous timing paths, so that the source clock domain and the destination clock domain of each equivalent synchronous timing path behave as coming from the same clock domain under clock - domain constraints; performing timing analysis on the equivalent synchronous timing paths to obtain path delay information; and checking the corresponding cross - clock - domain paths based on the path delay information of the equivalent synchronous timing paths to obtain the check results of the cross - clock - domain paths.

[0020] The technical solution provided by the embodiment of the present invention equivalently converts all cross - clock - domain paths in the chip design into synchronous timing paths, so as to directly and accurately obtain the path delay information of all equivalent synchronous timing paths by using timing analysis. Furthermore, based on the path delay information, timing analysis can be performed on the cross - clock - domain paths corresponding to the equivalent synchronous timing paths; it avoids missing the timing analysis of cross - clock - domain paths that do not conform to timing analysis (for example, non - critical cross - clock - domain paths without added constraints cannot be subjected to timing analysis). Thus, when performing timing analysis on cross - clock - domain paths in chip design, the comprehensiveness and completeness of the paths of the analyzed cross - clock - domain paths (i.e., equivalent synchronous timing paths) can be improved, the accuracy of the timing analysis of cross - clock - domain paths can be enhanced, and further the performance of chip design can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0022] Figure 1 is a flowchart of the method for checking cross - clock - domain paths provided by the embodiment of the present invention;

[0023] Figure 2 is a structural diagram of a cross - clock - domain path provided by the embodiment of the present invention;

[0024] Figure 3a is a structural diagram of a cross - clock - domain path with grouped output provided by the embodiment of the present invention;

[0025] Figure 3b is another structural diagram of a cross - clock - domain path with grouped output provided by the embodiment of the present invention;

[0026] Figure 4It is a schematic structural diagram of an equivalent synchronous timing path provided by an embodiment of the present invention;

[0027] Figure 5 It is another schematic flowchart of a method for checking a cross-clock domain path provided by an embodiment of the present invention;

[0028] Figure 6 It is a schematic structural diagram of a device for checking a cross-clock domain path provided by an embodiment of the present invention. Detailed implementation manners

[0029] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0030] As the complexity of chip design continues to increase, there are often multiple clock domains in a chip design. There may be synchronous or asynchronous relationships between these clock domains, which leads to the emergence of cross-clock domain (CDC) paths. For example, in the design of a System on Chip (SoC), different functional modules may be driven by clock signals provided by different clock domains. For functional modules such as processors, memories, and peripherals, their clock domains are different.

[0031] The design of CDC paths needs to be specially considered in chip design to ensure the correct transmission of signals between different clock domains and timing stability. When transmitting signals across clock domains, due to the uncertain phase relationship of clock signals in different clock domains, the signals transmitted across the clock domain path may be unstable at the sampling moment in the target clock domain, resulting in metastability problems. Therefore, the primary purpose of the design of CDC paths is to eliminate metastability problems.

[0032] For example, it can be achieved through register pipelining and custom dedicated pipelining registers (cells). The number of pipeline stages and cell types are determined according to the circuit characteristics. Secondly, data competition and hazards need to be considered. The asynchronous FIFO (First In First Out) pointer is implemented using Gray code to ensure that only 1 bit jumps each time. It is also necessary to ensure that the implementation path cannot be too long, otherwise the signal transmission time is too long, affecting performance. SDC (Synopsys Design Constraints) constraints are added during the backend implementation process, or report timing is formed.

[0033] The check of the CDC path provides the basis and direction for eliminating the metastability problem, which is the ultimate goal of timing analysis. Therefore, it is very necessary to check the CDC path for the design of the CDC path.

[0034] However, usually when checking the CDC path, it is implemented by SDC constraints. Only some key CDC paths are constrained in the SDC constraints. Therefore, the check of the CDC path in chip design is not comprehensive, resulting in omissions in the optimization and adjustment of the CDC path.

[0035] To solve the above problems, the embodiments of the present invention provide a method for checking cross-clock domain paths, which is used to improve the comprehensiveness and completeness of the paths when checking cross-clock domain paths in chip design, thereby improving the performance of chip design.

[0036] Please refer to Figure 1 , Figure 1 which is a schematic flow diagram of the method for checking cross-clock domain paths provided by the embodiments of the present invention.

[0037] As Figure 1 shown, the method includes the following steps:

[0038] Step S101, obtaining a set of cross-clock domain paths of the chip design, where each cross-clock domain path in the set of cross-clock domain paths includes a source clock domain and a destination clock domain with different clock domains.

[0039] The set of cross-clock domain paths includes all the cross-clock domain paths covered by the chip design, and can be obtained after processing the cross-clock domain paths detected by a cross-clock domain path checking tool (such as the 0-in tool).

[0040] The statement that each cross-clock domain path includes a source clock domain and a destination clock domain with different clock domains means that the clock signal sources of the source clock domain and the destination clock domain of each cross-clock domain path are different.

[0041] Step S102, performing clock domain constraints on the source clock domain and the destination clock domain of each cross-clock domain path to obtain equivalent synchronous timing paths.

[0042] The source clock domain and the destination clock domain of each equivalent synchronous timing path behave as coming from the same clock domain under clock domain constraints.

[0043] An equivalent synchronous timing path refers to a path that formally behaves as a synchronous timing path, that is, formally, the source clock domain and the destination clock domain come from the same clock domain. In fact, it is still a cross-clock domain path, realizing the function of transmitting signals across clock domains.

[0044] It should be noted that the clock domain constraint has no impact on the functional implementation of the cross-clock domain transmission of the CDC path, and is only for illustrative purposes.

[0045] Since the timing analysis of the CDC path only focuses on the actual delay of the signal, that is, the path delay information, and does not pay attention to the relationship between clock domains, the cross-clock domain path can be equivalent to a synchronous timing path through the method of clock domain constraint, so as to facilitate the subsequent timing analysis of the equivalent synchronous timing path, directly calculate the path delay information, that is, obtain the path delay information of its equivalent cross-clock domain path, without affecting the function of the cross-clock domain path itself, and at the same time can facilitate the automatic calculation of the path delay information of the cross-clock domain path.

[0046] Step S103: Perform timing analysis on the equivalent synchronous timing path to obtain path delay information.

[0047] Since the CDC path involves signal transmission between asynchronous clock domains (the source clock domain and the destination clock domain come from different clock domains), and the frequency and phase relationship between asynchronous clock domains are usually unknown. This makes it difficult to accurately calculate the delay of the signal during cross-clock domain transmission, resulting in no way to support the direct automatic calculation of path delay information for the CDC path. Therefore, when performing timing analysis on the CDC path, methods such as timing exception constraints and synchronization mechanisms are usually used to indirectly check the CDC path. This leads to the fact that the CDC paths without constraints in the SDC constraints in chip design will not be subjected to timing analysis, thus reducing the comprehensiveness and completeness of the paths during CDC path checking.

[0048] For synchronous timing paths, there are ways to automatically calculate path delay information. For example, the static timing analysis (STA) method can be used to calculate the path delay information of synchronous timing paths, or dynamic timing simulation, formal verification and other methods can also be used to calculate path delay information.

[0049] Therefore, in the embodiments of the present invention, the CDC path is preprocessed with clock domain constraint, so that the equivalent synchronous timing path shows the characteristics of a synchronous timing path under the clock domain constraint: the destination clock domain and the source clock domain come from the same clock domain. Furthermore, the timing analysis method can be used to directly calculate the path delay information of the equivalent synchronous timing path, and obtain the path delay information of each equivalent synchronous timing path, that is, obtain the path delay information of its corresponding equivalent cross-clock domain path. It is convenient to perform timing analysis on the CDC path based on the path delay information subsequently, making the timing analysis result of the CDC path more reasonable and accurate.

[0050] When performing timing analysis on equivalent synchronous timing paths, timing analysis tools can be used, such as the PT (PrimeTime) tool.

[0051] When the PT Session (data saved by the PT tool for a specified project) generates a timing report (report timing), that is, when obtaining path delay information, the "get_timing_path" command can be used. Of course, in other embodiments, the "report_timing" command can also be used to obtain the path delay information (Path Delay) of the equivalent synchronous timing path.

[0052] The "get_timing_path" instruction can return a set containing multiple timing path objects, and each object represents a timing path. Through the returned timing path objects, users can further analyze and process these paths, such as extracting specific timing attributes or performing more complex timing analysis.

[0053] The "report_timing" command can provide timing information of the complete cross-clock domain path from the starting point to the ending point, including path delay, clock information, timing slack, etc.

[0054] Step S104, check the cross-clock domain path corresponding to the equivalent synchronous timing path based on the path delay information of the equivalent synchronous timing path, and obtain the check result of the cross-clock domain path.

[0055] Based on the directly calculated path delay information of the equivalent synchronous timing path, it is more convenient and accurate to perform timing analysis on the corresponding cross-clock domain path.

[0056] The technical solution provided by the embodiments of the present invention converts all cross-clock domain paths in the chip design into equivalent synchronous timing paths, so as to directly and accurately obtain the path delay information of all equivalent synchronous timing paths by using timing analysis methods. Furthermore, based on the path delay information, timing analysis can be performed on the cross-clock domain paths corresponding to the equivalent synchronous timing paths; it avoids missing the timing analysis of cross-clock domain paths that do not meet the timing analysis requirements (for example, non-critical cross-clock domain paths without added constraints cannot be analyzed for timing). Therefore, when performing timing analysis on cross-clock domain paths in chip design, the comprehensiveness and completeness of the paths of the analyzed cross-clock domain paths (i.e., equivalent synchronous timing paths) can be improved, the accuracy of the timing analysis of the cross-clock domain paths can be enhanced, and thus the performance of the chip design can be improved.

[0057] To accelerate the execution efficiency of the method for checking cross-clock domain paths, the execution process can be preprocessed to reduce the time for generating path delay information. In some embodiments, after step S101, it may further include: preprocessing the cross-clock domain path set to remove incorrect paths, where the incorrect paths are cross-clock domain paths that do not exist in the chip design, so as to perform clock domain constraints based on each cross-clock domain path in the preprocessed cross-clock domain path set.

[0058] After obtaining the cross-clock domain path set, since the cross-clock domain path set is further processed based on the cross-clock domain paths obtained by the cross-clock domain path checking tool. And the cross-clock domain paths detected by the cross-clock domain path checking tool may include paths that do not exist in the chip design, which are usually referred to as incorrect paths: cdc_false_path. These paths refer to functional paths that do not actually exist in the chip design, but the cross-clock domain path checking tool may incorrectly identify them as existing paths. For example, a signal may enter the design test logic but not be synchronized, and in this case, it can be marked as cdc_false_path. Therefore, after obtaining the cross-clock domain path set, for some non-existent incorrect paths, they can be identified and removed in advance, thereby effectively reducing the time for performing timing analysis.

[0059] In order to equivalent the cross-clock domain path to a synchronous timing path and avoid affecting the performance of the cross-clock domain path during the process of processing the cross-clock domain path, in one embodiment, virtual clocks can be used to constrain the source clock domain and the destination clock domain of the cross-clock domain path. Step S102 includes:

[0060] Obtain a predefined clock group formed by virtual clocks; constrain the source clock domain and the destination clock domain of each cross-clock domain path to the clock group to obtain an equivalent synchronous timing path.

[0061] A virtual clock (Vclk) is defined by constraints and does not require specifying a target port or network. It only exists as a reference clock. This means that the virtual clock will not have any impact on the actual physical connections and signal transmission paths of the circuit. It is only an auxiliary tool for timing analysis and constraint setting. Therefore, as an auxiliary tool, the virtual clock can better meet the timing constraint requirements and optimize the timing performance of the circuit design without changing the characteristics of the cross-clock domain path itself by providing a reference clock and assisting in timing analysis.

[0062] In implementation, by separately grouping the virtual clocks (VCLKGROUP), these different clock domains can be clearly distinguished, ensuring that the timing analysis tool can perform correct timing analysis for each clock domain. In some cases, if virtual clocks are not used, the timing analysis tool may misjudge timing violations due to differences in clock path delays. For example, when there are different delays in the clock paths of input signals and internal clock paths, using virtual clocks can more accurately reflect the actual arrival time of signals and avoid unnecessary timing violations.

[0063] Based on this, in the embodiments of the present invention, when processing a cross-clock domain path into an equivalent synchronous timing path, the source clock domain and the destination clock domain of the cross-clock domain path can be constrained to a clock group. On the one hand, this can make the cross-clock domain path appear as a synchronous timing path. On the other hand, since the cross-clock domain path is processed by clock domain constraint, the timing analysis tool can identify and process the equivalent synchronous timing path, directly calculate the path delay information, instead of using other indirect methods to determine the path delay information, which is convenient for calculating the path delay information and can more accurately reflect the actual delay situation of the cross-clock domain path, improving the accuracy of the path delay information.

[0064] It can be seen that using virtual clocks and separately setting the group VCLKGROUP can enable the timing analysis tool to more accurately analyze the timing characteristics of equivalent synchronous timing paths, avoid unnecessary misjudgment of timing violations, simplify constraint settings, and optimize the timing analysis accuracy, thereby improving the reliability and performance of circuit design.

[0065] As the complexity of chip design increases, there are interactions between multiple clock domains and multiple functional modules in chip design, which makes the types of CDC paths more diverse. For example, the types of CDC paths can be one-to-many CDC paths, one-to-one CDC paths, many-to-one CDC paths, and many-to-many CDC paths. In each CDC path, the source clock domain and the destination clock domain are both two different clock domains.

[0066] A one-to-one CDC path refers to a path used to transfer the output signal of a functional module located in the source clock domain to a functional module located in another destination clock domain.

[0067] A one-to-many CDC path refers to a path used to transfer the output signal of a functional module located in the source clock domain clk1 to functional modules located in multiple different destination clock domains (such as clk2, clk3, clk4) simultaneously. For example, a global control signal may need to be sent to multiple sub-modules simultaneously to achieve unified control and coordination.

[0068] The many-to-one CDC path refers to a path used to converge the output signals of functional modules located in multiple source clock domains to a functional module located in a destination clock domain for comprehensive processing. For example, in a parallel computing architecture, the results generated by multiple computing units need to be transmitted to a result summary module.

[0069] The many-to-many CDC path refers to a path used to implement the interaction between the output signals of functional modules located in multiple source clock domains and functional modules located in multiple destination clock domains in some complex system architectures. For example, in a multi-processor system, data exchange and communication are required between different processors.

[0070] The cross-clock domain path between the one-to-one corresponding source clock domain clk1 and destination clock domain clk2 can ensure data integrity, avoid misjudgment of timing violations, and simplify the timing analysis process. Therefore, after processing it into an equivalent synchronous timing path subsequently, it can ensure the accuracy and reliability of the timing analysis tool when performing timing analysis on it. Therefore, for the convenience of subsequent accurate timing analysis, after the cross-clock domain path checking tool obtains the cross-clock domain paths of the chip design, the cross-clock domain paths are further processed so that the destination clock domain and source clock domain of the cross-clock domain paths are in a one-to-one corresponding relationship, that is, the cross-clock domain path is an independent path.

[0071] Please continue to refer to Figure 1 , the method may further include:

[0072] Step S100, forming a cross-clock domain path set.

[0073] The cross-clock domain path set can be a set formed by each independent cross-clock domain path after processing the cross-clock domain paths in the chip design, which is convenient for subsequent timing analysis and calculating path delay information.

[0074] Step S100 may include:

[0075] Obtain a path start point list and a path end point list of the cross-clock domain path. The start points recorded in the path start point list include the source clock domain of the cross-clock domain path and the functional modules located in the source clock domain. The end points recorded in the path end point list include the destination clock domain of the cross-clock domain path and the functional modules located in the destination clock domain; the clock domains of the source clock domain and the destination clock domain are different;

[0076] According to the clock domain association relationship, combine the start points and end points in the path start point list to obtain each cross-clock domain path with a one-to-one correspondence between the source clock domain and the destination clock domain;

[0077] Form a cross-clock domain path set based on each cross-clock domain path.

[0078] The list of path start points and the list of path end points of a cross-clock domain path can be obtained by using a cross-clock domain path checking tool. For example, the 0-in tool (a CDC path checking tool) can be used to check the chip design, and a cross-clock domain path checking report of the chip design is output. The checking report includes the list of path start points (start point list) and the list of path end points (end point list) of the cross-clock domain path.

[0079] Among them, the start points recorded in the list of path start points include the source clock domain. The checking report will list the corresponding source clock domain (Source Clock) when the cross-clock domain path transmits a signal, that is, the clock domain where the signal starts to be transmitted.

[0080] The end points recorded in the list of path end points include the destination clock domain (Destination Clock). For each destination clock domain, the checking report will list the end points where the signal is transmitted to this clock domain respectively.

[0081] The functional module located in the source clock domain is used to send out signal M, and the functional module located in the destination clock domain is used to receive signal M.

[0082] Usually, when checking the CDC paths in a chip design, the obtained CDC paths are output in the form of being grouped by clock domains. Therefore, for the convenience of performing timing analysis on each cross-clock domain path, in the embodiments of the present invention, each cross-clock domain path is processed so that its source clock domain and destination clock domain are in one-to-one correspondence. That is, the above-mentioned many-to-one CDC paths, many-to-many CDC paths, and one-to-many CDC paths are all processed into one-to-one CDC paths.

[0083] For example, a one-to-many CDC path is: the signal of the functional module in the source clock domain clk1 is transmitted to the functional modules in the destination clock domains clk2, clk3, and clk4, that is, one source clock domain clk1 corresponds to 3 different destination clock domains: clk2, clk3, and clk4.

[0084] After associating the clock groups in the above one-to-many CDC path, it is split into 3 independent cross-clock domain paths:

[0085] The first cross-clock domain path where the signal of the functional module in the source clock domain clk1 is transmitted to the functional module in the destination clock domain clk2;

[0086] The second cross-clock domain path where the signal of the functional module in the source clock domain clk1 is transmitted to the functional module in the destination clock domain clk3;

[0087] The third cross-clock domain path for the signal of the functional module in the source clock domain clk1 to be transmitted to the functional module in the destination clock domain clk4.

[0088] After the above processing, the CDC paths in the chip design can be represented in the form of one-to-one CDC paths, so as to facilitate the subsequent timing analysis of each cross-clock domain path.

[0089] For the convenience of understanding the structural form of the cross-clock domain path output by the cross-clock domain path checking tool described in this article, please refer to Figure 2 , Figure 2 which is a schematic structural diagram of the cross-clock domain path provided by an embodiment of the present invention.

[0090] As Figure 2 shown, the functional module at the starting point of this cross-clock domain path is register reg1, and the functional module at the ending point is register reg2. Among them, the clock signal of the clock port CK of register reg1 is provided by clock domain clk1, and the clock signal of the clock port CK of register reg2 is provided by clock domain clk2. The signal transmission direction is: the signal output port Q of register reg1 is transmitted to the data receiving port D of register reg2.

[0091] It should be noted that the types of the functional modules in the source clock domain and the destination clock domain are related to the type of the equivalent synchronous timing path. The type of the equivalent synchronous timing path is the same as the type of the synchronous timing path. For example, according to the types of the synchronous timing paths, the types of the equivalent synchronous timing paths can include:

[0092] The synchronous timing path of the register-to-register (reg-to-reg) type. In the reg-to-reg type of synchronous timing path, the types of the functional modules in the source clock domain and the destination clock domain are both registers, such as Figure 2 shown reg1 and reg2.

[0093] The synchronous timing path of the input-to-register type. In the input-to-register type of synchronous timing path, the type of the functional module in the source clock domain is the input port of the chip design, and the type of the functional module in the destination clock domain is a register.

[0094] The synchronous timing path of the register-to-output type. In the register-to-output type of synchronous timing path, the type of the functional module in the source clock domain is a register, and the type of the functional module in the destination clock domain is the output port of the chip design.

[0095] The input-to-output type of synchronous timing path. In the input-to-output type of synchronous timing path, the type of the functional module located in the source clock domain is the input port of the chip design, and the type of the functional module located in the destination clock domain is the output port of the chip design.

[0096] Of course, in other embodiments, the type of the equivalent synchronous timing path may also be a path from a macro (such as a memory) unit to a logic unit (such as a flip-flop, a logic gate, etc.) (the path between the macro and the logic). The starting point of such a path is the output pin or internal node of the macro unit, and the ending point of the path is the input pin or internal node of the logic unit.

[0097] Or it may also be a timing path from one macro unit to another macro unit (the path between the macro and the macro). The starting point and the ending point of such a path are both the pins or internal nodes of the macro unit.

[0098] That is to say, the embodiments of the present invention support the processing of any equivalent synchronous timing path abstracted as the same type as the above-mentioned synchronous timing path to perform timing analysis on the equivalent synchronous timing path and directly calculate the path delay information.

[0099] To further understand the manifestation form of the cross-clock domain path initially obtained by the cross-clock domain path checking tool, taking the 0in tool to check the cross-clock domain path as an example, the cross-clock domain paths grouped by clock domain output in its inspection report can be referred to Figure 3a and Figure 3b , Figure 3a is a schematic structural diagram of the cross-clock domain path grouped and output provided by the embodiments of the present invention, Figure 3b is another schematic structural diagram of the cross-clock domain path grouped and output provided by the embodiments of the present invention.

[0100] As Figure 3a and Figure 3b shown, grouped by the source clock domain clka, the cross-clock domain paths it includes can be expressed as:

[0101] Figure 3a The many-to-one CDC path shown in : the cross-clock domain path between the functional module reg11 located in the source clock domain clka and the functional module reg2 located in the destination clock domain clkb, and the path delay information generated by it is expressed as: PathDelay1, and the cross-clock domain path between the functional module reg12 located in the source clock domain clka and the functional module reg2 located in the destination clock domain clkb, and the path delay information generated by it is expressed as: Path Delay2.

[0102] Figure 3b The one-to-many CDC path shown: The cross-clock domain path between the functional module reg1 in the source clock domain clka and the functional module reg21 in the destination clock domain clkb, the path delay information generated by which is expressed as: PathDelay3, and the cross-clock domain path between the functional module reg1 in the source clock domain clka and the functional module reg22 in the destination clock domain clkb, the path delay information generated by which is expressed as: Path Delay4.

[0103] It can be seen that the cross-clock domain paths output according to clock grouping in chip design include: one-to-one CDC paths, one-to-many CDC paths, many-to-one CDC paths, and many-to-many CDC paths. Therefore, in order to facilitate processing various types of cross-clock domain paths into the form of one-to-one CDC paths, each group of source clock domains and destination clock domains can be combined according to the clock domain association relationship to form an independent cross-clock domain path. Finally, each independent cross-clock domain path forms a cross-clock domain path set, providing an implementation basis for subsequent processing of synchronous sequential circuits.

[0104] Taking the processing of a one-to-many CDC path into a one-to-one CDC path as an example for illustration. In order to associate the source clock domain in the path start point list with the destination clock domain in the path end point list, the check report usually organizes each group of clock domain combinations according to the clock domain association relationship (such as clock pair: Clock Pair). Each clock pair lists a source clock domain and multiple destination clock domains, as well as the path details between these clock domains. Thus, the specific path and related timing information of the signal transmitted from one source clock domain to multiple destination clock domains can be clearly seen, and then it can be split into CDC paths with one-to-one correspondence between the source clock domain and the destination clock domain, as follows:

[0105]

[0106] Each obtained independent cross-clock domain path includes a source clock domain and a destination clock domain with one-to-one correspondence, thus facilitating subsequent accurate timing analysis.

[0107] When processing a one-to-one CDC path, all start points in the path start point list and all end points in the path end point list can be traversed. The start points include the source clock domain and the functional modules located in the source clock domain, and the end points include the destination clock domain and the functional modules located in the destination clock domain.

[0108] Then, according to the clock domain association relationship, the source clock domain in each starting point and the functional modules in the source clock domain are combined with the corresponding associated destination clock domain and the functional modules in the destination clock domain to output independent CDC paths represented by "start / ck→end / D". Until all the starting points in the entire path starting point list and all the ending points in the path ending point list are traversed, each corresponding CDC path is output to form a cross-clock domain path set.

[0109] After obtaining the cross-clock domain path set, each cross-clock domain path in it can be processed for synchronous timing paths to form equivalent synchronous timing paths. Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of the equivalent synchronous timing path provided by the embodiment of the present invention.

[0110] For Figure 3a and Figure 3b the cross-clock domain paths shown, after processing, the independent cross-clock domain paths shown in Figure 2 are obtained. Furthermore, based on the cross-clock domain paths shown in Figure 2 , clock domain constraints are imposed on both the source clock domain and the destination clock domain, and the source clock domain and the destination clock domain are constrained to a clock group to obtain the equivalent synchronous timing paths shown in Figure 4 .

[0111] As shown in Figure 4 , for the equivalent synchronous timing path, the source clock domain: the clock domain where register reg1 is located, and the destination clock domain: the clock domain where register reg2 is located, are shown to come from the same clock domain: the clock group Vclk formed by the jointly constrained virtual clock. Thus, the cross-clock domain path can have the characteristics of a synchronous timing path, facilitating the timing analysis tool to identify and perform timing analysis, and directly calculating the path delay information (Path Delay).

[0112] When calculating the path delay information of each equivalent synchronous timing path, since the cross-clock domain path has been processed into a synchronous timing path (timing path) at this time, the instruction of the timing analysis tool (such as PT: PrimeTime): report_timing can be directly used to calculate the path delay information of this equivalent synchronous timing path.

[0113] The report_timing command is used to generate the timing report of the synchronous timing path in the chip design. It provides sufficient flexibility to clearly focus on a single synchronous timing path in the chip design or the path set formed by each synchronous timing path, such as the set formed by the equivalent synchronous timing paths after cross-clock domain path processing.

[0114] After the path delay information of each equivalent synchronous timing path is obtained, the path delay information can be used to check the cross-clock domain path corresponding to the equivalent synchronous timing path.

[0115] In one implementation, step S104 may include:

[0116] According to the design characteristics of the cross-clock domain path corresponding to the equivalent synchronous timing path, a check rule matching the design characteristics is determined; the path delay information of the equivalent synchronous timing path is checked using the check rule to obtain the check result of the cross-clock domain path.

[0117] Since different chip designs have different design requirements, the characteristics of the cross-clock domain paths designed under different design requirements are also different, so as to meet the functional implementation of the chip design.

[0118] Different design features have different timing requirements to be met. Based on the timing requirements, check rules are established in a targeted manner so that each design feature has a matching check rule to perform targeted timing checks.

[0119] Therefore, after obtaining the path delay information of each equivalent synchronous timing path, the matching check rules can be used to perform accurate checks in combination with the design characteristics of the cross-clock domain path corresponding to the equivalent synchronous timing path.

[0120] Please refer to Figure 5 , Figure 5 It is another flowchart diagram of the method for checking a cross-clock domain path provided by an embodiment of the present invention.

[0121] like Figure 5 As shown, the method comprises the following steps:

[0122] Step S200, obtaining a cross-clock domain path set of a chip design, wherein each cross-clock domain path in the cross-clock domain path set includes a source clock domain and a destination clock domain in different clock domains.

[0123] Step S201 , performing clock domain constraints on the source clock domain and the destination clock domain of each cross-clock domain path to obtain an equivalent synchronous timing path.

[0124] Step S202: Perform timing analysis on the equivalent synchronous timing path to obtain path delay information.

[0125] Step S203: determining a check rule matching the design characteristics according to the design characteristics of the cross-clock domain path corresponding to the equivalent synchronous timing path.

[0126] Step S204: Check the path delay information of the equivalent synchronous timing path using the checking rule to obtain the checking result of the cross-clock domain path.

[0127] Step S205: Determine the processing method for the cross-clock domain path according to the checking result.

[0128] Step S206: Judge whether the processing result of the processing method changes the functional modules in the source clock domain and / or destination clock domain of the cross-clock domain path. If so, execute Step S200; if not, execute Step S201.

[0129] Step S207: Stop checking the cross-clock domain path until the checking result of the processed cross-clock domain path meets the checking rule.

[0130] When processing the cross-clock domain path based on the checking result, the processing result may either change the path endpoints of the cross-clock domain path, that is, change the functional module in the source clock domain at the starting point of the cross-clock domain path, or the functional module in the destination clock domain at the ending point. For example, changing the path connection or logic function in the chip design results in modifications to the netlist or library file (lib). In the case of changing the path endpoints of the cross-clock domain path, at this time, the cross-clock domain path has undergone a substantial change. Therefore, start the timing analysis of the cross-clock domain path from the initial step again, that is, start execution from obtaining the cross-clock domain path set.

[0131] It may also not change the path endpoints of the cross-clock domain path. For example, according to the different EDA verifications and physical implementation progress, in the case of dividing the cycle of the entire chip design into different stages, for the placement and routing (P&R) processing performed for each stage, since the placement and routing process is based on the existing design logic and connection relationships and is an optimization of the existing paths, it will not affect the path endpoints of the cross-clock domain path and will not change the path endpoints of the cross-clock domain path.

[0132] In the case of not changing the path endpoints of the cross-clock domain path, at this time, the cross-clock domain path itself has not undergone a substantial change. Therefore, it is not necessary to perform timing analysis from the initial step of obtaining the cross-clock domain path set. Instead, re-constrain the clock domain of the cross-clock domain path, and reflect the adjusted timing situation in the equivalent synchronous timing path formed after re-constraining the clock domain. Therefore, execute Step S201 at this time to obtain the equivalent synchronous timing path.

[0133] Select different starting steps for timing analysis according to different processing results to quickly check the timing problems of the cross-clock domain path and subsequent processing of the cross-clock domain path.

[0134] In one implementation, step S205 may include:

[0135] When it is determined that the design characteristics of the cross-clock domain path meet the inspection rules, judge the optimizable situation of the cross-clock domain path, and when it is judged that the cross-clock domain path is optimizable, determine the processing method as: optimizing the cross-clock domain path; when it is determined that the design characteristics of the cross-clock domain path do not meet the inspection rules, determine the processing method as: adjusting the cross-clock domain path.

[0136] Different inspection results lead to different processing methods for the cross-clock domain path. When the inspection result meets the inspection rules, if the cross-clock domain path can be optimized, the path can be optimized, such as re-layout and routing the cross-clock domain path as described above to achieve path optimization.

[0137] When the inspection result does not meet the inspection rules, there is no problem of optimization at this time. The main problem is to adjust the chip design, improve the path design of the cross-clock domain path, and modify the connection relationship or logic function of the cross-clock domain path.

[0138] The examples of optimizing or adjusting the path in the above processing method are only for illustration. In the actual process, whether optimizing or adjusting the cross-clock domain path, the processing result can either change the functional modules in the source clock domain and / or the destination clock domain of the cross-clock domain path, or not change the functional modules in the source clock domain and / or the destination clock domain of the cross-clock domain path. Therefore, after selecting the processing method to process the cross-clock domain path, the subsequent determined re-execution steps also need to be determined according to the processing results generated by the processing method.

[0139] To support the timing analysis of cross-clock domain paths with different design characteristics, specific inspections can be carried out according to the inspection rules that match the design characteristics of the cross-clock domain path. In one implementation, when the cross-clock domain path is: the first cross-clock domain path with the design characteristics of controlling and implementing the chip design function; the inspection rule that matches the design characteristics of the first cross-clock domain path can be: the first inspection rule for inspecting the timing constraints of the first cross-clock domain path.

[0140] At this time, step S204 may include:

[0141] Calculate the timing margin based on the timing constraint reference value defined in the first inspection rule and the path delay information of the equivalent synchronous timing path;

[0142] If the timing margin is greater than or equal to the first value, the timing constraint of the first cross-clock domain path meets the timing constraint reference value, and it is determined that the check result is: the design characteristics of the first cross-clock domain path meet the first check rule; and the optimizable situation of the first cross-clock domain path is determined according to the value of the timing margin.

[0143] If the timing margin is less than the first value, the timing constraint of the first cross-clock domain path does not meet the timing constraint reference value, and it is determined that the check result is: the design characteristics of the first cross-clock domain path do not meet the first check rule.

[0144] The first cross-clock domain path can be a CDC path for transmitting critical data or a CDC path for transmitting control signals.

[0145] The first check rule is mainly used to check the timing constraint of the first cross-clock domain path. This is because when the first cross-clock domain path transmits critical data or control signals, certain timing constraints need to be met to ensure that the critical data or control signals are safely and accurately transmitted from one source clock domain to another destination clock domain. To avoid metastability problems and reduce the impact on circuit reliability.

[0146] The timing constraint can be the clock relationship between different clock domains, including information such as clock frequency and phase difference, or can also include the timing requirements for the data to reach the destination clock domain from the source clock domain, including maximum transmission delay, clock skew, etc.

[0147] The timing constraint can be set based on design requirements to form SDC constraints. For example, the "set_max_delay" is used to set the maximum delay constraint, which is used to ensure that the delay of the cross-clock domain path does not exceed a certain set value to check the setup time of the functional module (such as a register) located in the destination clock domain.

[0148] The "set_max_delay" is used to set the minimum delay constraint, which is used to ensure that the delay of the cross-clock domain path reaches at least a certain set value to meet the hold time requirement.

[0149] The timing constraint reference value can be the maximum delay constraint or the minimum delay constraint. The timing margin can be obtained by subtracting the path delay information of the already calculated equivalent synchronous timing path according to the specific representation of the timing constraint reference value. If the path delay information is less than or equal to the set_max_delay value set in the SDC constraint, the cross-clock domain path meets the maximum delay constraint; if the path delay information is greater than or equal to the set_min_delay value set in the SDC constraint, the cross-clock domain path meets the minimum delay constraint.

[0150] When the timing constraint reference value is the maximum delay constraint, the calculation of the timing margin can be the difference obtained by subtracting the path delay information from the set_max_delay value; when the timing constraint reference value is the minimum delay constraint, the calculation of the timing margin can be the difference obtained by subtracting the set_min_delay value from the path delay information.

[0151] The first value can be 0, that is, when the timing margin is positive or the path delay information meets the timing constraint reference value, it indicates that the first cross-clock domain path meets the first check rule. On the premise of meeting the first check rule, further determine whether there is an opportunity for optimization in the first cross-clock domain path. If there is, optimize the first cross-clock domain path, that is, the processing method at this time is optimization.

[0152] When the timing margin is negative, it indicates that the first cross-clock domain path does not meet the first check rule, and at this time, adjust the first cross-clock domain path.

[0153] In some other embodiments, in the case where the cross-clock domain path is: a second cross-clock domain path with the design characteristic of synchronous transmission of multi-bit data; the check rule matching the design characteristic of the second cross-clock domain path is: a second check rule for checking the timing state of the second cross-clock domain path.

[0154] At this time, step S204 may include:

[0155] Use the path delay information of the equivalent synchronous timing path to determine the write data delay information of the source clock domain and the read data delay information of the destination clock domain, and calculate the data skew using the write data delay information and the read data delay information;

[0156] And, use the path delay information of the equivalent synchronous timing path to determine the read pointer delay information of the source clock domain and the write pointer delay information of the destination clock domain, and calculate the pointer skew using the read pointer delay information and the write pointer delay information;

[0157] Use the clock frequency of the destination clock domain defined in the second check rule to determine the clock period of the destination clock domain;

[0158] Judge whether both the data skew and the pointer skew are less than the clock period;

[0159] If so, determine that the timing state of the second cross-clock domain path is stable, and determine the check result as: the design characteristic of the second cross-clock domain path meets the second check rule;

[0160] If not, determine that the timing state of the second cross-clock domain path is unstable, and determine the check result as: the design characteristic of the second cross-clock domain path does not meet the second check rule.

[0161] The second cross-clock domain path may be an asynchronous FIFO CDC path.

[0162] The second check rule is used to check the timing status of the second cross-clock domain path, that is, to check whether the timing of the second cross-clock domain path can be synchronized and can stably transmit multi-bit data. Ensure reliable data transmission between different clock domains and the stable operation of the FIFO.

[0163] When checking whether the second cross-clock domain path meets the second check rule, it can be achieved by calculating data skew, pointer skew, and clock period, and determining whether there are races and hazards. This helps improve the overall performance and reliability of chip design.

[0164] When calculating the data skew, since the timing analysis tool has been used to calculate the equivalent synchronous timing path to obtain the path delay information. For example, use the report_timing command of the PT tool to obtain the path delay information from the functional module (such as a register) in the source clock domain to the functional module (such as a register) in the destination clock domain. The report_timing command will generate a detailed path delay report, including the delays of the data path and the clock path.

[0165] Therefore, the write data delay information in the source clock domain can be determined from the path delay information: T data_write : T data_write is the delay of the data signal from the source register to the cross-clock domain boundary, and the read data delay information T data_read : T data_read is the delay of the data signal from the cross-clock domain boundary to the destination register.

[0166] Then calculate the data skew Data Skew = T data_read - T data_write .

[0167] In addition, the write pointer delay information T ptr_write : T ptr_write in the source clock domain can be determined from the path delay information, where T ptr_read : T ptr_read is the delay of the pointer signal from the source register to the cross-clock domain boundary, and the read pointer delay information T

[0168] Then calculate the pointer skew Pointer Skew = T ptr_read - T ptr_write .

[0169] Next, calculate the clock period from the clock frequencies defined in the second check rule. The clock period refers to the period time of the clock signal.

[0170] Ensure that the data skew and pointer skew are within an acceptable range. Usually, it is necessary to determine whether the data skew and pointer skew are less than or equal to one clock period to avoid data errors or pointer inconsistencies.

[0171] Therefore, after calculating the data skew, pointer skew, and clock period, it can be determined whether both the data skew and the pointer skew are less than the clock period. If so, it indicates that the timing state of the second cross-clock domain path is stable, and the design characteristics of the second cross-clock domain path meet the second check rule. Then, further consider whether the second cross-clock domain path has the possibility of optimization. If so, perform optimization.

[0172] When one of them is not less than the clock period, it indicates that the design characteristics of the second cross-clock domain path do not meet the second check rule. At this time, perform path adjustment on the second cross-clock domain path.

[0173] In some other embodiments, when the first cross-clock domain path includes a third cross-clock domain path having the design characteristic of synchronously transmitting critical data; the check rule matching the design characteristic of the third cross-clock domain path is: the third check rule for checking the timing performance of the third cross-clock domain path.

[0174] At this time, step S204 may include:

[0175] Judge whether the performance metrics defined in the third check rule exceed the path delay information of the equivalent synchronous timing path;

[0176] If so, determine that the timing performance of the third cross-clock domain path meets the standard, and determine the inspection result as: the design characteristics of the third cross-clock domain path meet the third check rule, and determine the optimizable situation of the third cross-clock domain path according to the difference between the path delay information and the performance metrics;

[0177] If not, determine that the timing performance of the third cross-clock domain path does not meet the standard, and determine the inspection result as: the design characteristics of the third cross-clock domain path do not meet the third check rule.

[0178] The third cross-clock domain path can be the cross-clock domain path for transmitting critical data as described above. That is to say, for the cross-clock domain path for transmitting critical data, when verifying the timing constraints, the timing performance can also be verified. This is because for the cross-clock domain path for transmitting critical data, verifying the timing constraints is to ensure the basic timing requirements and the security of data transmission, while verifying the timing performance is to optimize the system performance, consider the actual working conditions, and improve the design reliability. The two complement each other to jointly ensure the design quality of the CDC path and the overall system performance.

[0179] The performance metrics can be metrics that affect the overall performance of the chip design, such as the maximum delay (max delay), minimum delay (min delay), clock skew, etc., defined based on the design requirements.

[0180] After calculating the path delay information of the equivalent synchronous timing path, the path delay information can be used to compare the maximum delay, minimum delay, and clock skew respectively.

[0181] Among them, the maximum delay comparison is: comparing the maximum delay in the calculated path delay information with the maximum delay set in the performance metrics. If it is less than or equal to the set maximum delay, the performance requirements are met.

[0182] The minimum delay comparison is: comparing the minimum delay in the calculated path delay information with the minimum delay set in the performance metrics. If it is greater than or equal to the set minimum delay, the performance requirements are met.

[0183] The clock skew comparison is: checking whether the clock skew in the path delay information is within an acceptable range, usually less than or equal to a certain proportion of the clock period of the destination clock domain.

[0184] The clock period of the destination clock domain can be calculated based on the already set clock frequency.

[0185] In other embodiments, when the cross-clock domain path is a fourth cross-clock domain path with the design characteristic of processing signals with a low change frequency; the check rule matching the design characteristic of the fourth cross-clock domain path is: a fourth check rule for checking the relaxable situation of the timing constraints of the fourth cross-clock domain path.

[0186] At this time, step S204 may include:

[0187] Determine the maximum delay information and minimum delay information defined in the fourth check rule;

[0188] Use the path delay information to compare with the maximum delay information and the minimum delay information;

[0189] Determine whether the path delay information of the equivalent synchronous timing path is less than or equal to the maximum delay information, or greater than or equal to the maximum delay information;

[0190] If so, the fourth cross-clock domain path has timing margin, and determine the inspection result as: the design characteristics of the fourth cross-clock domain path meet the fourth inspection rule; and determine the optimizable situation of the fourth cross-clock domain path according to the timing margin;

[0191] If not, the fourth cross-clock domain path does not have timing margin, and determine the inspection result as: the design characteristics of the fourth cross-clock domain path do not meet the fourth inspection rule.

[0192] The fourth cross-clock domain path can be a static cross-clock domain path or a quasi-static cross-clock domain path.

[0193] A static cross-clock domain path refers to a cross-clock domain path in which the signals transmitted in the chip design always remain unchanged. For example, the initial value setting paths of some configuration registers, and these paths do not change during the system operation.

[0194] A quasi-static cross-clock domain path refers to a cross-clock domain path in which the signals transmitted in the chip design change very slowly. For example, the paths of some control signals, and these signals remain unchanged most of the time but occasionally change.

[0195] For the fourth cross-clock domain path, it can be determined whether the timing constraint can be relaxed by judging its timing margin.

[0196] In one implementation, when it is determined that the fourth cross-clock domain path is optimizable according to the timing margin, relax the timing of the fourth cross-clock domain path.

[0197] That is, when it is judged that the path delay information is much less than the maximum delay information, it is determined that the fourth cross-clock domain path is optimizable. At this time, it shows that the fourth cross-clock domain path has a large margin in timing, and the timing constraint can be considered to be relaxed.

[0198] Similarly, when it is judged that the path delay information is much greater than the minimum delay information, it is determined that the fourth cross-clock domain path is optimizable. At this time, it shows that the fourth cross-clock domain path is relatively safe in timing, and the timing can be considered to be relaxed.

[0199] Otherwise, do not consider relaxing the timing of the fourth cross-clock domain path, that is, it does not meet the fourth inspection rule.

[0200] It can be seen that the technical solution provided by the embodiment of the present invention can effectively check the timing of various cross-clock domain paths, and can perform timing analysis on the cross-clock domain paths that were originally not analyzed for timing and were thus missed, so as to timely detect the paths that do not meet the requirements or have excessive path skews in the cross-clock domain paths. At the same time, based on the generated path delay information, it can guide designers to add SDC constraints to some non-critical cross-clock domain paths (such as quasi-static cross-clock domain paths or static cross-clock domain paths), relax the timing, and perform targeted optimization on them, thereby significantly improving the efficiency of designers in P&R.

[0201] The embodiment of the present invention also provides a cross-clock domain path checking device for implementing the structure of the method described in any of the foregoing embodiments.

[0202] Please refer to Figure 6 , Figure 6 which is a schematic structural diagram of the cross-clock domain path checking device provided by the embodiment of the present invention.

[0203] As Figure 6 shown, the device may include:

[0204] A cross-clock domain path set acquisition module 61 for acquiring a cross-clock domain path set of a chip design, where each cross-clock domain path in the cross-clock domain path set includes a source clock domain and a destination clock domain with different clock domains;

[0205] A clock domain constraint module 62 for performing clock domain constraints on the source clock domain and the destination clock domain of each cross-clock domain path to obtain equivalent synchronous timing paths, where the source clock domain and the destination clock domain of each equivalent synchronous timing path behave as coming from the same clock domain under clock domain constraints;

[0206] A timing analysis module 63 for performing timing analysis on the equivalent synchronous timing paths to obtain path delay information;

[0207] An inspection result determination module 64 for checking the cross-clock domain path corresponding to it based on the path delay information of the equivalent synchronous timing path to obtain the inspection result of the cross-clock domain path.

[0208] Optionally, the clock domain constraint module 62 for performing clock domain constraints on the source clock domain and the destination clock domain of each cross-clock domain path to obtain equivalent synchronous timing paths includes:

[0209] Acquiring a pre-defined clock group formed by virtual clocks;

[0210] Constraining the source clock domain and the destination clock domain of each cross-clock domain path to the clock group to obtain equivalent synchronous timing paths.

[0211] Optionally, it further includes:

[0212] A cross-clock domain path set forming module 60 for forming a cross-clock domain path set;

[0213] The cross-clock domain path set forming module 60 for forming a cross-clock domain path set includes:

[0214] Obtain a path start point list and a path end point list of the cross-clock domain path. The start points recorded in the path start point list include the source clock domain of the cross-clock domain path and the functional modules located in the source clock domain. The end points recorded in the path end point list include the destination clock domain of the cross-clock domain path and the functional modules located in the destination clock domain; the clock domains of the source clock domain and the destination clock domain are different;

[0215] Combine the start points and end points in the path start point list according to the clock domain association relationship to obtain each cross-clock domain path with different source clock domains and destination clock domains;

[0216] Form a cross-clock domain path set based on each cross-clock domain path.

[0217] Optionally, the inspection result determination module 64 is used to inspect the corresponding cross-clock domain path based on the path delay information of the equivalent synchronous timing path to obtain the inspection result of the cross-clock domain path, including:

[0218] Determine an inspection rule matching the design characteristics according to the design characteristics of the cross-clock domain path corresponding to the equivalent synchronous timing path;

[0219] Use the inspection rule to inspect the path delay information of the equivalent synchronous timing path to obtain the inspection result of the cross-clock domain path.

[0220] Optionally, it further includes:

[0221] A cross-clock domain path processing module 65 for determining a processing method for the cross-clock domain path according to the inspection result;

[0222] A re-inspection execution step determination module 66 for determining the execution steps when re-inspecting the cross-clock domain path based on the processing results generated by different processing methods.

[0223] Wherein, when the processing result generated by the processing method is to change the functional modules located in the source clock domain and / or the destination clock domain in the cross-clock domain path, it is determined that when re-inspecting the cross-clock domain path, the cross-clock domain path set acquisition module 61 is controlled to execute the acquisition of the cross-clock domain path set;

[0224] When the processing result generated by the processing method is that the functional modules in the source clock domain and / or the destination clock domain in the cross-clock domain path are not changed, the clock domain constraint module 62 is rechecked when the cross-clock domain path is rechecked, and clock domain constraints are performed on the source clock domain and the destination clock domain of each cross-clock domain path to obtain an equivalent synchronous timing path.

[0225] Optionally, the timing analysis module 63 is a timing analysis tool; the set of cross-clock domain paths of the chip design obtained by the cross-clock domain path set acquisition module 61 is provided by a cross-clock domain path check tool.

[0226] The timing analysis tool can be a PT tool, and the cross-clock domain path check tool can be a 0in tool.

[0227] The technical solution provided by the embodiment of the present invention directly and accurately obtains the path delay information of all equivalent synchronous timing paths by equivalently converting all cross-clock domain paths in the chip design into synchronous timing paths, and then based on the path delay information, timing analysis can be performed on the cross-clock domain paths corresponding to the equivalent synchronous timing paths; it avoids missing the timing analysis of cross-clock domain paths that do not conform to timing analysis (for example, non-critical cross-clock domain paths without added constraints cannot be analyzed), so that when performing timing analysis on cross-clock domain paths in chip design, the path comprehensiveness and completeness of the analyzed cross-clock domain paths (i.e., equivalent synchronous timing paths) can be improved, the accuracy of the timing analysis of cross-clock domain paths can be improved, and thus the performance of chip design can be improved.

[0228] An embodiment of the present invention provides an electronic device, such as a computer device such as a terminal device or a server device, including a memory and a processor. The memory stores a program, and the processor calls the program stored in the memory to execute the cross-clock domain path check method described in any one of the foregoing embodiments.

[0229] An embodiment of the present invention provides a storage medium that stores a program, and when the program is executed, it implements the cross-clock domain path check method described in any one of the foregoing embodiments.

[0230] An embodiment of the present invention provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the cross-clock domain path check method described in any one of the foregoing embodiments.

[0231] The above describes multiple embodiment solutions provided by the embodiments of the present invention. The various optional methods described in each embodiment solution can be combined and cross-referenced with each other without conflict, so as to extend multiple possible embodiment solutions, all of which can be considered as the embodiment solutions disclosed and made public by the embodiments of the present invention.

[0232] Although the embodiments of the present invention are disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for checking a cross-clock domain path, characterized in that: include: Acquire a cross-clock domain path set of a chip design, wherein each cross-clock domain path in the cross-clock domain path set includes a source clock domain and a destination clock domain in different clock domains; Perform clock domain constraints on the source clock domain and the destination clock domain of each cross-clock domain path to obtain an equivalent synchronous timing path. Under the clock domain constraints, the source clock domain and the destination clock domain of each equivalent synchronous timing path appear to be from the same clock domain. Performing timing analysis on the equivalent synchronous timing path to obtain path delay information; Based on the path delay information of the equivalent synchronous timing path, the corresponding cross-clock domain path is checked to obtain the check result of the cross-clock domain path.

2. The method for checking a cross-clock domain path according to claim 1, characterized in that: The step of performing clock domain constraints on the source clock domain and the destination clock domain of each cross-clock domain path to obtain an equivalent synchronous timing path includes: Acquire a predefined clock group, wherein the clock group is formed by virtual clocks; The source clock domain and the destination clock domain of each cross-clock domain path are constrained to the clock group to obtain an equivalent synchronous timing path.

3. The method for checking a cross-clock domain path according to claim 2, wherein: Before the step of obtaining the cross-clock domain path set, the method further includes: forming a cross-clock domain path set; The forming of a cross-clock domain path set comprises: Obtain a path starting point list and a path ending point list of a cross-clock domain path, wherein the starting point recorded in the path starting point list includes a source clock domain of the cross-clock domain path and a functional module located in the source clock domain, and the ending point recorded in the path ending point list includes a destination clock domain of the cross-clock domain path and a functional module located in the destination clock domain; the source clock domain and the destination clock domain are different clock domains; According to the clock domain association relationship, the starting point and the ending point in the path starting point list are combined to obtain each cross-clock domain path with a one-to-one correspondence between the source clock domain and the destination clock domain; A cross-clock domain path set is formed based on each cross-clock domain path.

4. The method for checking a cross-clock domain path according to any one of claims 1 to 3, characterized in that: The step of checking the cross-clock domain path corresponding to the equivalent synchronous timing path based on the path delay information thereof to obtain the checking result of the cross-clock domain path includes: Determining, according to the design characteristics of the cross-clock domain path corresponding to the equivalent synchronous timing path, a check rule matching the design characteristics; The path delay information of the equivalent synchronous timing path is checked using the checking rule to obtain a checking result of the cross-clock domain path.

5. The method for checking a cross-clock domain path according to claim 4, characterized in that: After the step of using the inspection rule to inspect the path delay information of the equivalent synchronous timing path to obtain the inspection result of the cross-clock domain path, the method further includes: Determining a processing method for the cross-clock domain path according to the inspection result; Based on the processing results generated by different processing methods, determine the execution steps when rechecking the cross-clock domain path; Wherein, the processing result generated in the processing mode is: when the functional module located in the source clock domain and / or the destination clock domain in the cross-clock domain path is changed, the step of obtaining the cross-clock domain path set is performed when it is determined to recheck the cross-clock domain path; When the processing result generated by the processing method is: when the functional modules located in the source clock domain and / or the destination clock domain in the cross-clock domain path are not changed, it is determined to re-check the cross-clock domain path by executing the step of performing clock domain constraints on the source clock domain and the destination clock domain of each cross-clock domain path to obtain an equivalent synchronous timing path.

6. The method for checking a cross-clock domain path according to claim 5, characterized in that: The determining, according to the inspection result, a processing method for the cross-clock domain path includes: When it is determined that the inspection result is that the design characteristic of the cross-clock domain path meets the inspection rule, the optimizability of the cross-clock domain path is judged, and when it is judged that the cross-clock domain path is optimizable, the processing method is determined as: optimizing the cross-clock domain path; When it is determined that the inspection result is that the design characteristic of the cross-clock domain path does not meet the inspection rule, a processing manner is determined as: adjusting the cross-clock domain path.

7. The method for checking a cross-clock domain path according to claim 6, characterized in that: The cross-clock domain path is: a first cross-clock domain path having design characteristics for controlling and implementing chip design functions; The check rule that matches the design characteristic of the first cross-clock domain path is: a first check rule that checks the timing constraint of the first cross-clock domain path; The checking of the path delay information of the equivalent synchronous timing path by using the checking rule to obtain the checking result of the cross-clock domain path includes: Calculating a timing margin based on a timing constraint reference value defined in the first checking rule and path delay information of the equivalent synchronous timing path; If the timing margin is greater than or equal to the first value, the timing constraint of the first cross-clock domain path satisfies the timing constraint reference value, and the check result is determined as follows: the design characteristic of the first cross-clock domain path satisfies the first check rule; and the optimizability of the first cross-clock domain path is determined according to the value of the timing margin; If the timing margin is less than the first value, the timing constraint of the first cross-clock domain path does not meet the timing constraint reference value, and the check result is determined as: the design characteristic of the first cross-clock domain path does not meet the first check rule.

8. The method for checking a cross-clock domain path according to claim 6, wherein: The cross-clock domain path is: a second cross-clock domain path having a design characteristic of synchronously transmitting multi-bit data; the inspection rule matching the design characteristic of the second cross-clock domain path is: a second inspection rule for inspecting the timing state of the second cross-clock domain path; The checking of the path delay information of the equivalent synchronous timing path by using the checking rule to obtain the checking result of the cross-clock domain path corresponding thereto includes: Determine write data delay information of a source clock domain and read data delay information of a destination clock domain using the path delay information of the equivalent synchronous timing path, and calculate data skew using the write data delay information and the read data delay information; And, using the path delay information of the equivalent synchronous timing path to determine the read pointer delay information of the source clock domain and the write pointer delay information of the destination clock domain, and using the read pointer delay information and the write pointer delay information to calculate the pointer skew; Determine the clock period of the destination clock domain using the clock frequency of the destination clock domain defined in the second checking rule; Determine whether the data skew and the pointer skew are both smaller than the clock period; If yes, it is determined that the timing state of the second cross-clock domain path is stable, and the inspection result is determined as: the design characteristics of the second cross-clock domain path meet the second inspection rule; If not, it is determined that the timing state of the second cross-clock domain path is unstable, and the check result is determined as: the design characteristics of the second cross-clock domain path do not meet the second check rule.

9. The method for checking a cross-clock domain path according to claim 7, characterized in that: When the first cross-clock domain path includes: a third cross-clock domain path having a design characteristic of synchronously transmitting key data; the inspection rule matching the design characteristic of the third cross-clock domain path is: a third inspection rule for inspecting the timing performance of the third cross-clock domain path; The checking of the path delay information of the equivalent synchronous timing path by using the checking rule to obtain the checking result of the cross-clock domain path corresponding thereto includes: Determining whether the performance indicator defined in the third checking rule exceeds the path delay information of the equivalent synchronous timing path; If yes, it is determined that the timing performance of the third cross-clock domain path meets the standard, and the inspection result is determined as follows: the design characteristics of the third cross-clock domain path meet the third inspection rule, and according to the difference between the path delay information and the performance indicator, the optimizability of the third cross-clock domain path is determined; If not, it is determined that the timing performance of the third cross-clock domain path does not meet the standard, and the inspection result is determined as: the design characteristics of the third cross-clock domain path do not meet the third inspection rule.

10. The method for checking a cross-clock domain path according to claim 6, wherein: The cross-clock domain path is: a fourth cross-clock domain path having a design characteristic of processing a signal with a low change frequency; The checking rule that matches the design characteristics of the fourth cross-clock domain path is: a fourth checking rule that checks whether the timing constraints of the fourth cross-clock domain path can be relaxed; The checking of the path delay information of the equivalent synchronous timing path by using the checking rule to obtain the checking result of the cross-clock domain path includes: Determining maximum delay information and minimum delay information defined in the fourth checking rule; Comparing the path delay information with the maximum delay information and with the minimum delay information; Determine whether the path delay information of the equivalent synchronous timing path is less than or equal to the maximum delay information, or greater than or equal to the maximum delay information; If yes, the fourth cross-clock domain path has a timing margin, and the inspection result is determined as follows: the design characteristics of the fourth cross-clock domain path meet the fourth inspection rule; and the optimizability of the fourth cross-clock domain path is determined according to the timing margin; If not, the fourth cross-clock domain path does not have a timing margin, and the check result is determined as: the design characteristics of the fourth cross-clock domain path do not satisfy the fourth check rule.

11. The method for checking a cross-clock domain path according to any one of claims 1 to 3, characterized in that: After the step of obtaining the cross-clock domain path set of the chip design, the method further includes: The cross-clock domain path set is preprocessed to remove an erroneous path, where the erroneous path is a cross-clock domain path that does not exist in the chip design, so as to perform clock domain constraints based on each cross-clock domain path in the preprocessed cross-clock domain path set.

12. A device for checking a cross-clock domain path, characterized in that: include: A cross-clock domain path set acquisition module is used to acquire a cross-clock domain path set of a chip design, wherein each cross-clock domain path in the cross-clock domain path set includes a source clock domain and a destination clock domain with different clock domains; The clock domain constraint module is used to perform clock domain constraints on the source clock domain and the destination clock domain of each cross-clock domain path to obtain an equivalent synchronous timing path. Under the clock domain constraint, the source clock domain and the destination clock domain of each equivalent synchronous timing path are shown to be from the same clock domain. A timing analysis module, used to perform timing analysis on the equivalent synchronous timing path to obtain path delay information; The inspection result determination module is used to inspect the cross-clock domain path corresponding to the equivalent synchronous timing path based on the path delay information of the equivalent synchronous timing path, and obtain the inspection result of the cross-clock domain path.

13. The device for checking a cross-clock domain path according to claim 12, characterized in that: The clock domain constraint module is used to perform clock domain constraints on the source clock domain and the destination clock domain of each cross-clock domain path to obtain an equivalent synchronous timing path, including: Acquire a predefined clock group, wherein the clock group is formed by virtual clocks; The source clock domain and the destination clock domain of each cross-clock domain path are constrained to the clock group to obtain an equivalent synchronous timing path.

14. An electronic device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the method for checking a cross-clock domain path according to any one of claims 1 to 11.

15. A storage medium, characterized in that: The storage medium stores a program, and when the program is executed, the method for checking a cross-clock domain path according to any one of claims 1 to 11 is implemented.

16. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method for checking a cross-clock domain path according to any one of claims 1 to 11 is implemented.

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