Distributed multi-process time sequence violation analysis method

Abstract

The invention relates to a distributed multi-process time sequence violation analysis method, and belongs to the field of electronic design automation, and the method comprises the following steps: S1, segmenting a circuit diagram according to a driving port, each segmenting data block comprises a time sequence arc, pin information and connection information, and each connection data block comprises a start pin and a stop pin; s2, multiple processes are started, each process loads one segmented data block, a corresponding time sequence sub-graph is constructed and analyzed, and a dependency relationship among the time sequence sub-graphs is established among the processes through data exchange; s3, reading time sequence constraint information and a process library file of the corresponding time sequence sub-graph by each process, then performing time sequence calculation and pin flip value calculation according to a topological sequence, and completing dependency propagation through inter-process communication; and S4, outputting time sequence information to multiple processes, completing a time sequence report, and reporting a time sequence violation. According to the method, the analysis efficiency is greatly improved through distributed calculation, and the method can be suitable for all comprehensive stages.

Description

Technical Field

[0001] The present invention belongs to the field of electronic design automation (EDA), and particularly relates to a distributed multi-process timing violation analysis method. Background Art

[0002] With the improvement of integrated circuit technology, the scale of modern integrated circuit design has been continuously increasing. Traditional static timing analysis mainly adopts the technology of single machine and multi-threading. This method is limited by the capabilities of a single machine, and the timing analysis requires a long time. Due to the complexity of the circuit structure, in order to improve the efficiency of timing analysis, the distributed research of static timing analysis has emerged. Existing distributed schemes for static timing analysis include: A method for parallelly establishing a timing graph based on geometric information disclosed in the patent application with the publication number CN112257365A, comprising the following steps: dividing a circuit diagram into geometric blocks according to the geometric characteristics of the circuit diagram; starting multiple processes to parallelly establish temporary timing graphs in each geometric block; and splicing the temporary timing graphs established in each geometric block into a complete timing graph.

[0003] A distributed static timing analysis method disclosed in the patent application with the publication number CN113971383A, which extracts information associated with constraints and clock information from a file of a circuit design; determines a topological cone based on the information extracted from two or more partitions in the circuit design; and performs timing analysis on the partitions in the two or more partitions based on the topological cone.

[0004] The above existing distributed schemes for static timing analysis usually place a complete path on a single host, which will increase the complexity of partitioning, and due to the large differences in the number of layers of different paths and the circuit size, the parallel efficiency will be reduced; moreover, the above distributed static timing analysis methods also need to rely on the coordinate information of devices, and can only be adapted to the physical stage and cannot be applied to the early stage. Summary of the Invention

[0005] The present invention provides a distributed multi-process timing violation analysis method to solve problems such as low parallel efficiency and inability to be applied to the early stage existing in the existing distributed schemes for static timing analysis.

[0006] To solve the above technical problems, the technical solution provided by the present invention is: The present invention relates to a distributed multi-process timing violation analysis method, which comprises the following steps: S1. Divide a circuit diagram according to driving ports, and the divided data blocks include timing arcs, pin information, and connection information. The connection data block contains a starting pin and a terminating pin; S2. Start multiple processes. Each process loads a segmented data block, constructs a corresponding timing sub-graph, analyzes the timing sub-graph, and establishes a dependency relationship between the timing sub-graphs through data exchange among processes; S3. Each process reads the timing constraint information and the process library file of the corresponding timing sub-graph respectively, then performs timing calculation and pin flip value calculation according to the topological order, and completes dependency propagation through inter-process communication; S4. Output the timing information of multiple processes, complete the timing report, and report timing violations.

[0007] Preferably, the specific steps of S1 for segmenting the circuit diagram according to the driving port are as follows: S1.1. Construct a thread pool. The threads are divided into two parts. One part is the producer thread, which is responsible for traversing the circuit diagram, and the other part is the consumer thread, which is responsible for processing the traversed data; S1.2. Sequentially traverse the circuit diagram in a single-threaded manner, read the pin information and connection information, and put the obtained pin information and connection information into a memory queue; S1.3. Synchronously start the thread pool, read the pin information and connection information in the above memory queue, take out the attributes of the pins and connections, put the pins and connections into two arrays respectively, and perform array subscript calculation; S1.4. Read the data in the arrays, serialize the data, and store it in the medium. Then, according to different array subscripts, put the pins and connections into different paths of the medium to complete the segmentation of the circuit diagram.

[0008] Preferably, in S1.3, the size of the pin array is set to m , for a given set of pins , let the hash function be , where is the mapping of the pin id after hash operation, Z is the integer value after hash operation on the pin. To ensure that all pins are mapped into the pin array, take the modulo after hash operation on the pin id. The array subscript calculation method is: ; The array subscript calculation method is: , where l represents the connection, represents the hash value of the connection driving port id.

[0009] Preferably, the specific steps for each process in S2 to construct a corresponding timing sub-graph and analyze the timing sub-graph include: S2.1. Start the distributed system. Each process in the distributed system has a corresponding id identifier, and the sequence number of the id is 0~m-1, where m is the size of the pin array. Each process reads the corresponding array according to its own id and obtains the data in the array, thereby forming multiple partitions, and uses the id of each process as the corresponding partition id; S2.2. Multiple processes load the connection data and construct a timing subgraph inside the process , where V represents the set of pins and E represents the set of connections; S2.3. Multiple processes simultaneously generate the partition information of the pins. The partition information is a mapping from a pin to a partition id, records in which processes each pin exists, and writes this information to the shared medium; S2.4. The multi-process program reads the pin information and the pin partition information according to its own id, traverses all the partition ids in the pins, constructs the pin detail information. The pin detail information includes the basic attributes of the pin and the partition id. Copies of the pin detail information are made according to the partition id and placed into the corresponding storage medium according to the partition subscript.

[0010] Preferably, the specific steps of the timing calculation and the pin flip value calculation in S3 are as follows: S3.1. The multi-process program runs in parallel, reads the timing constraint file and the library mapping file information in the corresponding timing subgraph, and starts the calculation from the driving pin node without any dependencies using the topological order. Calculates the flip value of the pin according to the fan-out pin information, design constraints, and information in the library mapping file; S3.2. Transmit the flip value of the driving pin to all fan-out pins through the graph. For each fan-out pin, find the partition id where the fan-out pin is located. The calculation method of the partition id is , where is the hash function of the pin id, m is the size of the pin array, and propagates the flip value of this fan-out pin to other processes through the shared medium; S3.3. Each process synchronously checks the storage medium, reads the flip of the driving pin propagated to this process, and searches for the timing arc and driving pin of the pin corresponding to the flip value of the fan-out pin propagated to the process in the timing subgraph. If the fan-in pins of the driving pin have all completed the calculation of the flip, then calculate the delay of all timing arcs centered on the driving pin and the flip of the driving pin; S3.4. Determine whether the delay of the timing arc has been calculated. If not, return to S3.2 until all processes have completed the calculation of the delay of all timing arcs. If completed, it means that the calculation of this process is completed.

[0011] Preferably, the specific steps of the multi-process in S4 outputting the timing information to complete the timing report and calculating the timing violation are as follows: S4.1. The main process synchronizes and collects the latency and flip values calculated by each process from the shared medium until the end flag bits returned by all synchronized processes are received. At the same time, the received latency and flip values are marked in the timing diagram. S4.2. The main process traverses all paths in the timing diagram. For each path, the latency of each connection in the path is accumulated to calculate the arrival time. The formula for calculating the arrival time is: , where is the arrival time, is the latency of the connection in the path. S4.3. The main process calculates the required arrival time based on the information of the terminal pins of each path, the timing library information, and the design constraints. When performing the setup time check, the formula for the required arrival time is: , where is the arrival time of the capture clock, is the clock period, is the setup time; when performing the hold time check, the formula for the required arrival time is: , where is the arrival time of the capture clock, is the hold time. S4.4. The main process calculates the timing violation based on the arrival time and the required arrival time in each timing path, and completes the violation report. When performing the setup time check, the formula for the timing violation is: , where represents the arrival time calculated during the setup time check; When performing the hold time check, the formula for the timing violation is: , where represents the arrival time calculated during the hold time check; If the timing violation is negative, it means that there is a timing violation in this path, which is shown in the violation report.

[0012] Preferably, the number of the split data after the circuit diagram is split in S1 is the same as the number of processes in S2.

[0013] Adopting the technical solution provided by the present invention, compared with the prior art, it has the following beneficial effects: 1. The distributed multi - process timing violation analysis method involved in the present invention divides the circuit diagram, starts a multi - process program. Each program reads the data of its own partition or slice, then constructs a sub - graph and conducts data exchange; the multi - processes perform timing calculations respectively. The calculation involves data dependencies between processes and completes the overall timing calculation through communication; after the calculation is completed, the multi - processes output the calculation results respectively, and the single - machine program loads the timing results and completes the timing analysis report. Through distributed computing, the present invention greatly improves the analysis efficiency and is applicable to processing large - scale circuits.

[0014] 2. The distributed multi - process timing violation analysis method involved in the present invention, through data segmentation, distributed sub - graph construction and distributed timing analysis methods, does not depend on position coordinate information and does not depend on the distribution characteristics of the circuit structure. It has good scalability, can be easily implemented with a distributed system, and is applicable to all stages of synthesis. Brief Description of the Drawings

[0015] Figure 1 is the flow chart of the distributed multi - process timing violation analysis method; Figure 2 is the flow chart of the circuit diagram segmentation; Figure 3 is the flow chart of each process constructing the corresponding timing sub - graph and analyzing the timing sub - graph; Figure 4 is the flow chart of the timing calculation and the pin flip value calculation. Detailed Embodiment

[0016] To further understand the content of the present invention, the present invention will be described in detail in combination with embodiments. The following embodiments are used to illustrate the present invention but are not used to limit the scope of the present invention.

[0017] Refer to the attached Figure 1 As shown, a distributed multi - process timing violation analysis method involved in the present invention includes the following steps: S1. Segment the circuit diagram according to the driving ports. Refer to the attached Figure 2 As shown, the specific steps are: S1.1. Construct a thread pool. The threads are divided into two parts. One part is the producer thread, which is responsible for traversing the circuit diagram, and the other part is the consumer thread, which is responsible for processing the traversed data; S1.2. Sequentially traverse the circuit diagram in a single - thread manner, read the pin information and connection information, and put the obtained pin information and connection information into a memory queue, which is called queue A; S1.3. Synchronously start the thread pool, read the pin information and connection information in the above-mentioned A queue in the memory, extract the attributes of the pins and connections, and put the pins and connections into two arrays respectively. The size of the pin array is set to m For a given set of pins Let the hash function be where is the mapping of the pin id after hash operation, and Z is the integer value after hash operation on the pin. To ensure that all pins are mapped into the pin array, take the modulus after hash operation on the pin id. The calculation method of the array subscript is: ; The size of the connection array is also set to m The calculation method of the array subscript is: where l represents the connection, represents the hash value of the connection drive port id. Suppose the unique identifier id of a certain pin is 100, that is v = 100. Let the hash function be the result of the standard integer hash operation on this integer value as the hash input, that is h h(100) = 100. If the size of the pin array is m = 100, then the subscript of the pin array is: h h(100) % 10 = 100 % 10 = 0, that is, this pin is stored in the 0th item of the pin array. The calculation method of the connection array subscript is the same as that of the pin array subscript.

[0018] S1.4. Read the data in the array, serialize the data, and store it in the medium. The medium can be a network shared disk, a cache database, a document database, etc.; for the cache database, the data in the array can be placed in different key values according to the subscript index. For example, for the data with the subscript index of 0 in the pin array, its key can be "q_pin:0", and the value can adopt a queue structure to store the pin and connection information. Then, according to different array subscripts, the pins and connections are placed in different paths to complete the circuit diagram segmentation. The number of subscript indexes of the segmented data is the same as the number of processes of the distributed system used later.

[0019] The above-mentioned segmented data blocks include timing arcs, pin information, and connection information. Among them, the connection data block contains the starting pin and the ending pin; S2. Start multiple processes. Each process loads a segmented data block, constructs a corresponding timing subgraph, and analyzes the timing subgraph. Refer to the appendix Figure 3 shown. The specific steps are as follows: S2.1. Start the distributed system. Each process in the distributed system has a corresponding id identifier, and the sequence number of the id is 0~m-1, where m is the size of the pin array. Each process reads the corresponding key according to its own id to obtain the data in the array. For example, if the id of the process is 0, the read pin is located in the "q_pin:0" queue; through this step, multiple partitions can be formed, and the id of each process is used as the corresponding partition id; S2.2. Multiple processes load the connection data and construct a timing subgraph inside the process , where V represents the set of pins, E represents the set of connections, and the timing subgraph is a graph structure. According to the connection information and the timing arc information, the dependency relationship between the timing subgraphs can be constructed. Let <P i , P o > be a pair of connections or timing arcs, where P i , P o are pin ids, then an edge pointing from P i to P o is constructed. In the calculation, P o depends on P i , P i is the fan-in pin of P o , and P o is the fan-out pin of P i .

[0020] S2.3. Multiple processes simultaneously generate the partition information of the pins. The partition information is a mapping from a pin to a partition id, which records in which processes each pin exists, and writes this information to the shared medium. This information is saved as an array in memory. The array type can be a variable array, and the size of the array is set to m, then the corresponding recorded subscript is the hash value; S2.4. The multi-process program reads the information of the pins and the partition information of the pins according to its own id, traverses all the partition ids in the pins, constructs the pin detail information, which includes the basic attributes of the pins and the partition id, copies multiple copies of the pin detail information according to the partition id, and puts them into the corresponding storage medium according to the hash value; The dependency relationship between the timing subgraphs is also established through data exchange among the processes; S3. Each process reads the timing constraint information and the process library file of the corresponding timing subgraph respectively, and then performs timing calculation and pin flip value calculation according to the topological order, and completes the dependency propagation through inter-process communication; The specific steps of the timing calculation and the pin flip value calculation are as Figure 4 shown, and the specific steps are: S3.1. The multi - process program runs in parallel, reads the timing constraint files and library mapping file information in the corresponding timing sub - graph, starts the calculation from the driving pin nodes with no dependencies using topological order, and calculates the flip values of the pins according to the fan - out pin information, design constraints, and information in the library mapping file; S3.2. Propagate the flip of the driving pin through the graph to all fan - out pins. For each fan - out pin, find the partition id where the fan - out pin is located. The calculation method of the partition id is , where is the hash function of the pin id, m is the size of the pin array, and propagate the flip value of this fan - out pin to other processes through the shared medium; S3.3. Each process synchronously checks the storage medium, reads the flip of the driving pin propagated to this process, and searches for the timing arcs and driving pins of the pins corresponding to the flip values of the fan - out pins propagated to the process in the timing sub - graph. If the fan - in pins of the driving pin have all completed the calculation of the flip, then calculate the delay of all timing arcs centered on the driving pin and the flip of the driving pin; S3.4. Determine whether the delay of the timing arc has been calculated. If not, return to S3.2 until each process has completed the calculation of the delay of all timing arcs. If completed, it means that the calculation of this process is completed.

[0021] S4. Output the timing information for multiple processes, complete the timing report, and report the timing violations. The specific steps for calculating the timing violations are as follows: S4.1. The main process synchronously collects the delays and flip values calculated by each process from the shared medium until it receives the end flag bits returned by all synchronized processes. At the same time, mark the received delays and flip values in the timing graph; S4.2. The main process traverses all paths in the timing graph, and accumulates the delays of each connection in each path respectively to calculate the arrival time. The calculation formula for the arrival time is: , where is the arrival time, is the delay of the connection in the path. Assume there is a timing path that passes through CLK, DFF1:Q, AND:A, AND:Z, DFF2:D pins. The delay T from CLK to DFF1:Q is 0.1ns, the delay T2 from DFF1:Q to AND:A is 0.2ns, the delay T3 from AND:A to AND:Z is 0.1ns, and the delay T4 from AND:Z to DFF2:D is 0.1ns. Then the arrival time is: .

[0022] S4.3. The main process calculates the required arrival time based on the information of each path terminal pin, the timing library information, and the design constraints. When performing setup time checks, the required arrival time is calculated as follows: , where is the arrival time of the capture clock, is the clock period, is the setup time; when performing hold time checks, the required arrival time is calculated as follows: , where is the arrival time of the capture clock, is the hold time. For the example in S4.2, assume the arrival time of the capture clock , the clock period , the setup time , and the hold time . Then, when performing setup time checks, the required arrival time is . When performing hold time checks, the required arrival time is:

[0023] S4.4. The main process calculates the timing violation based on the arrival time and the required arrival time in each timing path and generates a violation report.

[0024] When performing setup time checks, the timing violation is calculated as follows: , where represents the arrival time calculated during setup time checks. For the examples in S4.2 and S4.3, ; When performing hold time checks, the timing violation is calculated as follows: , where represents the arrival time calculated during hold time checks. For the examples in S4.2 and S4.3, ; If the timing violation is negative, it indicates that there is a timing violation in this path, which will be shown in the violation report. In this example, Being negative indicates that the data has not remained stable within the time before the clock active edge arrives. At this time, the data captured by the capture flip-flop is unstable, which does not meet the setup time check. This record should be shown in the timing report. In addition, the timing report not only records the information of this path (starting pin information, etc., ending pin information, etc.), but also records the delay information of all nodes from the starting node to the nodes in this path, as well as the calculation results of AT and RAT, and shows Slack in the last line.

[0025] The present invention has been described in detail above in conjunction with the embodiments, but the content described is only the preferred embodiment of the present invention and cannot be considered as limiting the scope of implementation of the present invention. All equivalent changes and improvements made in accordance with the scope of the application of the present invention shall still fall within the scope covered by the patent of the present invention.

Claims

1. A distributed multi-process timing violation analysis method, characterized by: It includes the following steps: S1. The circuit diagram is segmented according to the driving port, and the segmented data block includes the timing arc, pin information and connection information, and the connection data block includes the start pin and the end pin; S2. Start multiple processes, each process loads a segmented data block, builds a corresponding time-series subgraph, analyzes the time-series subgraph, and establishes dependencies between time-series subgraphs through data exchange between processes; S3. Each process reads the timing constraint information and process library file of the corresponding timing subgraph respectively, and then performs timing calculation and pin flip value calculation according to the topological order, and completes dependency propagation through inter-process communication; S4. Output timing information for multiple processes, complete timing reports, and report timing violations.

2. The distributed multi-process timing violation analysis method according to claim 1, characterized in that: The specific steps of S1 dividing the circuit diagram according to the driving port are: S1.

1. Build a thread pool. The threads are divided into two parts: one is the producer thread, which is responsible for traversing the circuit diagram, and the other is the consumer thread, which is responsible for processing the traversed data; S1.

2. Traverse the circuit diagram sequentially in a single-threaded manner, read the pin information and the connection information, and put the obtained pin information and the connection information into a memory queue; S1.

3. Synchronously start the thread pool, read the pin information and connection information in the above memory queue, extract the properties of the pins and connections, put the pins and connections into two arrays respectively, and perform array subscript calculation; S1.

4. Read the data in the array, serialize the data, and store it in the medium. Then, according to different array indexes, place the pins and wires in different paths of the medium to complete the segmentation of the circuit diagram.

3. The distributed multi-process timing violation analysis method according to claim 2, characterized in that: In S1.3, the array size of the pins is set to m , for a given set of pins , let the hash function be ,in, is a mapping of the hash operation of the pin id, and Z is the integer value after the hash operation of the pin. All are mapped to the pin array, and the pin id is hashed and modulo. The array subscript is calculated as follows: ; The array size of the connection is also set to m , the array subscript is calculated as: ,in, l Indicates connection, A hash value representing the port ID of the wire driver.

4. The distributed multi-process timing violation analysis method according to claim 1, characterized in that: The specific steps of constructing a corresponding timing subgraph for each process of S2 and analyzing the timing subgraph include: S2.

1. Start the distributed system. Each process in the distributed system has a corresponding ID. The ID number is 0~m-1, and m is the size of the pin array. Each process reads the corresponding array according to its own ID and obtains the data in the array, thereby forming multiple partitions. The ID of each process is used as the corresponding partition ID; S2.

2. Loading connection data in multiple processes and constructing a timing subgraph within the process , where V represents the pin set and E represents the connection set; S2.

3. Multiple processes simultaneously generate pin partition information, the partition information is a mapping of a pin to a partition id, records which processes each pin exists in, and writes the information to a shared medium; S2.

4. The multi-process program reads the pin information and the pin partition information according to its own ID, traverses all partition IDs in the pin, and constructs the pin detail information. The pin detail information includes the basic attributes of the pin and the partition ID. Multiple copies of the pin detail information are copied according to the partition ID and placed in the corresponding storage medium according to the partition index.

5. The distributed multi-process timing violation analysis method according to claim 1, characterized in that: The specific steps of timing calculation and pin flip value calculation in S3 are: S3.

1. The multi-process program runs in parallel, reads the timing constraint file and library mapping file information in the corresponding timing subgraph, uses the topological order to start the calculation from the driver pin node without any dependencies, and calculates the pin flip value according to the fan-out pin information, design constraints, and information in the library mapping file; S3.

2. The flip value of the driving pin is passed to all fan-out pins through the graph. For each fan-out pin, find the partition ID where the fan-out pin is located. The partition ID is calculated as follows: ,in, is the hash function of the pin id, m is the size of the pin array, and the flip value of the fan-out pin is propagated to other processes through the shared medium; S3.

3. Each process synchronously checks the storage medium, reads the flip of the driving pin propagated to the process, and searches the timing arc and driving pin of the pin corresponding to the flip value of the fan-out pin propagated to the process in the timing subgraph. If the fan-in pins of the driving pin have completed the calculation of the flip, the delay of all timing arcs and the flip of the driving pin are calculated with the driving pin as the center; S3.

4. Determine whether the delay calculation of the timing arc is completed. If not, return to S3.2 until each process completes the delay calculation of all timing arcs. If completed, it means that the calculation of the process is completed.

6. The distributed multi-process timing violation analysis method according to claim 1, characterized in that: The S4 multi-process output timing information completes the timing report, and the specific steps of reporting the timing violation calculation are: S4.

1. The master process synchronously collects the delay and rollover values ​​calculated by each process from the shared medium until receiving the end flag returned by all synchronization processes, and marks the received delay and rollover values ​​into the timing diagram; S4.

2. The main process traverses all paths in the timing diagram, and accumulates the delay of each connection in each path to calculate the arrival time. The calculation formula for the arrival time is: ,in, is the arrival time, is the delay of the connection in the path; S4.

3. The main process calculates the required arrival time based on the information of each path terminal pin, the timing library information, and the design constraints. When the establishment time check is performed, the required arrival time The calculation formula is: ,in, To capture the arrival time of the clock, is the clock period, is the setup time; when performing a hold time check, the arrival time is required The calculation formula is: ,in, To capture the arrival time of the clock, To keep time; S4.

4. The main process calculates the timing violation based on the arrival time and required arrival time in each timing path and completes the violation report. When performing setup time checking, timing violations The calculation formula is: ， in, Indicates the arrival time calculated when establishing the time check; When performing hold time checks, timing violations The calculation formula is: ， in, Indicates the arrival time calculated during the hold time check; If the timing violation is a negative value, it means that there is a timing violation on this path, which is displayed in the violation report.

7. The distributed multi-process timing violation analysis method according to claim 1, characterized in that: After S1 divides the circuit diagram, the number of divided data is the same as the number of processes in S2.

Images