Inter-process communication method and device of microkernel operating system
By registering critical instruction pages and stack pages in a microkernel operating system, constructing process prefetch sets, and quickly loading the TLB, the problem of limited inter-process communication performance is solved, improving the system's communication efficiency and response speed, making it suitable for ubiquitous computing environments.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-04-07
AI Technical Summary
In microkernel operating systems, the performance of inter-process communication is limited by the existing IPC mechanism, resulting in frequent context switching and hidden overhead caused by the lack of TLB, which becomes a bottleneck in system performance, especially in ubiquitous computing environments where interactions are frequent and complex.
By registering critical instruction pages and stack pages during the service process initialization phase, a process prefetch set is constructed. Then, during the inter-process communication initiation phase, the tlbfill and tlbwr instructions of the LoongArch architecture are used to quickly load the target page table entries in the prefetch set into the TLB, thereby reducing the TLB miss rate and optimizing the inter-process communication path.
It significantly reduces the TLB miss rate, improves the communication efficiency and response speed between system services, enhances the applicability of the microkernel in high-throughput, low-latency application scenarios, and meets the high-efficiency and stable computing requirements of ubiquitous computing.
Smart Images
Figure CN121807585A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and in particular to an inter-process communication method and apparatus for a microkernel operating system. Background Technology
[0002] In microkernel operating systems, system services such as file systems, network services, and drivers run as independent user-space processes and interact through IPC (Inter-Process Communication) mechanisms. However, in the context of ubiquitous computing, the coupling between these system services is high, and interactions are frequent, with most being process calls. Their performance is limited by the existing microkernel IPC mechanism, becoming a bottleneck for the overall system performance. Summary of the Invention
[0003] To address the technical problems existing in the prior art, this invention provides an inter-process communication method and apparatus for a microkernel operating system, which can improve the efficiency of inter-process communication and reduce communication latency.
[0004] This invention provides an inter-process communication method for a microkernel operating system, comprising: registering critical instruction pages and stack pages during the service process initialization phase; constructing a process prefetch set based on the registered critical instruction pages and stack pages; and loading target page table entries from the process prefetch set into the user process TLB during the inter-process communication initiation phase for inter-process communication.
[0005] According to the inter-process communication method of a microkernel operating system provided by the present invention, the registration of critical instruction pages and stack pages includes: an instruction page prefetching mechanism based on static call chain analysis to identify potential function jump relationships in inter-process communication and critical service processing flows, and to designate the corresponding instruction pages as critical instruction pages; and a stack page prefetching mechanism based on spatial locality to predict stack pages along the stack growth direction, and to designate the predicted stack pages as critical stack pages.
[0006] According to the inter-process communication method of a microkernel operating system provided by the present invention, the instruction page prefetching mechanism based on static call chain analysis identifies potential function jump relationships in inter-process communication and critical service processing flows, including: scanning the binary file of the service process, parsing jump instructions, and determining the jump target address; and determining the physical page location based on the target address.
[0007] According to the inter-process communication method of a microkernel operating system provided by the present invention, the stack page prefetching mechanism based on spatial locality predicts stack pages along the stack growth direction, including: adding stack pointer analysis to the thread scheduler and inter-process communication entry logic, and predicting the stack pages to be accessed in the future by tracking the stack growth direction, the current stack frame size, and the call depth of the service thread.
[0008] According to the inter-process communication method of a microkernel operating system provided by the present invention, the method further includes: loading a target page table entry in the process prefetch set into the user process TLB using a page table loading instruction of the Loongson architecture.
[0009] According to the inter-process communication method of a microkernel operating system provided by the present invention, the method further includes: dynamically adjusting the loading priority of target page table entries in the process prefetch set during the context switching phase of inter-process communication; the priority order is determined according to historical communication frequency and current communication needs.
[0010] The present invention also provides an inter-process communication device for a microkernel operating system, comprising: a registration module for registering critical instruction pages and stack pages during the service process initialization phase; a construction module for constructing a process prefetch set based on the registered critical instruction pages and stack pages; and a loading module for loading target page table entries from the process prefetch set into the user process TLB during the inter-process communication initiation phase, so as to perform inter-process communication.
[0011] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement an inter-process communication method of any of the microkernel operating systems described above.
[0012] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements an inter-process communication method of a microkernel operating system as described above.
[0013] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements an inter-process communication method of any of the microkernel operating systems described above.
[0014] This invention provides an inter-process communication method and apparatus for a microkernel operating system. While maintaining system security, it optimizes the inter-process communication path of the microkernel, reduces implicit overhead, and improves the response speed and throughput of the microkernel in high-frequency communication scenarios. It provides a feasible technical solution for the implementation of high-performance microkernels in ubiquitous computing environments. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0016] Figure 1 This is a flowchart illustrating an inter-process communication method for a microkernel operating system provided by the present invention.
[0017] Figure 2 This is a schematic diagram illustrating the specific process of an inter-process communication method for a microkernel operating system provided by the present invention.
[0018] Figure 3 This is a schematic diagram of the structure of an inter-process communication device for a microkernel operating system provided by the present invention.
[0019] Figure 4 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0021] In modern computer systems, microkernel operating systems (such as seL4) have become an important architectural choice, especially in scenarios with high requirements for security, reliability, and flexibility. The core concept of a microkernel operating system is to minimize the core functions of the operating system (such as inter-process communication, scheduling, and memory management), while running other functions (such as file systems, network services, and device drivers) as independent user-mode processes. This design not only improves the modularity of the system but also enhances its security and maintainability. However, with the continuous development of computing environments, especially in the context of ubiquitous computing, this architecture faces new challenges.
[0022] Ubiquitous computing emphasizes the ubiquity of computing devices and services, enabling users to seamlessly access computing resources in their daily environments and achieve highly intelligent and automated information processing. In this environment, interactions between system services become more frequent and complex. System services such as file systems, network services, and drivers are no longer isolated modules but need to work closely together to complete various complex tasks. For example, a file transfer operation may involve the file system reading data, the network service transmitting data, and the driver controlling the hardware device. This highly coupled interaction model places higher demands on inter-process communication mechanisms.
[0023] In traditional microkernel operating systems, the design of IPC mechanisms primarily focuses on providing basic communication functions, such as message passing and synchronization mechanisms. However, these designs fall short in ubiquitous computing environments. First, frequent IPC calls lead to significant context switching overhead. Each IPC call requires switching from user mode to kernel mode and then back to user mode, a process that consumes a significant amount of CPU time and increases memory access latency. Second, since most interactions between system services are procedure calls, each call requires IPC, further exacerbating performance bottlenecks. For example, in a high-frequency file read / write scenario, IPC calls between the file system and network services can become a bottleneck for system performance, leading to a significant increase in overall response time.
[0024] Current mainstream microkernels typically do not optimize for TLB (Translation Lookaside Buffer) misses in inter-process communication paths. Traditional solutions mainly focus on directly reducing communication latency, such as by simplifying call paths or optimizing context switching. However, during frequent task switching and address space switching, the implicit overhead caused by TLB misses remains significant, limiting the overall system throughput and response speed.
[0025] In ubiquitous computing scenarios, microkernels still face the problems of high implicit overhead of inter-process communication and limited throughput, which is the technical motivation for proposing the TLB prefetching mechanism in this invention.
[0026] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating an inter-process communication method for a microkernel operating system provided by the present invention.
[0027] This invention provides an inter-process communication method for a microkernel operating system, comprising: 101: During the service process initialization phase, register critical instruction pages and stack pages; 102: Construct the process prefetch set based on the registered critical instruction pages and stack pages; 103: During the inter-process communication initiation phase, the target page table entry in the process prefetch set is loaded into the user process's TLB for inter-process communication.
[0028] This invention aims to reduce the inter-process communication latency of the LoongArch microkernel operating system in ubiquitous computing environments, thereby improving the interaction efficiency between system services, enhancing the applicability of the microkernel in high-throughput, low-latency application scenarios, and meeting the ubiquitous computing requirements for an efficient, stable, and scalable computing platform.
[0029] This invention provides an inter-process communication (IPC) method for a microkernel operating system, proposing the concept of a "process prefetch set." During the initialization phase of a system service process, critical instruction pages and stack pages are registered with the kernel. The kernel then constructs the process prefetch set based on this registration information. During the IPC initiation phase, the `tlbfill` and `tlbwr` instructions provided by the LoongArch architecture are used to quickly load the target page table entries from the prefetch set into the TLB. This process significantly reduces the TLB miss rate during IPC services, thereby greatly improving the communication efficiency between system services. This mechanism not only optimizes the direct communication overhead of IPC but also effectively reduces the implicit overhead caused by frequent task switching and address space switching. This invention improves the performance and scalability of the microkernel on ubiquitous computing platforms and has broad application value.
[0030] What needs to be explained is: Ubiquitous computing is a computing paradigm that emphasizes the ubiquity of computing devices and services, enabling users to access computing resources seamlessly in their daily environments and achieve highly intelligent and seamless interactive information processing.
[0031] A microkernel is an operating system architecture that retains only core functions such as inter-process communication, scheduling, and memory management, while running higher-level services such as drivers, file systems, and network protocol stacks in user space.
[0032] Inter-process communication (IPC) is a set of mechanisms provided by the operating system that enable different processes to exchange data or synchronize. In a microkernel architecture, IPC is the primary method for calling system services.
[0033] System services are a set of core functions provided by the operating system, including process management, file system, and network communication. In a microkernel architecture, system services typically run as user-mode processes and interact through inter-process communication (IPC).
[0034] Page tables are structures used by the operating system to manage virtual memory, mapping virtual addresses to physical addresses, enabling processes to use a larger address space than the actual physical memory, and achieving address isolation between processes.
[0035] A TLB (Time Limit List) is a hardware structure in the CPU used to cache recently accessed page table entries, accelerating the translation from virtual to physical addresses. A TLB miss results in additional accesses to the page table, thus increasing the implicit overhead of IPC context switching.
[0036] Call chain analysis is a static analysis of the function call relationships in a program, used to understand the program's execution flow and function call paths.
[0037] Spatial locality is the address proximity exhibited by a program when accessing memory, meaning that after a memory page is accessed, nearby memory pages are likely to be accessed again in a short period of time.
[0038] Please refer to Figure 2 , Figure 2 This is a schematic diagram illustrating the specific process of an inter-process communication method for a microkernel operating system provided by the present invention.
[0039] As a preferred embodiment, registering critical instruction pages and stack pages includes: an instruction page prefetching mechanism based on static call chain analysis, which identifies potential function jump relationships in inter-process communication and critical service processing flows, and designates the corresponding instruction pages as critical instruction pages; and a stack page prefetching mechanism based on spatial locality, which predicts stack pages along the stack growth direction and designates the predicted stack pages as critical stack pages.
[0040] As a preferred embodiment, the instruction page prefetching mechanism based on static call chain analysis identifies potential function jump relationships in inter-process communication and critical service processing flows, including: scanning the binary file of the service process, parsing jump instructions, and determining the jump target address; and determining the physical page location based on the target address.
[0041] In microkernel-based operating systems (such as seL4), system services follow a strict user-space componentization design, with many functions implemented through inter-process communication (IPC) between user-space servers. Compared to traditional monolithic kernels, microkernel architecture significantly improves system security and verifiability, but it also makes the system execution path highly dependent on high-frequency IPC calls across address spaces. This leads to the lack of a TLB (Translation Lookaside Buffer) becoming a key performance bottleneck in the IPC call chain.
[0042] In the user-space server model of seL4, IPC typically requires a complete round trip from user space to kernel space to the target server, then back to kernel space and finally back to user space, involving multiple function switches and cross-address space jumps. For systems using the Loongson 3A5000 architecture, the TLB is managed in software, and all TLB refills (page faults) must be handled by exception handlers. This overhead is significantly higher than that of hardware automatic refill architectures, making reducing TLB misses a key objective for optimizing system performance.
[0043] To address this, this invention proposes an instruction page prefetching mechanism based on static call chain analysis. This mechanism constructs the call chain of the service execution path based on static analysis of the seL4 service process. Since seL4 service components generally adhere to strict design specifications, their call chain structure is stable and highly predictable. Therefore, it is possible to accurately identify potential function jump relationships in IPC calls and critical service processing flows using static methods.
[0044] This invention employs a lightweight instruction page prefetching mechanism, its core being based on static call chain analysis of the service process's binary file. This invention directly scans the ELF executable file, focusing on resolving the jump target addresses of J-type / I-type jump instructions (such as j, jal, beq, bne, etc.) and inferring the location of the physical (or virtual) page based on the target address. These statically inferred target instruction pages are added to a "potential critical instruction page set." Before entering the inter-process communication logic, the kernel proactively maps these instruction pages and triggers TLB loading to ensure that all potentially accessed instruction pages in the call chain reside in the TLB in advance, improving the hit rate and reducing instruction access latency.
[0045] Before entering the IPC processing logic, the kernel performs pre-mapping and TLB placeholder preparation on the corresponding pages based on the "potential instruction page set" obtained from call chain analysis, so that TLB refill exceptions are not triggered during future function jumps. Compared with the traditional on-demand loading strategy, this method further aligns with the microkernel design philosophy of seL4: improving the execution efficiency of the IPC path through code structure-level knowledge while ensuring that isolation and formal security verification are not affected.
[0046] On the seL4+Loongson 3A5000 platform, this invention can significantly reduce the number of instruction TLB misses in the inter-process communication call chain, effectively reduce the round-trip latency of inter-process communication in high-frequency interface service scenarios, and improve the overall responsiveness of microkernel system services.
[0047] As a preferred embodiment, the stack page prefetching mechanism driven by spatial locality predicts stack pages along the stack growth direction, including: adding stack pointer analysis to the thread scheduler and inter-process communication entry logic, and predicting the stack pages to be accessed in the future by tracking the stack growth direction, the current stack frame size, and the call depth of the service thread.
[0048] In the seL4 microkernel, thread switching, exception handling, and IPC calls frequently trigger stack access, including the user-mode stack, exception stack, and seL4 kernel stack. The Loongson architecture used in the Loongson 3A5000 also relies on software-managed TLBs, meaning that any TLB miss caused by an unmapped stack page will trigger the exception handling process. The cost of this is particularly noticeable in the frequent switching paths of the microkernel, and it may even become a key factor affecting real-time performance and system throughput.
[0049] Based on the structural characteristic of stack access exhibiting significant spatial locality (stack grows contiguously), this invention proposes a spatial locality-driven stack page prefetching mechanism. This mechanism adds lightweight stack pointer (SP) analysis to the thread scheduler and inter-process communication entry logic of seL4. By tracking the stack growth direction, the current stack frame size, and the common call depth of service threads, it predicts one or more stack pages that may be accessed in the future.
[0050] When the system anticipates that the stack is about to grow to a new page boundary, it adds adjacent potential stack pages to the prefetch set before a function call or thread switch occurs, performs page table mapping and TLB loading preparation, thereby avoiding TLB refill exceptions when executing critical system paths. Because seL4 has explicit calling patterns and a controlled execution environment on paths such as IPC, scheduling, and software interrupts, this prediction typically maintains extremely high accuracy.
[0051] This mechanism is particularly effective on the Loongson 3A5000 platform. The 3A5000's TLB refill exception latency is relatively high and introduces additional pipeline flushing, making stack-related page fault overhead more significant. By prefetching stack pages, this invention significantly reduces TLB misses caused by stack page access during function calls and context switching in the critical path of seL4, improving the continuity of thread switching, system calls, and IPC processing, and enhancing the microkernel's execution efficiency at the system level.
[0052] Overall, the stack page prefetching mechanism based on spatial locality fully leverages the deterministic execution mode of seL4 and the characteristics of the Loongson architecture. It achieves effective optimization of TLB behavior without introducing additional runtime overhead, and is an important supplement to the high-performance and deterministic design philosophy of seL4.
[0053] As a preferred embodiment, it further includes: loading the target page table entry in the process prefetch set into the user process TLB using the page table load instruction of the Loongson architecture.
[0054] To ensure that prefetched pages are not only created in the page table but actually enter the processor's TLB, Loongson 3A5000's dedicated TLB operation instructions (such as tlbwr and tlbfill) are incorporated into the design of this invention. This architecture allows software to directly manipulate TLB mappings through registers. These native instructions are encapsulated in the seL4 kernel, enabling the prefetch logic to actively trigger tlbwr once in kernel mode, thereby forcibly writing the prefetched page into the TLB entry, achieving true TLB-level prefetching. This approach avoids the latency filling problem that traditional page table-level prefetching may face in a microkernel environment, ensuring that instruction pages and stack pages are already in the TLB before execution, thus bringing more practical performance benefits.
[0055] As a preferred embodiment, the method further includes: dynamically adjusting the loading priority of target page table entries in the process prefetch set during the context switching phase of inter-process communication; the priority order is determined based on historical communication frequency and current communication needs.
[0056] In microkernel operating systems (such as seL4), the performance of inter-process communication (IPC) depends not only on the effectiveness of the prefetch mechanism but also on the page table entry loading order during context switching. To further optimize IPC performance, this invention introduces a dynamic priority adjustment mechanism. During context switching, this mechanism dynamically adjusts the loading priority of target page table entries in the process prefetch set based on historical communication frequency and current communication needs.
[0057] The system maintains a communication frequency statistics table, recording how often each service process accesses critical page table entries in historical communications. At each IPC initiation, the system analyzes the specific needs of the current communication. During context switching, the system dynamically adjusts the loading priority of page table entries based on historical communication frequency and current communication needs. The loading order of page table entries is adjusted according to the calculated priority, prioritizing higher-priority page table entries. This dynamic priority adjustment mechanism optimizes the inter-process communication performance of the microkernel operating system, providing strong support for the design of high-performance microkernel systems.
[0058] This invention, implemented on the seL4 microkernel, employs a dual approach combining process prefetching, instruction call chain analysis, and stack space locality prediction, and was tested on a Loongson 3A5000 processor. The performance improvements were evaluated based on TLB miss rate, average IPC latency, and overall system throughput. This invention reduces the TLB miss rate by 45.6% and the average IPC latency by 31.4%, significantly improving the interaction efficiency between system services and the overall performance of the microkernel. While maintaining system security, this invention optimizes the microkernel IPC path, reduces implicit overhead, and improves the microkernel's response speed and throughput in high-frequency communication scenarios, providing a feasible technical solution for implementing high-performance microkernels in ubiquitous computing environments.
[0059] The inter-process communication device for a microkernel operating system provided by the present invention will be described below. The inter-process communication device for a microkernel operating system described below can be referred to in correspondence with the inter-process communication method for a microkernel operating system described above.
[0060] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of an inter-process communication device for a microkernel operating system provided by the present invention.
[0061] The present invention also provides an inter-process communication device for a microkernel operating system, comprising: a registration module 301, used to register critical instruction pages and stack pages during the service process initialization phase; a construction module 302, used to construct a process prefetch set based on the registered critical instruction pages and stack pages; and a loading module 303, used to load target page table entries from the process prefetch set into the user process TLB during the inter-process communication initiation phase, for inter-process communication.
[0062] This invention aims to reduce the latency of inter-process communication in the Loongson architecture microkernel operating system under ubiquitous computing environments, and to reduce TLB miss overhead caused by frequent task switching and address space switching. To this end, this invention proposes the following technical solutions: TLB prefetching mechanism for microkernel IPC: The concept of process prefetch set is proposed. During the initialization phase, the service process registers the critical instruction page and stack page. The kernel constructs the prefetch set and loads it quickly during the IPC initiation phase using the tlbfill and tlbwr instructions provided by the Loongson architecture. This significantly reduces TLB misses on the IPC path and improves communication efficiency.
[0063] Instruction page prefetching based on static call chain analysis: By analyzing the function call relationships of service processes, possible jump paths are identified, and corresponding instruction pages are added to the prefetch set to ensure that critical instructions hit the TLB in advance during IPC calls, thereby reducing latency.
[0064] Stack page prefetching based on spatial locality: Combining the locality characteristics of stack access, critical stack pages are predictively added to the prefetch set along the stack growth direction, reducing TLB misses caused by stack page access during function calls and context switching, thereby reducing implicit IPC overhead.
[0065] As a preferred embodiment, registering critical instruction pages and stack pages includes: an instruction page prefetching mechanism based on static call chain analysis, which identifies potential function jump relationships in inter-process communication and critical service processing flows, and designates the corresponding instruction pages as critical instruction pages; and a stack page prefetching mechanism based on spatial locality, which predicts stack pages along the stack growth direction and designates the predicted stack pages as critical stack pages.
[0066] As a preferred embodiment, the instruction page prefetching mechanism based on static call chain analysis identifies potential function jump relationships in inter-process communication and critical service processing flows, including: scanning the binary file of the service process, parsing jump instructions, and determining the jump target address; and determining the physical page location based on the target address.
[0067] As a preferred embodiment, the stack page prefetching mechanism driven by spatial locality predicts stack pages along the stack growth direction, including: adding stack pointer analysis to the thread scheduler and inter-process communication entry logic, and predicting the stack pages to be accessed in the future by tracking the stack growth direction, the current stack frame size, and the call depth of the service thread.
[0068] As a preferred embodiment, it further includes: loading the target page table entry in the process prefetch set into the user process TLB using the page table load instruction of the Loongson architecture.
[0069] As a preferred embodiment, the method further includes: dynamically adjusting the loading priority of target page table entries in the process prefetch set during the context switching phase of inter-process communication; the priority order is determined based on historical communication frequency and current communication needs.
[0070] Figure 4 An example is a schematic diagram of the structure of an electronic device, such as... Figure 4As shown, the electronic device may include a processor 401, a communications interface 402, a memory 403, and a communication bus 404. The processor 401, communications interface 402, and memory 403 communicate with each other via the communication bus 404. The processor 401 can call logical instructions in the memory 403 to execute inter-process communication methods of a microkernel operating system. These methods include: registering critical instruction pages and stack pages during the service process initialization phase; constructing a process prefetch set based on the registered critical instruction pages and stack pages; and loading target page table entries from the process prefetch set into the user process time table during the inter-process communication initiation phase to perform inter-process communication.
[0071] Furthermore, the logical instructions in the aforementioned memory 403 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0072] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the inter-process communication method of the microkernel operating system provided by the above methods. The method includes: registering critical instruction pages and stack pages during the service process initialization phase; constructing a process prefetch set based on the registered critical instruction pages and stack pages; and loading target page table entries from the process prefetch set into the user process TLB during the inter-process communication initiation phase to perform inter-process communication.
[0073] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements an inter-process communication method for a microkernel operating system provided by the methods described above. This method includes: registering critical instruction pages and stack pages during a service process initialization phase; constructing a process prefetch set based on the registered critical instruction pages and stack pages; and loading target page table entries from the process prefetch set into the user process time table during an inter-process communication initiation phase to perform inter-process communication.
[0074] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.
[0075] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.
[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for inter-process communication in a microkernel operating system, characterized in that, include: During the service process initialization phase, key instruction pages and stack pages are registered; Based on the registered key instruction pages and stack pages, construct the process prefetch set; During the inter-process communication initiation phase, the target page table entry in the process prefetch set is loaded into the user process TLB to enable inter-process communication.
2. The inter-process communication method for a microkernel operating system according to claim 1, characterized in that, The registered key instruction page and stack page include: The instruction page prefetching mechanism based on static call chain analysis identifies potential function jump relationships in inter-process communication and critical service processing flows, and uses the corresponding instruction pages as critical instruction pages. Based on a stack page prefetching mechanism driven by spatial locality, stack pages are predicted along the stack growth direction, and the predicted stack pages are used as critical stack pages.
3. The inter-process communication method for a microkernel operating system according to claim 2, characterized in that, The instruction page prefetching mechanism based on static call chain analysis identifies potential function jump relationships in inter-process communication and critical service processing flows, including: Scan the binary file of the service process, parse the jump instructions, and determine the target address for the jump; Determine the physical page location based on the target address.
4. The inter-process communication method for a microkernel operating system according to claim 2, characterized in that, The stack page prefetching mechanism based on spatial locality predicts stack pages along the stack growth direction, including: Add stack pointer analysis to the thread scheduler and inter-process communication entry logic. By tracking the growth direction of the stack, the current stack frame size, and the call depth of the service thread, predict the stack pages that will be accessed in the future.
5. The inter-process communication method for a microkernel operating system according to claim 1, characterized in that, Further includes: The target page table entries in the process prefetch set are loaded into the user process TLB using the page table loading instructions of the Loongson architecture.
6. The inter-process communication method for a microkernel operating system according to any one of claims 1 to 5, characterized in that, Also includes: During the context switching phase of inter-process communication, the priority of loading target page table entries in the process prefetch set is dynamically adjusted; The priority order is determined based on historical communication frequency and current communication needs.
7. An inter-process communication device for a microkernel operating system, characterized in that, include: The registration module is used to register key instruction pages and stack pages during the service process initialization phase. The construction module is used to construct the process prefetch set based on the registered key instruction pages and stack pages; The loading module is used to load the target page table entries in the process prefetch set into the user process TLB during the inter-process communication initiation phase, so as to perform inter-process communication.
8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the inter-process communication method of the microkernel operating system as described in any one of claims 1 to 6.
9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the inter-process communication method of the microkernel operating system as described in any one of claims 1 to 6.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the inter-process communication method of the microkernel operating system as described in any one of claims 1 to 6.