Chip array, beam steering array, slave chip array, slave chip

Abstract

The embodiments of the present disclosure provide a chip array, a beam control array, a slave chip array, and a slave chip. The chip array includes: a master chip; at least one slave chip chain, the slave chip chain includes multiple cascaded slave chips, and the slave chip includes a shift register; in the serial input state, the master chip is configured to: output a data frame chain to the slave chip chain; the slave chip chain is configured to: transmit the data of the data frame chain step by step in the slave chip chain; the data frame chain includes multiple serial data frames, and the order of the data frames matches the arrangement order of the slave chips; after the entire data frame chain is transmitted, the data frame is input into the shift register of the corresponding slave chip; in the non-serial input state, the master chip is configured to: enable all slave chips to perform unified parsing; the slave chip is configured to: parse the current data frame in its respective shift register in response to the master chip enabling parsing. The present disclosure can increase the number of slave chips controlled by the master chip.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design, and in particular to a chip array, a beam control array, a slave chip array, and a slave chip. Background Art

[0002] In traditional antenna arrays, the control data for each antenna's corresponding beam steering chip comes directly from the baseband chip, and these chips also need to directly feed data back to the baseband chip. When there are many antennas, the number of data traces also increases, occupying a large amount of printed circuit board (PCB) wiring resources and increasing wiring complexity. Overly complex PCB routing also results in longer data traces, degrading signal integrity and reducing beam steering speed. Summary of the Invention

[0003] The present disclosure provides a chip array, a beam steering array, a slave chip array, and a slave chip. The chip array includes:

[0004] Main chip;

[0005] At least one slave chip chain, the slave chip chain comprising a plurality of cascaded slave chips, the slave chips comprising shift registers; wherein the data input terminal of the first-stage slave chip is connected to the data output terminal of the master chip, and the data output terminal of the previous-stage slave chip is serially connected to the data input terminal of the next-stage slave chip;

[0006] In the serial input state:

[0007] The main chip is configured as follows:

[0008] Outputting a data frame chain to the slave chip chain;

[0009] The slave chip chain is configured as follows:

[0010] The data of the data frame chain is transmitted step by step in the slave chip chain; wherein the data frame chain includes a plurality of serial data frames, and the order of the plurality of data frames matches the arrangement order of the slave chips; after the entire data frame chain is transmitted, the data frame is input into the shift register of the corresponding slave chip;

[0011] In non-serial state:

[0012] The main chip is configured as follows:

[0013] enabling all the slave chips to perform unified parsing;

[0014] The slave chip is configured as follows:

[0015] In response to the master chip enabling parsing, the current data frame in each of the shift registers is parsed.

[0016] Because the chip array includes a master chip and at least one slave chip chain, the slave chip chain includes multiple cascaded slave chips, and the slave chips include shift registers. The data input of the first slave chip is connected to the data output of the master chip, and the data output of the previous slave chip is serially connected to the data input of the next slave chip. After the data is serially output from the shift register of the previous slave chip, it enters the shift register of the next slave chip. Therefore, through the serial cascade structure, the data lines used for data transmission can be reused, significantly reducing the number of traces between the master chip and the slave chips, and reducing the complexity of PCB wiring and resource utilization.

[0017] In the same slave chip chain, the data of the data frame chain is transmitted step by step in the slave chip chain. Different slave chips can reuse the data output terminal of the master chip, avoiding the impact of too many slave chips connected in parallel on the master chip line on signal quality, reducing the logic pin resources of the master chip, and significantly increasing the number of slave chips controlled by the master chip.

[0018] Since the master chip only drives the first slave chip in the slave chip chain, and the remaining slave chips are driven by the previous slave chip, it can also reduce the driving difficulty of the master chip, increase the clock frequency, and improve the beam switching speed;

[0019] The data frame positions are sequentially matched to the physical cascade positions of the slave chips. Data in the data frame chain is passed through the slave chip chain level by level, allowing each data frame to be accurately input into the corresponding slave chip's shift register. When the master chip uniformly triggers all slave chips to parse the data frame chain, the slave chips can obtain the data frames they need from their respective shift registers and accurately parse them. This allows for quick and unified configuration of a slave chip chain, improving read and write efficiency. Furthermore, by sequentially matching the data frame positions to the physical cascade positions of the slave chips, position matching can be achieved without addressing, simplifying hardware design and improving transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the control topology of a chip array;

[0021] Figure 2 A schematic diagram of the structure of a beamforming chip and a control chip;

[0022] Figure 3 A schematic structural diagram of a first chip array provided in an embodiment of the present disclosure;

[0023] Figure 4 A schematic diagram of the structure of the first data frame chain provided in an embodiment of the present disclosure;

[0024] Figure 5 A schematic diagram of the frame structure of a data frame provided in an embodiment of the present disclosure;

[0025] Figure 6 A schematic diagram of the structure of a second data frame chain and a schematic diagram of signal timing provided in an embodiment of the present disclosure;

[0026] Figure 7 A schematic diagram of the structure of a slave chip provided in an embodiment of the present disclosure;

[0027] Figure 8 A schematic diagram of data input and parsing provided in an embodiment of the present disclosure;

[0028] Figure 9 A schematic diagram of data string input provided in an embodiment of the present disclosure;

[0029] Figure 10 A schematic diagram of the structure of a tri-state output gate provided in an embodiment of the present disclosure;

[0030] Figure 11 A schematic structural diagram of a second chip array provided in an embodiment of the present disclosure;

[0031] Figure 12 A schematic structural diagram of a third chip array provided in an embodiment of the present disclosure;

[0032] Figure 13 A schematic structural diagram of a fourth chip array provided in an embodiment of the present disclosure;

[0033] Figure 14 This is a schematic structural diagram of the fifth chip array provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to illustrate the relevant disclosure and are not intended to limit the disclosure. It should also be noted that for ease of description, only the portions relevant to the relevant disclosure are shown in the drawings.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0036] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0037] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0038] Figure 1 Figure 2 shows a schematic diagram of the control topology of a chip array. Figure 1 As shown, the system includes a control chip and N+1 slave chips. The control chip, which can also be called a master chip, controller, etc., is the chip or device that controls the slave chips, specifically a baseband chip. The slave chips, also known as beamforming chips, beamsteering chips, or beamforming chips, perform beamforming. In each slave chip, the abbreviations have the following meanings: SDI represents the data input terminal; SDO represents the data output terminal; CLK represents the clock (or clock signal) input terminal; SEL0 through SELN represent the chip select signal input terminals for slave chips 0 through N. In the figures of the embodiments of the present disclosure, hexagons represent ports for data transmission. In the control chip, the abbreviations have the following meanings: SDI represents the data output terminal; CLK represents the clock output terminal; SDO represents the data readback terminal; and SEL0 through SELN represent the N+1 chip select signal output terminals.

[0039] Beamforming chips are one of the core components of phased array systems and are currently widely used in broadband satellite communications, millimeter wave 5G communications and other fields. Figure 2 Schematic diagram of the structure of a beamforming chip and a control chip provided by an embodiment of the present disclosure. Figure 2 As shown, the beamforming chip may include multiple RF channels. Figure 2 3 RF channels are shown in FIG. In some embodiments, the beamforming chip may include 4, 8 or 16 RF channels, etc., wherein the RF channel is a transmission channel for RF signals, including a transmitting channel for RF signals and a receiving channel for RF signals. Figure 2The receiving channel is used as an example for explanation. Each RF channel is coupled to an antenna and can receive RF signals from the antenna. Each RF channel includes a corresponding phase shifter and / or an amplitude adjuster. The phase shifter is used to shift the phase of the signal, and the amplitude adjuster is used to adjust the amplitude of the signal. The amplitude adjuster can be an attenuator or an amplifier. When the phased array system needs to point to a specific direction and realize a beam in a specific direction, the corresponding RF signal can be phase-shifted by the phase shifter in the phased array, and / or the corresponding RF signal can be amplitude-adjusted by the amplitude adjuster, so that a directional pattern in a specific direction and a corresponding beam can be obtained. The beamforming chip can also include a combiner to combine the signals of multiple RF channels and send the combined signal to the processor in the control chip. The processor can be a baseband processor, and the processor and the combiner can also include a modulator to modulate the RF signal into a digital signal, or modulate the digital signal into an RF signal.

[0040] Data controlling the phase shifters and amplitude modulators can be sent from the control chip to the beamforming chip and transmitted to each phase shifter and amplitude modulator to adjust the phase and amplitude of each phase shifter and amplitude modulator, respectively. Data transmission between the control chip and the beamforming chip can be accomplished using a serial peripheral interface (SPI). The control chip includes an SPI master, and the beamforming chip includes an SPI slave. In the serial-in mode, the SPI master sends data frames to the SPI slave. In the non-serial-in mode, the SPI slave parses the data frames and sends the parsed data to the corresponding phase shifter and amplitude modulator.

[0041] like Figure 1 and Figure 2 Slave chips (beamforming chips) typically use SPI to meet beam control requirements. SPI typically uses a chip select signal to select the slave chip to be controlled, and uses the CLK and SDI lines for serial data input. SPI also typically requires readback to verify the correctness of the serially input data. Therefore, the slave chip also has a data output port (SDO) connected to the master chip's data readback port (SDO).

[0042] like Figure 1As shown, the chip select signal input terminal SELj of the slave chip is connected to the corresponding chip select signal output terminal SELj of the control chip, j is an integer greater than or equal to 0 and less than or equal to N, and is used to receive the corresponding chip select signal j issued by the control chip; the clock input terminal CLK of the slave chip is connected to the clock output terminal CLK of the control chip, and is used to receive the clock issued by the control chip; the data input terminal SDI of the slave chip is connected to the data output terminal SDI of the control chip, and is used to receive the data signal issued by the control chip; the data output terminal SDO of the slave chip is connected to the data readback terminal SDO of the control chip, and is used to transmit the readback data to the control chip.

[0043] The topology of a controller chip array typically separates chip select signal lines to control different slave chips, but reuses clock and data signals. As the number of slave chips increases, more slave chips are connected in parallel to the clock and data signal lines. Due to parasitic capacitance on the data signal lines, connecting more slave chips in parallel increases the parasitic capacitance on the clock and data signal lines, resulting in poor signal quality. This limits the maximum number of slave chips that can be controlled by the master chip.

[0044] Based on this, an embodiment of the present disclosure provides a chip array comprising a master chip and at least one slave chip chain. The slave chip chain comprises a plurality of cascaded slave chips, each of which includes a shift register. The data input of a first-stage slave chip is connected to the data output of the master chip, and the data output of the previous-stage slave chip is serially connected to the data input of the next-stage slave chip. After data is serially output from the shift register of the previous slave chip, it enters the shift register of the next slave chip. Thus, through the serial cascade structure, the data lines used for data transmission can be reused, significantly reducing the number of traces between the master chip and the slave chips, and reducing PCB wiring complexity and resource usage.

[0045] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0046] In one embodiment of the present disclosure, see Figure 3 , the chip array 20 includes:

[0047] Main chip 201;

[0048] At least one slave chip chain 202 includes multiple cascaded slave chips 203. Each slave chip 203 includes a shift register 204. The shift register 204 is used to sequentially transmit data among the multiple slave chips 203 in the slave chip chain 202. The data input terminal SDI of the first-stage slave chip 203 is connected to the data output terminal SDI of the master chip 201, so that the master chip 201 receives serially input data (specifically, a data frame chain). The data output terminal SDO of the previous-stage slave chip 203 is serially connected to the data input terminal SDI of the next-stage slave chip 203, so that the data serially output by the previous-stage slave chip 203 is input to the next-stage slave chip 203.

[0049] In the embodiment of the present disclosure, the master chip 201 can send a data frame chain to the slave chip chain 202, and the data frame chain carries data for beamforming. The structure of the data frame chain can be as follows: Figure 4 As shown, the data frame chain includes N+1 serial data frames, which are used to perform read and write operations on the corresponding slave chip 203. Each data frame corresponds to a slave chip 203 in the slave chip chain 202, and the order of the N+1 data frames matches the arrangement order of the N+1 slave chips 203, so that each data frame can be transferred to the corresponding slave chip 203. Figure 3 Take slave chip chain 0 in the example, Figure 4 Data frame 0_0 corresponds to slave chip 0_0, ..., data frame 0_N-1 corresponds to slave chip 0_N-1, and data frame 0_N corresponds to slave chip 0_N. That is, data frame i corresponds to slave chip 0_i, where i is an integer and 0≤i≤N, and N is a positive integer. Each data frame is used to perform read and write operations on the corresponding slave chip 203.

[0050] In the serial input state (the state in which the data frame chain is serially input into the slave chip chain 202), the master chip 201 is configured to output the data frame chain to the slave chip chain 202. The slave chip chain 202 is configured to pass the data of the data frame chain step by step within the slave chip chain 202. Because the order of the multiple data frames matches the arrangement order of the multiple slave chips 203, after the entire data frame chain is transmitted, the multiple data frames are respectively input into the shift register 204 of the corresponding slave chip 203. No address addressing is required to ensure that each data frame is accurately input into the shift register 204 of the corresponding slave chip 203.

[0051] by Figure 3Taking slave chip chain 0 in the example, the data frame chain transmission process is as follows: After the first-level slave chip 0_N receives a data frame, it stores it in shift register 204. The data is shifted into shift register 204 bit by bit. After shift register 204 has stored a data frame, the first-level slave chip 0_N shifts the data out and transmits the data serially through data output terminal SDO to data input terminal SDI of the next-level slave chip 0_N-1. At the same time, the first-level slave chip 0_N continues to receive subsequent data bit by bit. The next-level slave chip 0_N-1 repeats the above process until the shift register 204 of all slave chips 203 is filled with data.

[0052] After the entire data frame chain is transmitted, the chip array 20 is in a non-serial state.

[0053] In the non-serial state, the master chip 201 is configured to enable all slave chips 203 in one or more slave chip chains 202, so that all slave chips 203 perform unified parsing;

[0054] All slave chips 203 in the slave chip chain 202 are configured to respond to the master chip 201's enable parsing, parse the current data frame in their respective shift registers 204, obtain their respective required data frames from their respective shift registers 204, and accurately parse their respective required data frames, thereby quickly and uniformly configuring one or more slave chip chains 202 and improving read and write efficiency. Furthermore, through the serial cascade structure of the slave chip chain 202, the data lines used for data transmission can be reused, significantly reducing the number of traces between the master chip 201 and the slave chips 203, and reducing PCB wiring complexity and resource usage.

[0055] In the same slave chip chain 202, the data of the data frame chain is transmitted step by step in the slave chip chain 202. Different slave chips 202 can reuse the data output terminal of the master chip 201, avoiding the impact of too many slave chips connected in parallel on the master chip 201 on signal quality, reducing the logic pin resources of the master chip 201, and significantly increasing the number of slave chips 203 controlled by the master chip 201.

[0056] Since the master chip 201 only drives the first slave chip 203 in the slave chip chain 202, the remaining slave chips 203 are driven by the previous slave chip 203, which can also reduce the driving difficulty of the master chip 201, increase the clock frequency, and improve the beam switching speed.

[0057] Since multiple slave chips 203 are cascaded to form a slave chip chain 202, on the basis of the master chip 201 being directly connected to N+1 slave chips 203, the master chip 201 can be further indirectly connected to a larger number of slave chips 203 by connecting the slave chips 203 in series. Since the multiple cascaded slave chips 203 are not directly connected to the master chip 201, the problem of too many slave chips directly connected to the master chip 201, which leads to large parasitic capacitance and thus poor signal quality, is avoided. Ultimately, the number of slave chips 203 that can be controlled by the master chip 201 is greatly increased without compromising the signal quality. Taking the number of slave chips 203 as (N+1)×(N+1) as an example, in Figure 1 In the comparison example shown, the master chip (control chip) needs to directly connect (N+1)×(N+1) slave chips. The number of connected slave chips is too large, and the parasitic capacitance on the connection line is large. Figure 3 In the chip array 20 shown, the master chip 201 only needs to connect to (N+1) first-stage slave chips 203, and these (N+1) first-stage slave chips 203 are each connected in series with multiple slave chips 203. The master chip 201 does not need to be burdened with too many slave chips 203, and the parasitic capacitance is significantly reduced.

[0058] It should be noted that in Figure 3 In the following related drawings, for the sake of clarity, only one reference numeral 202 and one reference numeral 203 are shown, and only Figure 3 A shift register 204 is shown in the slave chips 0_N. In fact, each slave chip 203 includes a shift register 204. Figure 3 The remaining slave chips 203 and subsequent figures are not shown. Slave chips 0_N to 0_0 constitute slave chip chain 0, slave chips 1_N to 1_0 constitute slave chip chain 1, ..., and slave chips N_N to N_0 constitute slave chip chain N.

[0059] It should also be noted that in the disclosed embodiment, the chip array 20 can be connected via an SPI interface. An SPI interface typically includes two modes: master and slave. In SPI communication, the master is responsible for controlling the initiation and termination of communication, as well as timing, and sends data frames to the slaves to write data to them. The slaves passively respond to the master's instructions to transmit data. In the disclosed embodiment, the master chip 201 (slave chip) can be the master, and the slave chips 203 (slave chips) can be the slaves. Each slave chip 203 can be a beamforming chip, each corresponding to multiple beams (e.g., 16 beams).

[0060] It should also be noted that in the embodiment of the present disclosure, some slave chip chains 202 may include multiple slave chips 203, while others may include only one slave chip 203, that is, at least one of the multiple slave chip chains 202 may include multiple slave chips 203. In addition, the number of slave chips 203 included in each slave chip chain 202 may be the same or different, and this is not specifically limited. Alternatively, it may include only one slave chip chain 202. As an example, Figure 3 As shown, the chip array 20 includes N+1 slave chip chains 202 , and each slave chip chain 202 includes N+1 slave chips 203 .

[0061] The master chip 201 can control whether the slave chip 203 enters the serial state by changing the state of the chip select signal. Figure 3 Taking the chip array 20 shown as an example, the master chip 201 includes multiple chip select signal output terminals SEL0, SEL1, ..., SELN for outputting chip select signals, which output chip select signal 0, chip select signal 1, ..., chip select signal N respectively; the slave chip 203 includes a chip select signal input terminal SELI and a chip select signal output terminal SELO.

[0062] In the slave chip chain 202, the chip select signal input terminal SELI of the first-level slave chip 203 is connected to the corresponding chip select signal output terminal SELi of the master chip 201, and is used to receive the chip select signal sent by the master chip 201. The chip select signal input terminal SELI of the latter-level slave chip 203 is connected to the chip select signal output terminal SELO of the previous-level slave chip 203, and is used to receive the chip select signal sent by the previous-level slave chip 203, so that the chip select signal is transmitted step by step in the slave chip chain 202, thereby saving the transmission path of the chip select signal.

[0063] The master chip 201 is configured to: for a slave chip chain 202 that needs to serialize data, change the state of the corresponding chip select signal to enable the slave chip chain 202 to enter the serializing state. For a slave chip chain 202 that needs to parse data, change the state of the corresponding chip select signal to enter the non-serializing state, and enable the slave chip chain 202 to perform parsing.

[0064] like Figure 3As shown, the N+1 slave chips 203 belonging to the same slave chip chain 202 reuse the same chip select signal, that is, slave chip chain i corresponds to chip select signal SELi. For example, the chip select signal can be transmitted serially within a slave chip chain 202. Taking slave chip chain 0 as an example, the chip select signal input terminal of the first slave chip 0_N is connected to the chip select signal output terminal SEL0 of the master chip 201 for outputting chip select signal 0. The chip select signal output terminal SELO of each slave chip 203 except the final slave chip 0_0 is connected to the chip select signal input terminal SELI of the next slave chip 203 to transmit the chip select signal to the next slave chip 203. In some embodiments, each slave chip 203 can also correspond to an independent chip select signal SEL.

[0065] Since not every slave chip chain 202 requires a data frame chain, the required slave chip chain 202 needs to be selected through a chip select signal, which determines whether it is in a serial state or enabled for parsing based on the state of the received chip select signal.

[0066] For example, when the chip select signal is in the first state, the slave chip 203 receiving the chip select signal is selected, indicating that it is in the serial-in state. The slave chip 203 only transmits data frames and does not parse them. When the chip select signal is in the second state, the slave chip 203 is enabled and does not transmit data frames, but instead parses them. It should be noted that the slave chip 203 does not perform any logical processing on the chip select signal; it simply passes the chip select signal to the subsequent slave chip 203. The first state can be a low level state (logic 0), and the second state can be a high level state (logic 1), but is not limited to these.

[0067] because Figure 3 Multiple slave chips 203 in a slave chip chain 202 reuse the same chip select signal, and the chip select signal is driven by the slave chip 203, which reduces the line burden of the master chip 201. Figure 1 In the comparison scheme, the chip select signal changes from selecting a slave chip 203 to selecting a slave chip chain 202.

[0068] In some embodiments, as Figure 3 As shown, the master chip 201 may further include a clock output terminal CLK for outputting a clock (or clock signal); the slave chip 203 may further include a clock input terminal CLKI and a clock output terminal CLKO;

[0069] In the slave chip chain 202, the clock input terminal CLKI of the first-level slave chip 203 is connected to the clock output terminal CLK of the master chip 201, and the clock input terminal CLKI of the next-level slave chip 203 is connected to the clock output terminal CLKO of the previous-level slave chip 203. The clock is transmitted step by step in the slave chip chain 202.

[0070] It should be noted that if Figure 3As shown, the clock input terminal CLKI of the first slave chip 203 in the slave chip chain 202 is connected to the clock output terminal CLK of the master chip 201, and the clock output terminal CLKO of the previous slave chip 203 is connected to the clock input terminal CLKI of the next slave chip 203, thereby realizing clock transmission throughout the entire slave chip chain 202. The N+1 slave chip chains 202 reuse the same clock issued by the master chip 201.

[0071] On the basis of the clock provided by the master chip 201, when stringing in data, a clock is provided to the slave chip chain 202 that needs to string in data, providing an accurate time reference for data transmission, ensuring that the master chip 201 and the slave chip chain 202 can send and receive data at the same rate.

[0072] like Figure 3 As shown in the figure, the SPI interface also has a readback function, which can detect whether the incoming data frame is erroneous. If an error is detected in the incoming data frame, it needs to be rewritten, so the readback function can be used for error correction. Figure 3 As shown, the master chip 201 may further include a data readback terminal SDO connected to the data output terminal SDO of the last slave chip 203 in the slave chip chain 202 to read back the output data signal (ie, readback data) of the last slave chip 203 .

[0073] exist Figure 3 In the embodiment, different slave chip chains 202 can share the data readback terminal SDO of the master chip 201 ; the data output terminal SDO of the last slave chip 203 in each slave chip chain 202 is connected to the same data readback terminal SDO in the master chip 201 .

[0074] Since the readback data is transmitted from the final-stage slave chip 203 back to the data readback terminal SDO of the master chip 201, at least the data output terminal of the final-stage slave chip 203 is a three-state output. Furthermore, in practice, chips are typically mass-produced, so multiple slave chips 203 typically have the same specifications and all have three-state output data output terminals. Here, a three-state output includes three states: a logic low level (logic 0, which can be recorded as the first logic state), a logic high level (logic 1, which can be recorded as the second logic state), and a high-impedance state. The high-impedance state is equivalent to disconnecting the output terminal from the circuit, with virtually no impact on the external circuit. This design allows multiple final-stage slave chips 203 to be connected to the same data readback terminal SDO of the master chip 201 without interfering with each other.

[0075] Based on the final stage slave chip 203 with tri-state output, the master chip 201 is configured to: enable the data output terminal of the final stage slave chip 203 to be read back;

[0076] The final-stage slave chip 203 is configured as follows: in response to enabling readback, the data output terminal of the slave chip 203 outputs a logic high level or a logic low level for outputting the readback data; wherein, the data output terminal of the slave chip 203 that is not enabled enters a high-impedance state and does not output the readback data.

[0077] For example, when the data of slave chip 0_0 needs to be read back, the master chip 201 can enable the data output end of slave chip 0_0 and disable slave chips 1_0 to N_0. In response to enabling read back, the data output end of slave chip 0_0 can output a logic level (logic high level or / and logic low level), and the data output ends of slave chips 1_0 to N_0 enter a high-impedance state and do not output a logic level. Therefore, the data output ends of slave chips 1_0 to N_0 will not affect the read back of slave chip 0_0.

[0078] like Figure 3 As shown, in the same slave chip chain 202, the clock, chip select signal, and data are all transmitted from the upper-level slave chip 203 to the lower-level slave chip 203. The transmission path lengths of the clock, chip select signal, and data are comparable, so the phases of the clock, chip select signal, and data are synchronized when passing through each level of slave chip 203.

[0079] Compared to Figure 1 The comparative example, Figure 3 In the illustrated scheme, the master chip 201 changes from controlling a particular slave chip 203 to controlling a particular slave chip chain 202. Due to the loss of the high-level duty cycle of the clock signal after passing through the slave chip 203, assuming that the high-level duty cycle of the clock signal loses 1% after each level of slave chip 203, and the initial high-level duty cycle of the clock signal input to the first-level slave chip 203 is 50%, then after passing through 50 levels of slave chips 203, the high-level duty cycle of the clock signal will become 0%, that is, the clock signal cannot be transmitted to the slave chips 203 at level 50 and beyond. That is, the number of slave chips 203 in the slave chip chain 202 is not infinitely cascaded, and the high-level loss of the clock during transmission in the slave chip 203 also needs to be considered. At the same time, since increasing the number of cascaded slave chips 203 will also increase the data transmission time, a compromise needs to be made between the data transmission time and the maximum number of slave chips 203 that can be controlled.

[0080] The following combination Figure 5 , illustrating an exemplary frame structure of a data frame provided in an embodiment of the present disclosure.

[0081] See also Figure 5, frame structure 1 is the most basic frame structure, including a frame header, control information, address bits and data bits. Among them, the frame header is a set of specific bit patterns or signal sequences used to identify and mark the start and end of the data frame, usually composed of a clock signal and the state of the host selection line. The frame header may contain the following information: selection of slave, data transmission mode, confirmation and verification information, etc. The control information is used to control the operation or method of data transmission. The control information may include information such as instructions. The control information determines what operation to perform on the frame after parsing the frame, such as a write operation or a read operation. The address bit is used to indicate the destination or source of data transmission. It is used for addressing, that is, the address bit determines where the data in the slave chip 203 is to be operated. For example, the address bit indicates the address of the storage unit in the slave chip 203. The storage unit can be understood as a register or a storage unit. In the embodiment of the present disclosure, it can be recorded as a second storage unit. For example, the slave chip (beamforming chip) may include multiple second storage units, and the multiple second storage units correspond to Figure 2 Each amplitude adjuster and each phase shifter is used to store corresponding amplitude adjustment data (such as data 4) or corresponding phase shift data (such as data 1). Data bits are used to transmit actual data. The data in the data bits is new data transmitted to the slave chip 203, such as data written to the storage unit of the slave chip 203 (such as amplitude adjustment data or phase shift data).

[0082] exist Figure 5 In the illustrated frame structure 1, the frame header, control information, address bits, and data bits may be arranged sequentially within the data frame. In other embodiments, the order of the control information, address bits, and data bits may be interchanged. Furthermore, the data frame structure may include a frame tail, which is a specific bit pattern or signal sequence used to indicate the end of the frame. The frame header, control information, address bits, and data bits may each comprise one or more bits.

[0083] Frame structures 2 through 7 are variants of frame structure 1, each adapting to different scenarios. For example, to save data frame transmission and parsing time, certain components can be omitted in different scenarios. For example, one or more of the frame header, control information, address bits, and data bits can be omitted to reduce data frame length and increase processing speed. Alternatively, a data frame can include multiple data bits, allowing data to be written to multiple storage units simultaneously, thereby increasing processing speed. The order of the remaining components, except for the frame header, is interchangeable across different frame structure variants.

[0084] Frame structure 2 has no address bit, and all the data in the data bits are written into a default storage unit. The slave chip 203 determines the operation mode according to the content of the control information. When the operation mode is a write operation, the data frame is a write frame, and the data in the data bits are written into the default storage unit. When the operation mode is a read operation, the data frame is a read frame, and the data is read from the default storage unit.

[0085] Frame structure 3 has no data bits. In this case, data is pre-stored in the default storage unit and is directly addressed and read. For example, in a write frame, the data in the default storage unit is written to the storage unit corresponding to the address bit; in a read frame, the data is read from the storage unit corresponding to the address bit.

[0086] Frame structure 4 retains only the data bits, and the data in the data bits can be written to the default storage location. Frame structure 4 defaults to a read frame. The operation mode can be determined based on pre-stored control information. For a write frame, the data bits are written to the default storage location. The default storage location is a pre-set storage location, and the location of the storage location can be determined without the need for address bits.

[0087] The frame structure 5 only includes a frame header and control information. The operation mode is determined according to the content of the control information. For a read frame, data is read from a default storage unit. For a write frame, default data is written to a default storage unit.

[0088] Frame structure 6 is a complete, merged data frame structure. Based on frame structure 1, it includes at least two data bits. Given a starting address, subsequent data is written sequentially to the storage cells corresponding to the starting address and subsequent addresses. The control information determines the operation mode. For a write frame, the address indicated by the address bits is used as the starting address, and the data in the data bits is written sequentially to multiple storage cells.

[0089] It can be seen that the data frame may include data bits, so a second register unit (storage unit) may be provided in the slave chip 203 to store the data bits.

[0090] Frame structure X in frame structure 7 is any one of frame structures 1 to 6, and further includes address information. This address information indicates the address of the slave chip 203, for example, indicating the row and column of the chip array where the slave chip 203 is located; or this address information simply indicates the row where the slave chip 203 is located. Unlike the address bit, which is used to indicate the storage unit where data is written or read, the address information is used by the slave chip 203 to verify its own address and address information. When its own address and address information are consistent, it determines whether it is in the serial input state (for the specific verification process, see Figure 13The proofreading in the embodiment will not be repeated here), which is equivalent to performing a second confirmation to ensure that the data frame is the data frame corresponding to the slave chip 203. This frame structure can be applied to the scenario where all slave chips 203 share a data output terminal of the master chip 201.

[0091] It should be noted that Figure 5 The following is only a schematic diagram of the frame structure of the data frame. In actual applications, the frame structure is not limited to this. On this basis, take the data frame chain composed of frame structure 1 as an example. Figure 6 Shows a schematic diagram of the data frame chain ( Figure 6 (a) in the figure and the signal timing diagram ( Figure 6 (b) in ). Figure 6 In (a), each data frame includes a frame header, control information, address bits, and data bits. Assume that there are four slave chips 203 cascaded in the slave chip chain 202. The frame header (head) is assumed to be only 1 bit, the control information (ctrl) is assumed to be only 1 bit, and the data address and data information have multiple bits. When stringing the data frame, the timing of the chip select signal, clock, and input data signal (data frame chain) is as follows: Figure 6 As shown in (b) of FIG, the data frame chain includes four data frames, Data Frame 0 through Data Frame 3. Here, the example uses a chip select signal with a first state of a low-level logic 0 and a second state of a high-level logic 1. However, the reverse is also possible and is not specifically limited. When the corresponding chip select signal is pulled low, the slave chip 203 does not perform any logical operations (such as parsing) on ​​the data frame and simply passes the data frame to the next slave chip 203. When the corresponding chip select signal is pulled high, the slave chip 203 stops passing the data frame and instead parses the data frame.

[0092] In some embodiments, Figure 6 The data frame structure in (a) is not limited to Frame Structure 1, and may also be any of Frame Structures 2 to 7. For example, when Frame Structure 2 is used, each data frame may not include address bits; when Frame Structure 3 is used, each data frame may not include data bits; when Frame Structure 4 is used, each data frame may include only data bits, and so on.

[0093] Figure 7 Several exemplary structural diagrams of the slave chip 203 provided in the embodiments of the present disclosure are shown. Figure 7In (a), each slave chip 203 includes a shift register 204. The shift register 204 is connected to the data input terminal SDI and data output terminal SDO of the same slave chip 203. The shift register 204 is used for serial data input and output within the slave chip 203. When data is serially input into a slave chip 203 via the data input terminal SDI, the data is stored in the shift register 204. The data is then transferred from the shift register 204 to the data output terminal SDO and then to the data input terminal SDI of the next-level slave chip 203, thereby achieving step-by-step data transmission within the slave chip chain 202.

[0094] like Figure 7 As shown in (b) of FIG. 2 , the slave chip 203 further includes a plurality of second register units 206 for storing a plurality of data bits from the shift register 204 , each of which may have multiple bits. In this solution, the second register units 206 are used to control the phase and / or amplitude.

[0095] In some cases, the number of the second register units 206 can be the same as the number of RF channels included in the slave chip 203 and correspond one to one. The second register units 206 are connected to the phase shifters and / or amplitude adjusters of the corresponding RF channels and output the stored data bits to the phase shifters and / or amplitude adjusters of the corresponding RF channels to control the phase and / or amplitude of the corresponding RF channels. For example, Figure 2 For the three RF channels, the slave chip 203 may include three second register units 206 . The second register unit 206 corresponding to RF channel 1 is used to store data 1 and data 4. Data 1 is used to control the phase of RF channel 1, and data 4 is used to control the amplitude of RF channel 1. The same applies to RF channels 2 and 3, and will not be repeated here.

[0096] For example, corresponding Figure 2 For the three RF channels, the slave chip 203 may include six second register units 206 , where each RF channel corresponds to two second register units 206 . Taking RF channel 1 as an example, one second register unit 206 corresponds to a phase shifter for storing data 1, and the other second register unit 206 corresponds to an amplitude adjuster for storing data 4. The same applies to RF channels 2 and 3, and will not be further described here.

[0097] In some embodiments, before the data in the data frame chain is passed through the slave chip chain 202, the slave chip chain 202 is further configured to pre-know the number of bits in the data frame from the slave chip 203. Thus, as the data in the data frame chain is passed through the slave chip chain 202, the slave chip 203 can count based on a clock and, when the count reaches the number of bits corresponding to the data frame, transmit the data to the slave chip 203 of the next level.

[0098] In one example, the number of bits of the data frames in the data frame chain is variable, that is, the number of bits of the data frames in the data frame chain sent by the master chip 201 may be different each time. For example, the frame structure of the data frame is variable: at the first moment, the structure of the data frame in the data frame chain sent by the master chip 201 is Figure 5 Frame structure 1 in the subsequent second moment, the structure of the data frame in the data frame chain sent by the main chip 201 is Figure 5 Frame structure 2 in; because the frame structure changes, the number of bits in the data frame changes.

[0099] The count value counted by the slave chip 203 adapts to the number of bits of the data frame, that is, the count value counted by the slave chip 203 changes with the number of bits of the data frame, so as to correctly string the data to the next stage according to the count value. Specifically, the data frame includes frame length information, which is used to indicate the number of bits of the data frame in the next data frame chain, so that the slave chip 203 can correctly transmit the data frame and transmit the data to the required slave chip 203. For example, when the structure of the data frame is frame structure 1~3, 5~7, the control information includes frame length information. When the structure of the data frame is frame structure 4, the data bits include frame length information. In one embodiment, at the first moment, the structure of the data frame in the data frame chain sent by the master chip 201 is Figure 5 The number of bits in the frame structure 1 is A1. When the data is input, the slave chip counts. When the count value reaches A1, the data is output to the next stage. After the data frame chain is transmitted, the slave chip parses the corresponding data frame and parses the frame length information from the control information, thereby knowing that the number of bits of the next data frame is A2. At the second moment, the structure of the data frame in the data frame chain sent by the master chip 201 is Figure 5 In the frame structure 2, the number of bits of the frame structure 2 is A2. When data is serially input, the slave chip counts, and when the count value reaches A2, the data is serialized to the next stage.

[0100] like Figure 7 As shown in (c), the slave chip 203 may further include a first register unit 205 connected to the shift register 204 for obtaining and storing frame length information.

[0101] In this case, a first register unit 205 (or frame type register) can be used to store the number of bits in the data frame (i.e., frame length information). When the number of bits of data input to the shift register 204 matches the frame length information pre-stored in the first register unit 205, the shift register 204 serializes the data to the next slave chip. In other words, the slave chip 203 can have a built-in counter that determines whether to output data to the next slave chip 203 by counting. The counter increments by one each time a piece of data is input to the shift register 204. When counting, the slave chip 203 uses the frame length information as the upper limit. When the count reaches this upper limit, the stored data frame is sent to the next slave chip 203. Because the count value dynamically adapts to the frame length information, the number of bits of data stored in the shift register 204 adapts to the frame length of the current data frame, facilitating accurate transmission of the data frame to the corresponding slave chip 203.

[0102] In other examples, the number of bits in the data frame may also remain unchanged, and the number of bits in the shift register 204 is always equal to the number of bits in the data frame. It should be noted that the number of bits in the shift register 204 is the number of data bits that the shift register can store. If the number of bits in each data frame chain sent by the master chip 201 remains unchanged and the number of bits in the shift register 204 is equal to the number of bits in the data frame, then when the shift register 204 is full, the data frame will be shifted out in each clock cycle, thereby achieving the goal of stringing the data frame bit by bit to the next slave chip 203. In other words, the specific method of transmitting the data of the data frame chain step by step in the slave chip chain 202 can be: the shift register 204 serially receives the data frame, and after the shift register 204 is full, the data frame is stringed out bit by bit. In this case, the first register unit 205 is not required to store the frame length information, nor is it necessary to count based on the clock, and the data frame may not include the frame length information.

[0103] In some embodiments, as Figure 7 As shown in (d), the shift register 204 may include an input shift register 2041 and an output shift register 2041. The input shift register 2041 is used to string data into the data input terminal SDI of the slave chip 203. The stringed data is first stored in the input shift register 2041. When the count value reaches the number of bits of the corresponding data frame, the data of the input shift register 2041 is copied to the output shift register 2042. The output shift register 2042 strings data out to the data output terminal SDO of the slave chip 203, thereby realizing the stringing out of data from the slave chip 203 to the next level.

[0104] It should be noted that the embodiment of the present disclosure may be provided with an input shift register 2041 and an output shift register 2042. The input shift register 2041 is used to serially receive a data frame input to the slave chip 203 to which it belongs. When the count value reaches the number of bits in the data frame, the data frame is first copied as a whole from the input shift register 2041 to the output shift register 2042, and then the output shift register 2042 serially outputs the data frame to the input shift register 2041 of the next slave chip 203. In this way, through this copy-and-then-serialize method, regardless of whether the number of bits in the data frame changes, only when the count value reaches the number of bits in the data frame is the data within the input shift register 2041 copied as a whole and sent to the output shift register 2042 for serial output. The count value can dynamically adapt to different data frame lengths, thereby avoiding data transmission errors and improving data transmission accuracy.

[0105] In some embodiments, the data frame structure and / or bit count corresponding to each slave chip 203 in the same slave chip chain 202 are identical, with only the data content being different. This allows for quick and convenient data frame transmission to the corresponding slave chip 203, enabling configuration of all slave chips 203. The frame content of each slave chip 203 in the slave chip chain 202 is completely independent, allowing different instructions to be sent to each slave chip 203, thereby enabling independent operation of each slave chip 203.

[0106] In some other embodiments, the data frame format and / or bit number required by each slave chip 203 may also be partially the same or completely different. Compared with a completely identical data frame chain, it is necessary to generate data frames adapted to the slave chip 203 for different slave chips 203, and each slave chip 203 needs to be configured with a corresponding method for receiving and parsing the data frame, so that the configuration of the data frame is more flexible and changeable.

[0107] The signal transmission, enabling method, data parsing method, data frame structure, etc. of the chip array 20 in the embodiment of the present disclosure are described in detail below with reference to specific embodiments.

[0108] by Figure 6 Taking the frame structure shown in (a) as an example, the data stored in the shift register 204 of each slave chip 203 during the data transmission process is briefly described. Figure 3 Take slave chip 0 in as an example, Figure 8 FIG. 2 shows the data changes in the shift register 204 of the slave chip 203 in the slave chip chain 0 when the data frame is a read frame. Figure 8As shown, the master chip 201 first sends out a data frame chain 0, which includes: data frame 00 corresponding to slave chip 0_0, data frame 10 corresponding to slave chip 0_1, ..., data frame N-10 corresponding to slave chip 0_N-1, and data frame N0 corresponding to slave chip 0_N. That is, for data frame a b , a indicates that it corresponds to slave chip 0_a, a=0, 1, 2, ..., N, b indicates that it belongs to data frame chain b, b=0, 1, 2, ....

[0109] like Figure 8 As shown, after the data frame chain 0 is transmitted, the shift register 204 of the slave chip 0_0 stores the data frame 00, the shift register 204 of the slave chip 0_1 stores the data frame 10, ..., the shift register 204 of the slave chip 0_N-1 stores the data frame (N-1)0, and the shift register 204 of the slave chip 0_N stores the data frame N0.

[0110] Master chip 201 then enables all slave chips 203 via a chip select signal. In response to the master chip 201's enable signal, each slave chip 203 parses the data frame (read frame) in its own shift register 204. After parses the control information in the data frame and confirms that the control information indicates a read operation, each slave chip 203 reads the required data (referred to as readback data) from the second register unit 206 and updates the data in the shift register 204 to the readback data. This data refresh corresponds to a read operation: a read operation shifts the data from the storage unit to the shift register 204 before transmitting it back out. Slave chip 203 also obtains the frame length information of the data frame in data frame chain 1 from the control information and stores this frame length information in the first register unit 205.

[0111] like Figure 8 As shown, after parsing data frame chain 0, the data frame is no longer stored in the shift register 204 of each slave chip 203, but readback data. It can be understood that since the readback data needs to be temporarily stored in the shift register 204, the number of data bits that the shift register 204 can store must be greater than or equal to the maximum number of bits of readback data.

[0112] After parsing is complete, master chip 201 sets chip select signal 0 to the first state, indicating that it is currently in the serial input state. Driven by a clock, data frames in data frame chain 1 are transmitted step by step through slave chips 0_N-0_0, simultaneously driving the transmission of readback data through the serially connected slave chips 203. Data frame 01 (including frame header 01, control information 01, address bit 01, and data bit 01) is transmitted to slave chip 0_N. Slave chip 0_N first stores received data frame 01 in its own shift register 204. Assume that each data frame in the data frame chain has a bit count of L1, where L1 is a positive integer and one bit of data is transmitted per clock cycle. The number of bits in a data frame includes the sum of the number of bits in the frame header, control information, address bits, and data bits.

[0113] When the count value of slave chip 0_N reaches L1, slave chip 0_N sends the data in its own shift register 204 to the shift register 204 of slave chip 0_N-1. Slave chip 203 may clear the count value and start counting again.

[0114] The readback data is sequentially transmitted to the next-level slave chip. The readback data 00 corresponding to the slave chip 0_0 is shifted out of the slave chip 0_0 and first transmitted back to the data readback terminal SDO of the master chip 201 for readback.

[0115] Next, data frame 11 (including frame header 11, control information 11, address bit 11, and data bit 11) is transmitted to slave chip 0_N-1. Slave chip 0_N-1 first stores the received data frame 01 in its own shift register 204. When the count value of slave chip 0_N-1 reaches L1, slave chip 0_N-1 sends the L1 bit of data currently in its own shift register 204 to the shift register 204 of slave chip 0_N-2.

[0116] The readback data is sequentially transmitted to the next-level slave chip, and the readback data 10 corresponding to the slave chip 0_1 is transmitted back to the data readback terminal SDO of the master chip 201 for readback.

[0117] And so on...

[0118] Finally, after data frame chain 1 is transmitted, data frame 01 is stored in the shift register 204 of slave chip 0_0, data frame 11 is stored in the shift register 204 of slave chip 0_1, ..., data frame (N-1)1 is stored in the shift register 204 of slave chip 0_N-1, and data frame N1 is stored in the shift register 204 of slave chip 0_N. At the same time, all readback data is read back.

[0119] In some embodiments, Figure 8The frame structure of the data frame is not limited to frame structure 1, and can also be any of frame structures 2 to 7. For example, when frame structure 2 is used, each data frame does not include an address bit, and the number of bits of the data frame is the sum of the number of bits of the frame header, control information, and data bits. Assume that the number of bits of the data frame is L2. Then, when the data is transmitted from the chip 203 step by step, when the count value of the chip 203 reaches L2, the data is transmitted to the next level of the chip 203; when the data frame chain is transmitted, the shift register 204 of each slave chip 203 stores the frame header, control information, and data bits;

[0120] When using frame structure 3, each data frame may not include data bits. The number of bits in a data frame is the sum of the number of bits in the frame header, control information, and address bits. Assuming that the number of bits in a data frame is L3, when data is transmitted from the slave chip 203 step by step, when the count value of the slave chip 203 reaches L3, the data is transmitted to the next slave chip 203. When the data frame chain is transmitted, the shift register 204 of each slave chip 203 stores the frame header, control information, and address bits.

[0121] When using frame structure 4, each data frame may include only data bits. The number of bits in the data frame is equal to the number of data bits. Assuming that the number of bits in the data frame is L4, when data is transmitted from the slave chip 203 stage by stage, when the count value of the slave chip 203 reaches L4, the data is transmitted to the slave chip 203 of the next stage. When the data frame chain is transmitted, the shift register 204 of each slave chip 203 stores the data bits, and so on.

[0122] Figure 9 The figure shows the data changes in the shift register 204 of the slave chip 203 in the slave chip chain 202 when the data frame is a write frame. After the transmission of data frame chain 0 is completed, the shift register 204 of slave chip 0_0 stores data frame 00, the shift register 204 of slave chip 0_1 stores data frame 10, ..., the shift register 204 of slave chip 0_N-1 stores data frame (N-1)0, and the shift register 204 of slave chip 0_N stores data frame N0. The master chip 201 then enables all slave chips 203 via a chip select signal. In response to the enable parsing of the master chip 201, each slave chip 203 parses the data frame in its own shift register 204. The slave chip 203 parses the control information of the data frame and confirms that the control information is a write operation. Then, each slave chip 203 writes the data bit into the corresponding second register unit 206 according to the address bit.

[0123] After parsing is complete, master chip 201 sets chip select signal 0 to the first state, indicating that it is currently in the serial input state. Driven by a clock, data frames in data frame chain 1 are transmitted step by step through slave chips 0_N-0_0, simultaneously driving data frame chain 0 to be transmitted step by step through the serially connected slave chips 203. Data frame 01 (including header 01, control information 01, address bit 01, and data bit 01) is transmitted to slave chip 0_N, and data frame 00 is shifted out of slave chip 0_0. Next, data frame 11 (including header 11, control information 11, address bit 11, and data bit 11) is transmitted to slave chip 0_N-1, and data frame 10 is shifted out of slave chip 0_0, and so on. Finally, after data frame chain 1 is transmitted, data frame 01 is stored in the shift register 204 of slave chip 0_0, data frame 11 is stored in the shift register 204 of slave chip 0_1, ..., data frame (N-1)1 is stored in the shift register 204 of slave chip 0_N-1, and data frame N1 is stored in the shift register 204 of slave chip 0_N. At the same time, all data frames in chain 1 are shifted out.

[0124] In some embodiments, Figure 9 The frame structure of the data frame in is not limited to frame structure 1, and can also be any frame structure of frame structures 2 to 7, which will not be repeated here.

[0125] In some embodiments, the data output terminal structure with three-state output is as follows Figure 10 As shown, including:

[0126] Output drive buffer, first control circuit M1 and second control circuit M2, the output drive buffer is connected to power supply VDD through the first control circuit M1, and the output drive buffer is connected to negative power supply VSS through the second control circuit M2;

[0127] Under the control of the control signal EN, the first control circuit M1 and the second control circuit M2 connect or disconnect the output driving buffer with the power supply VDD and the negative power supply VSS, and the output end of the output driving buffer outputs the read-back data.

[0128] It should be noted that in Figure 10 In the tri-state output gate shown, A represents the output data of the final slave chip, Y represents the output signal (readback data), and EN represents the control signal. EN is generated by the final slave chip and is enabled when the final slave chip needs to read back data; it is disabled when the final slave chip does not need to read back data. The first control circuit M1 is specifically a PMOS transistor, and the second control circuit M2 is specifically an NMOS transistor. This design utilizes an output driver buffer with a PMOS and NMOS transistor connected in series, resulting in a tri-state output.

[0129] The third control circuit M3 is connected between the second control circuit M2 and the control signal EN. It inverts the control signal EN and can be an inverter. When the control signal EN is high (disabled), both the PMOS transistor M1 and the NMOS transistor M2 are turned off, disconnecting the output drive buffer from both the power supply voltage VDD and the negative power supply VSS, presenting a high-impedance state and not outputting any signal. When the control signal EN is low (enabled), both the PMOS transistor M1 and the NMOS transistor M2 are turned on, the output drive buffer operates normally, and outputs a logic level (high level 1 or low level 0) based on the data A, thereby outputting the signal Y.

[0130] It can be seen that for the data output terminal SDO with a three-state output function, when the control signal EN is enabled, the data output terminal outputs the readback data to the master chip 201; when the control signal EN is disabled, the data output terminal is in a high-impedance state.

[0131] It should also be noted that Figure 10 The three-state output gate composed of the output driver and the MOS transistor shown is only an example. It can also be formed by a combination of a NAND gate, a NOR gate, and an output driver, or other circuit structures, which is not specifically limited.

[0132] In this way, since the output of the final-stage slave chip 203 is a three-state output, when one final-stage slave chip 203 outputs a high level or a low level, the outputs of the other final-stage slave chips 203 are in a high-impedance state, thereby achieving that only one of the read-back data of multiple final-stage slave chips 203 is output to the master chip 201 at the same time, solving the signal conflict problem.

[0133] In other embodiments, each slave chip chain 202 may correspond to a data readback terminal in the master chip 201, and the last-stage slave chip 203 in each slave chip chain 202 may be connected to the corresponding data readback terminal, so that no interference will be generated. In this case, the last-stage slave chip 203 may not have a three-state output function.

[0134] Furthermore, based on the aforementioned embodiments, this solution also provides more extended embodiments.

[0135] In some embodiments, the chip select signal can also be transmitted in a non-serial manner in the same slave chip chain. Figure 11 As shown, in the slave chip chain i, the chip select signal input terminal SELI of each slave chip 203 is respectively connected to the chip select signal output terminal SELi of the master chip 201 for obtaining the chip select signal from the master chip 201 .

[0136] It should be noted that in Figure 11In the example, the N+1 slave chips 203 in a slave chip chain 202 still reuse the same chip select signal, that is, the slave chip chain i corresponds to the chip select signal SELi. Figure 3 The difference is that the chip select signal is not transmitted step by step in the slave chip chain 202, but the chip select signal input terminal of each slave chip 203 in the slave chip chain i is connected to the chip select signal output terminal SELI of the output chip select signal SELi of the master chip 201. In this case, the slave chip 203 does not need a chip select signal output terminal, only a chip select signal input terminal SELI is required.

[0137] In this way, multiple slave chips 203 in a slave chip chain 202 reuse the same chip select signal, and all obtain the chip select signal from the master chip 201 rather than from the previous level slave chip 203, thereby improving signal accuracy.

[0138] In some embodiments, in the slave chip chain 202 , the clock input terminals CLKI of the slave chips 203 are respectively connected to the clock output terminals CLKO of the master chip 201 for obtaining clocks from the master chip 201 .

[0139] It should be noted that, in addition to the above Figure 3 In addition to the clock transmission method shown, the slave chip 203 can also obtain the clock by connecting the clock input terminal CLKI of each slave chip 203 to the clock output terminal CLK of the master chip 201. Each slave chip 203 obtains the clock directly from the master chip 201, and the clock is no longer transmitted step by step in the slave chip chain 202.

[0140] In some embodiments, the master chip 201 may further include multiple clock output terminals, each clock output terminal CLKi is connected to the clock input terminal CLKI of the first slave chip 203 in the corresponding slave chip chain i, or each clock output terminal CLKi is connected to the clock input terminal CLKI of each slave chip 203 in the corresponding slave chip chain i. When controlling the slave chip 203, a clock is only provided to the slave chip chain 202 that needs to string data in. The slave chip chain 202 that is provided with a clock will transmit data frames serially, and the slave chip chain 202 that is not provided with a clock will not transmit data frames serially.

[0141] In some embodiments, all slave chips 203 may not share the signal output terminal of the master chip 201, but each slave chip chain 202 corresponds to a signal output terminal of the master chip 201, and the signal input terminal SDI of the first slave chip 203 in the slave chip chain i is connected to the corresponding signal output terminal SDIi in the master chip 201, and the required slave chip chain 202 is enabled through the clock and / or chip select signal.

[0142] In some embodiments, the master chip 201 can not only read back data, but also read back the clock of the final slave chip. Figure 12 As shown, the master chip 201 may further include a clock readback terminal CLKO connected to the clock output terminal CLKO of the last-stage slave chip 203 in the slave chip chain 202 to read back the clock of the last-stage slave chip 203;

[0143] The master chip 201 is further configured to obtain a delay between the readback clock and the clock of the master chip 201 . The delay is used to accurately read back the data output by the final-stage slave chip 203 .

[0144] It should be noted that if the number of slave chips 203 in each slave chip chain 202 is equal, and the distance from the data output terminal of the final slave chip 203 in each slave chip chain 202 to the corresponding pin of the master chip 201 (i.e., the data readback terminal) is equal, then the delay of the output data signal of the final slave chip 203 in each slave chip chain 202 relative to the clock output by the master chip 201 can be assumed to be equal. Therefore, the master chip 201 only needs to delay its internal clock to sample the readback data from the slave chip chain 202. Specifically, the delay of the clock and output data signals can be equalized by setting the PCB trace length to be consistent.

[0145] However, if the number of slave chips 203 in each slave chip chain 202 is inconsistent, for example Figure 12 As shown, slave chip chain 0 includes M0+1 slave chips, slave chip chain 1 includes M1+1 slave chips, ..., slave chip chain N includes M N +1 slave chip, including M0, M1, ..., M N are different or partially identical positive integers less than N; or the distances between the data output terminal SDO of the last-stage slave chip 203 in each slave chip chain 202 and the corresponding pins of the master chip 201 vary greatly, then the prediction of the delay of the output data signal of each slave chip chain 202 by the master chip 201 becomes complicated, and each slave chip chain 202 needs to calibrate the delay.

[0146] Therefore, if Figure 12 As shown, the clock output terminal CLKO of the final slave chip 203 in each slave chip chain 202 can also be connected back to the master chip 201. This allows the delay between the clock output terminal CLKO of the final slave chip 203 and the output clock of the master chip 201 to be determined using only the readback clock. The delay of the slave chip chain 202 can be measured first, and the readback data can be interpreted based on the delayed clock to ensure synchronization between the readback data and the clock. For example, if the delay of the slave chip chain 202 is 5ns, the original readback data can be delayed by 5ns and used as the accurate readback data to determine whether the readback data is consistent with the data sent by the master chip 201.

[0147] In some embodiments, it is not limited to that each slave chip chain 202 corresponds to one chip select signal. All slave chip chains 202 can also reuse the same chip select signal. The data frame also carries the address information of the slave chip 203. Different slave chip chains 202 are distinguished by the address information. Figure 13 As shown, the master chip 201 may include only one chip select signal output terminal SEL, and all slave chips 203 reuse the same chip select signal. The chip select signal input terminal SELI of the first-level slave chip 203 in each slave chip chain 202 is connected to the chip select signal output terminal SEL of the master chip 201. The connection within the slave chip chain 202 is the same as the transmission of the chip select signal. Figure 3 .

[0148] It should be noted that in this case, since all slave chip chains 202 reuse the same chip select signal, this means that all slave chip chains 202 are simultaneously selected or unselected. However, in practice, not all slave chips 203 are selected simultaneously. Therefore, the data frame sent by slave chip 201 also carries the address information of slave chip 203. In this way, slave chip 203 first determines the address and parses the data frame only if the address information matches its own address. Otherwise, the data frame is not parsed.

[0149] It should be noted that the frame structure of the data frame carrying address information is as follows Figure 5 The frame structure is shown in 7.

[0150] In some embodiments, the data frame includes at least address information corresponding to the slave chip chain 202. Multiple slave chips 203 in the same slave chip chain 202 have the same address; the addresses of slave chips 203 in different slave chip chains 202 are different to distinguish different slave chip chains.

[0151] Correspondingly, the step of the slave chip 203 parsing the current data frame in the respective shift register 204 includes: determining whether the address information matches its own address, and if so, parsing the data frame.

[0152] It should be noted that if an entire slave chip chain 202 is selected, the address of each slave chip 203 in the slave chip chain 202 is matched. In this case, the slave chips 203 in the same slave chip chain 202 can share the same address. In this way, each address information is matched, which simplifies the complexity of data transmission.

[0153] In some embodiments, the slave chip 203 includes several address pins, and the address of the slave chip 203 is represented by whether the address pins are grounded.

[0154] It should be noted that when multiple slave chips 202 share a chip select signal, the chip address is used to distinguish whether parsing is required. Therefore, the slave chip 203 must verify its own address and address information. After the data frame chain is transmitted, each slave chip's shift register 204 stores the frame structure X and address information. When parsing is required, the slave chip first checks whether the address information in the frame structure matches the chip address. If so, the data frame is parsed and / or operated on. If not, the data frame is not parsed and / or operated on.

[0155] Specifically, the address of each slave chip 203 is confirmed by whether the address pin of the slave chip 203 is grounded. The grounding of the address pin represents 0, and the ungrounded address pin represents 1. For example, if the slave chip 203 has 4 address pins, a 4-bit chip address can be formed. Since there must be a ground around the chip on the PCB, it can be grounded nearby without occupying a lot of PCB wiring resources. In order to save the number of chip address pins, the slave chips 203 on a slave chip chain 202 can share a chip address. The consequence of sharing a chip address is only that all the slave chips 203 on a slave chip chain 202 have to parse the data frame, but the slave chips 203 on a slave chip chain 202 usually need to parse the data frame anyway, and it will not affect the normal operation of the chip array 10. At this time, the chip address is the address of the slave chip chain 202. In this way, the wiring resources of the chip select signal are saved.

[0156] In some embodiments, the present disclosure is not limited to the previous stage slave chip 203 driving one subsequent stage slave chip 203. The previous stage slave chip 203 can also be used to drive multiple subsequent stage slave chips 203. In some embodiments, for example, Figure 14 As shown, the slave chip chain 202 includes a main chain 2021 and multiple branches 2022; wherein the main chain 2021 includes at least one slave chip 203 connected in series, and each branch chain 2022 includes at least one slave chip 203 connected in series, forming a tree-like cascade structure;

[0157] The main chain includes at least the first slave chip 203 in the slave chip chain 202 . In each branch chain 2022 , the data input terminal SDI of the first slave chip 203 is connected to the data output terminal SDO of the last slave chip 203 in the main chain 2021 .

[0158] It should be noted that Figure 14 As shown in the example, the slave chip chain 0 is the slave chip chain 202 (branch 0_0 and branch 0_1) including the main chain 2021 (main chain 0) and the branch chain 2022. The slave chip chain N is the same slave chip chain as the above example, including slave chip N_N, slave chip N_N-1, ..., slave chip N_N-U3, where U3 is a positive integer less than N.

[0159] In slave chip chain 0, main chain 2021 includes only the first slave chip 0_N in slave chip chain 0. Therefore, slave chip 0_N is both the first-level slave chip and the last-level slave chip (i.e., the last slave chip) of main chain 0. Branch chain 0_0 includes slave chips 0_0_N-1, 0_0_N-2, ..., and 0_0_N_U0; branch chain 0_1 includes slave chips 0_1_N-1, 0_1_N-2, ..., and 0_1_N_U1. U0 and U1 are positive integers that are different or partially the same and less than N. If U0 and U1 are the same, then branches 0_0 and 0_1 have the same number of slave chips. If U0 and U1 are different, then branches 0_0 and 0_1 have different numbers of slave chips.

[0160] like Figure 14 As shown, the main chip 201 sends a data frame chain to the main chain 0, and the main chain 0 sends the data frame chain to the branch chain 0_0 and the branch chain 0_1 respectively, and parses them respectively. It can be understood that since each branch chain 2022 receives data from the same main chain 2021, each branch chain 2022 is connected to the same data frame chain.

[0161] This allows some slave chips 203 to drive multiple links (i.e., branches 2022). Whether to parse frame data is determined by whether the chip address in the frame structure matches, shifting the driving pressure from the driver chip (master chip 201) to the slave chip 203. Furthermore, the data of multiple branches 2022 connected to the same master chain 2021 is identical, making control more convenient. The remaining settings, such as data readback and clock readback, are the same as above and will not be further explained here.

[0162] The present disclosure also provides a beam steering array, including:

[0163] As the aforementioned chip array 20;

[0164] In the chip array 20 , the slave chip 203 is a beamforming chip, and the slave chip 203 also includes multiple radio frequency channels;

[0165] The data frame includes multiple data bits, which are used to write data to multiple radio frequency channels and control the phase and / or amplitude of the radio frequency channels.

[0166] It should be noted that the chip array 20 can also be applied to a scenario where any host controls multiple slaves, where the host is equivalent to the master chip 201 and the slave is equivalent to the slave chip 203 .

[0167] The embodiment of the present disclosure further provides a slave chip array, which is composed of all slave chip chains 202 in the aforementioned chip array 20;

[0168] The slave chip chain 202 is configured as follows:

[0169] In the serial input state:

[0170] The receiving master chip 201 outputs a data frame chain, and the data in the data frame chain is transmitted step by step in the slave chip chain 202; wherein the data frame chain includes multiple serial data frames, and the order of the multiple data frames matches the arrangement order of the slave chip 203; after the entire data frame chain is transmitted, the data frame is input into the shift register 204 of the corresponding slave chip 203;

[0171] In non-serial state:

[0172] In response to the master chip 201 enabling parsing, the current data frame in each shift register 204 is parsed.

[0173] The slave chip array may be at least one slave chip chain 202 in any of the above embodiments, for example, Figure 3 、 Figures 11 to 14 The slave chip chain 0 to the slave chip chain N in the embodiment. The configuration of the slave chip chain 202 can adopt the configuration of the slave chip chain 202 in any of the above embodiments, for example, it can be Figures 7 to 10 The configuration of the slave chip chain 202 is not described here in detail.

[0174] The embodiment of the present disclosure further provides a slave chip for implementing step-by-step transmission of data in a data frame chain in a slave chip chain, wherein the slave chip chain includes a plurality of cascaded slave chips, the data frame chain includes a plurality of serial data frames, and the order of the plurality of data frames matches the arrangement order of the slave chips;

[0175] The slave chip is configured as:

[0176] Know the number of bits of the current data frame in advance;

[0177] The data frame chain is received and counted based on the clock. When the count value reaches the number of bits of the corresponding data frame, the data is sent out of the chip one level later.

[0178] The slave chip can be the slave chip 203 in any of the above embodiments. The configuration of the slave chip 203 can adopt the slave chip configuration in any of the above embodiments, for example, it can be Figures 7 to 10 The slave chip configuration in Figure 3 、 Figures 11 to 14 Any one of the slave chip chains 202 will not be described here.

[0179] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0180] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0181] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0182] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0183] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0184] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0185] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A chip array, characterized in that: include: Main chip; At least one slave chip chain, the slave chip chain comprising a plurality of cascaded slave chips, the slave chips comprising shift registers; wherein the data input terminal of the first-stage slave chip is connected to the data output terminal of the master chip, and the data output terminal of the previous-stage slave chip is serially connected to the data input terminal of the next-stage slave chip; In the serial input state: The main chip is configured as follows: Outputting a data frame chain to the slave chip chain; The slave chip chain is configured as follows: The data of the data frame chain is transmitted step by step in the slave chip chain; wherein the data frame chain includes a plurality of serial data frames, and the arrangement order of the plurality of data frames in the data frame chain matches the physical arrangement order of the slave chips; after the entire data frame chain is transmitted, the plurality of data frames are respectively input into the shift register of the corresponding slave chip; In non-serial state: The main chip is configured as follows: enabling all the slave chips to perform unified parsing; The slave chip is configured as follows: In response to the master chip enabling parsing, the current data frame in each of the shift registers is parsed.

2. The chip array according to claim 1, characterized in that Before the data of the data frame chain is transmitted step by step in the slave chip chain, the slave chip chain is further configured as follows: The slave chip obtains in advance the number of bits of the data frame; The data of the data frame chain is transmitted step by step in the slave chip chain, including: The slave chip counts based on the clock, and when the count value reaches the number of bits corresponding to the data frame, the data is transmitted to the slave chip of the next level; The number of bits of the data frame is variable, and the count value is adapted to the number of bits of the data frame.

3. The chip array according to claim 2, characterized in that The data frame includes frame length information, which is used to indicate the number of bits of the data frame in the next data frame chain; The slave chip includes a first register unit for storing the frame length information.

4. The chip array according to claim 2, characterized in that The variable number of bits of the data frame includes: the variable frame structure of the data frame.

5. The chip array according to claim 2, characterized in that The shift register includes an input shift register and an output shift register, wherein the input shift register is used to input data from the data input terminal of the slave chip, and the output shift register is used to output data to the data output terminal of the slave chip; The slave chip is configured to copy the data of the input shift register to the output shift register when the count value reaches the corresponding number of bits of the data frame.

6. The chip array according to claim 1, characterized in that The number of bits of the data frame remains unchanged, and the number of bits of the shift register is equal to the number of bits of the data frame; The data of the data frame chain is transmitted stage by stage in the slave chip chain, including: the shift register receives the data frame in series, and after the shift register is full, the data frame is transmitted bit by bit.

7. The chip array according to claim 1, characterized in that The main chip also includes: A data read-back terminal connected to the data output terminal of the slave chip at the final stage; A clock readback terminal connected to the clock output terminal of the slave chip at the final stage; The master chip is further configured to obtain a delay between a readback clock and the master chip clock, wherein the delay is used to accurately read back data from the final-stage slave chip.

8. The chip array according to claim 7, characterized in that Different slave chip chains share the data read-back terminal; At least the data output terminal of the slave chip at the final stage is a three-state output, and the three-state output includes three states: a logic high level, a logic low level, and a high impedance state; The main chip is configured as follows: Enable the data output of the final slave chip that needs to be read back; The final slave chip is configured as follows: In response to enabling readback, the data output terminal outputs the logic high level or the logic low level; wherein the data output terminal that is not enabled enters the high impedance state.

9. The chip array according to claim 1, characterized in that The master chip further includes at least one chip select signal output terminal for outputting a chip select signal; the slave chip further includes a chip select signal input terminal; The chip select signal input terminals of the slave chips are respectively connected to the chip select signal output terminals of the master chip; Alternatively, the slave chip further includes a chip select signal output terminal; the chip select signal input terminal of the first-stage slave chip is connected to the chip select signal output terminal of the master chip, and the chip select signal input terminal of the subsequent-stage slave chip is connected to the chip select signal output terminal of the previous-stage slave chip, and the chip select signal is transmitted stage by stage in the slave chip chain; Outputting the data frame chain to the slave chip chain includes: Controlling the chip select signal to a first state; The step of enabling all the slave chips to perform unified parsing includes: The chip select signal is controlled to be in a second state.

10. The chip array according to claim 1, characterized in that The master chip further includes a clock output terminal for outputting a clock; the slave chip further includes a clock input terminal; The clock input terminals of the slave chips are respectively connected to the clock output terminals of the master chip; Alternatively, the slave chip further includes a clock output terminal; the clock input terminal of the first-stage slave chip is connected to the clock output terminal of the master chip, and the clock input terminal of the subsequent-stage slave chip is connected to the clock output terminal of the previous-stage slave chip, and the clock is transmitted step by step in the slave chip chain; The step of outputting a data frame chain to the slave chip chain includes: The clock is provided to the slave chip chain that needs to serially input data.

11. The chip array according to claim 1, characterized in that: The slave chip chain includes a main chain and multiple branches; wherein the main chain includes at least one slave chip connected in series, and each branch chain includes at least one slave chip connected in series; The main chain at least includes the first slave chip in the slave chip chain, and in each branch chain, the data input end of the first slave chip is connected to the data output end of the last slave chip in the main chain.

12. The chip array according to claim 1, characterized in that The data frame includes at least the address information of the corresponding slave chip; or the data frame includes at least the address information of the corresponding slave chip chain, and the multiple slave chips in the same slave chip chain have the same address; The step of parsing the current data frame in each of the shift registers includes: Determine whether the address information matches its own address; if so, parse the data frame.

13. The chip array according to claim 12, characterized in that: The slave chip includes a plurality of address pins, and the address of the slave chip is represented by whether the address pins are grounded.

14. The chip array according to any one of claims 1 to 13, characterized in that: The chip array is connected via an SPI interface.

15. A beam steering array, characterized in that: include: The chip array according to any one of claims 1 to 14; In the chip array, the slave chip is a beamforming chip, and the slave chip further includes a plurality of radio frequency channels; The data frame includes a plurality of data bits, which are used to write data to the plurality of radio frequency channels and control the phase and / or amplitude of the radio frequency channels.

16. The beam steering array according to claim 15, wherein: The slave chip includes a plurality of second register units for storing a plurality of the data bits from the shift register.

17. A slave chip array, characterized in that: include: At least one slave chip chain, the slave chip chain comprising a plurality of cascaded slave chips, the slave chips comprising shift registers; wherein the data input terminal of the first-stage slave chip is connected to the data output terminal of the master chip, and the data output terminal of the previous-stage slave chip is serially connected to the data input terminal of the next-stage slave chip; The slave chip chain is configured as follows: In the serial input state: Receive a data frame chain output by the master chip, wherein the data of the data frame chain is transmitted step by step in the slave chip chain; wherein the data frame chain includes a plurality of serial data frames, and the arrangement order of the plurality of data frames in the data frame chain matches the physical arrangement order of the slave chips; after the entire data frame chain is transmitted, the plurality of data frames are respectively input into the shift register of the corresponding slave chip; In non-serial state: In response to the master chip enabling parsing, the current data frame in each of the shift registers is parsed.

18. The slave chip array according to claim 17, characterized in that: Before the data of the data frame chain is transmitted step by step in the slave chip chain, the slave chip chain is further configured as follows: The slave chip obtains in advance the number of bits of the data frame; The data of the data frame chain is transmitted step by step in the slave chip chain, including: The slave chip counts based on the clock, and when the count value reaches the number of bits corresponding to the data frame, the data is transmitted to the slave chip of the next level; The number of bits of the data frame is variable, and the count value is adapted to the number of bits of the data frame.

19. The slave chip array according to claim 18, characterized in that: The data frame includes frame length information, which is used to indicate the number of bits of the data frame in the next data frame chain; The slave chip includes a first register unit for storing the frame length information.

20. The slave chip array according to claim 18, characterized in that: The variable number of bits of the data frame includes: the variable frame structure of the data frame.

21. The slave chip array according to claim 18, characterized in that: The shift register includes an input shift register and an output shift register, wherein the input shift register is used to input data from the data input terminal of the slave chip, and the output shift register is used to output data to the data output terminal of the slave chip; The slave chip is configured to copy the data of the input shift register to the output shift register when the count value reaches the corresponding number of bits of the data frame.

22. The slave chip array according to claim 17, characterized in that: The number of bits of the data frame remains unchanged, and the number of bits of the shift register is equal to the number of bits of the data frame; The data of the data frame chain is transmitted stage by stage in the slave chip chain, including: the shift register receives the data frame in series, and after the shift register is full, the data frame is transmitted bit by bit.

23. A slave chip, characterized in that: Used to implement step-by-step transmission of data in a data frame chain in a slave chip chain, wherein the slave chip chain includes a plurality of cascaded slave chips, the data frame chain includes a plurality of serial data frames, and the arrangement order of the plurality of data frames in the data frame chain matches the physical arrangement order of the slave chips; The slave chip is configured as: Knowing in advance the number of bits of the current data frame; The data frame chain is received, counted based on a clock, and when the count value reaches the number of bits corresponding to the data frame, the data is serially output from the chip of the next level.

24. The slave chip according to claim 23, characterized in that: The data frame includes frame length information, which is used to indicate the number of bits of the data frame in the next data frame chain; The slave chip includes a first register unit for storing the frame length information.

25. The slave chip according to claim 23, characterized in that: The variable number of bits of the data frame includes: the variable frame structure of the data frame.

26. The slave chip according to claim 23, characterized in that The slave chip includes a shift register, and the shift register includes an input shift register and an output shift register. The input shift register is used to input data from the data input terminal of the slave chip, and the output shift register is used to output data to the data output terminal of the slave chip. The slave chip is configured to copy the data of the input shift register to the output shift register when the count value reaches the corresponding number of bits of the data frame.

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