Display device and driving method thereof

Abstract

Aspects relate to a display device and a method of driving the same. The display device includes a display panel having pixels disposed thereon, a timing controller configured to output image data and emit a driving control signal based on an image signal and a control signal from an external component, a gate driver configured to apply a gate signal to the pixels, a data driver configured to apply a data voltage corresponding to the image data to the pixel, an emission driver configured to apply an emission signal to the pixel based on an emission driving control signal, and an emission signal voltage controller configured to change a voltage of the emission signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0186613, filed on December 20, 2023, the entire contents of which are incorporated herein by reference for all purposes. Technical field

[0003] The present disclosure relates to a display device and a driving method thereof. Background art

[0004] With the development of the information society, various demands for display devices for displaying images are increasing, and various types of display devices such as liquid crystal display (LCD) devices and organic light - emitting diode (OLED) display devices are utilized.

[0005] An image displayed on a display device may be a still image or a non - still (moving) image, and the non - still image may include various types such as a motion image, a game image, and a movie. The display device is driven in a variable refresh rate (VRR) mode, in which the driving frequency changes according to the type of the image, thereby reducing power consumption and extending the lifespan of the display device. Summary of the invention

[0006] Accordingly, the present disclosure relates to a display device and a driving method thereof that substantially achieve the above.

[0007] More specifically, a display device and a driving method thereof are provided for changing the voltage of a transmission signal based on the luminance difference between adjacent frames during low - speed driving.

[0008] The present disclosure also provides a display device and a method for driving the display device, the display device being configured to control a gate high voltage to a lower voltage when the luminance difference between adjacent frames is greater than or equal to a predetermined critical value.

[0009] Additional features and advantages of the present disclosure will be set forth in the following description, and in part will be obvious from the description, or may be learned by practice of the present disclosure. Other advantages of the present disclosure will be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0010] To achieve these and other advantages, and in accordance with the present disclosure, as embodied and broadly described, a display device includes: a display panel where pixels are disposed; a timing controller configured to output image data and emission drive control signals based on an image signal and a control signal from an external component; a gate driver configured to apply a gate signal to the pixels; a data driver configured to apply a data voltage corresponding to the image data to the pixels; an emission driver configured to apply an emission signal to the pixels based on the emission drive control signal; and an emission signal voltage controller configured to change a voltage of the emission signal.

[0011] The emission signal may be a square wave signal including a gate high voltage period and a gate low voltage period, and the emission signal voltage controller may change the gate high voltage based on a luminance difference of the image data between adjacent frames.

[0012] The emission signal voltage controller may set the gate high voltage to a first gate high voltage when the luminance difference between the adjacent frames is less than a critical value, and set the gate high voltage to a second gate high voltage less than the first gate high voltage when the luminance difference between the adjacent frames is greater than the critical value.

[0013] The display panel may be driven by a combination of a refresh frame and one or more skip frames, in the refresh frame, the data voltage is programmed to the pixels, and in the one or more skip frames, programming of the data voltage is omitted.

[0014] The adjacent frames may include the refresh frame.

[0015] When the luminance difference between the adjacent frames is greater than the critical value, the gate high voltage may be set to the second gate high voltage during the refresh frame, and the gate high voltage may be set to the first gate high voltage during the one or more skip frames after the refresh frame.

[0016] The emission signal voltage controller may include: an information collector configured to measure a first frame response time during low-frequency driving, determine the first gate high voltage in response to the first frame response time, and determine the second gate high voltage to allow the luminance difference between the adjacent frames to be less than the critical value; an image analyzer configured to obtain the image data on a frame-by-frame basis when driving the display panel at the low frequency, and determine the luminance difference of the image data between the adjacent frames; and a voltage selector configured to select the first gate high voltage as the gate high voltage when the luminance difference is less than the critical value, and select the second gate high voltage as the gate high voltage when the luminance difference is greater than or equal to the critical value.

[0017] The emission driver may include: a level shifter configured to generate a clock signal having a level between the gate high voltage and the gate low voltage; and a shift register configured to output the emission signal based on the clock signal output from the level shifter.

[0018] The pixel may include: a light-emitting element configured to emit light having a luminance corresponding to a driving current; a driving transistor configured to control the driving current flowing through the light-emitting element; a first transistor configured to apply the data voltage to a second electrode of the driving transistor in response to a second scan signal; a second transistor configured to connect a gate electrode of the driving transistor to a first electrode of the driving transistor in response to a first scan signal; a storage capacitor connected between the gate electrode of the driving transistor and an anode electrode of the light-emitting element; a third transistor configured to form a current path between a high-potential driving voltage and the first electrode of the driving transistor in response to a second emission signal; and a fourth transistor configured to form a current path between the driving transistor and the light-emitting element in response to a first emission signal.

[0019] As the gate high voltages of the first emission signal and the second emission signal are changed, the driving current may be controlled.

[0020] The pixel may further include a fifth transistor configured to apply an initialization voltage to the anode electrode of the light-emitting element in response to the first scan signal.

[0021] A method of driving a display device according to an aspect, the display device including a display panel and an emission driver, pixels being disposed at the display panel, the emission driver being configured to apply an emission signal to the pixels, the method may include: driving the display panel in a skipped frame, during which the emission driver applies the emission signal having a first gate high voltage to the pixels during a low-frequency driving period; and driving the display panel in a refresh frame, during which the emission driver applies the emission signal having a second gate high voltage different from the first gate high voltage to the pixels after the skipped frame.

[0022] During the refresh frame, a data voltage corresponding to image data may be programmed into the pixels, and during the skipped frame, programming of the data voltage may be omitted.

[0023] The second gate high voltage may be determined based on a luminance difference between adjacent frames.

[0024] The second gate high voltage may be less than the first gate high voltage.

[0025] The first gate high voltage may be determined according to a first frame response time during the low-frequency driving period. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a block diagram showing a configuration of a display device according to an aspect.

[0027] Figure 2 is a view showing a method of driving a display device according to an aspect.

[0028] Figure 3 is a view showing a luminance change of a pixel according to an aspect.

[0029] Figure 4 is a circuit diagram of a pixel according to an aspect.

[0030] Figure 5 is a block diagram showing a configuration of an emission driver according to an aspect.

[0031] Figure 6 is a block diagram showing a configuration of an emission signal voltage controller according to an aspect.

[0032] Figure 7 is a timing diagram showing a method of driving a pixel according to an aspect.

[0033] Figure 8 is a view showing a first aspect of a luminance change of a pixel according to emission signal voltage control.

[0034] Figure 9 It is a view showing a second aspect of the brightness change of a pixel controlled according to the emission signal voltage.

[0035] Figure 10 It is a view showing a third aspect of the brightness change of a pixel controlled according to the emission signal voltage.

[0036] Figure 11 It is a view showing a fourth aspect of the brightness change of a pixel controlled according to the emission signal voltage. Detailed Description

[0037] Hereinafter, aspects will be described with reference to the accompanying drawings. In the specification, when a first component (or region, layer, part, etc.) is described as "on", "connected" or "coupled to" a second component, this means that the first component can be directly connected / coupled to the second component, or a third component can be provided between them.

[0038] The same reference numerals denote the same components. In addition, for effective description of the technical content, the thickness, ratio, and size of the components are exaggerated in the drawings. The term "and / or" includes all one or more combinations that can be defined by the associated configuration.

[0039] Terms such as first and second can be used to describe various components, but the components are not limited by these terms. The terms are only used to distinguish one component from another. For example, without departing from the scope of the aspect, the first component can be referred to as the second component, and similarly, the second component can also be referred to as the first component. Unless the context clearly dictates otherwise, the singular form includes the plural form.

[0040] Terms such as "beneath", "underneath", "above", and "on top" are used to describe the relationship between the components shown in the drawings. The terms are relative concepts and are described with respect to the direction marked in the drawings.

[0041] It should be understood that terms such as "including" or "having" are intended to specify the presence of the features, quantities, steps, operations, components, parts, or combinations thereof described in the specification, and do not exclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, or combinations thereof.

[0042] Figure 1 It is a block diagram showing the configuration of a display device according to one aspect.

[0043] Reference Figure 1 , the display device 1 includes a timing controller 10, a gate driver 20, a data driver 30, an emission driver 40, a power supply unit 50, and a display panel 60.

[0044] The timing controller 10 may receive an image signal RGB and a control signal CS from an external host system or the like. The image signal RGB may include a plurality of grayscale data. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, a main clock signal, etc. The timing controller 10 may process the image signal RGB and the control signal CS according to the operating conditions of the display panel 60, and generate and output image data DATA, a gate driving control signal CONT1, a data driving control signal CONT2, an emission driving control signal CONT3, and a power control signal CONT4.

[0045] The gate driver 20 may generate a scan signal based on the gate driving control signal CONT1 output from the timing controller 10. The gate driver 20 may provide the generated scan signal to the pixels PX through a plurality of gate lines GL1 and GL2.

[0046] The data driver 30 may generate a data signal based on the image data DATA and the data driving control signal CONT2 output from the timing controller 10. The data driver 30 may provide the generated data signal to the pixels PX through a plurality of data lines DL.

[0047] The emission driver 40 may generate an emission signal based on the emission driving control signal CONT3 output from the timing controller 10. The emission driver 40 may provide the generated emission signal to the pixels PX through a plurality of emission lines EL1 and EL2.

[0048] The power supply unit 50 may generate a high-potential driving voltage VDD and a low-potential driving voltage VSS to be provided to the display panel 60 based on the power control signal CONT4. The power supply unit 50 may provide the generated driving voltages VDD and VSS to the pixels PX through corresponding power lines PL1 and PL2.

[0049] A plurality of pixels PX (or referred to as sub-pixels) are provided at the display panel 60. The pixel PX may be charged with a data voltage provided through the data line DL in response to a scan signal applied through the gate lines GL1 and GL2, and emit light having a luminance corresponding to the charged data voltage in response to an emission signal applied through the emission lines EL1 and EL2.

[0050] In one aspect, each pixel PX may display one of red, green, and blue. In another aspect, each pixel PX may display one of cyan, magenta, and yellow. In various aspects, each pixel PX may display one of red, green, blue, and white.

[0051] The timing controller 10, the gate driver 20, the data driver 30, the emission driver 40, and the power supply unit 50 may each be configured as a separate integrated circuit (IC) or at least partially integrated ICs. In addition, the gate driver 20 and the emission driver 40 may be configured in a gate type in a panel integrally formed with the display panel 60. In this aspect, the gate driver 20 and the emission driver 40 may constitute a gate-in-panel (hereinafter referred to as "GIP") type.

[0052] The display device 1 according to one aspect may further include an emission signal voltage controller 70. The emission signal voltage controller 70 may be included in the timing controller 10 as shown, or mounted in the same module as the power supply unit 50. However, this aspect is not limited thereto. That is, the emission signal voltage controller 70 may be provided as a separate component.

[0053] The emission signal voltage controller 70 may change the voltage of the emission signal output from the emission driver 40. For example, the emission signal voltage controller 70 may change the voltage of the emission signal by adjusting the driving voltage supplied to the emission driver 40, particularly the amplitude of the gate high voltage, based on the brightness change between adjacent frames. A more detailed operation of the emission signal voltage controller 70 will be described below.

[0054] In one aspect, the display device 1 may be driven in a variable refresh rate mode, in which the driving frequency may be changed. For example, the display device 1 may be driven at a refresh rate higher or lower than a predetermined reference refresh rate. When the display device 1 is driven at a rate lower than the reference refresh rate, it may be referred to as "low-speed driving" or "low-frequency driving", while when the display device 1 is driven at a rate higher than the reference refresh rate, it may be referred to as "high-speed driving" or "high-frequency driving". The refresh rate may be determined according to the type of image to be displayed, etc., but is not limited thereto.

[0055] The timing controller 10 may generate control signals CONT1 to CONT4 such that the pixels PX can be driven at various refresh rates. For example, the timing controller 10 may change the refresh rate by changing the frequency of the clock signals included in the control signals CONT1 to CONT4, adjusting the timing of the horizontal synchronization signal or the vertical synchronization signal, or driving the gate driver 20 in a mask manner.

[0056] Figure 2 is a view showing a method of driving a display device according to one aspect.

[0057] In the variable refresh rate mode, the display panel 60 may be driven in a combination of at least one refresh frame RP and at least one skip frame SP (see Figure 1) During the refresh frame RP, new image data can be provided to the display panel 60 such that each pixel PX (see Figure 1 ) can be programmed with a new data voltage, and the light-emitting element of the pixel PX can emit light in response to the programmed data voltage. The refresh frame RP can be subdivided into an initialization period, a sampling and programming period, a holding period, etc. for data voltage programming.

[0058] The process of programming a new data voltage into the pixel PX during the skip frame SP is omitted. During the skip period SP, the light-emitting element of each pixel PX can emit light in response to the data voltage programmed during the previous refresh period RP. The skip frame SP can be referred to as a holding frame.

[0059] In one aspect, in order to change the refresh rate, the length of a frame can be changed by adjusting the number or length of the skip periods SP. Then, the length of the refresh frame RP can be ensured sufficiently so that the data voltage can be programmed stably.

[0060] In this aspect, the generation period of the refresh period RP can be changed according to the variable refresh rate. The generation period of the refresh period RP increases as the refresh rate decreases, and the number of skip periods SP between the refresh periods RP increases as the refresh rate decreases.

[0061] For example, the generation period of the refresh period RP can be 1 / 120 second at 120 Hz, 1 / 60 second at 60 Hz, 1 / 24 second at 24 Hz, and 1 second at 1 Hz. The number of skip periods SP located between two adjacent refresh periods RP can be 0 at 120 Hz, 1 at 60 Hz, 4 at 24 Hz, 9 at 1 Hz, and Figure 2 The example of 24 Hz is shown in. However, this aspect is not limited thereto.

[0062] The refresh period RP includes a programming period PP and an emission period EP. During the programming period PP, a new data voltage is programmed into the pixel circuit PX, and during the emission period EP, the pixel PX emits light in response to the programmed data voltage.

[0063] The skip period SP only includes the emission period EP in which the emission signal EM (see Figure 1 ) has a conductive level. During the emission period EP, the pixel PX maintains the emission luminance of the previous refresh period RP.

[0064] Figure 3 is a view showing the luminance change of a pixel according to one aspect.

[0065] Referring together to Figure 2 and Figure 3, in one aspect, when programming the data voltage during the refresh frame RP after the skipped frame SP, a temporary potential difference may occur between the source electrode and the drain electrode of the driving transistor in the pixel PX (see Figure 1 ). Therefore, when the emission signal EM (see Figure 1 ) is turned on, the brightness of the pixel PX can increase rapidly as shown.

[0066] When the brightness of the pixel PX gradually decreases during the skipped frame SP due to leakage current in the pixel PX or the like, or when the brightness of the image data DATA (see Figure 1 ) displayed during the refresh frame RP after the skipped frame SP is higher than the brightness displayed during the skipped frame SP by a predetermined level, this phenomenon becomes more serious.

[0067] Depending on the response time of the pixel PX etc., the portion where this rapid increase in brightness occurs can be about 1 second, and as described above, the rapid increase in brightness within a relatively short time may be visible flicker to the user, resulting in deterioration of the image quality of the display device 1 (see Figure 1 ). Hereinafter, aspects for preventing such a flicker phenomenon will be described.

[0068] Figure 4 is a circuit diagram of a pixel according to one aspect.

[0069] Referring to Figure 4 , according to one aspect, the pixel PX may include a driving transistor DT, a light-emitting element LD connected to the driving transistor DT, and a control circuit for controlling the amount of driving current applied to the light-emitting element LD through the driving transistor DT. For example, the control circuit may include first to fifth transistors T1 to T5 and a storage capacitor Cst.

[0070] The driving transistor DT controls the driving current applied to the light-emitting element LD according to the gate-source voltage Vgs. The first electrode (e.g., source electrode) of the driving transistor DT is connected to the first power line PL1 to which a high-potential driving voltage VDD is applied through the first node N1, and its second electrode (e.g., drain electrode) is connected to the light-emitting element LD through the second node N2. The gate electrode of the driving transistor DT is connected to the third node N3. The driving transistor DT can be turned on according to the voltage applied to the third node N3 to control the amount of driving current flowing to the light-emitting element LD.

[0071] The first transistor T1 is connected between the data line DL and the second node N2. The gate electrode of the first transistor T1 is connected to the gate line GL2. The first transistor T1 can be turned on in response to a second scan signal Scan2 applied to the second gate line GL2. When the first transistor T1 is turned on, the data voltage Vdata applied to the data line DL can be applied to the second node N2, i.e., the second electrode of the driving transistor DT.

[0072] The second transistor T2 is connected between the gate electrode (i.e., the third node N3) and the first electrode (i.e., the first node N1) of the driving transistor DT. The gate electrode of the second transistor T2 is connected to the first gate line GL1. The second transistor T2 can be turned on in response to a first scan signal Scan1 applied to the first gate line GL1 to electrically connect the gate electrode of the driving transistor DT to the first electrode.

[0073] The storage capacitor Cst is connected between the third node N3 (i.e., the gate electrode of the driving transistor DT) and the fourth node N4 (i.e., the anode electrode of the light-emitting element LD). The storage capacitor Cst can be used to sample the threshold voltage of the driving transistor DT according to the source follower method.

[0074] The third transistor T3 is connected between the first power supply line PL1 to which a high-potential driving voltage VDD is applied and the driving transistor DT (i.e., the first node N1). The gate electrode of the third transistor T3 is connected to the second emission line EL2. The third transistor T3 can be turned on in response to an emission signal EM2 applied to the second emission line EL2. The second emission signal EM2 can be a predetermined square wave signal including a gate high voltage period and a gate low voltage period.

[0075] The fourth transistor T4 is connected between the driving transistor DT (i.e., the second node N2) and the light-emitting element LD. The gate electrode of the fourth transistor T4 is connected to the first emission line EL1. The fourth transistor T4 can be turned on in response to a first emission signal EM1 applied to the first emission line EL1. The first emission signal EM1 can be a predetermined square wave signal including a gate high voltage period and a gate low voltage period.

[0076] When the third transistor T3 and the fourth transistor T4 are turned on, a current path from the high-potential driving voltage VDD to the light-emitting element LD can be formed to allow a driving current to flow to the light-emitting element LD. The light-emitting element LD can emit light having a brightness corresponding to the amount of the applied driving current.

[0077] The fifth transistor T5 is connected between an initialization voltage line ViniL to which an initialization voltage Vini is applied and a fourth node N4 (i.e., the anode electrode of the light-emitting element LD). The gate electrode of the fifth transistor T5 is connected to the first gate line GL1. The fifth transistor T5 can be turned on in response to a first scan signal Scan1 applied to the first gate line GL1. When the fifth transistor T5 is turned on, the initialization voltage Vini can be applied to the anode electrode of the light-emitting element LD. The fifth transistor T5 is provided to initialize the anode electrode of the light-emitting element LD.

[0078] The light-emitting element LD may have an anode electrode connected to the fourth node N4 and a cathode electrode connected to a second power supply line PL2 to which a low-potential driving voltage VSS is applied. When the driving transistor DT and the third and fourth transistors T3 and T4 are turned on, a current path can be formed between the high-potential driving voltage VDD and the low-potential driving voltage VSS to allow a driving current to flow to the light-emitting element LD. The light-emitting element LD can emit light having a brightness corresponding to the amount of the applied driving current.

[0079] In Figure 4 the aspect shown, the transistors of the pixel PX may be formed of oxide semiconductor thin-film transistors. The oxide semiconductor thin-film transistor includes a gate electrode, a source electrode, and a drain electrode. The oxide semiconductor thin-film transistor has an active layer formed of an oxide semiconductor. Here, the oxide semiconductor may be set as an amorphous or crystalline oxide semiconductor. The oxide semiconductor thin-film transistor may be formed of an n-type transistor. The oxide semiconductor thin-film transistor can be processed at a low temperature and has a lower charge mobility than a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The oxide semiconductor thin-film transistor has excellent off-current characteristics.

[0080] However, this aspect is not limited thereto. That is, in another aspect, one or more transistors of the pixel PX may be p-type transistors or LTPS thin-film transistors. The LTPS thin-film transistor includes a gate electrode, a source electrode, and a drain electrode. The LTPS thin-film transistor has an active layer made of polycrystalline silicon. The LTPS thin-film transistor has a high electron mobility and thus has fast driving characteristics. The LTPS thin-film transistor may be formed of a p-type thin-film transistor or an n-type thin-film transistor.

[0081] Figure 5 is a block diagram showing a configuration of an emission driver according to one aspect.

[0082] Referring Figure 5 , the emission driver 40 may include a level shifter 41 and a shift register 42.

[0083] The level shifter 41 can generate a clock signal Clk, a start signal Vst, etc. based on the emission drive control signal CONT3 provided by the timing controller 10 and the drive voltage provided by the power supply unit 50. The drive voltage can include a gate high voltage VEH and a gate low voltage VEL. The level shifter 41 can generate a clock signal Clk having a voltage level between the gate high voltage VEH and the gate low voltage VEL. The clock signal Clk can be generated in the form of n phases with different phases, and n phases are such as 2 phases, 4 phases, and 8 phases (n is an integer greater than or equal to 2).

[0084] The shift register 42 can output emission signals EM1 and EM2 based on the signals Clk and Vst output from the level shifter 41, and the emission signals EM1 and EM2 can turn on or off the transistors formed on the display panel 60. The output emission signals EM1 and EM2 can be a predetermined square wave signal including a gate high voltage VEH period and a gate low voltage VEL period.

[0085] In one aspect, the drive voltage, particularly the gate high voltage VEH applied to the level shifter 41, can be changed. For example, the gate high voltage VEH can be changed by the emission signal voltage controller 70 according to the brightness difference between adjacent frames.

[0086] Figure 6 It is a block diagram showing the configuration of the emission signal voltage controller according to one aspect.

[0087] As referred to Figure 5 As described above, the emission signal voltage controller 70 is configured to change the drive voltage, particularly the gate high voltage VEH applied to the emission driver 40. For example, the emission signal voltage controller 70 can change the gate high voltage VEH according to the brightness change of the image data DATA between adjacent frames during low-frequency driving. To this end, the emission signal voltage controller 70 can include an information collector 71, an image determiner 72, and a voltage selector 73.

[0088] The information collector 71 can measure the first frame response (FFR) during low-frequency driving. When the brightness changes between adjacent frames, the amount by which the response time of the first frame starting to display the input image can change is the time required for the hysteresis characteristic of the drive transistor DT (see Figure 4 ) to change. During low-frequency driving, in the refresh frame RP after the skipped frame SP in which the brightness changes significantly between adjacent frames, the response time can increase.

[0089] The information collector 71 may determine a first gate high voltage Vori of the emission signals EM1 and EM2 optimized according to the first frame response time. That is, the first gate high voltage Vori may bias the first electrode and the gate of the driving transistor DT to a predetermined voltage before the threshold voltage of the driving transistor DT is sampled to be determined as a predetermined level, so as to minimize the first frame response time.

[0090] In addition, the information collector 71 may measure a second gate high voltage Vadj of the emission signals EM1 and EM2, which makes the luminance difference of the pixel PX between adjacent frames less than a predetermined critical value.

[0091] As described above, when the luminance of the image data DATA (see Figure 1 ) changes significantly between adjacent frames, the luminance of the light-emitting element LD (see Figure 4 ) that emits light corresponding to the image data may change significantly. In this case, the luminance change of the light-emitting element LD can be reduced by controlling the amplitude of the driving current applied to the light-emitting element LD. The amplitude of the driving current can be adjusted in response to the voltages of the gate electrodes of the third transistor T3 and the fourth transistor T4 (see Figure 4 ), that is, the gate high voltage VEH of the emission signals EM1 and EM2. More specifically, as the voltages of the gate electrodes of the third transistor T3 and the fourth transistor T4 (see Figure 4 ) decrease, the amplitude of the driving current applied to the light-emitting element LD may decrease, thereby limiting the luminance of the light-emitting element LD.

[0092] Therefore, the information collector 71 may measure the second gate high voltage Vadj of the emission signals EM1 and EM2, which can control the luminance change of the light-emitting element within a predetermined critical range, although the luminance change is rapid. The second gate high voltage Vadj can be determined in response to the luminance difference between adjacent frames. In addition, the second gate high voltage Vadj may be less than the first gate high voltage Vori. Therefore, the greater the luminance difference between adjacent frames, the smaller the second gate high voltage Vadj can be set.

[0093] The image determiner 72 may determine whether the display panel 60 is being driven at a low frequency. When the display panel 60 is driven at a low frequency, the image determiner 72 may acquire, on a frame-by-frame basis, the image data DATA to be displayed on the display panel 60 and determine the luminance difference of the image data DATA between adjacent frames. Here, the adjacent frames may be the current frame and the next frame, or may be the frame after a predetermined time point and the frame after the above-mentioned frame. That is, the image determiner 72 is configured to pre-analyze the luminance of the image data DATA to be displayed on the display panel 60.

[0094] The image determiner 72 can determine whether the luminance difference between adjacent frames is greater than or equal to a predetermined threshold value. More specifically, the image determiner 72 can determine whether the luminance between adjacent frames increases to the threshold value or more. For example, such an increase in luminance can occur when changing from black grayscale to white grayscale, when changing from low grayscale to low grayscale, when changing from low grayscale to high grayscale, or when changing from high grayscale to high grayscale.

[0095] Such an increase in luminance during low-frequency driving can occur in the refresh frame RP after the skipped frame SP. Although the skipped frames SP are consecutive, such an increase in luminance generally does not occur. Thus, the adjacent frames can include the refresh frame RP.

[0096] The voltage selector 73 can select the gate high voltage VEH of the emission signal EM based on the determination result of the image determiner 72. More specifically, when the luminance between adjacent frames increases, remains the same, or decreases to less than the threshold value, the voltage selector 73 selects the first gate high voltage Vori as the gate high voltage VEH. For example, during the skipped frame SP in which the luminance between adjacent frames does not change rapidly during low-frequency driving, the voltage selector 73 can select the first gate high voltage Vori as the gate high voltage VEH.

[0097] Conversely, when the luminance between adjacent frames increases to the threshold value or more, the voltage selector 73 selects the second gate high voltage Vadj as the gate high voltage VEH. For example, during the refresh frame RP in which the luminance between adjacent frames changes rapidly during low-frequency driving, the voltage selector 73 can select the second gate high voltage Vadj as the gate high voltage VEH.

[0098] The voltage selector 73 can send control information to the power supply unit 50 (see Figure 1 ) and / or the emission driver 40 to output the emission signals EM1 and EM2 according to the selected gate high voltage VEH.

[0099] Figure 7 is a timing diagram showing a method of driving pixels according to one aspect.

[0100] In the variable refresh rate mode, one frame can be configured as a combination of at least one refresh frame RP and at least one skipped frame SP.

[0101] The refresh period RP can include an initialization period t1, a sampling and programming period t2, a holding period t3, and an emission period t4.

[0102] During an initialization period t1, a first scan signal Scan1 at a conductive level is applied to turn on a second transistor T2 and a fifth transistor T5. Further, during the initialization period t1, a second emission signal EM2 at a conductive level is applied to turn on a third transistor T3. Accordingly, an initialization voltage Vini can be applied to a fourth node N4, and a high-potential driving voltage VDD can be applied to a first node N1.

[0103] During the initialization period t1, an anode electrode of a light-emitting element LD can be initialized to the initialization voltage Vini in response to a voltage at the fourth node N4, and a gate electrode and a first electrode of a driving transistor DT can be set to the high-potential driving voltage VDD in response to a voltage at the first node N1. Further, during the initialization period t1, a storage capacitor Cst can store a voltage corresponding to a difference between the high-potential driving voltage VDD and the initialization voltage Vini.

[0104] During a sampling and programming period t2, a first scan signal Scan1 and a second scan signal Scan2 at a conductive level are applied to turn on a first transistor T1, a second transistor t2, and a fifth transistor T5. Further, during the sampling and programming period t2, a data voltage Vdata corresponding to image data DATA (see Figure 1 ) of a corresponding frame is applied to a data line DL. Accordingly, the data voltage Vdata applied to the data line DL can be applied to a second node N2, and the initialization voltage Vini can be applied to the fourth node N4.

[0105] During the sampling and programming period t2, a gate electrode and a first electrode of a driving transistor DT are electrically connected through a second transistor T2 in an on state. Further, a voltage “high-potential driving voltage VDD - initialization voltage Vini” previously stored in the storage capacitor Cst can be applied to the gate electrode of the driving transistor DT to turn on the driving transistor DT.

[0106] In an on state, a current flowing through a first electrode and a second electrode can flow in the driving transistor DT. The current flows until a gate-source voltage Vgs of the driving transistor DT saturates to a threshold voltage Vth of the driving transistor DT. Accordingly, during the sampling and programming period t2, a voltage of the gate electrode of the driving transistor DT, i.e., a voltage at a third node N3, increases to “data voltage Vdata + threshold voltage Vth”.

[0107] As the voltage at the third node N3 increases, the storage capacitor Cst stores a voltage corresponding to a difference between the voltage at the third node N3 and the initialization voltage Vini, i.e., “data voltage Vdata + threshold voltage Vth - initialization voltage Vin”

[0108] During the holding period t3, the first scan signal Scan1 and the second scan signal Scan2 are switched to the cut-off level to turn off the first transistor T1, the second transistor T2, and the fifth transistor T5. During the holding period t3, the voltage at the third node N3 can be stably maintained by the storage capacitor Cst.

[0109] During the emission period t4, the first emission signal EM1 and the second emission signal EM2 at the conduction level are applied to turn on the third transistor T3 and the fourth transistor T4. During the emission period t4, a current path is formed from the high-potential drive voltage VDD to the light-emitting element LD via the driving transistor DT. Therefore, a drive current having an amplitude corresponding to the voltage programmed into the driving transistor DT can flow along the current path to allow the light-emitting element LD to emit light with a corresponding brightness.

[0110] During the emission period t4, the amplitude of the drive current applied to the light-emitting element LD is determined according to the gate-source voltage Vgs of the driving transistor DT. Here, since the gate voltage of the driving transistor DT has a value obtained by sampling and compensating for the threshold voltage Vdata of the driving transistor DT, the influence of the change in the threshold voltage Vth of the driving transistor DT can be eliminated.

[0111] The amplitude of the drive current applied to the light-emitting element LD can be further determined according to the gate-source voltage Vgs of the third transistor T3 and the fourth transistor T4. That is, the amplitude of the drive current can be further determined according to the gate voltages of the third transistor T3 and the fourth transistor T4, i.e., the voltages of the emission signals EM1 and EM2.

[0112] During the emission period t4 of the refresh frame RP, the first emission signal EM1 and the second emission signal EM2 are applied to the gate high voltage VEH controlled by the emission signal voltage controller 70 (see Figure 6 ). The gate high voltage VEH can be changed according to the brightness difference between the image data DATA during the refresh frame RP and the image information DATA during the skip frame SP before the refresh frame RP.

[0113] Between adjacent frames, the brightness can generally increase to a critical value or more. In this case, as shown, the gate high voltage VEH is controlled to the second gate high voltage Vadj by the emission signal voltage controller 70.

[0114] The second gate high voltage Vadj can have a value higher than the first gate high voltage Vori applied when the brightness difference between adjacent frames is not considered (see Figure 6)A lower level. Therefore, the drive current applied to the light-emitting element LD through the third transistor T3 and the fourth transistor T4 can be controlled to a low level, and as a result, the brightness of the light-emitting element LD can be reduced.

[0115] When the brightness of the light-emitting element LD is controlled in this way, the rapid change in the brightness of the light-emitting element LD as described in the reference Figure 3 can be eliminated, and the flicker phenomenon can be prevented. In addition, by reducing the drive current, the power consumption of the display device 1 can be reduced, and a low-power display device 1 can be realized.

[0116] The skip frame SP may include an anode initialization period t5 and an emission period t6.

[0117] During the anode initialization period t5, the emission signal EM can be switched to the cut-off level to turn off the third transistor T3 and the fourth transistor T4. In addition, during the anode initialization period t5, the second scan signal Scan2 at the conductive level is applied to turn on the first transistor T1.

[0118] During the anode initialization period t5, the anode initialization voltage can be applied to the data line DL. Therefore, the fourth node N4, that is, the anode electrode of the light-emitting element LD, is initialized to the anode initialization voltage.

[0119] During the anode initialization period t5, the light-emitting element LD does not emit light due to the initialization voltage Vini applied to the anode of the light-emitting element LD. Instead, the voltage of the gate electrode of the drive transistor DT can be maintained at the voltage programmed during the previous refresh frame RP through the storage capacitor Cst.

[0120] During the emission period t6, the first emission signal EM1 and the second emission signal EM2 at the conductive level are applied to turn on the third transistor T3 and the fourth transistor T4. During the emission period t4, the light-emitting element LD can emit light with a brightness corresponding to the voltage programmed during the previous refresh period RP.

[0121] The magnitude of the drive current applied to the light-emitting element LD can be further determined according to the gate-source voltage Vgs of the third transistor T3 and the fourth transistor T4. That is, the magnitude of the drive current can be further determined according to the gate voltages of the third transistor T3 and the fourth transistor T4, that is, the voltages of the emission signals EM1 and EM2.

[0122] During the emission period t6 of the refresh frame SP, the first emission signal EM1 and the second emission signal EM2 are applied to the gate high voltage VEH controlled by the emission signal voltage controller 70. During low-frequency driving, the gate high voltage VEH during the skip frame SP can be changed according to the luminance difference between the image data (DATA) during the previous refresh frame RP or the previous skip frame SP and the image data DATA during the current skip frame SP. Between adjacent frames, the luminance can generally be decreased, maintained, or increased to less than the critical value. In this case, as shown, the gate high voltage VEH is controlled to the first gate high voltage Vori by the emission signal voltage controller 70.

[0123] Meanwhile, during the anode initialization period t5 before the emission period t6, the anode of the light-emitting element LD is charged to the anode initialization voltage. Therefore, during the emission period t6, the luminance of the light-emitting element LD can reach the target luminance more quickly, thereby minimizing the charging delay of the light-emitting element LD.

[0124] Figure 8 is a view showing a first aspect of the luminance change of a pixel according to emission signal voltage control.

[0125] Reference Figure 8 , in one aspect, a black grayscale image can be displayed during the skip frame SP, and then a white grayscale image can be displayed during the refresh frame RP. In this aspect, the image luminance of the skip frame SP and the image luminance of the refresh frame RP are very large when they are at or above a predetermined threshold. Therefore, the gate high voltage VEH of the emission signal EM applied to the refresh frame RP is set to the second gate high voltage Vadj.

[0126] Since the gate high voltage VEH is controlled to a relatively low level during the refresh frame RP, the luminance of the light-emitting element LD is limited to a lower level. Therefore, the rapid change in the luminance of the light-emitting element LD during the refresh frame RP can be eliminated, and the flicker phenomenon can be prevented.

[0127] During the skip frame SP, since no new image data is applied, the image luminance does not change. Therefore, the gate high voltage VEH of the emission signal EM applied during the skip frame SP is set to the first gate high voltage Vori.

[0128] Therefore, the light-emitting element LD can emit light having a luminance corresponding to the driving current controlled according to the first gate high voltage Vori.

[0129] Figure 9 is a view showing a second aspect of the luminance change of a pixel according to emission signal voltage control.

[0130] Reference Figure 9, in one aspect, a first low gray-scale image can be displayed during the skip frame SP, and then a second low gray-scale image can be displayed during the refresh frame RP. Here, the second low gray-scale can be higher than the first low gray-scale.

[0131] In this aspect, the image brightness of the skip frame SP and the image brightness of the refresh frame RP can be very large when equal to or greater than a predetermined threshold. Therefore, the gate high voltage VEH of the emission signal EM applied during the refresh frame RP is set to the second gate high voltage Vadj.

[0132] Since the gate high voltage VEH is controlled to a relatively low level during the refresh frame RP, the brightness of the light-emitting element LD is limited to a lower level. Therefore, the rapid change in the brightness of the light-emitting element LD during the refresh frame RP can be eliminated, and the flicker phenomenon can be prevented.

[0133] At the same time, according to Figure 9 the second gate high voltage Vadj of the aspect has a level higher than the second gate high voltage Vadj of the aspect according to Figure 8 . Since the brightness difference between adjacent frames is smaller than the brightness difference in the aspect of Figure 8 , the second gate high voltage Vadj can be set to a relatively high level corresponding to the brightness difference.

[0134] During the skip frame SP, since no new image data is applied, the image brightness does not change. Therefore, the gate high voltage VEH of the emission signal EM applied during the skip frame SP is set to the first gate high voltage Vori.

[0135] Therefore, the light-emitting element LD can emit light with a brightness corresponding to the drive current controlled according to the first gate high voltage Vori.

[0136] Figure 10 is a view showing the brightness change of a pixel controlled according to the emission signal voltage in the third aspect.

[0137] Refer to Figure 10 , in one aspect, a low gray-scale image can be displayed during the skip frame SP, and then a high gray-scale image can be displayed during the refresh frame RP. In this aspect, the image brightness of the skip frame SP and the image brightness of the refresh frame RP can be very large when equal to or greater than a predetermined threshold. Therefore, the gate high voltage VEH of the emission signal EM applied during the refresh frame RP is set to the second gate high voltage Vadj.

[0138] Since the gate high voltage VEH is controlled to a relatively low level during the refresh frame RP, the brightness of the light-emitting element LD is limited to a lower level. Therefore, the rapid change in the brightness of the light-emitting element LD during the refresh frame RP can be eliminated, and the flicker phenomenon can be prevented.

[0139] Meanwhile, according to Figure 10 the second gate high voltage Vadj of the aspect has a level higher than that of the second gate high voltage Vadj of the aspect according to Figure 8 Since the luminance difference between adjacent frames is smaller than the luminance difference between adjacent frames in the aspect of Figure 8 the second gate high voltage Vadj can be set to a relatively high level corresponding to the luminance difference.

[0140] During the skipped frame SP, since no new image data is applied, the image luminance does not change. Therefore, the gate high voltage VEH of the emission signal EM applied during the skipped frame SP is set to the first gate high voltage Vori.

[0141] Therefore, the light-emitting element LD can emit light having a luminance corresponding to the drive current controlled according to the first gate high voltage Vori.

[0142] Figure 11 is a view showing a fourth aspect of the luminance change of the pixel controlled according to the emission signal voltage.

[0143] Refer to Figure 11 , in one aspect, a first high gray-scale image can be displayed during the skipped frame SP, and then a second high gray-scale image can be displayed during the refresh frame RP. Here, the second high gray-scale can be higher than the first high gray-scale.

[0144] In this aspect, the image luminance of the skipped frame SP and the image luminance of the refresh frame RP can be very large when they are equal to or greater than a predetermined threshold. Therefore, the gate high voltage VEH of the emission signal EM applied during the refresh frame RP is set to the second gate high voltage Vadj.

[0145] Since the gate high voltage VEH is controlled to a relatively low level during the refresh frame RP, the luminance of the light-emitting element LD is limited to a lower level. Therefore, a rapid change in the luminance of the light-emitting element LD during the refresh frame RP can be eliminated, and a flicker phenomenon can be prevented.

[0146] Meanwhile, according to Figure 11 the second gate high voltage Vadj of the aspect has a level higher than that of the second gate high voltage Vadj of the aspect according to Figure 8 Since the luminance difference between adjacent frames is smaller than the luminance difference between adjacent frames in the aspect of Figure 8 the second gate high voltage Vadj can be set to a relatively high level corresponding to the luminance difference.

[0147] During the skipped frame SP, since no new image data is applied, the image brightness does not change. Therefore, the gate high voltage VEH of the emission signal EM applied during the skipped frame SP is set to the first gate high voltage Vori.

[0148] Therefore, the light-emitting element LD can emit light having a brightness corresponding to the drive current controlled according to the first gate high voltage Vori.

[0149] According to the display device and its driving method according to the aspect, image anomalies such as flicker caused by rapid changes in brightness during low-frequency driving can be minimized.

[0150] According to the display device and its driving method according to the aspect, by preventing the flicker phenomenon through voltage control of the emission signal, there is no need to separately control the frequency or data voltage.

[0151] According to the display device and its driving method according to the aspect, an energy deviation phenomenon in which the light-emitting element becomes brightly visible due to rapid changes in brightness can be prevented, thereby improving the reliability of the light-emitting element.

[0152] According to the display device and its driving method according to the aspect, the power consumed can be reduced by lowering the voltage of the emission signal.

[0153] Therefore, according to the display device and its driving method according to the aspect, the operating characteristics of the display device can be improved, thereby reducing power consumption and realizing a low-power display device.

[0154] Although the aspects of the present disclosure have been described above with reference to the accompanying drawings, those skilled in the art to which the present disclosure pertains will be able to understand that the above technical configuration of the present disclosure can be implemented in other specific forms without changing its technical spirit or basic characteristics. Therefore, it should be understood that the above aspects are illustrative rather than restrictive in all respects. In addition, the scope of the present disclosure is described by the claims to be described below rather than the detailed description. In addition, the meaning and scope of the claims and all forms of changes or modifications derived from equivalent concepts should be interpreted as being included within the scope of the present disclosure.

Claims

1. A display device, comprising: a display panel, pixels being arranged at the display panel; a timing controller configured to output image data and an emission driving control signal based on an image signal and a control signal from an external component; a gate driver configured to apply a gate signal to the pixel; a data driver configured to apply a data voltage corresponding to the image data to the pixel; an emission driver configured to apply an emission signal to the pixel based on the emission drive control signal; as well as a transmission signal voltage controller configured to change the voltage of the transmission signal, The transmission signal is a square wave signal including a gate high voltage period and a gate low voltage period, and The emission signal voltage controller changes the gate high voltage based on a brightness difference of the image data between adjacent frames.

2. The display device according to claim 1, wherein: The transmission signal voltage controller is configured as follows: When the brightness difference between the adjacent frames is less than a critical value, setting the gate high voltage to a first gate high voltage; and When the brightness difference between the adjacent frames is greater than the critical value, the gate high voltage is set to a second gate high voltage that is smaller than the first gate high voltage.

3. The display device according to claim 2, wherein: During low frequency driving, the display panel is driven in a combination of a refresh frame in which the data voltage is programmed to the pixel and one or more skip frames in which programming of the data voltage is omitted.

4. The display device according to claim 3, wherein: The adjacent frames include the refresh frame.

5. The display device according to claim 3, wherein: When the brightness difference between the adjacent frames is greater than the critical value, the gate high voltage is set to the second gate high voltage during the refresh frame, and the gate high voltage is set to the first gate high voltage during the one or more skip frames after the refresh frame.

6. The display device according to claim 3, wherein: The transmission signal voltage controller comprises: an information collector configured to measure a first frame response time during low frequency driving, determine the first gate high voltage in response to the first frame response time, and determine the second gate high voltage to allow the brightness difference between the adjacent frames to be less than the critical value; an image analyzer configured to acquire the image data on a frame basis when the display panel is driven at the low frequency, and determine the brightness difference of the image data between the adjacent frames; and A voltage selector is configured to select the first gate high voltage as the gate high voltage when the brightness difference is less than the critical value, and to select the second gate high voltage as the gate high voltage when the brightness difference is greater than or equal to the critical value.

7. The display device according to claim 3, wherein: The transmitting driver comprises: a level shifter configured to generate a clock signal having a level between the gate high voltage and the gate low voltage; and A shift register is configured to output the transmission signal based on the clock signal output from the level shifter.

8. The display device according to claim 1, wherein: The pixels include: a light emitting element configured to emit light having a brightness corresponding to the driving current; a driving transistor configured to control the driving current flowing through the light emitting element; a first transistor configured to apply the data voltage to the second electrode of the driving transistor in response to a second scan signal; a second transistor configured to connect the gate electrode of the driving transistor to the first electrode of the driving transistor in response to a first scan signal; a storage capacitor connected between the gate electrode of the driving transistor and the anode electrode of the light emitting element; a third transistor configured to form a current path between a high potential driving voltage and the first electrode of the driving transistor in response to a second emission signal; and The fourth transistor is configured to form a current path between the driving transistor and the light emitting element in response to a first emission signal.

9. The display device according to claim 8, wherein: As the gate high voltages of the first emission signal and the second emission signal are changed, the driving current is controlled.

10. The display device according to claim 8, wherein: The pixel further includes a fifth transistor configured to apply an initialization voltage to the anode electrode of the light emitting element in response to the first scan signal.

11. A method for driving a display device, the display device comprising a display panel and an emission driver, pixels are arranged at the display panel, the emission driver is used to apply an emission signal to the pixels, the method comprising: ； driving the display panel with a skipped frame, during which the emission driver applies the emission signal having a first gate high voltage to the pixel during a low frequency driving period; as well as The display panel is driven in a refresh frame during which the emission driver applies the emission signal having a second gate high voltage different from the first gate high voltage to the pixel after the skipped frame.

12. The method according to claim 11, wherein: programming data voltages corresponding to image data to the pixels during the refresh frame, and Wherein, programming of the data voltage is omitted during the skipped frame.

13. The method according to claim 11, wherein: The second gate high voltage is determined based on a brightness difference between adjacent frames.

14. The method according to claim 11, wherein: The second gate high voltage is lower than the first gate high voltage.

15. The method according to claim 11, wherein: The first gate high voltage is determined according to a first frame response time during the low frequency driving.

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