Semiconductor structure

Abstract

A semiconductor structure (1) is provided, the semiconductor structure (1) comprising: a substrate (6); a trapping layer (3) on the substrate (6) and having a hydrogen concentration of less than 1018 at / cm3; a dielectric layer (4) disposed on the trap layer (3), the dielectric layer (4) comprising silicon oxide having nitrogen wherein a nitrogen / oxygen ratio is greater than 0.01; and a thin layer (5) located on the dielectric layer (4), the thin layer (5) being composed of a ferroelectric material.

Description

[0001] This application is a divisional application of the invention patent application with the application number 202080049468.3 (International Application No. PCT / EP2020 / 058462), the application date of March 26, 2020, and the invention title of "Method for Manufacturing a Structure Comprising a Thin Layer Transferred onto a Support Provided with a Charge Trapping Layer". Technical Field

[0002] The present invention relates to a method for manufacturing a structure comprising a thin layer transferred onto a support having a charge trapping layer. Background Art

[0003] Integrated devices are generally built on a substrate in the form of a wafer, which mainly serves as a support for the manufacture of the integrated devices. However, the increasing integration level and performance requirements of these devices have led to an ever more significant correlation between their performance level and the characteristics of the substrate on which the devices are formed. This is particularly true for radio frequency (RF) devices that process signals in the frequency range of approximately 3 kHz to 300 GHz, which are particularly suitable for the telecommunications field (telephony, Wi-Fi, Bluetooth, etc.).

[0004] As an example of device / substrate coupling, the electromagnetic field of high-frequency signals propagating in the device penetrates into the depth of the substrate and interacts with the possible charge carriers present therein. This results in an unnecessary consumption of some of the energy of the signal through insertion loss and a possible influence between components through crosstalk.

[0005] RF devices such as filters, switches, and antenna adapters, as well as power amplifiers, can be built on specially adapted substrates that take these phenomena into account and improve the performance level.

[0006] Therefore, high-resistivity silicon-on-insulator (HR SOI) substrates are known, which comprise a silicon support substrate having a resistivity greater than 1 kΩ·cm, a dielectric layer on the support substrate, and a thin silicon surface layer placed on the insulating layer. The substrate may also include a charge trapping layer provided between the support substrate and the dielectric layer. The trapping layer may comprise undoped polysilicon. The manufacture of such substrates is described, for example, in FR2860341, FR2933233, FR2953640, US2015 / 115480, US7268060, or US6544656. Generally, the intention is to limit the temperature and / or duration of the heat treatment applied to such a substrate to avoid recrystallization of the trapping layer, which would reduce its RF performance level.

[0007] There are other reasons why certain semiconductor structures cannot be exposed to high temperatures (e.g., above 600 °C or 1000 °C) during their fabrication or use. This is the case for structures formed from assemblies of two substrates having different coefficients of thermal expansion. One of the substrates forms a support for the structure, and a thin layer obtained from the other substrate is transferred onto this support.

[0008] The nature of the thin layer, e.g., when it consists of a ferroelectric material, can also limit the processing temperature of the structure to its Curie temperature, above which the material loses its permanent polarization.

[0009] In addition, when the thin layer contains components, there is sometimes a motivation to limit the exposure temperature of the semiconductor structure. These components can be formed directly on (or in) the structure or transferred onto the support to form the structure. At exposure temperatures higher than 400 °C or 600 °C, the diffusion of dopants or the metals constituting the components renders the components inoperable.

[0010] It is also possible to deliberately limit the temperature to which the structural elements are exposed. This is especially the case when forming charge trapping layers or dielectric layers by LPCVD (“Low-Pressure Chemical Vapor Deposition”) or PECVD (“Plasma-Enhanced Chemical Vapor Deposition”) techniques. These inexpensive techniques are applicable to multiple substrates and are carried out at a moderate temperature of around 600 degrees.

[0011] However, the applicant has observed that producing a structure comprising a layer for trapping charges and a dielectric layer by a manufacturing method that uses only moderate heat treatment (i.e., does not expose the structure to temperatures above 1000 °C) results in a structure having a much lower level of radiofrequency (RF) performance than expected.

[0012] As documented in the publication “White paper - RF SOI Characterisation” published by SOITEC in January 2015, the RF performance of a substrate can be characterized by the second harmonic distortion measurement result HD2. In the case of a semiconductor structure comprising a charge trapping layer and only moderate heat treatment being implemented, the applicant has observed that this HD2 characteristic can be between 55% and 75% of the expected value.

[0013] Object of the Invention

[0014] The present invention aims to solve this problem at least in part. More specifically, the object of the present invention is to propose a method for manufacturing a semiconductor structure that includes transferring a thin layer onto a support provided with a layer for trapping charges, the method not employing a heat treatment that exposes the structure to high temperatures but still obtaining a structure having a compatible level of RF performance. Summary of the Invention

[0016] To achieve this object, the present invention proposes a manufacturing method for manufacturing a structure, the structure including a thin layer transferred onto a support provided with a charge trapping layer, the manufacturing method including the following steps:

[0017] - Preparing the support, including forming the trapping layer on a base substrate, the trapping layer having a hydrogen concentration of less than 10 18 at / cm 3 ;

[0018] - Bonding the support to a donor substrate through a dielectric layer, the dielectric layer having a hydrogen concentration of less than 10 20 at / cm 3 or including a barrier preventing hydrogen diffusion towards the trapping layer or having a low hydrogen diffusion rate;

[0019] - Removing a part of the donor substrate to form the thin layer;

[0020] The manufacturing method exposes the structure (1) to a temperature lower than the maximum temperature of 1000 °C.

[0021] During the support preparation step, forming a trapping layer with a low hydrogen concentration avoids excessive charge trapping in this layer. Forming a dielectric layer that also has a low hydrogen concentration or prevents the diffusion of this hydrogen avoids or limits its diffusion towards the trapping layer, especially during the heat treatment to which the dielectric layer is exposed during the manufacturing method and after the bonding step. Alternatively, a barrier can be provided in the dielectric layer to prevent hydrogen diffusion from the dielectric layer towards the trapping layer.

[0022] According to other advantageous and non-limiting features of the present invention, individually or in any technically feasible combination:

[0023] · The trapping layer is deposited at a deposition temperature between 600 °C and 950 °C, and the step of preparing the support includes: a first annealing stage of annealing the trapping layer (3) in a hydrogen-poor atmosphere and at a temperature between the deposition temperature and 1000 °C;

[0024] · The deposition of the trapping layer implements the LPCVD technique;

[0025] · The trapping layer is formed by deposition at a temperature between 950 °C and 1100 °C;

[0026] · The deposition of the trapping layer is achieved in an epitaxial framework;

[0027] · The dielectric layer is produced by depositing a material having a hydrogen concentration greater than 10 20 at / cm 3 and subsequently applying a second annealing stage in a hydrogen-poor atmosphere;

[0028] · The second annealing stage lasts for at least one hour in a neutral atmosphere at a temperature between 800 °C and 900 °C;

[0029] · The dielectric layer is produced by depositing a material with a hydrogen concentration greater than 10 20 at / cm 3 onto the trapping layer before applying the first annealing stage;

[0030] · The dielectric layer is produced by thermally oxidizing the trapping layer at a temperature between 800 °C and 1000 °C.

[0031] · The dielectric layer includes the barrier, and the barrier is in direct contact with the trapping layer;

[0032] · The barrier consists of a SiN or AlN layer;

[0033] · The dielectric layer with a low hydrogen diffusion rate includes an oxide having nitrogen and a nitrogen / oxygen ratio greater than or equal to 0.01 or 0.05;

[0034] · The dielectric layer with a low hydrogen diffusion rate includes silicon oxide having nitrogen and a nitrogen / oxygen ratio between 0.01 and 0.25 or between 0.05 and 0.1.

[0035] · The manufacturing method includes: a step of forming a brittle plane in the donor substrate before the bonding step, and wherein the removal step is performed by breaking the donor substrate at the brittle plane;

[0036] · The thin layer is composed of a piezoelectric material and / or a ferroelectric material;

[0037] · The thin layer is made of lithium tantalate or lithium niobate.

[0038] According to another aspect, the present invention provides a structure that cannot be exposed to high temperatures, such as higher than 600 °C or 1000 °C, the structure comprising:

[0039] - A base substrate;

[0040] - A trapping layer disposed on the base substrate and having a hydrogen concentration less than 10 18 at / cm 3 ;

[0041] - A dielectric layer disposed on the trapping layer, the dielectric layer having a hydrogen concentration less than 10 20 at / cm 3 or including a barrier to prevent hydrogen diffusion into the trapping layer or having a low hydrogen diffusion rate;

[0042] - A thin layer disposed on the dielectric layer.

[0043] According to other advantageous and non - limiting features of the present invention, alone or in any technically feasible combination:

[0044] · The thin layer is made of a ferroelectric material having a permanent polarization and a Curie temperature between 600 °C and 1000 °C;

[0045] · The dielectric layer is in contact with the trapping layer and the thin layer;

[0046] · The dielectric layer having a low hydrogen diffusion rate includes an oxide having nitrogen and a nitrogen / oxygen ratio greater than or equal to 0.01 or 0.05;

[0047] · The dielectric layer having a low diffusion rate includes silicon oxide having nitrogen and a nitrogen / oxygen ratio between 0.01 and 0.25 or between 0.05 and 0.1. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Other features and advantages of the present invention will become apparent from the following detailed description of the invention with reference to the drawings, in which:

[0049] Figure 1 Figure 1 shows a structure, the manufacturing method of which is the object of the present specification. DETAILED DESCRIPTION

[0050] Figure 1 Shows structure 1, the manufacturing method of which is the object of the present specification. Structure 1 has a thin surface layer 5, a dielectric layer 4 and a support 2. The dielectric layer 4 includes an oxide such as silicon oxide, for example. The support 2 has a charge trapping layer 3 placed on a substrate 6. The trapping layer 3 is between the dielectric layer 4 and the underlying substrate 6. Preferably, the dielectric layer 4 is in contact with the trapping layer 3 and the thin layer 5.

[0051] Generally, structure 1 can be in the form of a circular wafer with a diameter that can be 100 mm, 200 mm, 300 mm or even 450 mm.

[0052] As described in the prior art documents presented in the preamble, structure 1 can be produced in various ways. As a general rule, structure 1 can be manufactured by a manufacturing method including bonding the support 2 and a donor substrate, with a dielectric layer inserted between the two elements, followed by the step of removing a part of the donor substrate to form the thin layer 5. The step of removing part of the donor substrate can be carried out by chemically - mechanically thinning the substrate. Preferably, by applying SmartCut TM ​​A technique is used to fabricate structure 1. According to this technique, a brittle plane formed by injecting light substances into a donor substrate is utilized to define the layer for forming the thin layer 5. Then, this layer is removed from the donor substrate by breaking at the brittle plane and transferred to the support 2 provided with the capture layer 3 through the dielectric layer 4 inserted between the support 2 and the donor substrate.

[0053] The base substrate 6 is typically several hundred micrometers thick. Preferably, the base substrate has a high resistivity greater than 1000 ohm·cm, and even more preferably greater than 2000 ohm·cm. Thus, this limits the density of charges, holes, or electrons that may move in the base substrate. However, the present invention is not limited to a base substrate 6 having such a resistivity, and when the base substrate has a more compatible resistivity of approximately several hundred ohm·cm, such as less than 1000 ohm·cm, or less than 500 ohm·cm, or even less than 10 ohm·cm, the present invention also provides RF performance advantages.

[0054] For reasons of usability and cost, the base substrate 3 is preferably made of single-crystalline silicon. For example, it can be a CZ silicon substrate with a low interstitial oxygen content between 6 ppm and 10 ppm, or an FZ silicon substrate with a particularly naturally very low interstitial oxygen content. It can also be a CZ silicon substrate with a high interstitial oxygen content (represented by the expression "high Oi") greater than 26 ppm. For example, it can be sapphire, glass, quartz, silicon carbide, etc. In certain cases, especially when the capture layer 3 is thick enough, such as greater than 30 μm thick, the base substrate 6 can have a standard resistivity of less than 1 kΩ·cm.

[0055] The capture layer 3 can be very different in nature, as documented in the literature of the prior art. Generally speaking, it is an amorphous layer having structural defects such as dislocations, grain boundaries, amorphous regions, interstitial sites, inclusions, pores, etc. These structural defects form traps for charges that are prone to circulate in the material, for example, at incomplete or dangling chemical bonds. This prevents conduction in the capture layer, so the capture layer has a high resistivity.

[0056] Advantageously, and for the sake of simplicity of implementation, the capture layer 3 is formed by a polysilicon layer. Its thickness, especially when it is formed on the resistive base substrate 6, can range from 0.3 μm to 3 μm. However, depending on the expected RF performance level of structure 1, other thicknesses below or above this range can be envisioned.

[0057] In order to seek to maintain the polycrystalline quality of this layer during the heat treatment applicable to structure 1, an amorphous layer made of, for example, silicon dioxide can be advantageously provided on the base substrate 6 before depositing the charge capture layer 3.

[0058] Alternatively, the trapping layer 3 can be formed by implanting a relatively heavy substance (such as argon) into the surface thickness of the base substrate 6 to form structural defects that constitute electrical traps there. The layer 3 can also be formed by porosifying the surface thickness of the base substrate 6 or by any other method capable of forming structural defects in the surface thickness of the substrate 6 that can trap charges.

[0059] The thin surface layer 5 can be of any suitable type. When the structure 1 is used to accommodate integrated semiconductor components, the thin layer 5 can be composed of single-crystalline silicon or any other semiconductor material such as germanium, silicon germanium, or silicon carbide. When the structure 1 is used to accommodate surface acoustic wave filters, the thin layer 5 can be composed of piezoelectric and / or ferroelectric materials such as lithium tantalate or lithium niobate. The thin layer 5 can also include: finished or semi-finished integrated components formed on a donor substrate and transferred to the support 2 during the steps of manufacturing the structure 1. Generally, the thickness of the thin layer can be between 10 nm and 10 microns.

[0060] A method for manufacturing the structure shown according to Figure 1 will now be described. This method constitutes a preliminary experiment that led to the present invention. According to this experimental method, using the LPCVD technique carried out between 600 °C and 650 °C, a polysilicon charge trapping layer 3 is formed on the silicon-based substrate 6 by deposition. The trapping layer 3 is approximately 1 micron thick.

[0061] A silicon oxide layer 300 nm to 1000 nm thick is deposited onto the trapping layer 3 using the PECVD technique carried out at a temperature of 600 °C, and this silicon oxide layer forms the dielectric layer 4 of the structure 1. After this deposition, a densification annealing is carried out at 600 °C for approximately 1 hour in a neutral or oxidizing atmosphere. Then, the layer is polished by a chemical mechanical polishing step (CMP), resulting in the removal of approximately 200 - 800 nanometers of oxide to provide a surface with a roughness less than 0.3 nm RMS in a 5 * 5 micron area.

[0062] Hydrogen ions are implanted through the first face of a lithium tantalate ferroelectric donor substrate to form a masked embrittlement plane. Thus, a first layer is defined between this embrittlement plane and the first face of the donor substrate. The donor substrate is bonded to the silicon oxide layer 4 placed on the support 2, and then the donor substrate is fractured at the embrittlement plane using a moderate heat treatment at approximately 400 °C. The first layer of the donor substrate is released to expose the free face of this layer, and thus this layer can be prepared to improve the crystal quality and surface conditions. This preparation includes a step of thinning the first layer by chemical mechanical polishing and a step of heat treatment at 500 °C for 1 hour in a neutral atmosphere.

[0063] The RF performance level expected from the resulting structure is estimated by determining the value of the HQF (Harmonic Quality Factor) as taught in US2015 / 0168326. This HQF value can be estimated from the depth resistivity profiles of the trapping layer 4 and the base substrate 6.

[0064] Then, the structure 1 so prepared is subjected to a characterization measurement called "second harmonic distortion" (HD2). This measurement is carried out at 900 MHz and is recorded in the "Whitepaper – RF SOI wafer characterisation" document presented in the introduction. More specifically, a coplanar waveguide is formed by depositing aluminum wires on the free surface of a thin surface layer of lithium tantalate. Then, a signal with a frequency of 900 MHz is applied to one end of the waveguide, and the second harmonic signal HD2 is measured at the other end. The weaker the second harmonic signal, the higher the performance level of the structure.

[0065] The HD2 measurement results and the HQF estimates are particularly relevant characteristics of the structure 1 because they highly represent the performance of the integrated RF devices that will be formed on this structure.

[0066] Surprisingly, the value of the HD2 characteristic of the structure 1 at the end of the method just described only corresponds to approximately 50% to 75% of the expected results provided by the HQF estimates.

[0067] Additional studies have enabled the applicant to recognize that this low performance level is related to the presence of excessive hydrogen in the charge trapping layer 3 and the dielectric layer 4. The dielectric layer (in this case SiO2) has a hydrogen content greater than 10 20 at / cm 3 and the trapping layer 3 has a hydrogen content greater than 10 18 at / cm 3 of hydrogen.

[0068] The dielectric layer 4, which is particularly rich in hydrogen, forms a type of reservoir, and when the difference in hydrogen concentration between the dielectric layer 4 and the trapping layer 3 is too large, and considering the heat treatment applied to the structure 1, the hydrogen retained in this layer 4 can diffuse towards the trapping layer 3. Thus, hydrogen is supplied from the dielectric layer 4 to the trapping layer. Then this hydrogen can neutralize the electrical traps in the trapping layer 3, especially at the interface between the trapping layer 3 and the dielectric layer 4. It should be noted that in conventional structures exposed to temperatures exceeding 1000 °C, such as in the final stage of completing the structure, the hydrogen contained in the dielectric layer 4 or the trapping layer 3 is removed by diffusion during the heat treatment, and thus this difference between the HD2 measurement results and the HQF estimates does not significantly occur.

[0069] Then, the Applicant has developed a manufacturing method using these mechanisms found, which does not employ a heat treatment that exposes the structure to high temperatures, but which produces a structure with a compatible level of RF performance. "Compatible" means that the deviation of the HD2 measurement results from its HQF estimate does not exceed 20%.

[0070] Generally, the method aims to form a trapping layer 3 with a relatively low hydrogen concentration to avoid excessive neutralization of charge traps. The aim is also to form a dielectric layer 4 with a low hydrogen concentration or that limits the diffusion of this hydrogen, to avoid or limit the migration of this hydrogen into the trapping layer, taking into account the heat treatment applied to the structure.

[0071] More specifically, the method repeats the steps of preparing the support 2, bonding the support 2 to the donor substrate, and removing a part of the donor substrate as just described. For all the reasons described in the introduction of this application, the structure 1 cannot be exposed to a temperature exceeding 1000 °C during its manufacture, during the bonding step or after this step. However, in this method, the aim is to form, during the step of preparing the support, a trapping layer 3 with a low hydrogen concentration of less than 10 18 at / cm 3 to avoid excessive neutralization of the traps in this layer 3. At the same time, the aim is to form the following dielectric layer 4, which also has a low hydrogen concentration (less than 10 20 at / cm 3 ) or that limits the diffusion of this hydrogen, to avoid the formation of hydrogen accumulations that will subsequently be able to diffuse towards the trapping layer 3 or at the interface with this layer. Alternatively, a barrier preventing the diffusion of hydrogen towards the trapping layer can be provided in the dielectric layer. Advantageously, when the dielectric layer does not have a barrier layer or when it cannot trap the hydrogen it contains, the aim is to limit the hydrogen concentration in the dielectric layer to less than 10 19 at / cm 3 , or even less than 10 18 at / cm 3 .

[0072] A number of embodiments can be envisaged for producing such a trapping layer 3 and dielectric layer 4.

[0073] Thus, according to a first embodiment of the trapping layer 3, it can be formed by deposition at a moderate temperature (for example strictly between 600 °C and 950 °C). This can be the deposition of a polysilicon layer formed by LPCVD technology implemented in a deposition furnace. It has been found that such a deposition results in the formation of a trapping layer 3 including a hydrogen concentration greater than 10 18 at / cm 3 and generally between this value and 10 19 at / cm 3 .

[0074] To reduce this concentration, according to this first embodiment, there is a first annealing stage of the capture layer at a temperature between the deposition temperature and 1000 °C in a hydrogen-poor atmosphere (i.e., less than 5 ppm). Advantageously, the temperature of the first annealing stage is higher than 620 °C and preferably lower than 900 °C, lasting for at least one hour and preferably for several hours. The hydrogen present in the capture layer 3 effectively diffuses out under these preferential annealing conditions, thereby reducing its concentration to below 10 18 at / cm 3 threshold, without damaging the polycrystalline nature of the capture layer due to recrystallization effects.

[0075] The first annealing stage can be carried out directly after the deposition of the capture layer 3 or after the formation of the dielectric layer 4 when the dielectric layer 4 is at least partially deposited on the capture layer 3, as will be described in the remainder of this specification.

[0076] According to a second embodiment of the capture layer 3, at a high temperature, for example, at a temperature between 950 °C and 1100 °C, the capture layer 3 is deposited on the base substrate 6. This can be the deposition of polycrystalline silicon produced in an epitaxial reactor. Under such deposition conditions, the capture layer 3 has a hydrogen concentration several times lower than that of the layer formed by the LPCVD technique. In all cases, care should be taken to ensure that this concentration is less than 10 18 at / cm 3 . In this second embodiment, where the capture layer 3 is directly formed to have a low hydrogen concentration, the first annealing stage provided in the previous embodiment for hydrogen out-diffusion is not necessary.

[0077] The dielectric layer 4 can, for its part, be formed by deposition on the capture layer 3. Alternatively, or additionally, it can be formed in whole or in part by deposition on the first face of the donor substrate. The choice of forming the dielectric layer 4 on the support or donor substrate depends on whether they can be exposed to relatively high temperatures.

[0078] Thus, and according to a first embodiment of the dielectric layer 4, the dielectric layer 4 is manufactured by depositing silicon oxide in a deposition furnace using the PECVD technique. This deposition is carried out at a moderate temperature, typically between 600 °C and 800 °C. In this case, the dielectric layer 4 has a significant hydrogen concentration greater than 10 20 at / cm 3 .

[0079] To reduce this concentration, a second annealing stage called "densification" is applied, similar to the above-described first annealing stage. Thus, it involves annealing in a hydrogen-poor atmosphere (i.e., less than 5 ppm) and exposing layer 4 to a temperature higher than its deposition temperature. It can be a neutral or oxidizing atmosphere. Preferably, the temperature is higher than 800 °C, typically between 800 °C and 900 °C. The annealing lasts for at least one hour and preferably several hours, so that finally hydrogen diffuses out of dielectric layer 4 and possibly hydrogen is released from self-trapping layer 3. At the end of this densification annealing, dielectric layer 4 has a hydrogen concentration of less than 10 20 at / cm 3 , and trapping layer 3 has a hydrogen concentration of less than 10 18 at / cm 3 .

[0080] It should be noted that the second densification annealing stage can change the properties of the dielectric layer other than its hydrogen concentration. It can in particular lead to a reduction in the diffusivity of hydrogen, that is to say the ability of this substance to diffuse into the material constituting the dielectric layer, such that hydrogen is less likely to diffuse towards trapping layer 3 even at relatively high concentrations (about 10 20 at / cm 3 ).

[0081] It is generally preferred to place dielectric layer 4 on support 2 rather than on the donor substrate. In fact, the support 2 can generally be heat-treated at the temperature of the first and / or second annealing stage, which is not always the case for the donor substrate. For example, the substrate can have a brittle transition plane, or be made of a ferroelectric material with a relatively low Curie temperature, or include components: the component will limit the thermal budget applicable to it to a relatively short time (i.e., less than 1 hour) in each of these cases. However, the present invention does not exclude that in some suitable cases, dielectric layer 4 can be at least partially formed on the donor substrate.

[0082] When dielectric layer 4 is formed on trapping layer 3 and the two layers have been deposited at a relatively low temperature, as just described, it is not necessary to apply the first and second annealing stages separately after each deposition step. As has been briefly mentioned, a single annealing stage can be carried out under conditions similar to the first and second annealing stages after dielectric layer 4 has been formed on trapping layer 3 at a low temperature. In other words, in this case, individual annealing of trapping layer 3 is not required before depositing dielectric layer 4.

[0083] According to a second embodiment of the dielectric layer 4, the dielectric layer 4 can be produced by thermal oxidation of the trapping layer 3. Such treatment can be carried out by exposing the support 2 provided with the trapping layer 3 to an oxidation furnace at a temperature strictly between 800 °C and 1000 °C and in an oxygen-rich atmosphere. It can be a dry or wet atmosphere. As is known per se, the duration of this exposure is selected according to the desired thickness of the dielectric layer 4. It is generally preferably to limit the oxidation temperature to 1000 °C to avoid any risk of recrystallization of the trapping layer 3. Furthermore, according to the second embodiment of this layer already described above, this dielectric layer 3 is preferably produced by oxidation of the trapping layer 3 formed at a high temperature. In fact, such a layer has a greater temperature stability with respect to the risk of recrystallization.

[0084] At the detection limit of traditional measurement methods, when the trapping layer 3 is made of silicon (which is usually the case), the dielectric layer 4 made of silicon dioxide formed by thermal oxidation of the trapping layer has a particularly low hydrogen concentration, on the order of a few 10 17 at / cm 3 . Optionally, a step of polishing the surface of the trapping layer 3 thus oxidized can be introduced to make it compatible with the subsequent bonding step.

[0085] The dielectric layer 4 can also be prepared according to a third embodiment, which is of particular interest when it is not possible to expose the dielectric layer 4 to a relatively high temperature (e.g., above 800 °C). In this case, the dielectric layer 4 is formed at a relatively low temperature, for example according to the first embodiment of this layer, and attention is paid to including a barrier in the dielectric layer 4 to prevent the diffusion of hydrogen into the trapping layer.

[0086] Thus, and although the dielectric layer 4 can have a hydrogen concentration greater than 10 20 at / cm 3 , the diffusion of the hydrogen contained in the dielectric layer 4 into the trapping layer 3 is prevented, which in turn has a concentration of less than 10 18 at / cm 3 . This thus avoids neutralizing the charge traps of this layer 3. In a variant, the dielectric layer 4 consists entirely of a barrier that retains any hydrogen that may be contained therein.

[0087] The barrier can consist of or include a layer of silicon nitride or aluminum nitride, the layer of silicon nitride or aluminum nitride having a thickness greater than 10 nanometers, and generally a thickness between 10 and 100 nanometers. The barrier can be deposited directly onto the trapping layer 3, for example by means of PECVD technology, before forming the remaining part of the dielectric layer 4 made, for example, of silicon dioxide and rich in hydrogen. Alternatively, the barrier can be formed on the donor substrate, and in this case after the remaining part of the dielectric layer 4 has been formed, so that the barrier can be brought into contact with the trapping layer 3 during the next step of bonding the donor to the support 2.

[0088] In another variant, the barrier layer is formed of a silicon oxide layer having a very low hydrogen concentration (about 10 17 at / cm 3 ). In this case, the barrier forms a buffer layer that absorbs hydrogen from the dielectric layer and thus prevents hydrogen from diffusing into the trapping layer 3. In this case, taking into account the thickness of the dielectric layer and its hydrogen concentration, a barrier layer of sufficient thickness will be provided such that after the hydrogen diffuses into the barrier layer, its hydrogen concentration does not exceed 10 20 at / cm 3 . This variant can be achieved when the dielectric layer is formed by deposition on the donor substrate side and the barrier is formed by thermal oxidation of the trapping layer 3, as described in the second embodiment regarding the dielectric layer 4.

[0089] According to yet another aspect, it can be provided that the dielectric layer 4 has any concentration of hydrogen, but the layer 4 has a low diffusivity of this hydrogen, which thus remains sufficiently trapped therein so as not to significantly diffuse into the trapping layer 3. In this case, the dielectric layer 4 can consist entirely of a layer formed of a material that prevents the hydrogen it contains from diffusing. Thus, it can relate to a deposited oxide having nitrogen and a nitrogen / oxygen ratio greater than or equal to 0.01 or advantageously greater than or equal to 0.05, such as silicon oxide SiO N . When the dielectric layer 4 is based on very common silicon oxide, a nitrogen / oxygen ratio not exceeding 0.1 or 0.25 can be selected so as not to overly change the properties of the material and to maintain a behavior equivalent or close to that of simple silicon oxide SiO2. It should be noted that such a nitrogen-rich oxide layer can be easily formed by deposition techniques, such as PECVD, at least one carrier gas of which can be selected as nitrogen, which can be introduced into the oxide layer in a controlled manner. The nitrogen / oxide ratio can be measured by a technique called EDX (Energy Dispersive X-ray Spectroscopy) or established from nitrogen and oxygen measurements determined by SIMS (Secondary Ion Mass Spectrometry) through the oxide layer 4.

[0090] Generally, when a structure including the following is annealed at 500 °C for 1 hour and results in a hydrogen concentration measured in the trapping layer at the end of the heat treatment of less than 10 18 at / cm 3 , the dielectric layer 4 can be considered to have a low hydrogen diffusivity:

[0091] - a dielectric layer that contains hydrogen at a concentration of at least 10 20 at / cm 3 and is provided in contact with this layer,

[0092] - a 1-μm trapping layer made of polycrystalline silicon initially containing hydrogen at a concentration of less than 10 18 at / cm 3 .

[0093] The dielectric layer 4 can be made of a material with a low diffusivity throughout its thickness, such as a deposited oxide containing nitrogen in the above proportions. Alternatively, in the configuration presented in the previous alternative, it can be stipulated that only one barrier layer is formed of this material with a low diffusivity to prevent hydrogen from diffusing towards the trapping layer 3.

[0094] Before the bonding step, at least some of the contact surfaces can be polished, especially those corresponding to the exposed surfaces of the deposited trapping and / or dielectric layers. In addition, as already seen, after this bonding step, a part of the donor substrate is removed to form the thin layer 5. This removal can be achieved by thinning or fracturing the donor substrate. To improve the characteristics of the thin layer 5, a step of preparing the transfer layer can be provided, such as a polishing and / or thermal annealing step.

[0095] The steps of bonding, removing a part of the donor substrate, and preparing the transfer layer are carried out at a moderate temperature, exposing the structure 1 to a temperature that is always below 1000 °C, preferably below 800 °C or 600 °C. More generally, the aim is to limit the temperature exposure of the dielectric layer 4 during at least the bonding step and after during the manufacturing method, thereby limiting the diffusion of hydrogen from this layer to the trapping layer 3. As a general rule, the higher the concentration in the dielectric layer (while remaining below the threshold of 10 20 at / cm 3 ), the more the maximum temperature to which the dielectric layer 4 and the structure 1 are exposed will be limited.

[0096] Regardless of the selected implementation of the trapping layer 3 and the dielectric layer 4, at the end of the manufacturing method just described, the structure 1 is obtained, as Figure 1 shown, which includes:

[0097] - A base substrate 6;

[0098] - A trapping layer 3, which is provided on the base substrate 6 and has a hydrogen concentration of less than 10 18 at / cm 3 ;

[0099] - A dielectric layer 4, which is provided on the trapping layer 3 and is advantageously in contact with this layer. The dielectric layer 4 has a hydrogen concentration of less than 10 20 at / cm 3 , or includes a barrier to prevent hydrogen from diffusing towards the trapping layer 3, or has any hydrogen concentration, but then has a very low hydrogen diffusivity.

[0100] - A thin layer 5, which is provided on the dielectric layer 4 and is preferably in contact with this layer. The thin layer 5 can be composed of a semiconductor material such as silicon, an insulator such as a ferroelectric material, or a layer including integrated semiconductor elements.

[0101] Advantageously, the hydrogen concentration in the dielectric layer is less than 10 19 at / cm 3 , or even 10 18 at / cm 3 .

[0102] The dielectric layer may comprise an oxide having nitrogen and a nitrogen / oxygen ratio greater than or equal to 0.01 or 0.05. In this case, its hydrogen concentration can be arbitrary. It may be composed of, or contain, silicon oxide having nitrogen and a nitrogen / oxygen ratio between 0.01 and 0.25 or between 0.05 and 0.1.

[0103] In the case where the thin layer is composed of a ferroelectric material having a Curie temperature below 1000 °C and typically between 600 °C and 1000 °C, the structure can be manufactured without exposing the thin layer to a temperature higher than the Curie temperature and thus maintaining its permanent polarization.

[0104] For example, a plurality of supports 2 are produced, which comprise a silicon-based substrate 6 having a resistivity of 3000 ohm·cm, and on the silicon-based substrate 6, a trapping layer 3 made of polycrystalline silicon with a thickness of 1 μm and formed by LPCVD, and a dielectric layer made of silicon oxide with a thickness of 300 nm and formed by PECVD technology are successively produced.

[0105] A densification annealing stage of the stack is applied to the first batch of supports thus produced at a temperature of 600 °C for 1 hour in an oxygen-rich atmosphere having less than 5 ppm of hydrogen.

[0106] The second batch and the third batch are each exposed to the densification annealing stage according to the invention at a temperature between 800 °C and 900 °C for at least 1 hour, said densification annealing stage being oxygen-rich and having less than 5 ppm of hydrogen.

[0107] After the densification annealing stage, the hydrogen concentration in the trapping layer ("H trapped - after densification") and the dielectric layer ("H dielectric") are measured.

[0108] Using the Smart Cut TM method, a thin surface layer 5 made of lithium tantalate is transferred onto each of the batches of supports 2. The layer is prepared such that it is finally 600 nm thick. The steps of manufacturing the structure include a moderate annealing not exceeding 600 °C. On the three batches of structures thus prepared, the hydrogen concentration in the trapping layer 3 ("H trapped - structure"), the second harmonic ("HD2" - for an applied signal of 15 dBm), and the resistivity distribution of the support 2 are measured to determine the quality factor ("HQF"). Note that this HQF value allows an estimate of the desired, compatible values of the RF performance of the structure.

[0109] The average results of the first batch, the second batch, and the third batch are shown in the following table:

[0110] Table 1

[0111]

[0112]

[0113] It can be seen that the RF performance level of the structure of the first batch, which has been processed with the prior art, is much lower than expected (HD2 / HQF ratio is 65%). It can be seen that the hydrogen concentration in different layers exceeds the limit value, especially just after the densification annealing stage ("after densification") and in the capture layer 3 in the final structure ("structure").

[0114] On the contrary, the RF performance levels of the structures of the second batch and the third batch, which have been processed according to the present invention, are significantly at the expected levels (HD2 / HQF ratios are 83% and 100% respectively).

[0115] It can be seen that the hydrogen concentration in the capture layer 3 measured after the structure is fully manufactured is greater than the concentration measured just after the densification annealing stage. However, this concentration remains less than or equal to 10 18 at / cm 3 of the threshold value, which allows the RF performance to remain compatible. Even after being heat-treated during the manufacturing of structure 1, the hydrogen present in the dielectric layer does not migrate significantly towards the capture layer.

[0116] It should be noted that the thinner the capture layer, the more sensitive the structure 1 with the capture layer 3 below the dielectric layer 4 is to the hydrogen contained in this layer. In fact, for the same amount of hydrogen diffusing from the dielectric layer 4 to the capture layer 3, the hydrogen concentration in this capture layer is greater in a relatively thin capture layer than in a relatively thick capture layer. Therefore, the solution of the present invention is particularly advantageous when the capture layer is less than 1 micron or 750 nm thick or less than or equal to 500 nm thick. In such a structure with a relatively thin capture layer less than 1 micron, in particular, a barrier layer or SiO N layer that can limit hydrogen diffusion and has a thickness of, for example, 20 - 50 nm can be integrated into the dielectric layer 4 as close as possible to the capture layer. For example, a silicon oxide layer can be formed on the capture layer, and this layer can be prepared using a nitrogen-based plasma to surface-incorporate the nitrogen before bonding it to another part of the dielectric layer 4 provided on the donor substrate side. Thus, a barrier layer made of nitrogen-rich SiO2 is formed on the surface thickness of the oxide layer, which prevents the hydrogen contained in the rest of the dielectric layer 4 from diffusing towards the capture layer.

[0117] As a reminder, the RF performance of a structure has a deterministic impact on the quality factor of components formed on that structure. Thus, in a further observation, the Applicant has verified that the anti-resonant conductance of resonators formed on a structure produced using the method according to the invention is directly related to the RF performance of that structure. Such resonators can be formed by cross-combs formed on a substrate identical or similar to those of the above-mentioned Batch 1 or Batch 2. The quality factor of such resonators is generally determined as the ratio between the resistance at the anti-resonant frequency and the bandwidth greater than half of that resistance. On resonators produced on the structures of Batch 2 and Batch 3 according to the invention, this quality factor has been evaluated as being much higher than that of resonators produced on the structures of Batch 1.

[0118] Of course, the present invention is not limited to the described embodiments, and variations can be added without departing from the scope of the invention as defined by the claims.

[0119] In particular, the thin layer 5 can comprise or be formed of a ferroelectric material, such as LiTaO3, LiNbO3, LiAlO3, BaTiO3, PbZrTiO3, KNbO3, BaZrO3, CaTiO3, PbTiO3 or KTaO3.

[0120] The donor substrate from which the thin layer 5 is obtained can take the form of a circular wafer of standardized dimensions, such as 150 mm or 200 mm in diameter. However, the present invention is in no way limited to these dimensions or this shape. The donor substrate can already have been removed from an ingot of ferroelectric material, the removal having been carried out such that the donor substrate has a predetermined crystal orientation, or the donor substrate can even comprise a layer of ferroelectric material bonded to a substrate support.

[0121] The crystal orientation of the thin ferroelectric material layer can be selected according to the intended application. Thus, for LiTaO3 materials, it is common practice to select an orientation between 30° and 60° XY, or between 40° and 50° XY, particularly in the case where it is intended to use the properties of the thin layer to form a surface acoustic wave (SAW) filter. With regard to LiNbO3 materials, it is common practice to select an orientation of approximately 128° XY. However, the present invention is in no way limited to a specific crystal orientation.

Claims

1. A semiconductor structure (1), the semiconductor structure (1) comprising: - A base substrate (6); - A capture layer (3), the capture layer (3) being located on the base substrate (6) and having a hydrogen concentration of less than 10 18 at / cm 3 ; - A dielectric layer (4) disposed on the capture layer (3), the dielectric layer (4) comprising silicon oxide having nitrogen, wherein the nitrogen / oxygen ratio is greater than 0.01; - A thin layer (5) located on the dielectric layer (4), the thin layer (5) being composed of a ferroelectric material.

2. The semiconductor structure (1) according to claim 1, wherein, The dielectric layer (4) consists of silicon oxide SiO N over its entire thickness, where the nitrogen / oxygen ratio is greater than or equal to 0.

01.

3. The semiconductor structure (1) according to claim 1, wherein, The silicon oxide SiO of the dielectric layer (4) N The portion of the thickness has nitrogen, where the nitrogen / oxygen ratio is less than or equal to 0.

25.

4. The semiconductor structure (1) according to claim 1, wherein, The thin layer (5) is made of LiTaO3 or LiNbO3.

5. The semiconductor structure (1) according to claim 4, wherein, The thin layer (5) is made of LiTaO3 and has an orientation between 30° and 60° XY, or an orientation between 40° and 50° XY.

6. The semiconductor structure (1) according to claim 4, wherein, The thin layer (5) is made of LiNbO3 and has an orientation substantially equal to 128° XY.

7. The semiconductor structure (1) according to claim 1, wherein, The base substrate (6) is made of single crystal silicon.

8. The semiconductor structure (1) according to claim 1, wherein, The base substrate (6) has a resistivity greater than 1000 ohm·cm.

9. The semiconductor structure (1) according to claim 1, wherein, The base substrate (6) has a resistivity greater than 2000 ohm·cm.

10. The semiconductor structure (1) according to claim 1, wherein, The capture layer (3) is formed of a polysilicon layer.

11. The semiconductor structure (1) according to claim 1, wherein, The capture layer (3) has a thickness less than 1 micron.

12. The semiconductor structure (1) according to claim 10, wherein, The capture layer (3) has a thickness less than 500 nm.

13. The semiconductor structure (1) according to claim 1, wherein, The thin layer (5) carries a surface acoustic wave filter.

14. The semiconductor structure (1) according to claim 1, the semiconductor structure (1) being in the form of a circular plate.

15. The semiconductor structure (1) according to claim 1, wherein, The dielectric layer (4) has a hydrogen concentration of less than 10 20 at / cm 3 .

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