Wafer thinning method and semiconductor device thereof
By using a grinding film instead of bonded slides during wafer thinning, combined with sputtering process and laser annealing, the problems of fragmentation risks and organic matter contamination are solved, effectively controlling warpage and improving wafer stability are achieved.
Patent Information
- Application Number
- CN202510449756.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-10
- Publication Date
- 2025-06-20
AI Technical Summary
In the prior art, in the process of thinning of ultra-thin wafers used in silicon carbide (SiC) semiconductor power devices, there is a risk of fragmentation and organic contamination during back metal deposition.
Instead of the bonded slide, a thinning process is performed through the second surface to form a wafer of target thickness and warpage, and a first sputtering process and laser annealing are performed in an environment of vacuum and preset temperature to reduce warpage. Subsequently, the back metal layer is formed and the abrasive film is removed.
It effectively reduces the risk of fragmentation and organic matter contamination during the back process, controls warpage within the target range, and ensures the stability and quality of the wafer in subsequent processes.
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Figure CN120184008A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and particularly to a wafer thinning method and a semiconductor device thereof. Background Art
[0002] A wafer is a very important raw material in industrial manufacturing fields such as integrated circuits (ICs), microelectromechanical systems (MEMS), and advanced packaging (AP). Generally, it needs to be thinned before subsequent processing or packaging processes.
[0003] Currently, in order to solve the problem of accessing ultra-thin (≤120um) wafers for silicon carbide (SiC) semiconductor power devices, the industry generally adopts a bonding method to improve the strength and flatness of the substrate. However, the bonding process usually has the disadvantage of high cost (requiring the introduction of process machines, bonding adhesives, bonding carriers, and porous ceramic disks). At the same time, since silver metal is usually used in the backside metallization of power devices, oxidation and contamination are very likely to occur during the debonding process.
[0004] Therefore, how to reduce the risk of fragmentation while reducing the organic contamination during backside metal deposition has become one of the technical problems that need to be solved urgently by the workers in this field. Summary of the Invention
[0005] Based on this, in view of the technical problems in the prior art, it is necessary to provide a wafer thinning method that can at least reduce the risk of fragmentation during backside processes and the organic contamination during backside metal deposition.
[0006] In a first aspect, the present application provides a wafer thinning method, including: pasting a grinding film on a first surface of the wafer; the grinding film is used to support the wafer; the wafer includes a second surface opposite to the first surface;
[0007] Performing a thinning process on the wafer via the second surface; wherein, the thinned wafer has a target thickness and a first warpage;
[0008] After forming a seed metal layer covering the second surface by a first sputtering process in an environment of vacuum and a preset temperature, performing a laser annealing process to reduce the first warpage to within a target range;
[0009] Performing a second sputtering process on the top surface of the seed metal layer to form a backside metal layer at a preset temperature;
[0010] Removing the grinding film.
[0011] In the wafer thinning method of the above embodiments, based on the characteristics of high hardness and low warpage of silicon carbide (SiC) wafers, a grinding film is used instead of a bonding carrier. After thinning, the wafer with the target thickness and the first warpage degree can still be vacuum adsorbed. At the same time, the front surface of the wafer (i.e., the first surface) is completely protected by the grinding film during the sputtering process (the first sputtering process and the second sputtering process), and the deposited metal will not be contaminated by the organic matter required for the bonding process.
[0012] In addition, through the synergistic effect of the first sputtering process and the laser annealing process, the warpage degree (the first warpage degree) is controlled within the process allowable range and reduced to the target range, so that while the film has no change and there is no residual glue on the wafer surface, the problem that the grinding film cannot balance the warpage after thinning can be effectively alleviated, and the risk of fragmentation during the back process is reduced.
[0013] In some embodiments, the preset temperature range is 100°C - 120°C.
[0014] In some embodiments, before the first sputtering process, it includes:
[0015] In the SEZ machine, a cleaning process is performed on the wafer.
[0016] In some embodiments, the first sputtering process lasts for a first preset duration;
[0017] The second sputtering process lasts for a second preset duration;
[0018] The first preset duration is less than the second preset duration.
[0019] In some embodiments, the seed metal layer includes a composition of titanium, nickel, and silver.
[0020] In some embodiments, the target range is 950μm - 1050μm.
[0021] In some embodiments, the target thickness is 100μm - 120μm.
[0022] In some embodiments, the thickness range of the grinding film is 180μm - 280μm.
[0023] In some embodiments, the material of the grinding film includes polyimide and / or polyurethane.
[0024] In a second aspect, the present application further provides a semiconductor device, including a wafer prepared by the wafer thinning method in any of the above embodiments. The semiconductor device of the above embodiments and the wafer thinning method provided by the present invention are based on the same inventive concept. Therefore, the semiconductor device using this wafer has all the advantages of the wafer thinning method provided by the present invention, and will not be elaborated here one by one. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0026] Figure 1 It is a process demonstration diagram of a wafer thinning method in the prior art;
[0027] Figure 2 It is a flowchart of a wafer thinning method provided in an embodiment;
[0028] Figure 3 It is a process demonstration diagram of a wafer thinning method provided in an embodiment;
[0029] Figure 4 It is a schematic cross-sectional view of the obtained structure after pasting the grinding film 20 in step S102 of the wafer thinning method provided in an embodiment;
[0030] Figure 5 It is a schematic view of the obtained structure morphology after steps S104 and S106 in the wafer thinning method provided in an embodiment;
[0031] Figure 6 It is a schematic cross-sectional view of the obtained structure after step S108 in the wafer thinning method provided in an embodiment;
[0032] Figure 7 It is a comparison diagram of the morphology of pasting and removing the grinding film on the front side of the wafer.
[0033] Description of the reference numerals:
[0034] 10. Wafer; 20. Grinding film; 31. Seed metal layer; 32. Back metal layer. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0035] In order to facilitate the understanding of the present application, the following will describe the present application more comprehensively with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art belonging to the technical field of the present application. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.
[0037] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be denoted as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for instance, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0038] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may also include other orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.
[0039] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprises" and / or "comprising" are used in this specification, the presence of the stated features, integers, steps, operations, elements, and / or components can be ascertained, but one or more other features, integers, steps, operations, elements, components, and / or groups thereof are not precluded from existence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.
[0040] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application, so that variations in the shapes shown can be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular typically has rounded or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present application.
[0041] Please refer to Figure 1 , Figure 1 which is a process demonstration diagram of a prior art wafer thinning method. The existing wafer thinning methods mainly include: pasting a bonding carrier on the front surface (the first surface) of the wafer by an adhesive method to implement the front surface support process. Flip the wafer and perform chemical mechanical polishing (CMP) on the back surface (the second surface). Subsequently, clean the wafer and perform process steps such as high-temperature degassing, sputter coating, and cooling to form a seed metal layer. Flip the wafer again, perform a debonding process in advance, and then form a back metal layer by thick metal sputtering.
[0042] Although this process flow reduces the oxidation of silver metal in the back metal layer and the risk of contamination during the debonding process, since the sputtering process requires high-temperature degassing and cooling, it causes the accumulation of internal thermal stress in the wafer. After the thinned wafer loses the bonding carrier, it cannot obtain good physical support and forms warps of various asymmetric shapes. When the warpage degree is too large, the wafer becomes difficult to adsorb and fix. In addition to the risk of fragmentation, it may cause the subsequent back surface process to not proceed smoothly.
[0043] Based on this, please refer to Figure 2 , the present application provides a wafer thinning method, including: step S102 - step S110. Among them, the semiconductor structure obtained after passing through steps S102 - S110 can be referred to Figure 6 . For the convenience of understanding the present application, Figure 6 an example of a semiconductor structure prepared by using the preparation method of the present application is provided. There can be other suitable examples of the semiconductor structure prepared by the present application, and the present application does not limit them herein.
[0044] The following combines the attached Figures 3 - 7The following specific embodiments further elaborate on the wafer thinning method proposed by the present invention. The advantages and features of the present invention will become clearer based on the following description and the claims. It should be noted that the attached drawings are in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.
[0045] Step S102: Paste the grinding film 20 on the first surface 10a of the wafer 10. The specific process demonstration is as Figure 3 (1); The grinding film 20 is used to support the wafer 10; The wafer 10 includes a second surface 10b facing away from the first surface 10a. The cross-sectional schematic diagram of the obtained structure is as Figure 4 shown.
[0046] Among them, in some embodiments, the thickness range of the grinding film 20 is 180μm - 280μm. For example, 180μm, 205μm, 230μm, 255μm or 280μm.
[0047] Here, in this embodiment, the thickness of the grinding film 20 is 230μm. Since silicon carbide (SiC) has a large stress, using a 230μm, relatively thick grinding film 20 can effectively release its stress and ensure a certain mechanical support strength, reducing the breakage rate of the wafer 10 in subsequent processes.
[0048] It should be understood that the functional elements pre-formed on or in the substrate near the first surface 10a of the wafer 10 are omitted because they are not the focus of the invention of this application.
[0049] Furthermore, in some embodiments, the material of the grinding film 20 includes polyimide (PI) and / or polyurethane (PU).
[0050] Exemplarily, the above structure is formed by using a film laminating device.
[0051] Among them, polyimide (PI) is mainly used for structural support; polyurethane (PU) is mainly used as a stress buffer layer. In this embodiment, the grinding film 20 can be a single-layer structure, that is, it only includes any one of polyimide (PI) and polyurethane (PU), or it can be a laminated structure formed by two materials. When the grinding film 20 is a laminated structure, polyimide is used to provide rigid support, and polyurethane is used to achieve stress buffering. Therefore, the specific structure can be set according to the actual situation and will not be specifically limited here.
[0052] Step S104: Perform a thinning process on the wafer 10 through the second surface 10b. The specific process demonstration is as Figure 3 (2); Among them, the thinned wafer 10 has a target thickness and a first warpage degree.
[0053] Further, in some embodiments, the target thickness is 100 μm - 120 μm. For example, it can be 100 μm, 110 μm, or 120 μm. Here, in this embodiment, the target thickness is 110 μm, which is mainly used for high-power devices.
[0054] Exemplarily, the CMP process can be adopted to thin the entire wafer 10 to 110 μm. Compared with the Taiko thinning process, the CMP process does not require circumferential cutting, and the complexity and cost of the overall process are lower. In the grinding process, both the rate and precision can be more accurately controlled, thereby effectively improving the yield rate of the wafer 10 and the utilization rate of the effective area.
[0055] Step S106: After forming the seed metal layer 31 covering the second surface by using the first sputtering process in an environment of vacuum and a preset temperature, perform a laser annealing process to reduce the first warpage to within the target range. The specific process demonstration is as Figure 3 (3)- Figure 3 (5).
[0056] Among them, since the grinding film 20 is a conventional material, it can withstand 100°C - 120°C. In some embodiments, the preset temperature range is 100°C - 120°C. For example, it can be 100°C, 110°C, or 120°C.
[0057] Among them, in some embodiments, the target range is 950 μm - 1050 μm. For example, it can be 950 μm, 1000 μm, or 1050 μm.
[0058] Specifically, after being thinned in step S104, the internal stress of the wafer 10 is very large, and the grinding film 20 cannot balance the stress on the wafer after thinning. In the embodiments mentioned in this application, the thinned wafer 10 has a first warpage of approximately 2800 μm. Therefore, in order to optimize the warpage of the above-mentioned laminated wafer 10 to the target range, a low-temperature first sputtering process with a shorter single-chip process time is adopted in step S106, combined with rapid thermal annealing to optimize the warpage of the wafer.
[0059] Specifically, in some embodiments, before the first sputtering process, it includes: performing a cleaning process on the wafer 10 in a SEZ (Soft Etch Zone) machine.
[0060] Exemplarily, in the conventional sputtering process, before sputtering coating, the wafer 10 needs to be loaded into a degassing chamber for high-temperature degassing process. After completing the metal sputtering process, it is added to a cooling chamber to wait for the wafer 10 to cool down.
[0061] In this embodiment, first, in the SEZ machine, the wafer 10 is wet-etched and cleaned to remove the surface adsorbed particles generated by grinding. Subsequently, the cleaned wafer 10 is sent into the vacuum sputtering chamber, and the conventional high-temperature degassing (Degas) and soft etchant (HSE) cleaning steps are cancelled to prevent the temperature from exceeding the maximum tolerance temperature of 120 °C of the grinding film, which may affect the film reliability. The mechanical pump is started to pump the chamber to a vacuum state, and then helium gas is introduced into the chamber, and the seed metal layer 31 is deposited on the second surface 10b by magnetron sputtering coating. After the sputtering process is completed, without waiting for cooling, the laser annealing process is directly carried out, thereby further shortening the single-chip process time.
[0062] Figure 5 The structural morphology obtained after steps S104 and S106 is shown. After measurement, the first warpage degree decreases from the initial 2800 μm to about 1000 μm. After the seed metal process and laser annealing, the warpage problem of the thinned wafer 10 is significantly improved, and the wafer 10 can still be fixed by vacuum adsorption to ensure the smooth progress of the subsequent backside metal process.
[0063] The above embodiment successfully improves the warpage problem of the wafer 10 without adding extra process steps, thereby reducing the debris risk in the subsequent process and improving the process stability.
[0064] Further, in some embodiments, the seed metal layer includes a composition of titanium (Ti), nickel (Ni), and silver (Ag).
[0065] In the above embodiment, in order to enhance the adhesion between nickel (Ni), silver (Ag) and the second surface 10b, titanium (Ti) can be sputtered first as an adhesion layer to increase the adhesion between the subsequent metal and the second surface 10b and prevent nickel (Ni), silver (Ag) from diffusing into the silicon carbide (SiC) material, thereby improving the quality of the backside metal layer.
[0066] Step S108: At a preset temperature, a second sputtering process is performed on the top surface of the seed metal layer 31 to form the backside metal layer 32. The specific process demonstration is as Figure 3 (6)- Figure 3 (7).
[0067] Exemplarily, similar to step S106, the wafer 10 is first cleaned, and the degassing, HSE cleaning, and cooling steps are also cancelled. The backside metal layer 32 is formed by sputtering coating. The schematic cross-sectional view of the obtained structure is as Figure 6 shown.
[0068] Further, in some embodiments, the first sputtering process lasts for a first preset duration;
[0069] The second sputtering process lasts for a second preset duration;
[0070] The first preset duration is less than the second preset duration.
[0071] Specifically, the first sputtering process and the second sputtering process are similar in terms of operating parameters and procedures. However, in order to effectively reduce the pollution risk during the deposition of the back metal layer 32 and ensure sufficient deposition thickness, a longer sputtering time and evacuation duration are required when coating this layer. The seed metal layer 31 is usually thinner and has lower requirements for the coating duration, and the time required for the process is shorter. Therefore, the first preset duration is less than the second preset duration.
[0072] Step S110: Remove the grinding film 20. The specific process demonstration is as Figure 3 (8).
[0073] Exemplarily, flip the wafer 10 so that the grinding film 20 faces upward, and use a film peeling device to remove the grinding film 20. The wafer thinning method provided in this application skips the oxygen ion cleaning process and the high-temperature and high-humidity (HAST) test that takes 96 hours. Compared with the traditional process, the process flow is greatly shortened. The entire thinning process only takes 72 hours to complete starting from the film pasting process. In addition, no residual glue is found on the front side of the wafer after the film is removed.
[0074] It should be understood that although Figure 1 the steps in the flowchart of Figure 1 are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, the execution of these steps has no strict order restriction, and these steps can be executed in other orders. Moreover,
[0075] Please refer to Figure 7 In some embodiments, the present application provides a semiconductor device including a wafer prepared by the wafer thinning method in any of the above embodiments. Figure 7 It is a topographic contrast diagram of pasting and removing the grinding film on the front side (the first surface) of the wafer. It can be seen from the figure that after all the processes are completed using this solution, there is no residual glue on the front side of the wafer, and the back metal has high robustness.
[0076] In addition, compared with the traditional bonding carrier process which is prone to metal interface contamination due to the penetration of organic adhesives, the wafer thinning method provided in the present application utilizes the back-side process of the power device without the need for photolithography, and uses a grinding film as both a support and protective material, effectively avoiding the risk of back-side metal contamination during the debonding process. At the same time, the selection of conventional grinding films and low-temperature magnetron sputtering processes (the first sputtering process and the second sputtering process) can effectively reduce the process cost of semiconductor devices based on the wafer, providing a new technical path for the integration of high-density power modules of semiconductor devices.
[0077] In the above embodiments, the wafer thinning method and the semiconductor device provided by the present application have the following unexpected technical effects:
[0078] Compared with the traditional bonding process, which has the inherent defects of organic matter penetration and contamination of the metal interface, the risk of residual glue, and film denaturation under high-temperature processes, the wafer thinning method provided in this application uses abrasive film as the supporting and protective material on the front side of the wafer. The film sticking and peeling methods are simple and compatible with existing production line equipment, reducing the difficulty and cost of the entire process.
[0079] In addition, in order to address the problems of oxidation and contamination in the traditional debonding process, as well as the accumulation of thermal stress in the back metal layer process after debonding, which increases the risk of fragmentation, the film peeling process of the grinding film is placed after the back metal layer process, so that the grinding film can protect the wafer during the entire process and provide mechanical support. At the same time, by shortening the low-temperature magnetron sputtering process time and combining the laser annealing process, the problem of warping after thinning that cannot be balanced when the grinding film replaces bonding is alleviated.
[0080] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0081] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A wafer thinning method, characterized in that: For silicon carbide wafers, including: A grinding film is attached to the first surface of the wafer; the grinding film is used to support the wafer; the wafer includes a second surface opposite to the first surface; Performing a thinning process on the wafer via the second surface; wherein the wafer after thinning has a target thickness and a first warpage; In a vacuum environment and a preset temperature, a seed metal layer covering the second surface is formed by a first sputtering process, and then a laser annealing process is performed to reduce the first warpage to a target range; At the preset temperature, performing a second sputtering process on the top surface of the seed metal layer to form a back metal layer; The abrasive film is removed.
2. The wafer thinning method according to claim 1, characterized in that: The preset temperature range is 100°C-120°C.
3. The wafer thinning method according to claim 1, characterized in that: Prior to the first sputtering process, the process includes: A cleaning process is performed on the wafer in the SEZ machine.
4. The wafer thinning method according to claim 3, characterized in that: The first sputtering process lasts for a first preset time period; The second sputtering process lasts for a second preset time period; The first preset time length is shorter than the second preset time length.
5. The wafer thinning method according to claim 3, characterized in that: The seed metal layer includes a combination of titanium, nickel and silver.
6. The wafer thinning method according to claim 1, characterized in that: The target range is 950 μm-1050 μm.
7. The wafer thinning method according to any one of claims 1 to 6, characterized in that: The target thickness is 100 μm-120 μm.
8. The wafer thinning method according to any one of claims 1 to 6, characterized in that: The thickness of the grinding film ranges from 180 μm to 280 μm.
9. The wafer thinning method according to any one of claims 1 to 6, characterized in that: The material of the grinding film includes polyimide and / or polyurethane.
10. A semiconductor device, characterized in that: include: A wafer prepared by the wafer thinning method as described in claims 1-9.