Device preparation method and semiconductor device

Abstract

The invention provides a device preparation method and a semiconductor device. The manufacturing method of the device comprises the steps that a first electric conduction piece and a first heat conduction piece in a first chip are synchronously formed, and the first electric conduction piece and the first heat conduction piece are electrically isolated; synchronously forming a second electric conduction piece and a second heat conduction piece in a second chip, and electrically isolating the second electric conduction piece from the second heat conduction piece; and bonding the first chip and the second chip so as to enable the first heat conduction piece and the second heat conduction piece to be in thermal communication and form a heat conduction channel.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a method for fabricating a device and a semiconductor device. Background Art

[0002] When a semiconductor device is operating, it usually generates heat and causes the temperature to rise. If the semiconductor device cannot be cooled in time, it will cause the semiconductor device to operate in a high-temperature environment for a long time, resulting in performance degradation or failure.

[0003] Therefore, there is a need to dissipate heat from the semiconductor device. Summary of the Invention

[0004] One object of the present disclosure is to provide a method for fabricating a device and a semiconductor device.

[0005] According to a first aspect of the present disclosure, there is provided a method for fabricating a device, including:

[0006] simultaneously forming a first conductive member and a first heat conductive member in a first chip, wherein the first conductive member and the first heat conductive member are electrically isolated;

[0007] simultaneously forming a second conductive member and a second heat conductive member in a second chip, wherein the second conductive member and the second heat conductive member are electrically isolated; and

[0008] bonding the first chip and the second chip so that the first heat conductive member is in thermal communication with the second heat conductive member to form a heat conduction path.

[0009] In some embodiments, simultaneously forming the first conductive member and the first heat conductive member in the first chip includes:

[0010] forming a plurality of first vias in a first predetermined layer of the first chip and filling the plurality of first vias with a conductive and heat conductive material to simultaneously form a first conductive portion of the first conductive member and a first heat conductive portion of the first heat conductive member; and / or

[0011] forming one or more layers of first wirings on a second predetermined layer of the first chip to simultaneously form a second conductive portion of the first conductive member and a second heat conductive portion of the first heat conductive member, wherein the one or more layers of first wirings extend in a plane perpendicular to the thickness direction.

[0012] In some embodiments, simultaneously forming the second conductive member and the second heat conductive member in the second chip includes:

[0013] forming a plurality of second vias in a third predetermined layer of the second chip and filling the plurality of second vias with a conductive and heat conductive material to simultaneously form a third conductive portion of the second conductive member and a third heat conductive portion of the second heat conductive member; and / or

[0014] Form one or more second wirings on a fourth preset layer of the second chip to synchronously form a fourth conductive part of the second conductive member and a fourth heat-conductive part of the second heat-conductive member, wherein the one or more second wirings extend in a plane perpendicular to the thickness direction.

[0015] In some embodiments, bonding the first chip and the second chip includes:

[0016] Form a bonding layer on a first side of the first chip and / or a second side of the second chip, and bond the first chip and the second chip through the bonding layer, wherein the first side of the first chip is adjacent to the second side of the second chip, and the first heat-conductive member and the second heat-conductive member are in thermal communication via bonding pads in the bonding layer.

[0017] In some embodiments, a part of a surface of one of the first chip and the second chip adjacent to the other is exposed to the environment to form an exposed portion, wherein a heat-conductive member in the chip having the exposed portion is partially located in the exposed portion to be partially exposed to the environment.

[0018] In some embodiments, the method for manufacturing the device further includes:

[0019] Form a third heat-conductive member on an exposed surface of the exposed portion, wherein the third heat-conductive member is in thermal communication with the heat-conductive member in the chip having the exposed portion.

[0020] In some embodiments, the method for manufacturing the device further includes:

[0021] Determine the position of a hot spot region in the first chip and / or the second chip through thermal simulation, and determine the positions of the first heat-conductive member and the second heat-conductive member based on the position of the hot spot region through thermal simulation, so that the heat conduction channel conducts the heat of the hot spot region.

[0022] According to a second aspect of the present disclosure, there is provided a semiconductor device, including:

[0023] A first chip, the first chip includes a patterned first functional layer, a first part of the patterned first functional layer is configured to be used as a first conductive member, and a second part of the patterned first functional layer is configured to be used as a first heat-conductive member, wherein the first conductive member is electrically isolated from the first heat-conductive member;

[0024] A second chip, the second chip being bonded to one side of the first chip, the second chip including a patterned second functional layer, a first portion of the patterned second functional layer being configured to serve as a second conductive member, a second portion of the patterned second functional layer being configured to serve as a second heat conductive member, wherein the second conductive member is electrically isolated from the second heat conductive member,

[0025] wherein the first heat conductive member is in thermal communication with the second heat conductive member and forms a heat conduction channel.

[0026] In some embodiments, the first heat conductive member and the first conductive member are formed synchronously, and the second heat conductive member and the second conductive member are formed synchronously.

[0027] In some embodiments, the first functional layer includes a first substrate, a first device layer, and a first wiring layer stacked in sequence in the thickness direction, and the second functional layer includes a second substrate, a second device layer, and a second wiring layer stacked in sequence in the thickness direction,

[0028] wherein the second wiring layer is disposed face to face with the first substrate or the second substrate is disposed face to face with the first substrate.

[0029] In some embodiments, the first heat conductive member includes a first heat conductive portion and / or a second heat conductive portion, and the second heat conductive member includes a third heat conductive portion and / or a fourth heat conductive portion,

[0030] wherein the first heat conductive portion is filled in a first through hole opened in at least one of the first substrate, the first device layer, and the first wiring layer,

[0031] The first wiring layer includes one or more layers of first wirings extending in a plane perpendicular to the thickness direction, wherein at least a portion of the one or more layers of first wirings is configured to serve as the second heat conductive portion,

[0032] The third heat conductive portion is filled in a second through hole opened in at least one of the second substrate, the second device layer, and the second wiring layer,

[0033] The second wiring layer includes one or more layers of second wirings extending in a plane perpendicular to the thickness direction, wherein at least a portion of the one or more layers of second wirings is configured to serve as the fourth heat conductive portion.

[0034] In some embodiments, a portion of the surface of one of the first chip and the second chip adjacent to the other is exposed to the environment to form an exposed portion, wherein the heat conductive member in the chip having the exposed portion is partially located in the exposed portion to be partially exposed to the environment.

[0035] Other features and advantages of the present disclosure will become clearer from the following detailed description of the exemplary embodiments of the present disclosure with reference to the accompanying drawings. Description of the Drawings

[0036] The drawings forming a part of the specification depict embodiments of the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.

[0037] With reference to the accompanying drawings, the present disclosure can be more clearly understood from the following detailed description, where:

[0038] Figure 1 A schematic diagram of the temperature distribution before and after a reasonable layout of the chip in an example is shown;

[0039] Figure 2 A schematic diagram of heat dissipation of the chip in an example is shown;

[0040] Figure 3 A schematic flow diagram of a method for manufacturing a device according to an exemplary embodiment of the present disclosure is shown;

[0041] Figure 4 A schematic diagram of synchronously forming a first conductive part and a first heat-conducting part according to an exemplary embodiment of the present disclosure is shown;

[0042] Figure 5 A schematic diagram of synchronously forming a third conductive part and a third heat-conducting part according to an exemplary embodiment of the present disclosure is shown;

[0043] Figure 6 A schematic diagram of synchronously forming a second conductive part and a second heat-conducting part according to an exemplary embodiment of the present disclosure is shown;

[0044] Figure 7 A schematic diagram of synchronously forming a second conductive part and a second heat-conducting part according to another exemplary embodiment of the present disclosure is shown;

[0045] Figure 8 A schematic diagram of synchronously forming a fourth conductive part and a fourth heat-conducting part according to an exemplary embodiment of the present disclosure is shown;

[0046] Figure 9 A schematic diagram of synchronously forming a fourth conductive part and a fourth heat-conducting part according to another exemplary embodiment of the present disclosure is shown;

[0047] Figure 10 A schematic diagram of the structure of a semiconductor device according to an exemplary embodiment of the present disclosure is shown;

[0048] Figure 11A schematic structural diagram of a semiconductor device according to another exemplary embodiment of the present disclosure is shown;

[0049] Figure 12 A schematic structural diagram of a semiconductor device according to yet another exemplary embodiment of the present disclosure is shown;

[0050] Figure 13 A schematic flowchart of constructing a heat conduction channel through thermal simulation according to an exemplary embodiment of the present disclosure is shown.

[0051] Note that in the embodiments described below, sometimes the same reference numerals are used commonly between different drawings to denote the same parts or parts having the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0052] For ease of understanding, the positions, sizes, ranges, etc. of the various structures shown in the drawings and the like sometimes do not represent the actual positions, sizes, ranges, etc. Therefore, the disclosed invention is not limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. In addition, the drawings do not have to be drawn to scale, and some features may be enlarged to show the details of specific components. Detailed Embodiments

[0053] Now, various exemplary embodiments of the present disclosure will be described in detail with reference to the drawings. It should be noted that unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure.

[0054] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way a limitation on the present disclosure or its application or use. Those skilled in the art will understand that they merely illustrate exemplary ways in which the present disclosure can be implemented, rather than exhaustive ways.

[0055] Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods, and devices should be regarded as part of the specification.

[0056] Three-dimensional integrated chips have the advantages of high density, high performance, and small volume, and are thus widely used in a variety of modern electronic devices. In three-dimensional integrated chips, as the number of stacked structures increases, the thermal resistance between the hot spots inside the chip and the outer surface increases significantly, hindering the effective dissipation of heat, making the heat generated during chip operation easily accumulate inside, and there may be overheating phenomena, resulting in performance degradation and reduced reliability.

[0057] In some examples, the components in the chip can be reasonably arranged to make the hot spots in the chip evenly distributed and reduce thermal coupling. For example, Figure 1 Figures (a) and (b) in Figure 1 respectively show the schematic diagrams of the chip temperature before and after the optimized layout of the chip. Among them, Figure 1 Figure (c) in Figure 1 is the grayscale schematic diagram corresponding to Figure (a) in Figure 1 ; Figure (d) in Figure 2 is the grayscale schematic diagram corresponding to Figure (b) in

[0058] Although this method can alleviate the problem of excessive local temperature caused by overly concentrated hot spot distribution to a certain extent, the heat in each hot spot area is still likely to accumulate inside the chip, resulting in poor heat dissipation. Or, in some examples, as shown in Figure 2 thermal interface materials (TIM) 3, integrated heat sinks 4, heat sinks 5, etc. can be used on the ball grid array (BGA) substrate 1 and silicon substrate 2 of the chip to reduce the thermal resistance from the chip to the boundary, so as to assist in heat dissipation on the chip surface. However, this method of dissipating heat on the chip surface by additionally introducing TIM materials, heat sinks and heat sinks is difficult to effectively handle the heat accumulated inside the chip. Or, in some examples, microchannel technology can also be used to generate channels for the coolant to flow inside or around the chip, and the flowing coolant is used to cool the chip. However, this method additionally introduces a microchannel processing technology, which has great process difficulty and high cost.

[0058] To solve the above problems, the present disclosure provides a device manufacturing method, in which a corresponding heat conducting member is formed synchronously while forming the conductive member of the chip to construct a heat conducting channel, without introducing additional process steps to separately form the heat conducting member, which can effectively reduce the heat accumulation while saving the device manufacturing cost, reduce the thermal resistance, and improve the heat dissipation ability of the chip.

[0059] In an exemplary embodiment of the present disclosure, as shown in Figures 3 to 4 , Figures 6 to 7 , Figures 10 to 12 the device manufacturing method may include:

[0060] Step S110, synchronously forming the first conductive member 130 and the first heat conducting member 140 in the first chip 100.

[0061] Among them, the synchronously formed first conductive member 130 and first heat conducting member 140 may be electrically isolated to avoid short circuits in related circuits.

[0062] In some embodiments, as shown in Figure 4 , Figures 10 to 12As shown, the first heat conducting member 140 may include a first heat conducting portion 141 extending in the thickness direction, such that heat may be conducted in the thickness direction via the first heat conducting portion 141. Correspondingly, the first conducting member 130 formed synchronously with the first heat conducting member 140 may also include a first conducting portion 131 extending in the thickness direction.

[0063] In some embodiments, as Figure 4 shown, synchronously forming the first conducting member 130 and the first heat conducting member 140 in the first chip 100 may include: forming a plurality of first through holes 120 in a first preset layer 110 of the first chip 100, and filling the plurality of first through holes 120 with a conductive and heat conductive material to synchronously form the first conducting portion 131 of the first conducting member 130 and the first heat conducting portion 141 of the first heat conducting member 140.

[0064] Specifically, as Figure 4 shown in (a) of

[0065] Step S111, forming a patterned first anti-etching layer 10 on the first preset layer 110 of the first chip 100 by using a photolithography process.

[0066] Specifically, an anti-etching material may be deposited on the first preset layer 110. Then, a patterned first anti-etching layer 10 may be formed on the first preset layer 110 of the first chip 100 by using electron beam exposure or ion beam exposure and then developing. Alternatively, based on a first mask, a photolithography process may be used to transfer the pattern of the first mask to the anti-etching material to form a patterned first anti-etching layer 10. In this way, subsequently, the first conducting portion 131 of the first conducting member 130 and the first heat conducting portion 141 of the first heat conducting member 140 may be formed synchronously based on the first mask, without separately setting different masks for the formation of the first conducting portion 131 and the first heat conducting portion 141, reducing the preparation difficulty of the device and saving the preparation cost.

[0067] Furthermore, as Figure 4 shown in (b) of

[0068] Step S112, etching the first preset layer 110 under the protection of the first anti-etching layer 10 to form a plurality of first through holes 120.

[0069] In some embodiments, as Figure 4 shown in (b) of Figures 10 to 12 shown, the first preset layer 110 may be, for example, a first substrate 160 of the first chip 100. Among them, asFigure 4 in (b) of Figure 10 and Figure 12 As shown, only the first substrate 160 may be etched to form the first through hole 120 formed in the first substrate 160. Alternatively, as Figure 4 in (b) of Figure 11 shown, the first substrate 160 and the first device layer 170 of the first chip 100 may be etched in sequence to form the first through hole 120 formed in the first substrate 160 and the first device layer 170.

[0070] In some embodiments, as Figure 4 in (b) of Figure 11 shown, the first preset layer 110 may be, for example, the first wiring layer 180 of the first chip 100. Among them, the first wiring layer 180 may be etched to form the first through hole 120 formed in the first wiring layer 180.

[0071] Furthermore, as Figure 4 shown in (c), synchronously forming the first conductive member 130 and the first heat conductive member 140 in the first chip 100 may further include:

[0072] Step S113, filling the conductive and heat conductive material in a plurality of first through holes 120 to synchronously form the first conductive part 131 of the first conductive member 130 and the first heat conductive part 141 of the first heat conductive member 140.

[0073] Among them, the conductive and heat conductive material may include, for example, a metal material. Metal materials generally have relatively high thermal conductivity and electrical conductivity. By using metal materials to form the corresponding heat conductive members, the heat dissipation performance of the chip can be effectively improved without introducing additional heat conductive materials to form the heat conductive members, reducing the device manufacturing cost.

[0074] In some embodiments, as Figure 6 , Figure 7 and Figure 11 shown, the first heat conductive member 140 may include a second heat conductive part 142 extending in a plane parallel or coincident with the main plane of the first chip 100, or rather, the first heat conductive member 140 may include a second heat conductive part 142 extending in a plane perpendicular to the thickness direction, so that heat can be conducted in a plane perpendicular to the thickness direction via the second heat conductive part 142. Correspondingly, the first conductive member 130 formed synchronously with the first heat conductive member 140 may also include a second conductive part 132 extending in a plane perpendicular to the thickness direction. In some embodiments, the second heat conductive part 142 may be thermally connected to the first heat conductive part 141. As Figure 11 shown, the second heat conductive part 142 may be configured to thermally connect a plurality of first heat conductive parts 141.

[0075] In some embodiments, such as Figures 6 to 7 shown, synchronously forming the first conductive member 130 and the first heat conductive member 140 in the first chip 100 may include: forming one or more layers of first wirings on the second preset layer 150 of the first chip 100 to synchronously form the second conductive portion 132 of the first conductive member 130 and the second heat conductive portion 142 of the first heat conductive member 140, wherein the one or more layers of first wirings may extend in a plane perpendicular to the thickness direction.

[0076] Specifically, in some embodiments, such as Figure 6 shown in (a) to (c) of

[0077] Step S114, depositing a conductive and heat conductive material 30 in the form of a continuous thin film on the second preset layer 150;

[0078] Step S115, forming a patterned second anti-etching layer 40 on the conductive and heat conductive material 30 by using a lithography process;

[0079] Step S116, etching the portion of the conductive and heat conductive material 30 not covered by the second anti-etching layer 40 to form one or more layers of first wirings.

[0080] Wherein, a part of the one or more layers of first wirings may be configured to be used as the second conductive portion 132, and another part may be configured to be used as the second heat conductive portion 142. Thus, the second conductive portion 131 and the second heat conductive portion 142 can be synchronously formed.

[0081] In a specific example, the second anti-etching layer 40 may be formed only by photoresist, or may also be formed by materials such as deposited silicon nitride. In some embodiments, step S115 may include depositing an anti-etching material on the conductive and heat conductive material 30 and transferring the pattern of the second mask to the anti-etching material by using a lithography process based on the second mask to form the patterned second anti-etching layer 40. Considering that the remaining second anti-etching layer 40 after step S116 etches to form one or more layers of first wirings may affect the subsequent processes, in some embodiments, the remaining second anti-etching layer 40 may also be removed.

[0082] Or, in some other embodiments, such as Figure 7 shown in (a) to (c) of

[0083] Step S117, forming a patterned photoresist layer 50 on the second preset layer 150 of the first chip 100 by using a lithography process;

[0084] Step S118, depositing a conductive and heat-conductive material 30 in the form of a continuous thin film;

[0085] Step S119, using a lift-off process to remove the photoresist layer 50 and the conductive and heat-conductive material 30 thereon, so that the remaining conductive and heat-conductive material 30 forms one or more first wirings, thereby synchronously forming a second conductive portion 132 of the first conductive member 130 and a second heat-conductive portion 142 of the first heat-conductive member 140.

[0086] Among them, step S117 may include depositing a photoresist material on the second preset layer 150, and may transfer the pattern of the second mask to the photoresist material by a photolithography process based on the second mask, so as to form a patterned photoresist layer 50.

[0087] In some of the above embodiments using the second mask, there is no need to separately provide different masks for the formation of the second conductive portion 132 and the second heat-conductive portion 142. The second conductive portion 132 of the first conductive member 130 and the second heat-conductive portion 142 of the first heat-conductive member 140 can be synchronously formed through the second mask, reducing the preparation difficulty of the device and saving the preparation cost.

[0088] In some embodiments, the second preset layer 150 may be, for example, the first substrate 160 of the first chip 100. In this way, one or more first wirings can be formed on the first substrate 160. Alternatively, in some embodiments, as Figures 6 to 7 、 Figures 10 to 12 shown, the second preset layer may be, for example, the first device layer 170 of the first chip 100, and the first device layer 170 may be located above the first substrate 160. In this way, one or more first wirings can be formed on the first device layer 170. Among them, the one or more first wirings may be at least a part of the first wiring layer 180 of the first chip 100.

[0089] As Figure 3 、 Figure 5 、 Figures 8 to 12 shown, the method for manufacturing the device according to the present disclosure may further include:

[0090] Step S120, synchronously forming a second conductive member 230 and a second heat-conductive member 240 in the second chip 200.

[0091] Among them, the synchronously formed second conductive member 230 and second heat-conductive member 240 may be electrically isolated from each other to avoid short-circuiting of related circuits.

[0092] In some embodiments, as Figure 5 、 Figures 8 to 12As shown, the second heat conducting member 240 may include a third heat conducting portion 241 extending in the thickness direction, such that heat may be conducted in the thickness direction via the third heat conducting portion 241. Correspondingly, the second conducting member 230 formed synchronously with the second heat conducting member 240 may also include a third conducting portion 231 extending in the thickness direction.

[0093] In some embodiments, as Figure 5 shown, synchronously forming the second conducting member 230 and the second heat conducting member 240 in the second chip 200 may include: forming a plurality of second through holes 220 in a third preset layer 210 of the second chip 200, and filling the plurality of second through holes 220 with a conductive and heat-conductive material, so as to synchronously form the third conducting portion 231 of the second conducting member 230 and the third heat conducting portion 241 of the second heat conducting member 240.

[0094] Specifically, as Figure 5 shown in (a) of

[0095] Step S121, forming a patterned third anti-etching layer 20 on the third preset layer 210 of the second chip 200 by using a photolithography process.

[0096] Specifically, an anti-etching material may be deposited on the third preset layer 210, and then, a patterned third anti-etching layer 20 may be formed on the third preset layer 210 of the second chip 200 by using electron beam exposure or ion beam exposure and then developing. Alternatively, based on a third mask, a photolithography process may be used to transfer the pattern of the third mask to the anti-etching material to form a patterned third anti-etching layer 20. Thus, subsequently, the third conducting portion 231 of the second conducting member 230 and the third heat conducting portion 242 of the second heat conducting member 240 may be formed synchronously based on the third mask, without separately setting different masks for the formation of the third conducting portion 231 and the third heat conducting portion 241, reducing the preparation difficulty of the device and saving the preparation cost.

[0097] Further, as Figure 5 shown in (b) of

[0098] Step S122, etching the third preset layer 210 under the protection of the third anti-etching layer 20 to form a plurality of second through holes 220.

[0099] In some embodiments, as Figure 5 shown in (b) of Figures 10 to 12As shown, the third preset layer 210 may be, for example, the second substrate 260 of the second chip 200. Among them, only the second substrate 260 may be etched to form the second through hole 220 formed in the second substrate 260. Alternatively, as Figure 5 shown in (b) of Figure 12 , the second substrate 260 and the second device layer 270 may be etched to form the second through hole 220 formed in the second substrate 260 and the second device layer 270.

[0100] In some embodiments, as Figure 5 shown in (b) of Figures 10 to 12 , the third preset layer 210 may be, for example, the second wiring layer 280 of the second chip 200. Among them, the second wiring layer 280 may be etched to form the second through hole 220 formed in the second wiring layer 280.

[0101] Furthermore, as Figure 5 shown in (c), synchronously forming the second conductive member 230 and the second heat conductive member 240 in the second chip 200 may further include:

[0102] Step S123: Fill the conductive and heat conductive material in the plurality of second through holes 220 to synchronously form the third conductive portion 231 of the second conductive member 230 and the third heat conductive portion 241 of the second heat conductive member 240.

[0103] In some embodiments, as Figures 8 to 12 shown, the second heat conductive member 240 may include a fourth heat conductive portion 242 extending in a plane parallel or coincident with the main plane of the second chip 200, or rather, the second heat conductive member 240 may include a fourth heat conductive portion 242 extending in a plane perpendicular to the thickness direction, so that heat can be conducted in the plane perpendicular to the thickness direction via the fourth heat conductive portion 242. Correspondingly, the second conductive member 230 formed synchronously with the second heat conductive member 240 may also include a fourth conductive portion 232 extending in a plane perpendicular to the thickness direction. In some embodiments, the fourth heat conductive portion 242 may be thermally connected to the third heat conductive portion 241. As Figures 10 to 12 shown, the fourth heat conductive portion 242 may be configured to thermally connect a plurality of third heat conductive portions 241.

[0104] In some embodiments, as Figures 8 to 9 shown, synchronously forming the second conductive member 230 and the second heat conductive member 240 in the second chip 200 may include: forming one or more layers of second wiring on the fourth preset layer 250 of the second chip 200 to synchronously form the fourth conductive portion 232 of the second conductive member 230 and the fourth heat conductive portion 242 of the second heat conductive member 240, wherein the one or more layers of second wiring may extend in a plane perpendicular to the thickness direction.

[0105] Specifically, in some embodiments, as Figure 8 shown in (a) to (c) of

[0106] forming one or more second wirings on the fourth preset layer 250 of the second chip 200 by using a photolithography process may include:

[0107] Step S124, depositing a conductive and heat-conductive material 60 in a continuous thin film form on the fourth preset layer 250;

[0108] Step S125, forming a patterned fourth anti-etching layer 70 on the conductive and heat-conductive material 60 by using a photolithography process;

[0109] Step S126, etching the part of the conductive and heat-conductive material 60 not covered by the fourth anti-etching layer 70 to form one or more second wirings.

[0110] Among them, a part of the one or more second wirings can be configured to be used as the fourth conductive part 232, and another part can be configured to be used as the fourth heat-conductive part 242. In this way, the fourth conductive part 232 and the fourth heat-conductive part 242 can be formed synchronously.

[0111] Alternatively, in some other embodiments, as Figure 9 shown in (a) to (c) of

[0112] forming one or more second wirings on the fourth preset layer 250 of the second chip 200 by using a photolithography process may include:

[0113] Step S127, forming a patterned photoresist layer 80 on the fourth preset layer 250 of the second chip 200 by using a photolithography process;

[0114] Step S128, depositing a conductive and heat-conductive material 60 in a continuous thin film form; Step S129, using a lift-off process to remove the photoresist layer 80 and the conductive and heat-conductive material 60 thereon, so that the remaining conductive and heat-conductive material 80 forms one or more second wirings, so as to synchronously form the fourth conductive part 232 of the second conductive member 230 and the fourth heat-conductive part 242 of the second heat-conductive member 240.

[0115] Among them, step S127 may include depositing a photoresist material on the fourth preset layer 250, and may transfer the pattern of the fourth mask to the photoresist material by using a photolithography process based on the fourth mask to form a patterned photoresist layer 80.

[0116] In some embodiments of using the fourth mask above, there is no need to separately provide different masks for the formation of the fourth conductive part 232 and the fourth heat-conducting part 242. The fourth conductive part 232 of the second conductive member 230 and the fourth heat-conducting part 242 of the second heat-conducting member 240 can be synchronously formed through the fourth mask, reducing the preparation difficulty of the device and saving the preparation cost.

[0117] In some embodiments, the fourth preset layer 250 may be, for example, the second substrate 260 of the second chip 200. Thus, one or more layers of second wirings can be formed on the second substrate 260. Alternatively, in some embodiments, as Figures 8 to 9 、 Figures 10 to 12 shown, the fourth preset layer 250 may be the second device layer 270 of the second chip 200, and the second device layer 270 may be located above the second substrate 260. Thus, one or more layers of second wirings can be formed on the second device layer 270. Among them, one or more layers of second wirings can be used as at least a part of the second wiring layer 280 of the second chip 200.

[0118] As Figure 3 、 Figures 10 to 12 shown, the method for preparing the device according to the present disclosure may further include:

[0119] Step S130, bonding the first chip 100 and the second chip 200 so that the first heat-conducting member 140 and the second heat-conducting member 240 are in thermal communication to form a heat-conducting channel.

[0120] In some embodiments, bonding the first chip 100 and the second chip 200 may include: forming a bonding layer 410 on at least one of the first side of the first chip 100 and the second side of the second chip 200. Among them, the first side of the first chip 100 and the second side of the second chip 200 may be adjacent to each other face to face, and the first heat-conducting member 140 of the first chip 100 and the second heat-conducting member 240 of the second chip 200 may be in thermal communication via the bonding pads 411 in the bonding layer 410. In a specific example, a hybrid bonding process may be used to bond the first chip 100 and the second chip 200 to improve the packaging integration degree of the first chip 100 and the second chip 200 and form a corresponding bonding layer 410 between the first side of the first chip 100 and the second side of the second chip 200.

[0121] In some embodiments, in order to improve the bonding effect to make the connection between the first chip 100 and the second chip 200 more stable, thereby improving the performance of the fabricated semiconductor device, bonding materials can be deposited on the first side of the first chip 100 and the second side of the second chip 200 respectively to form a bonding layer 410 for bonding the first chip 100 and the second chip 200.

[0122] In some embodiments, the first conductive member 130 of the first chip 100 and the second conductive member 230 of the second chip 200 can be electrically connected via corresponding bonding pads in the bonding layer 410. Among them, the bonding pads 411 for realizing the electrical connection between the first conductive member 130 and the second conductive member 230 can be electrically isolated from the bonding pads 411 for realizing the thermal communication between the first heat conductive member 140 and the second heat conductive member 240 to avoid short circuit.

[0123] In some embodiments, as Figures 10 to 12 shown, a part of the surface of one of the first chip 100 and the second chip 200 adjacent to the other is exposed to the environment to form an exposed portion 420. Alternatively, the area of the first chip 100 can be unequal to the area of the second chip 200, so that a part of the larger one of the first chip 100 and the second chip 200 forms an exposed portion 420 exposed to the environment relative to the smaller one. Among them, the heat conductive member in the chip with the exposed portion 420 can be partially located in the exposed portion 420 to be partially exposed to the environment, so that heat can be transmitted from the exposed portion 420 to the environment through the heat conduction channel. In a specific example, the area of the first chip 100 can be larger than the area of the second chip 200, and the first chip 100 can form an exposed portion 420 exposed to the environment relative to the second chip 200. Among them, the first heat conductive member 140 (for example, the first heat conductive part 141 and / or the second heat conductive part 142) can be partially located in the exposed portion 420 to be partially exposed to the environment. Alternatively, in another specific example, the area of the second chip 200 can be larger than the area of the first chip 100, the second chip 200 can form an exposed portion 420 exposed to the environment relative to the first chip 100, and the second heat conductive member 240 (for example, the third heat conductive part 241 and / or the fourth heat conductive part 242) can be partially located in the exposed portion 420 to be partially exposed to the environment. In this way, the heat in the first chip 100 or the second chip 200 can be timely transferred from the heat conductive member of the exposed portion 420 outside the first chip 100 and the second chip 200, which can effectively reduce the possibility of heat accumulation in the first chip 100 or the second chip 200, reduce the thermal resistance of the fabricated device and improve the heat dissipation effect of the device.

[0124] To further improve the heat dissipation effect of the semiconductor device, in some embodiments, as Figures 10 to 12As shown, a third heat conducting member 430 may also be formed on the exposed surface of the exposed portion 420, wherein the third heat conducting member 430 is in thermal communication with the heat conducting member in the chip having the exposed portion 420. For example, when the exposed portion 420 is formed on the first chip 100 and is exposed relative to the second chip 200, the third heat conducting member 430 may be in thermal communication with the first heat conducting member 140. Alternatively, when the exposed portion 420 is formed on the second chip 200 and is exposed relative to the first chip 100, the third heat conducting member 430 may be in thermal communication with the second heat conducting member 240.

[0125] In some cases, the internal heat distribution in each chip of the semiconductor device is usually non-uniform during operation. For example, the area closer to the location of the devices in the chip usually has a higher heat generation rate, such as Figures 10 to 12 the hot spot region 440 shown. To enable the heat conducting channel to conduct the heat of the hot spot region 440 as much as possible, in some embodiments, the position of the hot spot region 440 in the first chip 100 and / or the second chip 200 may be determined by thermal simulation, and the positions of the first heat conducting member 140 and the second heat conducting member 240 may be determined based on the position of the hot spot region 440 by thermal simulation, so that the heat conducting channel formed by the thermal communication between the first heat conducting member 140 and the second heat conducting member 240 can conduct the heat of the hot spot region 440 and reduce the heat accumulation in the hot spot region 440. In this way, the position of the hot spot region 440 is determined by thermal simulation and the positions of the heat conducting members in the chip are determined accordingly, thereby constructing a heat conducting channel capable of transferring the heat of the hot spot region 440 and improving the heat dissipation efficiency.

[0126] In some embodiments, the hot spot regions 440 of the chip may also be evenly distributed by reasonably arranging the first chip 100 and / or the second chip 200. For example, by avoiding the concentrated distribution of the working devices in the chip in the same area, the thermal coupling of the chip can be reduced to lower the local maximum temperature on the chip, and thus the temperature distribution of the chip can be made more uniform.

[0127] Such as Figures 10 to 12As shown, a corresponding third heat conducting member 430 may be arranged at a position of the heat conducting channel that is exposed to the environment, so that heat can be quickly dissipated after being transferred out. Considering that the arrangement of the third heat conducting member 430 will affect the construction of the heat conducting channel. For example, the layout of the first chip and the second chip has usually been pre-designed, and the positions where the third heat conducting member 430 can be arranged are limited. Therefore, it is necessary to comprehensively consider the positions where the third heat conducting member 430 can be arranged to construct a heat conducting channel for transferring the heat of the hot spot area. Specifically, in some embodiments, the position of the third heat conducting member 430 may be determined, and based on the position of the third heat conducting member 430 and the position of the hot spot area, the positions of the first heat conducting member 140 and the second heat conducting member 240 may be determined to construct a heat conducting channel with an optimized path, thereby further improving the heat dissipation efficiency of the device.

[0128] In a specific example, as Figure 13 shown, the method for manufacturing the device of the present disclosure may further include:

[0129] Step S210, obtaining the logic design and layout of the first chip 100 and the second chip 200;

[0130] Step S220, determining the position of the hot spot area inside at least one of the first chip 100 and the second chip 200 through thermal simulation;

[0131] Step S230, determining the positions where the third heat conducting member 430 can be arranged according to the layout of the first chip 100 and the second chip 200;

[0132] Step S240, designing a heat conducting channel according to the position of the hot spot area and the positions where the third heat conducting member 430 can be arranged;

[0133] Step S250, inserting the designed heat conducting channel into the layout of the first chip 100 and the second chip 200;

[0134] Step S260, determining whether the first chip 100 and the second chip 200 meet the preset thermal simulation requirements through thermal simulation. If they meet, execute Step S270 and perform subsequent device manufacturing according to the designed heat conducting channel. Otherwise, return to Step S240 and re-design the heat conducting channel.

[0135] In this way, the corresponding heat conducting channel can be flexibly constructed through thermal simulation, and the heat conducting channel can be effectively constructed under different chip stacking structures, improving the heat dissipation effect of the device.

[0136] In a specific example, determining whether the first chip 100 and the second chip 200 meet the preset thermal simulation requirements through thermal simulation may, for example, determine whether the chip temperature is less than or equal to the preset temperature.

[0137] In some embodiments, step S240 may include determining the optimal layout position closest to the hot spot area among the positions where the third heat conducting member 430 can be arranged according to the position of the hot spot area, determining an optimal path according to the position of the hot spot area and the optimal layout position of the third heat conducting member 430, and designing a heat conduction channel based on the optimal path.

[0138] In a specific example, a heat conduction channel connecting the hot spot area and the third heat conducting member 430 can be constructed by selecting corresponding metal components in a Process Design Kit (PDK). The optimal path can be, for example, the shortest path that can connect the hot spot area and the third heat conducting member 430 using the metal components in the PDK without affecting the original layout of the chip. By determining the optimal path to construct the corresponding heat conduction channel, the efficiency of heat conduction from the hot spot area of the chip to the outside is greatly improved, enabling the heat to be released to the outside in a shorter time, thereby keeping the chip operating at a lower working temperature and avoiding performance degradation and failures caused by overheating. In some embodiments, corresponding metal components can be pre-selected to form a preset heat conduction channel, and thermal simulation can be used to predict the heat transfer situation inside the chip under the preset heat conduction channel, so as to optimize the position and interconnection of the metal components according to the heat transfer situation, thereby ensuring the best heat dissipation effect.

[0139] The metal components can include, for example, at least one of Through Silicon Via, metal vias, metal wirings, heat conducting pads, bonding pads, Package balls, and Bumps. Metal components generally have a high thermal conductivity. By constructing a heat conduction channel with metal components, the heat inside the chip can be quickly conducted to the outside, thereby effectively reducing the temperature of the hot spot area, reducing the thermal resistance of the chip, and improving the heat dissipation capacity.

[0140] Thus, according to the results of the thermal simulation and in combination with the device preparation method in some of the above embodiments, a corresponding semiconductor device (such as Figures 10 to 12 the semiconductor device 300 shown) can be prepared.

[0141] In some embodiments, at least some of the selected metal components can be configured to form the first heat conducting member 140 and / or the second heat conducting member 240 as shown in Figures 10 to 12 ...

[0142] According to another aspect of the present disclosure, a semiconductor device 300 is also provided, as shown in Figures 10 to 12 ... The semiconductor device 300 may include a first chip 100 and a second chip 200, wherein the second chip 200 can be bonded to one side of the first chip 100.

[0143] The first chip 100 may include a patterned first functional layer. Among them, a first part of the patterned first functional layer may be configured to serve as a first conductive member, a second part of the patterned first functional layer may be configured to serve as a first heat conductive member 140, and the first conductive member may be electrically isolated from the first heat conductive member 140. To clearly show the heat conduction path concisely, Figures 10 to 12 The first conductive member in the first chip 100 and the second conductive member in the second chip 200 are not shown.

[0144] In some embodiments, the first part and the second part of the patterned first functional layer may be formed synchronously. That is to say, the first heat conductive member 140 and the first conductive member may be formed synchronously, so that the first heat conductive member 140 can be formed synchronously based on the steps of the existing manufacturing process of the first chip 100 without introducing additional manufacturing steps.

[0145] In some embodiments, the first heat conductive member 140 may include a first heat conductive part 141. Among them, the first heat conductive part 141 may extend in the thickness direction to conduct heat in the thickness direction. Alternatively, in some embodiments, the first heat conductive member 140 may include a second heat conductive part 142 extending in a plane perpendicular to the thickness direction to conduct heat in a plane perpendicular to the thickness direction.

[0146] As Figures 10 to 12 shown, the first functional layer may include a first substrate 160, a first device layer 170, and a first wiring layer 180 stacked in sequence in the thickness direction. In some embodiments, the first heat conductive part 141 may be filled in a first through hole 120, and the first through hole 120 may be opened in at least one of the first substrate 160, the first device layer 170, and the first wiring layer 180. In Figure 10 and Figure 12 the example shown, the first through hole 120 may be opened in the first substrate 160, and a vertical through-silicon via located in the first substrate 160 may be formed by filling a corresponding conductive and heat conductive material. In Figure 11In the illustrated example, the first vias 120 may be formed in the first substrate 160 and the first device layer 170. By filling corresponding conductive and heat-conductive materials, through-silicon vias located in the first substrate 160 and the first device layer 170 may be formed, for example. Further, the first vias 120 may also be formed in the first wiring layer 180. By filling corresponding conductive and heat-conductive materials, metal vias located in the first wiring layer 180 may be formed, for example. In a specific example, the positions in the first chip 100 where the first vias 120 are to be formed may be determined in advance, such as through thermal simulation, to determine the position of the first heat-conductive portion 141 in the first chip 100. In some embodiments, the first conductive portion of the first conductive member may also be filled in the corresponding first vias. Herein, the first conductive portion and the first heat-conductive portion 141 may be electrically isolated from each other.

[0147] In some embodiments, the first wiring layer 180 may include one or more layers of first wirings extending in a plane perpendicular to the thickness direction. At least a portion of the one or more layers of first wirings may be configured to serve as the second heat-conductive portion 142 of the first heat-conductive member 140. For example, a part of the one or more layers of first wirings may be configured to serve as the second heat-conductive portion 142 of the first heat-conductive member 140, and another part may be configured to serve as the second conductive portion of the second conductive member. Herein, the second heat-conductive portion 142 and the second conductive portion may be electrically isolated from each other. Alternatively, the first wiring layer 180 may further include one or more layers of conductive wirings extending in a plane perpendicular to the thickness direction to serve as the second conductive portion of the second conductive member. Herein, the conductive wirings and the first wirings may be electrically isolated from each other.

[0148] The second chip 200 may include a patterned second functional layer. Herein, the first part of the patterned second functional layer may be configured to serve as the second conductive member, and the second part of the patterned second functional layer may be configured to serve as the second heat-conductive member 240. The second conductive member and the second heat-conductive member 240 may be electrically isolated from each other. Herein, the second heat-conductive member 240 of the second chip 200 may be in thermal communication with the first heat-conductive member 140 of the first chip 100 to form a heat conduction channel, so as to facilitate heat conduction between the first chip 100 and the second chip 200 and reduce heat accumulation.

[0149] In some embodiments, the first part and the second part of the patterned second functional layer may be formed synchronously. That is to say, the second heat-conductive member 240 and the second conductive member may be formed synchronously, so that the second heat-conductive member 240 can be formed synchronously based on the steps of the existing manufacturing process of the second chip 200 without introducing additional manufacturing steps.

[0150] In some embodiments, the second heat conducting member 240 may include a third heat conducting portion 241, wherein the third heat conducting portion 241 may extend in the thickness direction to conduct heat in the thickness direction. Alternatively, in some embodiments, the second heat conducting member 240 may include a fourth heat conducting portion 242 extending in a plane perpendicular to the thickness direction to conduct heat in a plane perpendicular to the thickness direction.

[0151] As Figures 10 to 12 shown, the second functional layer may include a second substrate 260, a second device layer 270, and a second wiring layer 280 stacked in sequence in the thickness direction. Among them, as Figure 10 and Figure 11 shown, the second wiring layer 280 may be disposed face to face with the first substrate 160, or, as Figure 12 shown, the second substrate 260 may be disposed face to face with the first substrate 160.

[0152] In some embodiments, the third heat conducting portion 241 may be filled in the second through hole 220, and the second through hole 220 may be opened in at least one of the second substrate 260, the second device layer 270, and the second wiring layer 280. In Figure 10 and Figure 11 the example shown, the second through hole 220 may be opened in the second wiring layer 280, and a metal through hole located in the second wiring layer 280 may be formed by filling a corresponding conductive and heat conducting material. In Figure 12 the example shown, the second through hole 220 may be opened in the second substrate 260 and the second device layer 270, and a vertical silicon through hole located in the second substrate 260 and the second device layer 270 may be formed by filling a corresponding conductive and heat conducting material. In another example, the second through hole 220 may also be opened in the second substrate 260, and a vertical silicon through hole located in the second substrate 260 may be formed by filling a corresponding conductive and heat conducting material. In a specific example, the position where the second through hole 220 is to be opened in the second chip 200 may be determined in advance, for example, by thermal simulation, to determine the position of the third heat conducting portion 241 in the second chip 200. In some embodiments, the third conductive portion of the second conductive member may also be filled in the corresponding second through hole, wherein the third conductive portion and the third heat conducting portion may be electrically isolated.

[0153] In some embodiments, the second wiring layer 280 may include one or more layers of second wirings extending in a plane perpendicular to the thickness direction, wherein at least a portion of the one or more layers of second wirings may be configured to serve as a fourth heat-conducting portion 242 of the second heat-conducting member 240. For example, a part of the one or more layers of second wirings may be configured to serve as the fourth heat-conducting portion 242 of the second heat-conducting member 240, and another part may be configured to serve as the fourth conducting portion of the second conducting member, wherein the fourth heat-conducting portion 242 may be electrically isolated from the fourth conducting portion. Alternatively, the second wiring layer 280 may further include one or more layers of conductive wirings extending in a plane perpendicular to the thickness direction to serve as the fourth conducting portion of the second conducting member, wherein the conductive wirings may be electrically isolated from the second wirings.

[0154] To improve the heat dissipation effect of the device, the heat-conducting channel may be partially exposed to the environment. For example, a part of the first heat-conducting member 140 and / or the second heat-conducting member 240 may be exposed to the environment to transfer the heat in the first chip 100 and the second chip 200 out to the environment through the heat-conducting channel. In some embodiments, one end of the heat-conducting channel may be located on the surface of the first chip 100 or the second chip 200 that is exposed to the environment, so that the heat is transferred out through the heat-conducting channel from the exposed surface. For example, one end of the first heat-conducting member 140 may be located on the surface of the first chip 100 that is exposed to the environment, and the other end may be used for thermal communication with the second heat-conducting member 240, so that the heat in the first chip 100 and the second chip 200 is transferred out from the exposed surface of the first chip 100 through the heat-conducting channel. Alternatively, one end of the second heat-conducting member 240 may be located on the surface of the second chip 200 that is exposed to the environment, and the other end may be used for thermal communication with the first heat-conducting member 140, so that the heat in the first chip 100 and the second chip 200 is transferred out from the exposed surface of the second chip 200 through the heat-conducting channel. In some embodiments, a corresponding heat dissipation device or heat-conducting member may be arranged at the position where the heat-conducting channel is exposed to the environment to further promote the transfer of the heat in the heat-conducting channel to the environment outside the chip, thereby further improving the heat dissipation effect.

[0155] To enable the heat in the first chip 100 and the second chip 200 to be transferred out of the first chip 100 and the second chip 200 in a timely manner, in some embodiments, as Figures 10 to 12 shown, one of the first chip 100 and the second chip 200 may be exposed to the environment relative to the other on the adjacent surface, so as to form an exposed portion 420. Alternatively, the area of the first chip 100 is not equal to the area of the second chip 200, so that the larger one of the first chip 100 and the second chip 200 is exposed to the environment relative to the smaller one to form an exposed portion 420. Wherein, the heat-conducting member in the chip having the exposed portion 420 may be partially located in the exposed portion 420, so that the heat is transferred out through the heat-conducting channel from the exposed portion 420.

[0156] In some embodiments, the area of the first chip 100 may be larger than the area of the second chip 200. The first chip 100 may be formed with an exposed portion 420 that is exposed relative to the second chip 200. For example, at least one of the first substrate 160, the first device layer 170, and the first wiring layer 180 may be formed with the exposed portion 420. Among them, the first heat conducting member 140 (for example, the first heat conducting portion 141 and / or the second heat conducting portion 142) may be partially located in the exposed portion 420 to be partially exposed to the environment. Alternatively, in some embodiments, as Figures 10 to 12 shown, the second chip 200 may be formed with an exposed portion 420 that is exposed relative to the first chip 100. For example, at least one of the second substrate 260, the second device layer 270, and the second wiring layer 280 may be formed with the exposed portion 420. Among them, the second heat conducting member 240 (for example, the third heat conducting portion 241 and / or the fourth heat conducting portion 242) may be partially located in the exposed portion 420 to be partially exposed to the environment.

[0157] In this way, the heat in the first chip 100 or the second chip 200 can be timely transferred from the heat conducting member of the exposed portion 420 outside the first chip 100 and the second chip 200, which can effectively reduce the possibility of heat accumulation in the first chip 100 or the second chip 200, reduce the device thermal resistance and improve the heat dissipation effect of the device.

[0158] To further improve the heat dissipation effect of the semiconductor device 300, in some embodiments, the semiconductor device 300 of the present disclosure may further include a third heat conducting member 430 located on the exposed surface of the exposed portion 420. Among them, the third heat conducting member 430 may be in thermal communication with the heat conducting member in the chip having the exposed portion 420. The exposed portion 420 can provide more layout space for the third heat conducting member 430, so that the heat dissipation channel with the third heat conducting member 430 can be constructed more flexibly, improving the flexibility of the process. The third heat conducting member 430 may include, for example, a heat conducting pad and a heat dissipation device connected to the heat conducting pad to promote the heat in the heat dissipation channel to be dissipated to the environment, thereby further improving the heat dissipation effect.

[0159] In some implementations, the semiconductor device 300 may further include a bonding layer 410. Among them, the bonding layer 410 is located between the first chip 100 and the second chip 200 and may be configured to bond the first chip 100 and the second chip 200 to improve the packaging integration degree of the semiconductor device 300. Among them, the first heat conducting member 140 and the second heat conducting member 240 may be in thermal communication via the bonding pad 411 in the bonding layer 410.

[0160] In some embodiments, the heat conduction channel formed by the first heat conducting member 140 and the second heat conducting member 240 may be configured to transfer the heat of the hot spot region 440 in the first chip 100 and / or the second chip 200, wherein the hot spot region 440 may be determined according to the layout of the first chip 100 and the second chip 200. As Figures 10 to 12 shown, when the hot spot region 440 is located in the first chip 100, one end of the first heat conducting member 140 may be configured to be close to the hot spot region 440, and the other end of the first heat conducting member 140 may be configured to be in thermal communication with the second heat conducting member 240, so that the heat of the hot spot region 440 of the first chip 100 can be conducted through the first heat conducting member 140 and the second heat conducting member 240, reducing the heat accumulation in the hot spot region 440 of the first chip 100, thereby effectively improving the heat dissipation capacity of the device. When the hot spot region 440 is located in the second chip 200, one end of the second heat conducting member 240 may be configured to be close to the hot spot region 440, and the other end of the second heat conducting member 240 may be configured to be in thermal communication with the first heat conducting member 140, so that the heat of the hot spot region 440 of the second chip 200 can be conducted through the first heat conducting member 140 and the second heat conducting member 240, reducing the heat accumulation in the hot spot region 440 of the second chip 200, thereby effectively improving the heat dissipation capacity of the device.

[0161] In Figures 10 to 12 the example shown, the heat at the hot spot region 440 of the first chip 100 can be conducted to the bonding layer 410 through the first heat conducting member 140, then conducted to the second heat conducting member 240 through the bonding pad 411 of the bonding layer 410, and then conducted to the third heat conducting member 430 through the second heat conducting member 240, thereby conducting the heat at the hot spot region 440 to the external environment to achieve heat exchange.

[0162] In addition, the semiconductor device 300 of the present disclosure can also be prepared by the device preparation method as described above.

[0163] In the technical solution of the present disclosure, the corresponding heat conducting member is formed synchronously while forming the conductive member of the chip to construct a heat conduction channel. Without introducing additional process steps to separately form the heat conducting member on the basis of the original chip preparation process, it can save the device preparation cost while effectively reducing the heat accumulation, reducing the thermal resistance, and improving the chip heat dissipation capacity. In addition, it can effectively reduce the working temperature of the chip, thereby effectively solving the overheating problem of the chip, improving the performance stability of the chip, and prolonging the service life of the chip. According to some embodiments of the present disclosure, without adding additional heat dissipation devices (such as heat sinks, fans, etc.), the heat conduction channel can be constructed according to the metal components inside the chip, which enables the chip to maintain a high heat dissipation efficiency while maintaining a small size and high integration design, meeting the strict requirements of modern electronic devices for volume and weight.

[0164] In the description and claims, words such as "left", "right", "front", "rear", "top", "bottom", "upper", "lower", "higher", "lower", etc., if present, are used for descriptive purposes and not necessarily to describe a fixed relative position. It should be understood that such words are interchangeable under appropriate circumstances, so that the embodiments of the present disclosure described herein, for example, can operate in other orientations different from those shown or otherwise described herein. For example, when the device in the drawings is inverted, a feature originally described as "above" other features can then be described as "below" the other features. The device can also be oriented in other ways (rotated 90 degrees or in other orientations), and the relative spatial relationships will be correspondingly interpreted at that time.

[0165] In the description and claims, when it is said that an element is "above", "attached" to, "connected" to, "coupled" to, or "in contact" with another element, etc., the element can be directly above, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or there can be one or more intermediate elements. In contrast, when it is said that an element is "directly" "above", "directly attached" to, "directly connected" to, "directly coupled" to, or "directly in contact" with another element, there will be no intermediate element. In the description and claims, a feature is arranged "adjacent" to another feature, which can mean that a feature has a part that overlaps with the adjacent feature or a part that is above or below the adjacent feature.

[0166] As used herein, the word "exemplary" means "serving as an example, instance, or illustration", rather than as a "model" to be precisely replicated. Any implementation described herein exemplarily is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, the present disclosure is not limited by any theory expressed or implied in the technical field, background art, summary of the invention, or detailed description.

[0167] As used herein, the word "substantially" means including any minor variations caused by design or manufacturing defects, tolerances of devices or components, environmental effects, and / or other factors. The word "substantially" also allows for differences from a perfect or ideal situation caused by parasitic effects, noise, and other practical considerations that may exist in an actual implementation.

[0168] Additionally, for reference purposes only, terms such as "first", "second", etc. may also be used in this document and are thus not intended to be limiting. For example, unless the context clearly indicates otherwise, the words "first", "second", and other such numerical words referring to structures or elements do not imply an order or sequence.

[0169] It should also be understood that when the term "comprising / including" is used in this document, it indicates the presence of the stated features, wholes, steps, operations, units, and / or components, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units, and / or components and / or their combinations.

[0170] In this disclosure, the term "provide" is used broadly to cover all ways of obtaining an object, so "providing an object" includes, but is not limited to, "purchasing", "preparing / manufacturing", "arranging / setting", "installing / assembling", and / or "ordering" the object, etc.

[0171] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit this disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0172] Those skilled in the art should be aware that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed among additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of a particular operation, and the order of operations can be changed in various other embodiments. However, other modifications, variations, and substitutions are also possible. The aspects and elements of all the embodiments disclosed above can be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the drawings should be regarded as illustrative rather than restrictive.

[0173] Although some specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of this disclosure. The embodiments disclosed herein can be combined arbitrarily without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A method for preparing a device, characterized in that: The device preparation method comprises: Synchronously forming a first conductive member and a first thermal conductive member in a first chip, wherein the first conductive member and the first thermal conductive member are electrically isolated; synchronously forming a second conductive member and a second thermal conductive member in a second chip, wherein the second conductive member and the second thermal conductive member are electrically isolated; and The first chip and the second chip are bonded to make the first heat conducting member thermally connected to the second heat conducting member and form a heat conducting channel.

2. The method for preparing the device according to claim 1, characterized in that: The method of synchronously forming a first conductive member and a first thermal conductive member in a first chip includes: Forming a plurality of first through holes in the first predetermined layer of the first chip, and filling the plurality of first through holes with an electrically conductive and thermally conductive material to synchronously form a first conductive portion of the first conductive member and a first thermally conductive portion of the first thermally conductive member; and / or One or more first wiring layers are formed on the second preset layer of the first chip to simultaneously form a second conductive portion of the first conductive member and a second heat conductive portion of the first heat conductive member, wherein the one or more first wiring layers extend in a plane perpendicular to the thickness direction.

3. The method for preparing the device according to claim 1, characterized in that: The method of synchronously forming a second conductive member and a second thermal conductive member in the second chip includes: forming a plurality of second through holes in the third preset layer of the second chip, and filling the plurality of second through holes with an electrically conductive and thermally conductive material to synchronously form a third conductive portion of the second conductive member and a third thermally conductive portion of the second thermally conductive member; and / or One or more layers of second wiring are formed on a fourth preset layer of the second chip to simultaneously form a fourth conductive portion of the second conductive member and a fourth heat conductive portion of the second heat conductive member, wherein the one or more layers of second wiring extend in a plane perpendicular to the thickness direction.

4. The method for preparing the device according to claim 1, characterized in that: Bonding the first chip and the second chip includes: A bonding layer is formed on the first side of the first chip and / or the second side of the second chip, and the first chip and the second chip are bonded through the bonding layer, wherein the first side of the first chip is adjacent to the second side of the second chip, and the first heat conductive member is thermally connected to the second heat conductive member via a bonding pad in the bonding layer.

5. The method for preparing the device according to claim 1, characterized in that: A portion of a surface of one of the first chip and the second chip adjacent to the other is exposed to the environment to form an exposed portion, wherein a heat conductor in the chip having the exposed portion is partially located in the exposed portion to be partially exposed to the environment.

6. The method for preparing the device according to claim 5, characterized in that: The device preparation method also includes: A third heat conductor is formed on the exposed surface of the exposed portion, wherein the third heat conductor is in thermal communication with a heat conductor in the chip having the exposed portion.

7. The method for preparing the device according to claim 1, characterized in that: The device preparation method also includes: The position of the hot spot area in the first chip and / or the second chip is determined by thermal simulation, and the position of the first heat conductive member and the second heat conductive member is determined based on the position of the hot spot area by thermal simulation, so that the heat conductive channel conducts heat to the hot spot area.

8. A semiconductor device, characterized in that: The semiconductor device comprises: a first chip, the first chip comprising a patterned first functional layer, a first portion of the patterned first functional layer being configured to function as a first conductive member, a second portion of the patterned first functional layer being configured to function as a first thermal conductive member, wherein the first conductive member is electrically isolated from the first thermal conductive member; a second chip, the second chip being bonded to one side of the first chip, the second chip comprising a patterned second functional layer, a first portion of the patterned second functional layer being configured to function as a second conductive member, a second portion of the patterned second functional layer being configured to function as a second thermal conductive member, wherein the second conductive member is electrically isolated from the second thermal conductive member, Wherein, the first heat conducting member is thermally connected to the second heat conducting member to form a heat conducting channel.

9. The semiconductor device according to claim 8, wherein: The first heat-conducting member and the first electrically conductive member are formed synchronously, and the second heat-conducting member and the second electrically conductive member are formed synchronously.

10. The semiconductor device according to claim 8, wherein: The first functional layer includes a first substrate, a first device layer, and a first wiring layer stacked in sequence in the thickness direction, and the second functional layer includes a second substrate, a second device layer, and a second wiring layer stacked in sequence in the thickness direction. The second wiring layer is arranged face to face with the first substrate or the second substrate is arranged face to face with the first substrate.

11. The semiconductor device according to claim 10, wherein: The first heat-conducting member includes a first heat-conducting portion and / or a second heat-conducting portion, and the second heat-conducting member includes a third heat-conducting portion and / or a fourth heat-conducting portion. The first heat conducting portion is filled in a first through hole, and the first through hole is opened in at least one of the first substrate, the first device layer and the first wiring layer. the first wiring layer includes one or more layers of first wiring extending in a plane perpendicular to the thickness direction, wherein at least a portion of the one or more layers of first wiring is configured to function as the second heat conducting portion, The third heat conducting portion is filled in a second through hole, and the second through hole is opened in at least one of the second substrate, the second device layer, and the second wiring layer. The second wiring layer includes one or more layers of second wiring extending in a plane perpendicular to the thickness direction, wherein at least a portion of the one or more layers of second wiring is configured to function as the fourth heat conducting portion.

12. The semiconductor device according to claim 8, wherein: A portion of a surface of one of the first chip and the second chip adjacent to the other is exposed to the environment to form an exposed portion, wherein a heat conductor in the chip having the exposed portion is partially located in the exposed portion to be partially exposed to the environment.

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