Semiconductor device and forming method and detection method thereof
By first performing chemical mechanical grinding processes during semiconductor manufacturing, then performing etching and trimming processes to obtain trimming steps, the problems of excessive white edge width and poor bonding of wafer edges are solved, improving bonding quality and reducing production risks.
Patent Information
- Application Number
- CN202311766954.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-20
- Publication Date
- 2025-06-20
AI Technical Summary
During semiconductor manufacturing, the width of the white edge of the wafer edge is much larger than the width of the trimming, and there are bubbles, resulting in problems such as peeling the wafer edge, contaminating the machine, and scrapping.
By first performing a chemical mechanical grinding process to obtain a first dielectric layer of a predetermined thickness, then, an etching process and a trimming process are performed after the chemical mechanical grinding process to obtain a trimming step, edge collapse of the first dielectric layer at the edge of the wafer is avoided, thereby improving the mixing bonding quality.
It effectively reduces the white edge width of the wafer, improves the quality of wafer bonding, and reduces the risks of wafer edge peeling, contamination of machines and scrapping.
Smart Images
Figure CN120184037A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a semiconductor device, a forming method thereof, and a detecting method thereof. Background Art
[0002] During the manufacturing process of multi-chip stacking using the hybrid bonding process, copper-copper interconnection between wafers is achieved, thereby reducing the resistance of the resistor-capacitance (RC) circuit; and the device performance is improved without increasing the area of the semiconductor device. Semiconductor factories commonly use a C-SAM (Contactless Scanning Acoustic Microscope) to detect wafers after the hybrid bonding process, and judge whether the hybrid bonding process is healthy and whether the result meets the expected effect by checking the width of the white edge, the size and quantity of bubbles at the edge of the wafer.
[0003] Generally, the well-bonded interface appears black under the C-SAM; if there are bubbles, voids or steps at the bonding interface, it appears white under the C-SAM.
[0004] Normally, within the error range, the width of the white edge at the wafer edge is equal to the trimming width. When the width of the white edge significantly exceeds the trimming width, it indicates that there is a problem with the semiconductor process.
[0005] Currently, during the wafer runs in semiconductor factories, it is found that as the trimming width of the front-end process increases, after the hybrid bonding process is completed, when detecting the wafer edge under the C-SAM, the width of the white edge at the wafer edge is much larger than the trimming width, and there are also some bubbles. These problems will cause risks such as edge peeling, machine contamination, and scrapping of the wafer in the subsequent process. Summary of the Invention
[0006] The purpose of the present invention is to provide a semiconductor device, a forming method thereof, and a detecting method thereof, so as to solve at least one of the problems that the width of the white edge at the wafer edge is much larger than the trimming width, there are some bubbles, wafer edge peeling, machine contamination, and scrapping.
[0007] To solve the above technical problems, a forming method of a semiconductor device provided by the present invention includes:
[0008] Providing at least two wafers, each of the wafers including a substrate and a first dielectric layer on the substrate;
[0009] Performing a chemical mechanical polishing process to make the thickness of the first dielectric layer reach a predetermined thickness;
[0010] Performing an etching process to form an initial step at the edge of the substrate;
[0011] Perform a trimming process to further increase the depth and width of the initial step to form a trimmed step;
[0012] Perform a hybrid bonding process to achieve bonding between the wafers.
[0013] Optionally, after performing the trimming process, the width of the trimmed step is 2.5 mm to 4 mm, and the depth of the trimmed step is 140 um to 160 um.
[0014] Optionally, the width of the initial step is 0.9 mm to 1.1 mm, and the depth of the initial step is 9 um to 11 um.
[0015] Optionally, the depth of the initial step is greater than the predetermined thickness of the first dielectric layer.
[0016] Optionally, the predetermined thickness of the first dielectric layer is 5500 angstroms to 6500 angstroms.
[0017] Optionally, the hybrid bonding process includes:
[0018] Form a second dielectric layer that covers the trimmed step and the first dielectric layer;
[0019] Form metal contact holes that penetrate through the first dielectric layer and the second dielectric layer;
[0020] Form metal plugs that are located within the metal contact holes;
[0021] Perform a hybrid bonding process to achieve metal interconnection between the wafers.
[0022] Optionally, after performing the hybrid bonding process, an annealing process is performed on the wafer.
[0023] Based on the same inventive concept, the present invention also provides a method for detecting a semiconductor device. For a semiconductor device fabricated by using the method for forming a semiconductor device described in any one of the above, the white edge width at the edge of the wafer after the hybrid bonding process is detected by an ultrasonic scanning microscope, and the white edge width is less than the width of the trimmed step.
[0024] Optionally, the width of the trimmed step is 2.5 mm to 4 mm.
[0025] Based on the same inventive concept, the present invention also provides a semiconductor device fabricated by using the method for forming a semiconductor device described in any one of the above.
[0026] In a semiconductor device, a method for forming the same, and a method for detecting the same provided by the present invention, a first dielectric layer with a predetermined thickness is obtained by first performing a chemical mechanical polishing process. Then, an etching process and a trimming process are performed after the chemical mechanical polishing process to obtain a trimming step, avoiding the edge collapse of the first dielectric layer at the wafer edge in the prior art where the etching process and the trimming process are first performed and then the chemical mechanical polishing process is performed, resulting in incomplete bonding during the subsequent hybrid bonding process, and further resulting in a white edge width at the wafer edge being greater than the trimming width and peeling at the wafer edge. Therefore, the present invention can effectively reduce the white edge width of the wafer, improve the wafer bonding quality, reduce the risks of wafer edge peeling, contaminating the machine tool, and scrapping, etc. Description of the Drawings
[0027] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:
[0028] Figure 1 is an ultrasonic scanning microscope image of a wafer after hybrid bonding in the prior art.
[0029] Figure 2 is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention.
[0030] Figures 3 to 10 is a schematic structural diagram corresponding to the steps of a method for forming a semiconductor device according to an embodiment of the present invention.
[0031] Figure 11 is an ultrasonic scanning microscope image of a wafer after hybrid bonding according to an embodiment of the present invention.
[0032] In the drawings:
[0033] 20 - wafer; 21 - white edge;
[0034] 10 - substrate; 11 - first dielectric layer; 12 - initial step; 12a - trimming step; 13 - second dielectric layer; 14 - metal contact hole; 14a - metal plug; 15 - white edge. Detailed Embodiments
[0035] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structures. In particular, the focus that each drawing needs to show is different, and sometimes different scales are used.
[0036] As used in the present invention, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features. In addition, as used in the present invention, an element disposed on another element generally only means that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the two elements may be directly or indirectly connected, coupled, cooperated or transmitted through an intermediate element, rather than being construed as indicating or implying the spatial position relationship between the two elements, that is, an element may be inside, outside, above, below or on one side of another element in any orientation, unless otherwise explicitly stated in the content. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0037] Figure 1 is an ultrasonic scanning microscope image of a wafer after hybrid bonding in the prior art. The inventors have found through research that in the hybrid bonding process, when the trimming width in the previous process is 1.1 mm, the white edge contour of the wafer is clear and smooth during ultrasonic scanning microscope detection; due to the product requirements of the factory, when the trimming width in the previous process is greater than or equal to 2.5 mm; at this time, when using the conventional hybrid bonding process, the contour of the white edge 21 of the wafer 20 detected by the ultrasonic scanning microscope is very rough, and the width of the white edge 21 at the wafer edge (about 3.5 mm - 4.2 mm) is much larger than the trimming width, as Figure 1 shown, the wafer bonding effect is not good, and there is a phenomenon of wafer edge peeling.
[0038] Based on this, the core idea of the present invention is to first perform a chemical mechanical polishing process to obtain a first dielectric layer with a predetermined thickness, and then, after the chemical mechanical polishing process, perform an etching process and a trimming process to obtain a trimming step, avoiding the edge collapse of the first dielectric layer at the wafer edge in the prior art when performing the etching process and the trimming process first and then the chemical mechanical polishing process, resulting in incomplete bonding during the subsequent hybrid bonding process, and further resulting in a white edge width at the wafer edge greater than the trimming width and wafer edge peeling. Therefore, the present invention can effectively reduce the white edge width of the wafer, improve the wafer bonding quality, reduce the risks of wafer edge peeling, contaminating the machine tool, and scrapping.
[0039] Specifically, Figure 2 is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention. AsFigure 2 As shown, this embodiment provides a method for forming a semiconductor device, including:
[0040] Step S10: Provide at least two wafers, each of which includes a substrate and a first dielectric layer on the substrate;
[0041] Step S20: Perform a chemical mechanical polishing process to make the thickness of the first dielectric layer reach a predetermined thickness;
[0042] Step S30: Perform an etching process to form an initial step at the edge of the substrate;
[0043] Step S40: Perform a trimming process to further increase the depth and width of the initial step to form a trimmed step;
[0044] Step S50: Perform a hybrid bonding process to achieve bonding between the wafers.
[0045] Figures 3 to 10 is a schematic structural diagram corresponding to the steps of the method for forming a semiconductor device according to an embodiment of the present invention. The following will be described in detail Figures 3 to 10 the formation process of the semiconductor device.
[0046] As Figure 3 shown, provide at least two wafers, each of which includes a substrate 10 and a first dielectric layer 11 on the substrate 10; the substrate 10 can provide an operation platform for subsequent processes, and it can be any substrate well-known to those skilled in the art for carrying semiconductor integrated circuit components, which can be a bare chip or a wafer after an epitaxial growth process. Specifically, the substrate is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate, etc. In this embodiment, the substrate is a silicon substrate. The material of the first dielectric layer 11 is, for example, an oxide, and is formed by a chemical vapor deposition process or a thermal oxidation process. The thickness of the first dielectric layer 11 is, for example, 35000 angstroms to 37000 angstroms. The first dielectric layer 11 is used to fill the height difference between the middle and the edge of the substrate 10.
[0047] As Figure 4 shown, perform a chemical mechanical polishing process (CMP) to make the thickness of the first dielectric layer 11 reach a predetermined thickness; the predetermined thickness of the first dielectric layer 11 is, for example, 5500 angstroms to 6500 angstroms. That is, in this step, the thickness of the first dielectric layer is polished to the predetermined thickness by a chemical mechanical polishing process.
[0048] As Figure 5As shown, an etching process is performed to form an initial step 12 at the edge of the substrate 10; the etching process is a bevel etch process to form an initial step 12 at the outermost edge of the substrate 10, forming a stepped shape with a higher middle and a lower edge. The depth of the initial step 12 is greater than the predetermined thickness of the first dielectric layer 11. The width of the initial step 12 is, for example, 0.9 mm to 1.1 mm, and the width of the initial step 12 can also be 1 mm. The depth of the initial step is, for example, 9 μm to 11 μm, and the depth of the initial step can also be 10 μm. Specifically, a patterned photoresist layer is formed on the first dielectric layer after the chemical mechanical polishing process. The patterned photoresist layer exposes the edge of the substrate 10. Using the patterned photoresist layer as a mask, the first dielectric layer 11 and the substrate 10 are etched in sequence to form the initial step 12. After the step of forming the initial step 12, if the patterned photoresist layer has not been completely consumed, a photoresist removal process is also required. Usually, an ashing process or a stripping method is used to remove the remaining patterned photoresist layer.
[0049] As Figure 6 shown, a trimming process is performed to further increase the depth and width of the initial step 12 to form a trimmed step 12a; when the width of the trimmed step is greater than or equal to 2.5 mm, for example, it is 2.5 mm to 4 mm, and the depth of the trimmed step is, for example, 140 μm to 160 μm, and can be 150 μm. The trimming process is, for example, using a diamond knife to cut out a trimmed step 12a at the edge of the wafer. Performing the bevel etch process and the trimming process after the chemical mechanical polishing process, especially in the process where the width of the trimmed step is greater than or equal to 2.5 mm, avoids the problem that part of the first dielectric layer collapses in the process of first performing the bevel etch process and the trimming process and then the chemical mechanical polishing process, resulting in poor wafer edge bonding in the subsequent hybrid bonding process, a white edge width greater than the trimming width, and the presence of bubbles in the ultrasonic scanning microscope detection. In this embodiment, the chemical mechanical polishing process is first performed, and then the bevel etch process and the trimming process are performed. After the subsequent hybrid bonding process, in the ultrasonic scanning microscope detection, the white edge width of the wafer is within the trimming width range, and the bonding at the wafer edge is good; and it improves the bonding quality, reduces the risks of wafer edge peeling, contaminating the machine tool, and scrapping; and ensures the normal and stable flow of the product during wafer processing.
[0050] As Figures 7 - 10 shown, a hybrid bonding process is performed to achieve bonding between the wafers.
[0051] Specifically, as Figure 7As shown, a second dielectric layer 13 is then formed, and the second dielectric layer 13 covers the trimming step 12a and the first dielectric layer 11; the material of the second dielectric layer 13 is, for example, an oxide or a nitride, and can be formed by chemical vapor deposition or thermal oxidation processes.
[0052] As Figure 8 As shown, a metal contact hole 14 is formed, and the metal contact hole 14 penetrates through the first dielectric layer 11 and the second dielectric layer 13; the metal contact hole 14 is formed by a dry etching process. Specifically, a patterned photoresist layer is formed on the second dielectric layer 13, and the patterned photoresist layer exposes a part of the second dielectric layer 13. Using the patterned photoresist layer as a mask, the second dielectric layer 13 and the first dielectric layer 11 are etched in sequence to form the metal contact hole 14. In some embodiments, a metal interconnection layer is formed in the substrate 10, and the metal contact hole 14 is connected to the metal interconnection layer. After the step of forming the metal contact hole 14, if the patterned photoresist layer has not been completely consumed, a photoresist removal process is also required, and usually an ashing process or a stripping method is used to remove the remaining patterned photoresist layer.
[0053] As Figure 9 As shown, a metal plug 14a is formed, and the metal plug 14a is located in the metal contact hole 14; the material of the metal plug 14a is, for example, copper, and is formed by physical vapor deposition. In some embodiments, a metal interconnection layer is formed in the substrate 10, and the metal plug 14a is connected to the metal interconnection layer.
[0054] As Figure 10 As shown, a hybrid bonding process is performed to achieve metal interconnection between the wafers. Specifically, one of the wafers is flipped, and the metal plugs of the two wafers are aligned. Through the hybrid bonding process, metal interconnection between the wafers is achieved, that is, copper interconnection between the wafers is achieved.
[0055] After performing the hybrid bonding process, an annealing process is performed on the wafer. The process temperature of the annealing process is, for example, 340 degrees to 360 degrees, and the process time of the annealing process is, for example, 110 minutes to 130 minutes.
[0056] Figure 11It is the ultrasonic scanning microscope image of the wafer after hybrid bonding in the embodiment of the present invention. This embodiment also provides a detection method for a semiconductor device. For a semiconductor device fabricated by using the semiconductor device forming method described in any one of the above, the width of the white edge at the wafer edge after the hybrid bonding process is detected by an ultrasonic scanning microscope (C-SAM), that is, the white edge defect is inspected. Generally, the area with a good bonding interface appears black under the ultrasonic scanning microscope; if there are bubbles or voids or steps at the bonding interface, it appears white under the ultrasonic scanning microscope. Under normal circumstances, within the error range, the width of the white edge at the wafer edge is equal to the width of the edge trimming. When the width of the white edge significantly exceeds the width of the edge trimming, it indicates that there are problems in the semiconductor process. As Figure 11 shown, the width of the white edge 15 of the wafer is smaller than the width of the edge trimming step, and the contour of the white edge 15 is clear and smooth, and there are no other bubble-like defects around it. It should be emphasized that the width of the edge trimming step of the wafer in this embodiment is greater than or equal to 2.5 mm, for example, it is 2.5 mm to 4 mm.
[0057] Please continue to refer to Figures 3 - 10 , this embodiment also provides a semiconductor device fabricated by using the semiconductor device forming method described in any one of the above, including: a substrate 10, a first dielectric layer 11 is formed on the substrate 10, and a second dielectric layer 13 covering the first dielectric layer 11, the second dielectric layer 13 not only covers the first dielectric layer 11, but also fills the edge trimming step 12a. A plurality of metal contact holes 14 are formed in the first dielectric layer 11 and the second dielectric layer 13, and metal plugs 14a are formed in the metal contact holes 14. In some embodiments, a metal interconnection layer is formed in the substrate 10, and the metal plugs 14a are connected to the metal interconnection layer. For the wafer after the hybrid bonding process, the metal plugs of the two wafers are bonded together to achieve copper-to-copper connection between the wafers.
[0058] In summary, in a semiconductor device, its forming method, and detection method provided by the embodiment of the present invention, by first performing a chemical mechanical polishing process to obtain a first dielectric layer with a predetermined thickness, and then performing an etching process and an edge trimming process after the chemical mechanical polishing process to obtain an edge trimming step, it avoids the edge collapse of the first dielectric layer at the wafer edge in the prior art when first performing the etching process and the edge trimming process and then performing the chemical mechanical polishing process, resulting in incomplete bonding during the subsequent hybrid bonding process, and further resulting in a white edge width at the wafer edge greater than the edge trimming width and wafer edge peeling. Therefore, the present invention can effectively reduce the white edge width of the wafer, improve the wafer bonding quality, reduce the risks of wafer edge peeling, machine tool contamination, and scrapping.
[0059] It should also be recognized that although the present invention has been disclosed above in preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or it can be modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.
Claims
1. A method for forming a semiconductor device, characterized in that, Comprising: Providing at least two wafers, each of the wafers comprising a substrate and a first dielectric layer on the substrate; Performing a chemical mechanical polishing process to make the thickness of the first dielectric layer reach a predetermined thickness; Performing an etching process to form an initial step at the edge of the substrate; Performing a trimming process to further increase the depth and width of the initial step to form a trimmed step; Performing a hybrid bonding process to achieve bonding between the wafers; 2. The method for forming a semiconductor device according to claim 1, characterized in that, After performing the trimming process, the width of the trimmed step is 2.5 mm to 4 mm, and the depth of the trimmed step is 140 μm to 160 μm.
3. The method for forming a semiconductor device according to claim 1, characterized in that, The width of the initial step is 0.9 mm to 1.1 mm, and the depth of the initial step is 9 μm to 11 μm.
4. The method for forming a semiconductor device according to claim 1, characterized in that, The depth of the initial step is greater than the predetermined thickness of the first dielectric layer.
5. The method for forming a semiconductor device according to claim 1, characterized in that, The predetermined thickness of the first dielectric layer is 5500 angstroms to 6500 angstroms.
6. The method for forming a semiconductor device according to claim 1, characterized in that, The hybrid bonding process includes: Forming a second dielectric layer that covers the trimmed step and the first dielectric layer; Forming a metal contact hole that penetrates the first dielectric layer and the second dielectric layer; Forming a metal plug that is located within the metal contact hole; Performing a hybrid bonding process to achieve metal interconnection between the wafers; 7. The method for forming a semiconductor device according to claim 1, characterized in that, After performing the hybrid bonding process, performing an annealing process on the wafers; 8. A method for detecting a semiconductor device, characterized in that, For a semiconductor device fabricated by the method for forming a semiconductor device according to any one of claims 1 to 7, detecting the white edge width of the wafer edge after the hybrid bonding process by an ultrasonic scanning microscope, and the white edge width is less than the width of the trimmed step.
9. The method for detecting a semiconductor device according to claim 8, characterized in that, The width of the trimmed step is 2.5 mm to 4 mm.
10. A semiconductor device, characterized in that, Fabricated by the method for forming a semiconductor device according to any one of claims 1 to 7.