Semiconductor device chip and preparation method thereof

Abstract

The invention provides a semiconductor device chip and a preparation method thereof, and the method comprises the steps: sequentially depositing an N-DBR layer, an active layer and a P-DBR layer on a substrate, depositing a protection layer on the periphery, carrying out the dry etching until the N-DBR layer penetrates through the protection layer, the P-DBR layer and the active layer, and goes deep into the N-DBR layer, carrying out the evaporation of a P-type electrode on the P-DBR layer, and carrying out the evaporation of an N-type electrode on one side of the substrate; performing dry etching on the chip semi-finished product according to the cutting channel pattern until the chip semi-finished product penetrates through the N-DBR layer, the active layer, the P-DBR layer and the substrate and goes deep into the N-type electrode to obtain a cutting channel, and performing chip separation along the cutting channel to obtain a target semiconductor device chip. And meanwhile, the chip preparation method is simplified, the chip preparation efficiency is improved, and the cost is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor device chip and a preparation method thereof. Background Art

[0002] A semiconductor device is an electronic device with conductivity between that of a good conductor and an insulator, which uses the special electrical properties of semiconductor materials to perform specific functions and can be used to generate, control, receive, transform, amplify signals, and perform energy conversion.

[0003] In the process of fabricating existing semiconductor device chips, the stacking of multiple layers can cause the wafer to be easily warped during the chip fabrication process. Since the electrode layer is relatively thick and is usually fabricated by vacuum evaporation coating, the stacking of the epitaxial film layer and the electrode layer will further increase the wafer warping, resulting in a high risk of film layer peeling and wafer breakage during chip fabrication. At the same time, the warp of the wafer affects the fabrication of the contact hole structure, resulting in a low yield of the chip.

[0004] In the prior art, an adhesion layer, a stress correction layer, and a passivation layer are usually fabricated on the back of the chip to correct the stress so that the chip warping degree is within a preset range. Since the adhesion layer, the stress correction layer, and the passivation layer are usually fabricated using precious metals, the cost of chip fabrication is increased, and the fabrication of the adhesion layer, the stress correction layer, and the passivation layer is relatively complex, affecting the chip fabrication efficiency. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention provides a semiconductor device chip and a preparation method thereof to solve the problems raised in the above background art.

[0006] In the first aspect, an embodiment of the present invention provides the following technical solution: a preparation method of a semiconductor device chip, comprising: S1. Provide a substrate, and periodically and alternately stack a plurality of first stacks and second stacks on the substrate to obtain an N-DBR layer; S2. Deposit an active layer on the N-DBR layer, and periodically and alternately stack a plurality of third stacks and fourth stacks on the active layer to obtain a P-DBR layer; S3. Deposit a protective layer on the periphery of the substrate, the N-DBR layer, the active layer, and the P-DBR layer; S4. Define a stress release groove pattern, and perform dry etching according to the stress release groove pattern until it penetrates through the protective layer, the P-DBR layer, the active layer, and deep into the N-DBR layer to obtain a stress release groove; S5. Prepare a P-type metal, evaporate the P-type metal onto the P-DBR layer to obtain a P-type electrode, bond the side of the P-type electrode away from the substrate to a substrate, prepare an N-type metal, evaporate the N-type metal onto one side of the substrate to obtain an N-type electrode, and remove the substrate to obtain a chip semi-finished product; S6. Define a dicing lane pattern, and perform dry etching on the chip semi-finished product according to the dicing lane pattern until it penetrates through the N-DBR layer, the active layer, the P-DBR layer, the substrate and into the N-type electrode to obtain a dicing lane, and separate the chips along the dicing lane to obtain a target semiconductor device chip.

[0007] Compared with the prior art, the beneficial effects of the present application are as follows: The present invention does not change the chip device structure, adopts another process technology, prepares stress release grooves on the chip, and can effectively realize the stress release process through the stress release grooves, thereby reducing the chip fragmentation rate. At the same time, the chip preparation method is simplified, the chip preparation efficiency is improved, and the cost is reduced.

[0008] Preferably, both the first stack and the third stack are GaAs layers, and both the second stack and the fourth stack are AlGaAs layers.

[0009] Preferably, the range of the alternating stacking period of the first stack and the second stack in the N-DBR layer is 10-20.

[0010] Preferably, the range of the alternating stacking period of the third stack and the fourth stack in the P-DBR layer is 10-20.

[0011] Preferably, the protective layer is specifically a SiN layer and an Al2O3 layer, and the thickness of the protective layer is 4300A-5200A.

[0012] Preferably, an oxidation ring is provided between the P-DBR layer and the active layer.

[0013] Preferably, the materials of the P-type electrode and the N-type electrode are both one or a combination of more of Ti, Ni, Al, Pt, Au, and Ge.

[0014] Preferably, the stress release groove penetrates into the first stack close to the active layer in the N-DBR layer.

[0015] Preferably, the distance between the bottom of the dicing lane and the bottom of the N-type electrode is 3.5um-7um.

[0016] In a second aspect, an embodiment of the present invention further provides the following technical solution: A semiconductor device chip, which is prepared by using the preparation method of the semiconductor device chip as described above. Brief Description of the Drawings

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a flowchart of a method for preparing a semiconductor device chip provided in the first embodiment of the present invention; Figure 2 It is a schematic diagram of a semi-finished product generated in step S2 of the method for preparing a semiconductor device chip provided in the first embodiment of the present invention; Figure 3 It is a structural diagram of the N-DBR layer provided in the first embodiment of the present invention; Figure 4 It is a structural diagram of the P-DBR layer provided in the first embodiment of the present invention; Figure 5 It is a schematic diagram of a semi-finished product generated in step S3 of the method for preparing a semiconductor device chip provided in the first embodiment of the present invention; Figure 6 It is a schematic diagram of a semi-finished product generated in step S4 of the method for preparing a semiconductor device chip provided in the first embodiment of the present invention; Figure 7 It is a schematic diagram of a semi-finished product generated in step S5 of the method for preparing a semiconductor device chip provided in the first embodiment of the present invention; Figure 8 It is a schematic structural diagram of a scribe line provided in the first embodiment of the present invention; Figure 9 It is a structural diagram of a semiconductor device chip provided in another embodiment of the present invention.

[0019] Description of the Reference Numerals:

[0020] The following will further describe the embodiments of the present invention in conjunction with the drawings. Detailed Description of the Embodiments

[0021] The following will describe in detail the embodiments of the present invention. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are intended to explain the embodiments of the present invention and should not be construed as limiting the present invention.

[0022] In the description of the embodiments of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings. These are only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention.

[0023] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present invention, "a plurality" means two or more, unless otherwise specifically defined.

[0024] In the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "mounted", "connected", "connected to", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0025] Embodiment 1 As Figure 1 shown, the first embodiment of the present invention provides a method for preparing a semiconductor device chip, and the method includes: As Figure 2 , Figure 3 shown, S1: Provide a substrate 1, and periodically and alternately stack a plurality of first stacks 21 and second stacks 22 on the substrate 1 to obtain an N-DBR layer 2; Specifically, the substrate 1 here is specifically a GaAs substrate, which is a commonly used substrate in the prior art, so it will not be elaborated here; In this embodiment, the first stack 21 and the second stack 22 are respectively a GaAs layer and an AlGaAs layer, and the range of the alternating stacking period of the first stack 21 and the second stack 22 in the N-DBR layer 2 is 10 to 20, that is, the first stack 21 and the second stack 22 are continuously and alternately deposited in a cycle of 10 to 20 times; At the same time, the first layer closest to the substrate 1 is the first stack 21, and then from bottom to top are the second stack 22, the first stack 21, and the second stack 22 in sequence.

[0026] As Figure 2 、 Figure 4 shown, S2, deposit an active layer 3 on the N-DBR layer 2, and periodically stack a plurality of third stacks 51 and fourth stacks 52 alternately on the active layer 3 to obtain a P-DBR layer 5; Specifically, the active layer 3 here is specifically a quantum well barrier layer, which is a common structure in the prior art, so it will not be elaborated here.

[0027] In this embodiment, the third stack 51 and the fourth stack 52 are a GaAs layer and an AlGaAs layer respectively, and the range of the alternating stacking period of the third stack 51 and the fourth stack 52 in the P-DBR layer 5 is 10-20, that is, the third stack 51 and the fourth stack 52 are continuously deposited alternately in a cycle of 10-20 times; At the same time, the first layer closest to the active layer 3 is the third stack 51, and then the fourth stack 52, the third stack 51, and the fourth stack 52 are arranged from bottom to top in sequence; In this embodiment, an oxidation ring 4 is provided between the P-DBR layer 5 and the active layer 3; Specifically, the manufacturing process of the oxidation ring 4 is after manufacturing the active layer 3 and after manufacturing the P-DBR layer 5. The specific manufacturing method is: controlling the oxygen flow rate and the heating temperature in the chamber (300°C - 500°C) to control the oxidation rate, ensuring the stability of the oxidation rate, controlling the oxidation aperture size with time, and the aperture size of the oxidation ring 4 is 4um - 20um. By setting the oxidation ring 4, it is possible to limit the light spot from emitting laterally through its lateral structural shape.

[0028] As Figure 5 shown, S3, deposit a protective layer 6 around the substrate 1, the N-DBR layer 2, the active layer 3, and the P-DBR layer 5; Specifically, the protective layer 6 here is a double-layer structure, namely a SiN layer and an Al2O3 layer. The thickness of the SiN layer is 4000A - 4200A, and the thickness of the Al2O3 layer is 300A - 1000A. After preparing the oxidation ring 4, in order to play a protective role, the PECVD method is used to deposit a silicon nitride thin film at a temperature of 270 degrees - 310 degrees to obtain the SiN layer, and then the ALD method is used to deposit an aluminum oxide thin film to obtain the Al2O3 layer. By setting the protective layer 6, it can play a role in protecting the center and prevent subsequent water vapor from invading and causing the lateral oxidation aperture to continue to oxidize and grow.

[0029] As Figure 6 shown, S4, define a stress release groove pattern, and perform dry etching according to the stress release groove pattern until it penetrates the protective layer 6, the P-DBR layer 5, the active layer 3 and penetrates into the N-DBR layer to obtain a stress release groove 8; Specifically, the stress relief groove 8 here is prepared by an ICP dry etching process with the protection of the photoresist.

[0030] In this embodiment, the stress relief groove 8 penetrates into the first first stack 21 of the N-DBR layer 2 close to the active layer 3, that is, it is ensured that the stress relief groove 8 penetrates into the first layer structure of the N-DBR layer 2 closest to the active layer 3, that is, the first first stack 21 closest to the active layer 3. In actual situations, etching can also continue downward as long as the N-DBR layer 2 is not penetrated. By dry etching to the first first stack 21, the cost can be further reduced.

[0031] Such as Figure 7 As shown, in S5, a P-type metal is prepared, and the P-type metal is evaporated on the P-DBR layer 5 to obtain a P-type electrode 7. The side of the P-type electrode 7 away from the substrate 1 is bonded to a substrate. An N-type metal is prepared, and the N-type metal is evaporated on one side of the substrate to obtain an N-type electrode 9. The substrate is removed to obtain a chip semi-finished product; Specifically, the preparation processes of the P-type electrode 7 and the N-type electrode 9 here are the same. Specifically: in the yellow light process (using a spin coater MRGS150, coating positive photoresist for 5 s to 10 s, with a thickness of 0.8 um to 10 um, a temperature of 85 °C to 110 °C, and a rotation speed of 2500 rpm to 4000 rpm), the shape required for the P-type or N-type is defined (the exposure energy and the full exposure energy of the exposure machine are both 5000 mJ to 10000 mJ, and the developer uses a 2.38% TMAH developer, with a development time of 30 s to 300 s). Then, metal is evaporated (using an evaporator Peva-920EC, and the evaporated metal film is any one or a combination of titanium Ti, nickel Ni, aluminum Al, platinum Pt, gold Au, germanium Ge, and the deposition rate of the metal film is 0.5 A / min to 10 A / min, with a thickness of 50 um to 100 um) onto the chip. The photoresist is removed using the immersion lift-off process (using an NMP solution, with a temperature of 80 °C to 90 °C, an immersion time of 20 min to 60 min, and a high-pressure spray time of 2 min to 5 min), and the photoresist is removed. The metal covering the photoresist will also be lifted off, and the remaining metal forms a P-type pattern or an N-type pattern. Then, the metal sintering alloying process (with a temperature of 360 °C to 440 °C, introducing N2 gas, with a flow rate of 2 L / min to 10 L / min, and a time of 1 min to 10 min) is carried out to make the metal contact resistance lower to form an ohmic contact, so as to obtain the P-type electrode 7 and the N-type electrode 9.

[0032] Such as Figure 8As shown, S6: Define a scribe lane pattern, and perform dry etching on the semi-finished chip according to the scribe lane pattern until it penetrates through the N-DBR layer 2, the active layer 3, the P-DBR layer 5, the substrate 1 and deep into the N-type electrode 9 to obtain a scribe lane 10, and perform chip separation along the scribe lane 10 to obtain a target semiconductor device chip; Specifically, since several chips are usually fabricated simultaneously on the same substrate 1, by determining the scribe lane 10 and during the subsequent separation process, several chips can be divided along the scribe lane 10, thus obtaining several target semiconductor device chips.

[0033] In this embodiment, the distance between the bottom of the scribe lane 10 and the bottom of the N-type electrode 9 is 3.5um - 7um. By setting the distance between the bottom of the scribe lane 10 and the bottom of the N-type electrode 9, the chip separation process can be facilitated.

[0034] As Figure 9 shown, in another embodiment of the present invention, a semiconductor device chip is further provided, and the semiconductor device chip is fabricated by using the above-mentioned fabrication method of the semiconductor device chip.

[0035] In summary, the present invention does not change the chip device structure, adopts another process technology, prepares stress release grooves 8 on the chip, and through the stress release grooves 8, the stress release process can be effectively realized, thereby reducing the chip fragmentation rate. At the same time, the chip fabrication method is simplified, the chip fabrication efficiency is improved, and the cost is reduced.

[0036] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device chip, characterized in that, The method includes: S1. Provide a substrate, and periodically and alternately stack a plurality of first stacks and second stacks on the substrate to obtain an N-DBR layer; S2. Deposit an active layer on the N-DBR layer, and periodically and alternately stack a plurality of third stacks and fourth stacks on the active layer to obtain a P-DBR layer; S3. Deposit a protective layer around the substrate, the N-DBR layer, the active layer, and the P-DBR layer; S4. Define a stress relief groove pattern, and perform dry etching according to the stress relief groove pattern until it penetrates through the protective layer, the P-DBR layer, the active layer and deep into the N-DBR layer to obtain a stress relief groove; S5. Prepare a P-type metal, evaporate the P-type metal on the P-DBR layer to obtain a P-type electrode, bond the side of the P-type electrode away from the substrate to a substrate, prepare an N-type metal, evaporate the N-type metal on one side of the substrate to obtain an N-type electrode, and remove the substrate to obtain a chip semi-finished product; S6. Define a dicing lane pattern, and perform dry etching on the chip semi-finished product according to the dicing lane pattern until it penetrates through the N-DBR layer, the active layer, the P-DBR layer, the substrate and deep into the N-type electrode to obtain a dicing lane, and separate the chips along the dicing lane to obtain a target semiconductor device chip.

2. The method for manufacturing a semiconductor device chip according to claim 1, characterized in that, Both the first stack and the third stack are GaAs layers, and both the second stack and the fourth stack are AlGaAs layers.

3. The method for manufacturing a semiconductor device chip according to claim 1, characterized in that, The range of the alternating stacking period of the first stack and the second stack in the N-DBR layer is 10-20.

4. The method for manufacturing a semiconductor device chip according to claim 1, characterized in that, The range of the alternating stacking period of the third stack and the fourth stack in the P-DBR layer is 10-20.

5. The method for manufacturing a semiconductor device chip according to claim 1, characterized in that, The protective layer is specifically a SiN layer and an Al2O3 layer, and the thickness of the protective layer is 4300A-5200A.

6. The method for manufacturing a semiconductor device chip according to claim 1, characterized in that, An oxidation ring is provided between the P-DBR layer and the active layer.

7. The method for manufacturing a semiconductor device chip according to claim 1, characterized in that, The materials of the P-type electrode and the N-type electrode are both one or more combinations of Ti, Ni, Al, Pt, Au, and Ge.

8. The method for manufacturing a semiconductor device chip according to claim 1, characterized in that, The stress relief groove penetrates into the first first stack near the active layer in the N-DBR layer.

9. The method for manufacturing a semiconductor device chip according to claim 1, characterized in that, The distance between the bottom of the dicing lane and the bottom of the N-type electrode is 3.5um-7um.

10. A semiconductor device chip, characterized in that, The semiconductor device chip is prepared by using the preparation method of the semiconductor device chip according to any one of claims 1-9.

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