Stacked package structure

Abstract

The invention relates to a stacked packaging structure, which comprises a first packaging piece and a second packaging piece which are longitudinally stacked and electrically connected, any one or each packaging piece comprises a first substrate, a second substrate and an intermediate substrate, the opposite surfaces of the first substrate and the second substrate are respectively provided with a first flip chip and a second flip chip, and the intermediary substrate is electrically connected between the opposite surfaces of the first substrate and the second substrate, so that signal transmission is realized between the first flip chip and the second flip chip. By adopting the intermediary substrate, the structural damage caused by thermal stress can be avoided, and the flip chips do not need to be coated by a sealing colloid, so that the sealing colloid can be prevented from being separated from the substrate.

Description

Technical Field

[0001] The present invention relates to a stacked packaging structure, and more particularly to a packaging structure that realizes electrical connection by using an interposer substrate. Background Art

[0002] In order to effectively integrate different types or multiple packaging components, the stacked semiconductor packaging (Package on Package, PoP) technology can stack multiple packaging components three-dimensionally into a miniaturized component to reduce the space occupied by the packaging components in the product.

[0003] Please refer to Figure 4 As shown, according to the existing stacked semiconductor packaging technology, a top package 100 is stacked on top of a bottom package 200, and the top package 100 is electrically connected to the bottom package 200. Each of the top package 100 and the bottom package 200 has a chip inside. For high-bandwidth packages (high bandwidth PoP), the common bottom package 200 further includes an upper substrate 201, a lower substrate 202, and several copper conductive pillars 230 (pillars) longitudinally electrically connected between the upper / lower substrates 201, 202. An encapsulant (EMC) 240 is filled between the upper / lower substrates 201, 202 to cover the chips inside the bottom package.

[0004] However, when forming the copper conductive pillars 230 between the upper substrate 201 and the lower substrate 202, the copper conductive pillars 230 are usually formed by electroplating. If voids are formed inside the copper conductive pillars 230 during the electroplating process, the copper conductive pillars 230 may be damaged due to thermal stress, affecting their electrical transmission ability; furthermore, the thermal expansion coefficients (CTE) of the encapsulant 240 and the upper / lower substrates 201, 202 are different, resulting in a problem of thermal separation between the encapsulant 240 and the upper / lower substrates 201, 202. Therefore, the existing stacked packaging components really need to be further improved. Summary of the Invention

[0005] In view of this, the main object of the present invention is to provide a "stacked packaging structure" to reduce the possibility of structural damage to the electrical connection components in the packaging components due to thermal stress and without the need to use traditional encapsulants.

[0006] To achieve the foregoing object, the stacked packaging structure of the present invention includes:

[0007] A first package;

[0008] A second package, stacked and connected to the first package, wherein the second package includes:

[0009] A first substrate having an inner surface and an outer surface opposite to each other, the outer surface being electrically connected to the first package, and a first flip-chip being electrically connected to the inner surface;

[0010] A second substrate having an inner surface and an outer surface opposite to each other, the inner surface of the second substrate facing the inner surface of the first substrate, and a second flip-chip being electrically connected to the inner surface of the second substrate;

[0011] An intermediate substrate being electrically connected between the inner surface of the first substrate and the inner surface of the second substrate, encapsulant being distributed between the intermediate substrate and the first substrate, encapsulant being distributed between the intermediate substrate and the second substrate, the intermediate substrate forming a chip accommodating opening, and the first flip-chip and the second flip-chip corresponding to the chip accommodating opening;

[0012] A plurality of external connectors being disposed on the outer surface of the second substrate.

[0013] In the present invention, the first substrate and the second substrate are electrically connected by an intermediate substrate, and there is no need to use an electroplating process to form copper conductive pillars, so that the destruction of the copper conductive pillar structure caused by thermal stress can be avoided. There is no encapsulant (EMC) covering the chips between the first substrate and the second substrate, so the problem of separation between the encapsulant and the first substrate or the second substrate will not occur. Description of the Drawings

[0014] Figure 1 : A cross-sectional schematic diagram of the first embodiment of the stacked package structure of the present invention.

[0015] Figure 2 : A cross-sectional schematic diagram of the second embodiment of the stacked package structure of the present invention.

[0016] Figure 3 : A cross-sectional schematic diagram of the third embodiment of the stacked package structure of the present invention.

[0017] Figure 4 : A cross-sectional schematic diagram of a conventional stacked package structure. Detailed Description of the Invention

[0018] Please refer to Figure 1As shown, according to the first embodiment of the stacked packaging structure of the present invention, the stacked packaging structure includes a first packaging component A and a second packaging component B, and the first packaging component A is vertically disposed above the second packaging component B. Any one or both of the first packaging component A and the second packaging component B may have the specific structures introduced below. In this example, the structure of the first packaging component A is not particularly limited. For example, a memory chip is provided inside the first packaging component A, and the second packaging component B includes a first substrate 10, a second substrate 20, and an interposer substrate 40 shown in the figure.

[0019] The first substrate 10 has an outer surface 11 and an inner surface 12 opposite to each other. The outer surface 11 faces the first packaging component A, and a plurality of outer contacts 110 are provided on the outer surface 11. The plurality of outer contacts 110 are correspondingly electrically connected to the first packaging component A. For example, the outer contacts 110 and the first packaging component A are connected by solder balls.

[0020] The inner surface 12 of the first substrate 10 is a flat surface, and a first flip-chip 31 is provided on the inner surface 12. The first flip-chip 31 is electrically connected to the inner surface 12 by the contacts at its bottom, and underfill is filled between the bottom of the first flip-chip 31 and the first substrate 10; a plurality of inner contacts 120 are provided on the inner surface 12 around the first flip-chip 31, and the plurality of inner contacts 120 are electrically connected to the corresponding outer contacts 110 through a first redistribution layer 13 formed inside the first substrate 10.

[0021] The second substrate 20 has an outer surface 21 and an inner surface 22 opposite to each other. The inner surface 22 faces the inner surface 12 of the first substrate 10. A second flip-chip 32 is provided on the inner surface 22, and the second flip-chip 32 is electrically connected to the inner surface 22 by the contacts at its bottom; a plurality of inner contacts 220 are further provided on the inner surface 22 around the second flip-chip 32. The non-active surface of the second flip-chip 32 faces the non-active surface of the first flip-chip 31, and underfill is injected between the bottom of the second flip-chip 32 and the second substrate 20. Whether it is the first flip-chip 31 or the second flip-chip 32, the underfill is likely to form micro pores inside during the curing process due to its material properties. The plurality of micro pores have a ventilation function. If water vapor is generated, the plurality of micro pores can also discharge the water vapor to avoid the water vapor remaining between the chip and the substrate.

[0022] A plurality of outer contacts 210 are provided on the outer surface 21, and the plurality of outer contacts 210 are electrically connected to corresponding inner contacts 220 through a second rewiring layer 23 formed inside the second substrate 20. An external connector 24, such as a solder ball, is further provided on the surface of each of the outer contacts 210 and serves as a contact for external electrical connection of the stacked package structure of the present invention.

[0023] The interposer substrate 40 has an upper surface 41 and a lower surface 42 opposite to each other. A plurality of upper contacts 410 are formed on the upper surface 41, and a plurality of lower contacts 420 are formed on the lower surface 42. The plurality of upper contacts 410 are electrically connected to the lower contacts 420 through an internal rewiring layer 43 inside the interposer substrate 40. The plurality of upper contacts 410 are used to connect to the inner contacts 120 of the first substrate 10 (for example, electrically connected through solder or conductive bumps), and the plurality of lower contacts 420 are used to connect to the inner contacts 220 of the second substrate 20 (for example, electrically connected through solder or conductive bumps). A filling adhesive 45 is distributed between the interposer substrate 40 and the first substrate 10 and the second substrate 20. The filling adhesive 45 can protect the electrical connection structures between the plurality of upper contacts 410, lower contacts 420 and the inner contacts 120, 220 respectively, and reduce the probability of breakage and separation between the interposer substrate 40 and the first substrate 10 and the second substrate 20. An opening 47 is formed in the interposer substrate 40 at positions corresponding to the first flip chip 31 and the second flip chip 32. The opening 47 is surrounded by the first substrate 10, the second substrate 20 and the plurality of filling adhesives 45 to form a chip accommodating space 50. The first flip chip 31 and the second flip chip 32 are correspondingly located inside the chip accommodating space 50, and the non-active surfaces and side wall surfaces of the first flip chip 31 and the second flip chip 32 are directly exposed inside the chip accommodating space 50 without being coated with a filling adhesive or other encapsulant.

[0024] The interposer substrate 40 not only provides the function of electrical connection, but also provides a supporting role between the first substrate 10 and the second substrate 20 to maintain an appropriate gap d between the first substrate 10 and the second substrate 20. In an embodiment, the thickness of the interposer substrate 40 is greater than the sum of the heights of the two chips of the first flip chip 31 and the second flip chip 32.

[0025] Please refer to Figure 2As shown, this is the second embodiment of the stacked packaging structure of the present invention. Among them, on the inner surface 12 of the first substrate 10 around the first flip-chip 31, a first annular groove 61 is formed; on the inner surface 22 of the second substrate 20, a second annular groove 62 is formed around the second flip-chip 32. Both the first annular groove 61 and the second annular groove 62 are located inside the chip accommodation space 50. During the process of injecting the filling glue 45, the first annular groove 61 and the second annular groove 62 can prevent excessive glue from overflowing everywhere, achieving the effect of preventing glue overflow.

[0026] Please refer to Figure 3 As shown, this is the third embodiment of the stacked packaging structure of the present invention. Among them, compared with the first embodiment, on the inner surface 12 of the first substrate 10 around the first flip-chip 31, a first annular dam 63 is formed; on the inner surface 22 of the second substrate 20, a second annular dam 64 is formed around the second flip-chip 32. Both the first annular dam 63 and the second annular dam 64 are located inside the chip accommodation space 50. During the process of injecting the filling glue 45, the first annular dam 63 and the second annular dam 64 can prevent excessive glue from overflowing everywhere, achieving the effect of preventing glue overflow.

[0027] The present invention electrically connects the first substrate 10 and the second substrate 20 by using an intermediate substrate 40, and then coats the intermediate substrate 40 with a filling glue 45. Since there is no need to use an electroplating process to form conductive elements, the problem of structural damage caused by thermal stress can be avoided. Furthermore, when the intermediate substrate 40 is butted against the first substrate 10 and the second substrate 20, the pitch of the upper contacts 410 and the lower contacts 420 of the intermediate substrate 40 can be narrowed according to requirements to accommodate a larger number of contacts to be butted against the first substrate 10 and the second substrate 20, which is more suitable for packaging products with a large number of contacts. For example, the pitch between the several upper contacts 410 and the lower contacts 420 of the intermediate substrate 40 is different from the pitch between the outer contacts 110 and 210 of the first substrate 10 and the second substrate 20. In an embodiment, the pitch between the several upper contacts 410 and the lower contacts 420 is smaller than the pitch between the outer contacts 110 and 210. On the other hand, the present invention does not require a sealing colloid (EMC) to coat between the first substrate 10 and the second substrate 20, so the problem of separation between the sealing colloid and the substrate caused by the difference in thermal expansion coefficient will not occur.

[0028] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments of equivalent changes within the scope of the technical solution of the present invention by using the above-disclosed technical content. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A stacked package structure, characterized in that: Include: a first packaging component; A second package, stacked and connected to the first package, wherein the second package comprises: A first substrate having an inner surface and an outer surface opposite to each other, wherein the outer surface is electrically connected to the first package, and a first flip chip is electrically connected to the inner surface; A second substrate having an inner surface and an outer surface opposite to each other, wherein the inner surface of the second substrate faces the inner surface of the first substrate, and a second flip chip is electrically connected to the inner surface of the second substrate; An intermediate substrate is electrically connected between the inner surface of the first substrate and the inner surface of the second substrate, a filling glue is distributed between the intermediate substrate and the first substrate, a filling glue is distributed between the intermediate substrate and the second substrate, and an opening is formed in the intermediate substrate, and the first flip chip and the second flip chip correspond to the opening; A plurality of external connecting members are arranged on the outer surface of the second substrate.

2. The package-on-package structure according to claim 1, wherein: A first annular groove is formed on the inner surface of the first substrate around the first flip chip; A second annular groove is formed on the inner surface of the second substrate around the second flip chip.

3. The package-on-package structure according to claim 1, wherein: On the inner surface of the first substrate, a first annular dam is formed around the first flip chip; A second annular convex dam is formed on the inner surface of the second substrate around the second flip chip.

4. The package-on-package structure according to claim 1, wherein: The inner surface of each of the first substrate and the second substrate is a flat surface; the non-active surfaces of the first flip chip and the second flip chip face each other and are spaced apart by a distance.

5. The package-on-package structure according to claim 1, wherein: The opening of the intermediate substrate is surrounded by the first substrate, the second substrate and the filling glue to form a chip accommodating space. The first flip chip and the second flip chip are located in the chip accommodating space.

6. The package-on-package structure according to claim 5, wherein: The non-active surfaces and sidewall surfaces of the first flip chip and the second flip chip are exposed outside the chip accommodating space and are not covered.

7. The package-on-package structure according to claim 1, wherein: The intermediate substrate has an upper surface and a lower surface opposite to each other, the upper surface is formed with a plurality of upper contacts, the lower surface is formed with a plurality of lower contacts, the plurality of upper contacts are electrically connected to the plurality of lower contacts through an internal redistribution layer inside the intermediate substrate; A plurality of inner contacts are disposed on the inner surface of the first substrate, and a plurality of outer contacts are disposed on the outer surface, wherein the plurality of inner contacts and the plurality of outer contacts are electrically connected to each other through a first redistribution layer in the first substrate, wherein the plurality of inner contacts are connected to the plurality of upper contacts of the intermediate substrate; A plurality of inner contacts are arranged on the inner surface of the second substrate, and a plurality of outer contacts are arranged on the outer surface. The plurality of inner contacts and the plurality of outer contacts are electrically connected correspondingly through a second redistribution layer in the second substrate, wherein the plurality of inner contacts of the second substrate are connected to the plurality of lower contacts of the intermediate substrate.

8. The package-on-package structure according to claim 7, wherein: The contact pitch between the plurality of upper contacts of the intermediate substrate is different from the contact pitch between the outer contacts of the first substrate; The contact pitch between the plurality of lower contacts of the intermediate substrate is different from the contact pitch between the outer contacts of the second substrate.

9. The package-on-package structure according to claim 7, wherein: The contact pitch between the plurality of upper contacts of the intermediate substrate is smaller than the contact pitch between the outer contacts of the first substrate; The contact pitch between the plurality of lower contacts of the intermediate substrate is smaller than the contact pitch between the outer contacts of the second substrate.

10. The package-on-package structure according to claim 1, wherein: The thickness of the intermediate substrate is greater than the sum of the heights of the first flip-chip chip and the second flip-chip chip.

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