Stacked package structure

Abstract

The invention relates to a stacked packaging structure, which comprises a first packaging piece and a second packaging piece which are longitudinally stacked and electrically connected, any one or each packaging piece comprises a first substrate and a second substrate, a chip accommodating groove is formed in the inner side surface of the first substrate, and the chip accommodating groove is formed in the inner side surface of the second substrate. A chip containing groove is formed in the first substrate, a first flip chip is arranged in the chip containing groove, a second flip chip is arranged on the inner side face, facing the chip containing groove, of the second substrate, and a plurality of inner side contacts are arranged on the opposite surfaces of the first substrate and the second substrate. The first substrate and the second substrate are correspondingly and electrically connected through the plurality of inner side contacts, and the first flip chip and the second flip chip do not need to be wrapped by a sealing colloid, so that the problem that the sealing colloid is separated from the substrates can be avoided.

Description

Technical Field

[0001] The present invention relates to a stacked package structure, and more particularly to a package structure that can be directly butt-jointed with a relative substrate. Background Art

[0002] In order to effectively integrate different types or multiple package components, the stacked semiconductor package (Package on Package, PoP) technology can stack multiple package components three-dimensionally into a miniaturized component to reduce the space occupied by the package components in the product.

[0003] Please refer to Figure 5 As shown, according to the existing stacked semiconductor package technology, a top package 100 is stacked on top of a bottom package 200, and the top package 100 is electrically connected to the bottom package 200. A chip is respectively disposed inside the top package 100 and the bottom package 200. For a high bandwidth package (high bandwidth PoP), the common bottom package 200 further includes an upper substrate 201, a lower substrate 202, and several copper conductive pillars 230 (pillars) longitudinally electrically connected between the upper / lower substrates 201, 202. An encapsulant (EMC) 240 is filled between the upper / lower substrates 201, 202 to cover the chips inside the bottom package.

[0004] When forming the copper conductive pillars 230 inside the encapsulant 240 between the upper substrate 201 and the lower substrate 202, the copper conductive pillars 230 are usually formed by electroplating. If voids are formed inside the copper conductive pillars 230 during the electroplating process, the copper conductive pillars 230 may be damaged due to thermal stress, affecting the electrical transmission ability. Furthermore, the thermal expansion coefficients (CTEs) of the encapsulant 240 and the upper / lower substrates 201, 202 are different, resulting in a problem of thermal separation between the encapsulant 240 and the upper / lower substrates 201, 202. Therefore, the existing stacked package components really need to be further improved. Summary of the Invention

[0005] In view of this, the main object of the present invention is to provide a stacked package structure to reduce the possibility of structural damage of the electrical connection components in the package components due to thermal stress, and without using an encapsulant to cover the chips.

[0006] To achieve the foregoing object, the stacked package structure of the present invention includes:

[0007] A first package;

[0008] A second package, stacked and connected to the first package, wherein the second package includes:

[0009] A first substrate has an inner surface and an outer surface opposite to each other. The outer surface is electrically connected to the first package. The inner surface is recessed towards the outer surface to form a chip receiving groove. A first flip chip is electrically connected to an inner bottom surface of the chip receiving groove. Wherein, a protective layer covers both the inner bottom surface and the surrounding inner side surfaces of the chip receiving groove;

[0010] A second substrate has an inner surface and an outer surface opposite to each other. The inner surface of the second substrate is electrically connected to the inner surface of the first substrate. A second flip chip is disposed on the inner surface of the second substrate at a position corresponding to the chip receiving groove;

[0011] Several external connectors are disposed on the outer surface of the second substrate.

[0012] In the present invention, the first substrate and the second substrate are directly electrically connected to each other, and a chip receiving groove is formed in one of the substrates to accommodate the first and second chips. Since it is not necessary to coat the first and second chips with an encapsulant (EMC), the problem of separation between the encapsulant and the substrate caused by different coefficients of thermal expansion can be avoided; nor are there conductive copper pillars formed inside the encapsulant, so the problem of structural damage to the conductive copper pillars caused by thermal stress can be avoided. Description of the Drawings

[0013] Figure 1 : A cross-sectional schematic view of the first embodiment of the stacked package structure of the present invention.

[0014] Figure 2 : A cross-sectional schematic view of the second embodiment of the stacked package structure of the present invention.

[0015] Figure 3 : A cross-sectional schematic view of the third embodiment of the stacked package structure of the present invention.

[0016] Figure 4 : A cross-sectional schematic view of the fourth embodiment of the stacked package structure of the present invention.

[0017] Figure 5 : A cross-sectional schematic view of a conventional stacked package structure. Detailed Description of the Invention

[0018] Please refer to Figure 1As shown, according to the first embodiment of the stacked packaging structure of the present invention, the structure includes a first package A and a second package B, and the first package A is vertically disposed above the second package B. Any one or both of the first package A and the second package B may have the specific structures described below. In this example, the structure of the first package A is not particularly limited. For example, a memory chip is provided inside the first package A, and the second package B includes a first substrate 10, a second substrate 20, a first flip-chip 31, and a second flip-chip 32 as shown in the figure.

[0019] The first substrate 10 has an outer surface 11 and an inner surface 12 opposite to each other. The outer surface 11 faces the first package A, and a plurality of outer contacts 110 are provided on the outer surface 11. The plurality of outer contacts 110 are correspondingly electrically connected to the first package A. For example, the outer contacts 110 and the first package A are connected by solder balls.

[0020] The inner surface 12 of the first substrate 10 is recessed inward in the direction facing the outer surface 11 to form a chip receiving groove 16. The first flip-chip 31 is electrically connected to the inner bottom surface of the chip receiving groove 16. The first flip-chip 31 is electrically connected to the inner surface 12 by the contacts at its bottom. An underfill is filled between the bottom of the first flip-chip 31 and the first substrate 10. A plurality of inner contacts 120 are provided on the inner surface 12 around the chip receiving groove 16. The plurality of inner contacts 120 are electrically connected to the corresponding outer contacts 110 through a first redistribution layer 13 formed inside the first substrate 10. In one embodiment, the pitch between the inner contacts 120 is smaller than the pitch between the outer contacts 110.

[0021] In this embodiment, a protective layer 18 may further be covered on the inner bottom surface and the inner side surfaces around the chip receiving groove 16. The protective layer 18 can be used to protect any metal layer exposed inside the chip receiving groove 16. For example, if a part of the first redistribution layer 13 is exposed inside the chip receiving groove 16, the first redistribution layer 13 can be protected by covering the protective layer 18.

[0022] The second substrate 20 has an opposite outer surface 21 and an inner surface 22. The inner surface 22 faces the inner surface 12 of the first substrate 10 and is spaced apart by a distance d. A second flip-chip 32 is disposed on the inner surface 22. The second flip-chip 32 is electrically connected to the inner surface 22 by contacts at its bottom. The non-active surface of the second flip-chip 32 faces the non-active surface of the first flip-chip 31. Underfill is also injected between the bottom of the second flip-chip 32 and the second substrate 20. Whether it is the first flip-chip 31 or the second flip-chip 32, during the curing process of the underfill, due to its material properties, micro-voids are likely to form inside. These micro-voids have a ventilation function. If moisture is generated, these micro-voids can also discharge the moisture, preventing the moisture from remaining between the chip and the substrate. And several inner contacts 220 are disposed on the periphery of the second flip-chip 32 on the inner surface 22. These inner contacts 220 are correspondingly electrically connected to the inner contacts 120 of the first substrate 10. For example, conductive bumps 121 and 221 are respectively formed on the surfaces of the inner contacts 120 and 220, and these conductive bumps 121 and 221 are correspondingly connected to each other.

[0023] Several outer contacts 210 are disposed on the outer surface 21. These outer contacts 210 are electrically connected to the corresponding inner contacts 220 through a second rewiring layer 23 formed inside the second substrate 20. In an embodiment, the pitch between the inner contacts 220 is smaller than the pitch between the outer contacts 210. An external connector 24 is further disposed on the surface of each of the outer contacts 210. These external connectors 24 are, for example, solder balls and serve as the contacts for external electrical connection of the stacked package structure of the present invention.

[0024] A chip accommodation space 50 is formed between the chip accommodation groove 16 of the first substrate 10 and the second substrate 20, such that the first flip-chip 31 and the second flip-chip 32 are located inside the chip accommodation space 50. The non-active surface and the peripheral surface of each chip do not need to be coated with an encapsulant (EMC), but are directly exposed inside the chip accommodation space 50. The relative distance between the first flip-chip 31 and the second flip-chip 32 can be determined according to the depth of the chip accommodation groove 16. The depth of the chip accommodation groove 16 is greater than the sum of the heights of the first flip-chip 31 and the second flip-chip 32.

[0025] Please refer to Figure 2 As shown in the second embodiment of the stacked package structure of the present invention, after the conductive bumps 121 and 221 are connected to each other, underfill 40 is further injected into the gap between the opposite inner surfaces 12 and 22. These underfills 40 can coat the conductive bumps 121 and 221, preventing them from being broken or separated due to stress and damaging the electrical connection.

[0026] Please refer to Figure 3 As shown, it is the third embodiment of the stacked packaging structure of the present invention. Compared with the first embodiment, on the inner bottom surface of the chip accommodating groove 16 around the first flip chip 31, a first annular groove 61 is formed; on the inner side surface 22 of the second substrate 20, a second annular groove 62 is formed around the second flip chip 32. Both the first annular groove 61 and the second annular groove 62 are located inside the chip accommodating space 50. During the process of injecting the plurality of underfills, the first annular groove 61 and the second annular groove 62 can prevent excessive colloid from overflowing everywhere, achieving the effect of preventing colloid overflow. In one embodiment, the position of the first annular groove 61 corresponds to the position of the second annular groove 62. In another embodiment, the position of the first annular groove 61 is misaligned with the position of the second annular groove 62.

[0027] Please refer to Figure 4 As shown, it is the fourth embodiment of the stacked packaging structure of the present invention. Compared with the first embodiment, on the inner bottom surface of the chip accommodating groove 16 around the first flip chip 31, a first annular dam 63 is formed; on the inner side surface 22 of the second substrate 20, a second annular dam 64 is formed around the second flip chip 32. Both the first annular dam 63 and the second annular dam 64 are located inside the chip accommodating space 50. During the process of injecting the underfill, the first annular dam 63 and the second annular dam 64 can prevent excessive colloid from overflowing everywhere, achieving the effect of preventing colloid overflow. In one embodiment, the position of the first annular dam 63 is misaligned with the position of the second annular dam 64. In another embodiment, the height of the first annular dam 63 is greater than the height of the first flip chip 31; the height of the second annular dam 64 is greater than the height of the second flip chip 32.

[0028] The present invention directly electrically connects the contacts on the opposite surfaces of the first substrate and the second substrate. The chips can be accommodated in the chip accommodating grooves of one of the substrates, and each chip does not need to be coated with encapsulant (EMC). Therefore, the problem of separation between the encapsulant and the substrate caused by the difference in thermal expansion coefficient will not occur; nor is it necessary to form conductive copper pillars inside the encapsulant, so the problem of damage to the conductive copper pillar structure caused by thermal stress can be avoided.

[0029] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the disclosed technical content within the scope of the technical solution of the present invention. However, as long as it does not depart from the technical content of the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A stacked package structure, characterized in that: Include: a first packaging component; A second package, stacked and connected to the first package, wherein the second package comprises: A first substrate having an inner surface and an outer surface opposite to each other, the outer surface being electrically connected to the first package, the inner surface being concave toward the outer surface to form a chip accommodating groove, a first flip chip being electrically connected to an inner bottom surface of the chip accommodating groove, wherein the inner bottom surface and surrounding inner side surfaces of the chip accommodating groove are all covered with a protective layer; A second substrate having an inner surface and an outer surface opposite to each other, the inner surface of the second substrate being electrically connected to the inner surface of the first substrate, and a second flip chip being arranged on the inner surface of the second substrate at a position corresponding to the chip accommodating groove; A plurality of external connecting members are arranged on the outer surface of the second substrate.

2. The package-on-package structure according to claim 1, wherein: A first annular groove is formed on the inner bottom surface of the chip accommodating groove of the first substrate around the first flip chip; A second annular groove is formed on the inner surface of the second substrate around the second flip chip.

3. The stacked package structure according to claim 2, wherein: The position of the first annular groove corresponds to the position of the second annular groove.

4. The stacked package structure according to claim 2, wherein: The position of the first annular groove is offset from the position of the second annular groove.

5. The package-on-package structure according to claim 1, wherein: A first annular dam is formed on the inner bottom surface of the chip accommodating groove of the first substrate around the first flip chip; A second annular convex dam is formed on the inner surface of the second substrate around the second flip chip.

6. The package-on-package structure according to claim 5, wherein: The position of the first annular convex dam is offset from the position of the second annular convex dam.

7. The package-on-package structure according to claim 5, wherein: The height of the first annular dam is greater than the height of the first flip-chip chip; the height of the second annular dam is greater than the height of the second flip-chip chip.

8. The package-on-package structure according to claim 1, wherein: The non-active surfaces and peripheral surfaces of the first flip chip and the second flip chip are exposed outside the chip accommodating groove without being covered.

9. The package-on-package structure according to claim 1, wherein: A plurality of inner contacts are disposed on the inner surface of the first substrate, and a plurality of outer contacts are disposed on the outer surface, wherein the plurality of inner contacts and the plurality of outer contacts are electrically connected to each other through a first redistribution layer in the first substrate, wherein a contact spacing between the plurality of inner contacts is smaller than a contact spacing between the outer contacts; A plurality of inner contacts are arranged on the inner surface of the second substrate to electrically connect the plurality of inner contacts of the first substrate. The plurality of inner contacts of the second substrate and the plurality of external connecting parts are electrically connected correspondingly through a second redistribution layer in the second substrate, wherein the contact spacing between the plurality of inner contacts of the second substrate is smaller than the contact spacing between the plurality of external connecting parts of the second substrate.

10. The package-on-package structure according to claim 1, wherein: The depth of the chip accommodating groove is greater than the sum of the heights of the first flip-chip chip and the second flip-chip chip.

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