Semiconductor device and method of forming protective layer on substrate to avoid damage during packaging

Abstract

A semiconductor device has a substrate and a protective layer formed on a saw track of the substrate. The protective layer may extend over the width of the saw track. The protective layer may extend less than or greater than the width of the saw track. The electrical component is disposed on a surface of the substrate. The connector is disposed on a surface of the substrate. A slot mold having a lower housing and an upper housing is used to deposit an encapsulant on the electrical component. During sealing, the sealant should not migrate to the connector. A high pressure is applied to the upper housing of the slot mold to prevent sealant migration to the connector. The protective layer protects the substrate from high pressures during sealing. A shielding layer is formed over the encapsulant.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more particularly to semiconductor devices and methods for forming a protective layer on a substrate to avoid damage during packaging. Summary of the Invention

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a variety of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communication, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

[0003] Semiconductor devices, especially in high-frequency applications such as radio frequency (RF) wireless communication, typically include one or more integrated passive devices (IPDs) to perform necessary electrical functions. Multiple semiconductor dies and IPDs can be integrated into a system-in-package (SiP) module for higher density and extended electrical functions in a small space. Within the SiP module, the semiconductor dies and IPDs are disposed on a first surface of a substrate for structural support and electrical interconnection. A sealant is deposited on the semiconductor dies, IPDs, and the substrate. Electrical connectors are disposed on the first surface of the substrate for electrical communication between the electrical components and external devices.

[0004] An antenna can be disposed on a second surface of the substrate to provide wireless communication for the SiP module. In the case where an antenna is added, the SiP constitutes an antenna-in-package (AiP). In any case, it is important that the sealant does not migrate from the electrical components to the connectors. Any sealant reaching the connectors can cause defects in the SiP or AiP. A chase mold is used for sealing. The chase mold includes a lower housing and an upper housing. The SiP or AiP is placed in the lower housing and then enclosed by the upper housing. Considerable pressure is typically applied to the upper housing to prevent the molding compound from creeping onto the connectors. However, the high pressure on the upper housing required to prevent unwanted leakage of the sealant into the connector area can also cause the substrate or the SiP or AiP to crack or be damaged. It is desirable to prevent the sealant from migrating into the connector area without damaging the substrate or the SiP or AiP in order to reduce or minimize defects. Brief Description of the Drawings

[0005] Figure 1a - 1c A semiconductor wafer having multiple semiconductor dies separated by saw tracks is illustrated;

[0006] Figure 2a - 2n A process for forming an AiP substrate is illustrated, where a protective layer is formed in the saw tracks to limit the pressure on the substrate during packaging;

[0007] Figure 3a - 3d Illustrates additional details of the protective layer;

[0008] Figure 4a - 4b Illustrates additional details of the sealed protective layer;

[0009] Figure 5a - 5c Illustrates the sealed AiP substrate with a shielding layer;

[0010] Figure 6a - 6b Illustrates the singulation of the AiP substrate;

[0011] Figure 7a - 7b Illustrates the singulated AiP with a shielding layer; and

[0012] Figure 8 Illustrates a printed circuit board (PCB) on which different types of packages are disposed on the surface of the PCB. Detailed Description

[0013] In the following description with reference to the figures, the invention is described in one or more embodiments, where like numbers represent like or similar elements. While the invention is described in terms of the best mode for achieving the purposes of the invention, those skilled in the art will appreciate that the invention is intended to cover substitutions, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents, which are supported by the following disclosure and the drawings. The term "semiconductor die" as used herein refers to both the singular and plural forms of the word and may thus refer to both a single semiconductor device and multiple semiconductor devices.

[0014] Two complex manufacturing processes are typically used to fabricate semiconductor devices: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, and resistors create relationships between the voltages and currents necessary to perform circuit functions.

[0015] Backend manufacturing refers to cutting or singulating a completed wafer into individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnection, and environmental isolation. To singulate the semiconductor die, the wafer is scribed and broken along non-functional regions of the wafer (referred to as saw streets or scribe lines). The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor die are placed on a package substrate that includes pins or contact pads for interconnection with other system components. Then, the contact pads formed on the semiconductor die are connected to the contact pads within the package. The electrical connection can be achieved with conductive layers, bumps, pillar bumps, conductive adhesives, or wire bonding. A sealant or other molding material is deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system and the functionality of the semiconductor device is made available to other system components.

[0016] Figure 1a A semiconductor wafer 100 having a base substrate material 102 is shown, where the base substrate material 102 is, for example, silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor die or components 104 are formed on the wafer 100 and are separated by non-active die-to-die wafer regions or saw streets 106. The saw streets 106 provide a cutting area to singulate the semiconductor wafer 100 into individual semiconductor die 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100 - 450 millimeters (mm). The semiconductor die 104 can process RF signals transmitted and received through an antenna.

[0017] Figure 1b A cross-sectional view of a portion of the semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or non-active surface 108 and an active surface 110 that contains analog or digital circuitry that is implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and functionality of the die. For example, the circuitry can include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement an analog circuit or a digital circuit, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), a memory, or other signal processing circuitry. The semiconductor die 104 can also include IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0018] Use PVD, CVD, electrolytic electroplating, electroless plating processes, or other suitable metal deposition processes to form a conductive layer 112 on the active surface 110. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 operates as a contact pad for an electrical circuit connected to the active surface 110.

[0019] Use evaporation, electrolytic electroplating, electroless plating, ball-drop, or screen printing processes to deposit a conductive bump material on the conductive layer 112. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. Use a suitable attachment or bonding process to bond the bump material to the conductive layer 112. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 114. In one embodiment, the bumps 114 are formed on an under-bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesion layer. The bumps 114 can also be compression bonded or thermocompression bonded to the conductive layer 112. The bumps 114 represent one type of interconnect structure that can be formed on the conductive layer 112. Interconnect structures can also use bonding wires, conductive adhesives, columnar bumps, micro-bumps, or other electrical interconnections.

[0020] In Figure 1c it, a saw blade or a laser cutting tool 118 is used to singulate the semiconductor wafer 100 into individual semiconductor die 104 through saw streets 106. The individual semiconductor die 104 can be inspected and electrically tested to identify known good die or units (KGD / KGU) after singulation.

[0021] Figure 2a - 2n Illustrated is a process for forming an AiP substrate, where a protective layer is formed in the saw street to limit the pressure on the substrate during sealing; Figure 2a Shown is a cross-sectional view of an interconnect and antenna substrate 120, including a core material 121, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials for structural support. Alternatively, the core material 121 can be a multi-layer flexible laminate, ceramic, copper-clad laminate (CCL), glass, or epoxy molding compound. The core material 121 can include one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder mask, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. Conductive vias 123 are formed through the core material 121 by forming vias through the core material and filling the vias with a conductive material.

[0022] An insulating layer 130 is formed on the surface 125 of the core material 121. The insulating layer 130 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. In one embodiment, the insulating layer 130 is a solder mask. The insulating layer 130 can be formed using PVD, CVD, printing, lamination, spin coating, spraying, sintering, or thermal oxidation. A portion of the insulating layer 130 is removed by etching or laser direct ablation (LDA), and one or more conductive layers 122 are formed on the surface 125 of the core material 121. The conductive layer 122 can be formed before the insulating layer 130. The conductive layer 122 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer 122 can be formed using PVD, CVD, electroplating, electroless plating processes, or other suitable metal deposition processes. The conductive layer 122 provides horizontal and vertical electrical interconnections across the substrate 120. Depending on the design and function of the semiconductor die 104 and other electrical components, portions of the conductive layer 122 can be electrically common or electrically isolated. The insulating layer 130 provides isolation between the conductive layers 122. There can be multiple conductive layers (such as 122) separated by multiple insulating layers (such as 130).

[0023] An insulating layer 132 is formed on a surface 131 of the core material 121 opposite to the surface 125. The insulating layer 132 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. In one embodiment, the insulating layer 132 is a solder mask. PVD, CVD, printing, lamination, spin coating, spraying, sintering, or thermal oxidation can be used to form the insulating layer 132. A portion of the insulating layer 132 is removed by etching or LDA, and one or more conductive layers 124 are formed on the surface 131 of the core material 121. The conductive layer 124 can be formed before the insulating layer 132. The conductive layer 124 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. PVD, CVD, electroplating, electroless plating process, or other suitable metal deposition processes can be used to form the conductive layer 124. In one embodiment, the conductive layer 124 operates as an antenna region 129 to transmit and receive RF signals for later installed electrical components. The electrical components will be electrically connected to the antenna region 129 by means of the vertical and horizontal segments of the conductive layer 122 and the conductive vias 123. Depending on the design and function of the semiconductor die 104 and other electrical components, portions of the conductive layer 124 can be electrically common or electrically isolated. The insulating layer 132 provides isolation between the conductive layers 124. There can be multiple conductive layers (such as 124) separated by multiple insulating layers (such as 132). With the antenna region 129, the interconnect substrate 120 becomes an AiP substrate.

[0024] Figure 2b is a top view of the substrate 120. The substrate 120 includes die or component mounting locations 135a, 135b, 135c, and 135d for later installed electrical components. The substrate 120 also includes connector mounting locations 137a, 137b, 137c, and 137d for later installed connectors. Note that the regions 133 separate the die or component mounting locations 135a - 135d from the connector mounting locations 137a - 137d respectively. The regions 133 provide clamping regions or lines to avoid the situation or possibility of the sealant migrating onto the connectors and contaminating the connectors, where the sealant will later cover the electrical components, which is further explained below. As shown, the saw streets 139a - 139f separate the die or component mounting locations 135a - 135d and the connector mounting locations 137a - 137d.

[0025] Use PVD, CVD, electrolytic plating, electroless plating processes or other suitable metal deposition processes to form a protective layer 134 on the insulating layer 130 and / or the core substrate 121. In one embodiment, the protective layer 134 is a conductive layer made of one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. The protective layer 134 spans the width of the saw tracks 139a - 139f to protect the insulating layer 130 during subsequent sealing processes, as described below.

[0026] Figure 2c Another embodiment of the protective layer 134 is illustrated, which is shown as a narrow strip measuring less than the width of the saw tracks 139a - 139f. Figure 2d Yet another embodiment of the protective layer 134 is illustrated, which is shown as spanning the width and length of the saw tracks 139d - 139f. Elements with similar functions are given the same reference numerals.

[0027] In Figure 2e multiple electrical components 140a - 140d are disposed on the surface 126 of the interconnect substrate 120 to be electrically and mechanically connected to the conductive layer 122. A pick - and - place operation is used to position each of the electrical components 140a - 140d on the substrate 120. For example, the electrical components 140a and 140c can be discrete electrical devices or IPDs, such as diodes, transistors, resistors, capacitors, and inductors, where the terminals 144 are disposed on the surface 126 of the interconnect substrate 120 and are electrically and mechanically connected to the conductive layer 122. The electrical components 140b and 140d can be similar to the semiconductor die 104 from Figure 1c where the active surface 110 and the bumps 114 are oriented towards the surface 126 of the substrate 120. Alternatively, the electrical components 140a - 140d can include other semiconductor dies, semiconductor packages, surface - mount devices, discrete electrical devices, or IPDs.

[0028] The electrical components 140a - 140d are brought into contact with the surface 126 of the substrate 120. The bumps 114 are reflowed to mechanically and electrically connect the electrical components 140b and 140d to the conductive layer 122. A conductive adhesive 146 bonds the electrical components 140a and 140c to the conductive layer 122.

[0029] In a similar manner, a plurality of electrical connectors 142a - 142b are disposed on the surface 126 of the interconnect substrate 120 to be electrically and mechanically connected to the conductive layer 122. A pick - and - place operation is used to position each of the connectors 142a - 142b on the substrate 120. The connectors 142a - 142b are brought into contact with the surface 126 of the substrate 120 and are mechanically and electrically connected to the conductive layer 122, for example, with a conductive adhesive similar to 146 or bumps similar to 114.

[0030] Figure 2f Shows electrical components 140a - 140d and connectors 142a - 142b mechanically and electrically connected to the conductive layer 122 of the interconnect substrate 120, which will be referred to hereinafter as assembly 150. Figure 2g Is a top view of the assembly 150, where the electrical components 140a - 140d are disposed in die and component mounting locations 135a - 135d, and the connectors 142a - 142b are disposed in connector mounting locations 137a - 137d. The assembly 150 also includes saw streets 139a - 139f, where a protective layer 134 is disposed in the saw streets.

[0031] In Figure 2h , the assembly 150 is disposed on a slot die 152, including a lower slot die housing 154 and an assembly pocket 156. As Figure 2i shown, the assembly 150 is placed in the assembly pocket 156 of the lower slot die housing 154.

[0032] In Figure 2j , an upper slot die housing 158 of the slot die 152 is disposed on the assembly 150 and the assembly pocket 156. The upper slot die housing 158 includes cavities or pockets 160 intended to cover the electrical components 140a - 140d and cavities or pockets 162 intended to cover the connectors 142a - 142b. The pockets 160 and 162 define side walls 166 of the upper slot die housing 158. Figure 2k Shows a bottom view of the pockets 160 and 162 and the side walls 166 of the upper slot die housing 158. As Figure 2l shown, the upper slot die housing 158 is disposed on the lower slot die housing 154, where the electrical components 140a - 140d are contained within the pocket 160, and the connectors 142a - 142b are contained within the pocket 162.

[0033] The purpose of the slot mold 152 is to deposit a sealant around the electrical components 140a - 140d using a process called finger molding. However, no sealant should reach the connectors 142a - 142b because that situation could contaminate the connectors and cause defects in the assembly 150. Therefore, when force F is applied, the upper slot mold housing 158 makes a tight seal against the lower slot mold housing 154. The high - pressure contact between the upper slot mold housing 158 and the lower slot mold housing 154 is to prevent the sealant from creeping under and around the sidewalls 166 into the connector mounting locations 137a - 137d and contaminating the connectors 142a - 142b. However, the high - pressure contact between the upper slot mold housing 158 and the lower slot mold housing 154 contacts the assembly 150 at least partially at the contact points or regions 168a, 168b, and 168c. Specifically, the sidewalls 166 of the upper slot mold housing 158 surrounding the cavities 160 and 162 apply a significant pressure against the insulating layer 130 and the interconnect substrate 120 at least at the contact points or regions 168a - 168c. The pressure can rupture the insulating layer 130, and the rupture can spread to other areas of the substrate 120.

[0034] To avoid damaging the interconnect substrate 120 (i.e., to avoid rupturing the insulating layer 130 or any other part of the substrate), a protective layer 134 has been formed in the saw tracks 139a - 139f. Figure 3a Additional details of a portion of the assembly 150 are shown, where the electrical component 140b is disposed in the die or component mounting location 135a and the connector 142a is disposed in the connector mounting location 137a of the interconnect substrate 120. The protective layer 134 is formed in the insulating layer 130 along, for example, the saw tracks 139a and 139b. Specifically, the protective layer 134 is formed at the positions and / or intersections along the clamping lines 182 in the saw tracks 139a - 139f, where the sidewalls 166 will contact the insulating layer 130 of the substrate 120.

[0035] Figure 3bis a top view of the protective layer 134 formed in the insulating layer 130 along the saw tracks 139a - 139c. The clamping line 182 is the contact area between the sidewall 166 of the upper channel mold housing 158 and the insulating layer 130 on the interconnect substrate 120. The protective layer 134 in the saw tracks 139a - 139f operates as a support structure that can withstand the pressure from the sidewall 166 at the contact points 168a - 168c under the force F without damaging the insulating layer 130 or any other part of the interconnect substrate 120. Although the sidewall 166 of the upper channel mold housing 158 does contact the insulating layer 130 for a tight seal and to prevent the sealant 170 from creeping under or around the sidewall 166 of the upper channel mold housing and onto the connector 142a, the protective layer 134 limits the pressure on the insulating layer to avoid damage to the insulating layer 130 and / or the interconnect substrate 120.

[0036] Figure 3c is similar to Figure 3b Another embodiment, where the protective layer 134 occupies less than the width of the saw tracks 139a - 139c. Again, the protective layer 134 limits the pressure on the insulating layer 130 to avoid damage to the insulating layer 130 and / or the interconnect substrate 120.

[0037] Figure 3d is similar to Figure 3b Another embodiment, where the protective layer 134 occupies the length of the clamping line 182. Again, the protective layer 134 limits the pressure on the insulating layer 130 to avoid damage to the insulating layer 130 and / or the interconnect substrate 120.

[0038] Returning to Figure 2m , the sealant or molding compound 170 is injected into the recess 160 and deposited above and around the electrical components 140a - 140d and the substrate 120 up to the saw tracks 139a - 139f, which is called finger molding. The sealant 170 can be a polymer composite, such as an epoxy resin with fillers, an epoxy acrylate with fillers, or a polymer with appropriate fillers. The sealant 170 is non - conductive, provides structural support, and environmentally protects the semiconductor device from external factors and contaminants.

[0039] Figure 4a Shows additional details of a portion of the assembly 150, where the electrical component 140b is disposed in the die or component mounting location 135a, and the connector 142a is disposed in the connector mounting location 137a of the interconnect substrate 120, and the sealant 170 is disposed around to finger - mold the electrical components. The protective layer 134 is formed in the insulating layer 130 along, for example, the saw track 139b. Figure 4bis a top view of the protective layer 134 formed in the insulating layer 130 along the saw tracks 139a - 139c. The clamping line 182 is the area of contact between the side wall 166 of the upper channel mold housing 158 and the insulating layer 130 on the interconnect substrate 120. The protective layer 134 in the saw tracks 139a - 139f operates as a support structure that can withstand the pressure from the side wall 166 at the contact points 168a - 168c under the force F without any damage to any other part of the insulating layer 130 or the interconnect substrate 120. Although the side wall 166 of the upper channel mold housing 158 does contact the insulating layer 130 for a tight seal and to prevent the sealant from creeping under or around the side wall 166 of the upper channel mold housing 158 and onto the connector 142a, the protective layer 134 limits the pressure on the insulating layer to avoid damage to the insulating layer 130 and / or the interconnect substrate 120.

[0040] Return to Figure 2n , the upper channel mold housing 158 is lifted away from the lower channel mold housing 154. Figure 5a Shows the assembly 150 after removal of the channel mold 152, where the sealant 170 is deposited around or finger - molded onto the electrical components 140a - 140d. Figure 5b Shows a top view of the assembly 150, where the sealant 170 is deposited around or finger - molded onto the electrical components 140a - 140d. The sealant extends up to the saw tracks 139a - 139f, but due to the tight side wall 166 and the protective layer 134 in the area 133 of the protective substrate 120, the sealant does not reach the connectors 142a - 142b. There is no sealant on the connectors 142a - 142b. Due to the protective layer 134 limiting the pressure on the insulating layer 130 and / or the substrate 120, the substrate 120 remains undamaged by the channel mold 152.

[0041] The electrical components 140a - 140d may include IPDs that are vulnerable to or generate EMI, RFI, harmonic distortion, and inter - device interference. For example, the IPDs included within the electrical components 140a - 140d provide the electrical characteristics required for high - frequency applications, such as resonators, high - pass filters, low - pass filters, band - pass filters, symmetric Hi - Q resonant transformers, and tuning capacitors. In another embodiment, the electrical components 140a - 140d include digital circuits that switch at high frequencies, which may interfere with the operation of the IPDs in the assembly.

[0042] To address EMI, RFI, harmonic distortion, and inter - device interference, an electromagnetic shielding material 176 is applied over the sealant 170, as Figure 5cAs shown. The electromagnetic shielding material 176 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, the electromagnetic shielding material 176 can be carbonyl iron, stainless steel, nickel silver, low carbon steel, silicon iron steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference.

[0043] In Figure 6a , a saw blade or laser cutting tool 178 is used to singulate the assembly 150 into individual semiconductor packages through saw tracks 139a - 139f, or, in the case where the conductive layer 124 operates as an antenna, into individual AiP 180a - 180d. Figure 6b A top view of singulation along lines 184a and 184b is shown. Singulation through saw tracks 139a - 139f leaves the shielding material 176 on the sealant 170 at the edges of the AiP 180a - 180d. The protective layer 134 is typically (although not necessarily) removed during singulation.

[0044] Figure 7a An illustration of the singulated AiP 180a is shown. Figure 7b is a perspective view of the singulated AiP 180a. The shielding material 176 on the sealant 170 extends to the edges of the AiP 180a. The AiP 180b will have a similar view. After singulation, the shielding material 176 can be formed on the sealant 170. The AiP 180a is suitable for mobile electrical devices such as 5G phones, as well as other portable multimedia devices.

[0045] Figure 8 An illustration of an electrical device 400 having a chip carrier substrate or PCB 402 is shown, where multiple semiconductor packages are disposed on the surface of the PCB 402, including the AiP 180a - 180d. Depending on the application, the electrical device 400 can have one type of semiconductor package or multiple types of semiconductor packages.

[0046] The electrical device 400 can be an independent system that uses semiconductor packages to perform one or more electrical functions. Alternatively, the electrical device 400 can be a sub-component of a larger system. For example, the electrical device 400 can be part of a tablet computer, cellular phone, digital camera, communication system, or other electrical device. Alternatively, the electrical device 400 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include a microprocessor, memory, ASIC, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for a product to be accepted in the market. The distance between semiconductor devices can be reduced to achieve higher density.

[0047] In Figure 8 , the PCB 402 provides a common substrate for providing structural support and electrical interconnection for semiconductor packages disposed on the PCB. Conductive signal traces 404 are formed on or within the surface of the PCB 402 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition processes. The signal traces 404 provide electrical communication between each semiconductor package, mounted component, and other external system components. The traces 404 also provide power and ground connections to each semiconductor package.

[0048] In some embodiments, the semiconductor device has two package levels. The first-level package is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second-level package involves mechanically and electrically attaching the intermediate substrate to the PCB. In other embodiments, the semiconductor device may have a first-level package in which the die is mechanically and electrically disposed directly on the PCB. For illustrative purposes, several types of first-level packages are shown on the PCB 402, including a wirebond package 406 and a flip chip 408. Additionally, several types of second-level packages including a ball grid array (BGA) 410, a bump chip carrier (BCC) 412, a land grid array (LGA) 416, a multi-chip module (MCM) or SIP module 418, a quad flat no-lead package (QFN) 420, a quad flat package 422, an embedded wafer-level ball grid array (eWLB) 424, and a wafer-level chip-scale package (WLCSP) 426 are shown disposed on the PCB 402. In one embodiment, the eWLB 424 is a fan-out wafer-level package (Fo-WLP), and the WLCSP 426 is a fan-in wafer-level package (Fi-WLP). Depending on system requirements, any combination of semiconductor packages configured with first and second-level package styles and any combination of other electrical components can be connected to the PCB 402. In some embodiments, the electrical device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electrical devices and systems. Because semiconductor packages include complex functions, electrical devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less likely to fail and are less expensive to manufacture, resulting in lower costs for consumers.

[0049] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations can be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A semiconductor device, comprising: substrate; A protective layer formed on the saw streets of the substrate; an electrical component disposed on a surface of the substrate; and An encapsulant is deposited on the electrical component, wherein the protective layer protects the substrate during encapsulation. 2 . The semiconductor device according to claim 1 , further comprising a connector provided on a surface of the substrate.

3. The semiconductor device according to claim 1, wherein The protective layer extends over the width of the saw street. The semiconductor device according to claim 1 , wherein the protection layer extends smaller than or larger than a width of the saw street. 5 . The semiconductor device according to claim 1 , further comprising a shielding layer formed on the sealant.

6. A semiconductor device comprising: substrate; forming a protective layer on a surface of a substrate; an electrical component disposed on a surface of the substrate; and An encapsulant is deposited on the electrical component, wherein the protective layer protects the substrate during encapsulation. 7 . The semiconductor device according to claim 6 , further comprising a connector provided on a surface of the substrate.

8. The semiconductor device according to claim 6, wherein: The protection layer is formed on the saw streets of the substrate. 9 . The semiconductor device according to claim 8 , wherein the protection layer extends smaller than or larger than a width of the saw street.

10. The semiconductor device according to claim 6, further comprising a shielding layer formed on the sealant.

11. A method for manufacturing a semiconductor device, comprising: providing a substrate; forming a protective layer on the saw streets of the substrate; disposing an electrical component on a surface of the substrate; and An encapsulant is deposited over the electrical component, wherein the protective layer protects the substrate during encapsulation.

12. The method of claim 11, further comprising providing a connector on a surface of the substrate.

13. The method of claim 11, wherein the protective layer extends across a width of the saw street. The method of claim 11 , wherein the protective layer extends less than or greater than a width of the saw street.

15. The method of claim 11, further comprising forming a shielding layer on the sealant.

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