Mixing depth cavity for embedded bridge structures

Abstract

The invention relates to a mixed depth cavity for an embedded bridge structure. Embodiments disclosed herein include an apparatus. In an embodiment, the apparatus includes a substrate and a first cavity in the substrate. In an embodiment, the first cavity has a first depth. In an embodiment, a second cavity is provided in the substrate, where the second cavity has a second depth different from the first depth. In an embodiment, a first die is located in a first cavity, where the first die has a first thickness. In an embodiment, a second die is located in the second cavity, where the second die has a second thickness different from the first thickness.

Description

Background Art

[0001] Computing architectures continue to scale to smaller form factors while advancing towards higher bandwidths and computing capabilities. One solution to achieve this design goal is to use a chiplet architecture. Instead of a single large chip, multiple smaller chiplets are stitched together via a bridge. When the bridge is embedded in the underlying package substrate, the bridge can be referred to as an embedded bridge solution. Existing bridge solutions typically do not allow power to pass through the thickness of the bridge. Instead, traces are routed over the bridge to provide power within the footprint of the bridge. This complicates the wiring and increases the length of the power delivery path, which can affect performance.

[0002] In some instances, bridges with vias are used to provide wiring through the thickness of the bridge rather than around the bridge. However, this can lead to the use of multiple different types of bridge structures within the package substrate. For example, a first bridge may include vias, and a second bridge may not include vias. This difference can result in a difference in the thickness of the bridge. Thus, integrating the bridges into the package substrate becomes complicated. For example, cavities with different depths may be required to accommodate different types of bridges. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1A is a cross-sectional view of a package substrate with an embedded bridge according to an embodiment, the embedded bridge including power wiring that wraps around the bridge.

[0004] Figure 1B is a cross-sectional view of a package substrate with an embedded bridge according to an embodiment, the embedded bridge including power wiring through the thickness of the bridge.

[0005] Figure 2A is a cross-sectional view of a package substrate according to an embodiment, the package substrate having a first bridge with a first thickness and a second bridge with a second thickness.

[0006] Figure 2B is a cross-sectional view of a package substrate according to an embodiment, the package substrate having a first bridge in a cavity through a buildup layer and a second bridge in a cavity that does not fully penetrate the buildup layer.

[0007] Figure 3A is a cross-sectional view of a package substrate according to an embodiment, the package substrate having a cavity for a bridge, wherein the cavity has vertical sidewalls.

[0008] Figure 3B is a cross-sectional view of a package substrate according to an embodiment, the package substrate having a cavity for a bridge, wherein the cavity has sloped sidewalls.

[0009] Figure 3CA cross-sectional view of an encapsulated substrate according to an embodiment, the encapsulated substrate having a cavity for a bridge, wherein the cavity has a serrated profile sidewall.

[0010] Figure 3D A cross-sectional view of an encapsulated substrate according to an embodiment, the encapsulated substrate having a cavity for a bridge, wherein the cavity has a sidewall with an offset vertical portion.

[0011] Figures 4A - 4K A cross-sectional view depicting a process for forming an encapsulated substrate having a cavity according to an embodiment, the cavity having a non-uniform depth for accommodating different types of bridge structures.

[0012] Figure 5 A cross-sectional view of an encapsulated substrate according to an embodiment, the encapsulated substrate having a first bridge in a first cavity and a second bridge in a second cavity, the second cavity being formed at an edge of the encapsulated substrate.

[0013] Figure 6 A cross-sectional view of an electronic system having an encapsulated substrate according to an embodiment, the encapsulated substrate including different bridge architectures and cavities having different depths.

[0014] Figure 7 A schematic diagram of a computing device constructed according to an embodiment. Detailed Description

[0015] Electronic systems according to various embodiments are described herein, and more particularly, architectures having encapsulated substrates that include cavities of different depths to accommodate different types of bridge die. In the following description, various aspects of illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to other artisans in the field. However, it will be apparent to those skilled in the art that the present disclosure may be practiced using only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of illustrative implementations. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

[0016] The various operations will be described sequentially as a number of discrete operations in a manner most helpful in understanding the present disclosure, however, the order of description should not be construed as implying that these operations are necessarily order dependent. In particular, these operations need not be performed in the order presented.

[0017] Various embodiments or aspects of the present disclosure are described herein. In some implementations, different embodiments are implemented separately. However, the embodiments are not limited to the embodiments being implemented in isolation. For example, two or more different embodiments can be combined together so as to be implemented as a single device, process, structure, etc. In some instances, all of the various embodiments can be combined together. In other instances, a portion of the first embodiment can be combined with a portion of one or more different embodiments. For example, a portion of the first embodiment can be combined with a portion of the second embodiment, or a portion of the first embodiment can be combined with a portion of the second embodiment and a portion of the third embodiment.

[0018] As described above, electronic packaging architectures are moving toward including various embedded bridge architectures. The bridge is a building block that allows for the communication coupling of various core particles. Depending on the needs of the system, two or more different types of bridges may be used within a single package substrate. For example, a standard bridge structure may be used. The standard bridge structure may include high-density wiring to link the core particles together. In addition to the high-density wiring, a second type of bridge structure may include vias that pass through the thickness of the bridge. When the bridge is a silicon substrate or die, the via may be referred to as a through-silicon via (TSV). Different types of bridge structures may require different types of integration processes. Therefore, the ability to integrate various bridge architectures is necessary in order to manufacture advanced electronic packaging architectures.

[0019] An example of a typical embedded bridge structure is shown in Figure 1A In. Figure 1A , a cross-sectional view of a package substrate 110 is shown according to an embodiment. In an embodiment, the package substrate 110 includes a core 112. The core 112 may be any suitable core material. For example, the core 112 may include an organic core with glass fiber reinforcement, or the core 112 may include a substantially solid glass layer. Although shown as a monolithic structure, the core 112 typically includes conductive vias passing through the thickness of the core 112. In an embodiment, a buildup layer 114 may be provided over the core 112. The buildup layer 114 may also be provided over the bottom of the core 112. Since the bridge 120 is located in the top portion of the package substrate 110, the bottom portion of the package substrate 110 is shown from the top for clarity. Figure 1A Omitted. The buildup layer 114 may include an organic dielectric material. For example, multiple dielectric layers may be laminated on top of each other to form a larger structure of the buildup layer 114. In an embodiment, the buildup layer 114 may include conductive wiring, such as vias 113, pads 115, traces 117, etc. The conductive wiring may include copper, copper alloys, or other metal materials.

[0020] In an embodiment, the bridge 120 is embedded within the build-up layer 114. In some embodiments, the bridge 120 may also be referred to as a "die" or a "bridge die". The bridge 120 can be a dimensionally stable material. For example, the bridge 120 may include silicon, other semiconductor materials, ceramics, glass, etc. In an embodiment, conductive wiring (e.g., traces, pads, etc.) may be provided on the bridge 120. For example, the pad 123 is shown in Figure 1A . In some instances, the wiring may be provided in a back-end-of-line (BEOL) layer (not shown) on top of a dimensionally stable base material (e.g., silicon). The BEOL layer may include dielectric materials such as silicon oxide, silicon nitride, organic dielectrics, etc. The dimensional stability of the bridge 120 allows for fine line and space (L / S) dimensions in order to provide electrical coupling between overlying dies ( Figure 1A not shown). In an embodiment, the bridge 120 may be provided on top of the etch stop layer 121. The etch stop layer 121 may include copper, etc. The bridge 120 may be fixed to the etch stop layer 121 via an adhesive 122, etc.

[0021] In the illustrated embodiment, there are no vias through the thickness of the bridge 120. Thus, power cannot be routed through the bridge 120. Instead, power is provided in a path that passes adjacent to the sidewalls of the bridge 120. Once above the level of the top surface of the bridge 120, the trace 117 can route power into the coverage area of the bridge 120. This increases the length of the power delivery path and reduces performance. Additionally, the lateral wiring makes the wiring within the package substrate 110 more complex.

[0022] Thus, embodiments disclosed herein may use a bridge 120 that includes a via 124. An example of such an embodiment is shown in Figure 1B . As shown in the figure, the via 124 passes through at least a portion of the thickness of the bridge 120. Through the via 124, the pad 125 at the bottom of the bridge 120 is coupled to the pad 123 at the top of the bridge 120. In an embodiment, the bottom pad 125 is coupled to the pad 115 in the build-up layer 114 via solder 126, etc. For necessary electrical connections, the thickness variation of the build-up layer 114 needs to be low.

[0023] When the glass core 112 is used, the thickness variation is typically improved. The improvement is maximized when the bridge 120 is moved closer to the surface of the glass core 112. That is, it is beneficial to reduce the thickness of the build-up layer 114 between the bridge 120 and the core 112. However, when the bridge 120 is moved closer to the core 112, the likelihood of damaging the core 112 increases. The core 112 is fragile and prone to cracking or other damage. Therefore, some amount of buffer layer is currently necessary between the core 112 and the bottom of the bridge 120.

[0024] As can be understood, compared with Figure 1Bcompared to the bridge 120 in Figure 1A the bridge 120 in

[0025] can be of different thicknesses. As such, the corresponding cavities in the build-up layer 114 need to be formed to different depths to accommodate the different heights of the bridge 120. In the assembly of the build-up layer, this may require different processing procedures. In some instances, using a laser drilling process, the cavities can be formed, the laser drilling process including forming etch stop layers at different depths. In other instances, photoimageable dielectrics (PIDs) can be used to form the cavities using photolithography.

[0026] Now referring to Figure 2A , a cross-sectional view of a packaged substrate 210 is shown according to an embodiment. In the embodiment, the packaged substrate 210 includes a core 212 and a build-up layer 214 over the core 212. In the illustrated embodiment, the build-up layer 214 is only shown above the core 212. However, it should be understood that a build-up layer 214 (with associated electrical wiring) can also be provided below the core 212.

[0027] A via 205 through the thickness of the core 212 can be provided. The via 205 can be a conductive material, such as copper or an alloy of copper. In an embodiment, the via 205 can have any suitable cross-sectional shape. For example, in Figure 2A the via 205 has slanted sidewalls such that the top of the via 205 is wider than the bottom of the via 205. In other embodiments, the via 205 can have substantially vertical sidewalls. Other embodiments can include a via 205 having an hourglass-shaped cross-section.

[0028] In an embodiment, the core 212 can be a glass layer or an organic dielectric material. In the case of an organic dielectric material, reinforcing fibers can be provided within the core 212. For example, glass fibers, etc. can be embedded in the core 212. In the case of a glass layer, the core 212 can be substantially all glass. The core 212 can be a solid material, the solid material including a glass material having an amorphous crystal structure, where the solid glass core can also include various structures filled with one or more other materials (e.g., metals, metal alloys, dielectric materials, etc.), such as vias, cavities, channels, or other features. As such, the core 212 can be distinguished from, for example, a "prepreg" or "RF4" core of a printed circuit board (PCB) substrate, which typically includes glass fibers embedded in a resin organic material (such as epoxy resin).

[0029] The core 212 can have any suitable size. In a particular embodiment, the core 212 can have a thickness of approximately 50 μm or greater. For example, the thickness of the core 212 can be between approximately 50 μm and approximately 1.4 mm. However, smaller or larger thicknesses can also be used. The core 212 can have an edge size (e.g., length, width, etc.) of approximately 10 mm or greater. For example, the edge size can be between approximately 10 mm and approximately 250 mm. However, larger or smaller edge sizes can also be used. More generally, the area size of the core 212 (from a top-down plan view) can be between approximately 10 mm x 10 mm and approximately 250 mm x 250 mm. In an embodiment, the core 212 can have a first side that is perpendicular or orthogonal to a second side. In a more general embodiment, the core 212 can include a rectangular prism volume having sections (e.g., vias) that are removed and filled with other materials (e.g., metal, etc.).

[0030] The core 212 can include a single monolithic glass layer. In other embodiments, the core 212 can include two or more discrete glass layers stacked on top of each other. The discrete glass layers can be provided in direct contact with each other, or the discrete glass layers can be mechanically coupled to each other by an adhesive or the like. The discrete glass layers in the core 212 can each have a thickness of less than approximately 50 μm. For example, the discrete glass layers in the core 212 can have a thickness between approximately 25 μm and approximately 50 μm. However, in some embodiments, the discrete glass layers can have a larger or smaller thickness. As used herein, "approximately" can refer to a range of values within ten percent of the stated value. For example, approximately 50 μm can refer to a range between 45 μm and 55 μm.

[0031] The core 212 can be any suitable glass formulation that has the necessary mechanical robustness and compatibility with semiconductor package manufacturing and assembly processes. For example, the core 212 can include aluminosilicate glass, borosilicate glass, alumino-borosilicate glass, silica, fused silica, etc. In some embodiments, the core 212 can include one or more additives such as, but not limited to, Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, or Zn. More generally, the core 212 can include silicon and oxygen, and any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, or zinc. In an embodiment, the core 212 can include at least 23% silicon (by weight) and at least 26% oxygen (by weight). In some embodiments, the core 212 can also include at least 5% aluminum (by weight).

[0032] In an embodiment, the build-up layer 214 may include an organic dielectric material, such as a build-up film. For example, two or more build-up film layers may be laminated on top of each other to form a larger structure of the build-up layer 214. The build-up layer 214 may include electrical wirings (not shown), such as vias, pads, traces, etc. Using a standard packaging process, the electrical wirings may be processed along with the formation of the build-up layer 214.

[0033] In an embodiment, a plurality of bridge die 220 may be inserted or embedded within the build-up layer 214. As used herein, the bridge die 220 may also be referred to as a bridge, die, or substrate. The bridge die 220 may include materials suitable for providing high-density or fine line / space (L / S) wiring. Such high-density wiring is used to communicatively couple the overlying die 245 together. For example, the bridge die 220 may include silicon or another semiconductor material. According to certain embodiments, glass, ceramic, etc. may also be used. In some instances, the bridge die 220 may include a substrate layer having an overlying dielectric wiring layer (not shown), which may include dielectric layers (e.g., silicon dioxide, silicon nitride, etc.). In some instances, such an overlying dielectric wiring layer may be referred to as a BEOL layer.

[0034] In the illustrated embodiment, the package substrate 210 includes a pair of bridge die 220A and 220B. The two bridge die 220A and 220B may be different from each other. For example, the first bridge die 220A may include a via 224. The via 224 may be a TSV that at least partially penetrates the thickness of the bridge die 220A. The via 224 may electrically couple a pad 225 at the bottom of the bridge die 220A to a pad 223 at the top of the bridge die 220A. This allows power, signals, etc. to be routed through the thickness of the bridge die 220A without the need to route power around the bridge die 220A. Thus, the bridge die 220A may be electrically coupled to the pad 215 on the build-up layer 214 via an interconnect 226 (e.g., solder, etc.). In other instances, the bridge die 220A may be hybrid bonded to the pad 215. The second bridge die 220B may include a standard bridge structure without a via. Thus, at the bottom of the bridge die 220B, an electrical connection may not be required. This allows the bottom of the cavity 230B to terminate at the etch stop layer 207. For example, the etch stop layer 207 may be a metal layer, such as a copper layer.

[0035] In an embodiment, the differences between bridge die 220A and 220B can result in the need for different cavity 230 architectures. For example, cavity 230A is deeper than cavity 230B. That is, the distance between the bottom surface of cavity 230A and core 212 can be less than the distance between the bottom surface of cavity 230B and core 212. The difference in cavity 230 depth can be achieved through any number of package assembly processes, as will be described in more detail below. In an embodiment, the difference in depth can be at least approximately 5 μm, at least 10 μm, at least 20 μm, or at least 50 μm from each other. However, in some instances, smaller differences can also be used.

[0036] In an embodiment, bridges 220A and 220B can communicatively couple overlying die 245 together. For example, three die 245A, 245B, and 245C are shown in Figure 2A FIG. Through first bridge die 220A, first die 245A and second die 245B are communicatively coupled together, and through second bridge die 220B, second die 245B and third die 245C are communicatively coupled together. Die 245 can have pads 246 that are coupled to pads 223 through interconnects 247, such as any first-level interconnect (FLI) architecture (e.g., solder, copper bumps, hybrid bonding, etc.). Die 245 can be any type of die, such as a central processing unit (CPU), a graphics processing unit (GPU), an XPU, a communication die, a memory die, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc.

[0037] In Figure 2A the embodiment shown, bridge die 220A and 220B are placed in cavities 230A and 230B without any underfill or embedding material. However, in some instances, underfill or molding material can be provided around interconnects 226 and / or fill (or at least partially fill) the remainder of cavities 230A and 230B.

[0038] Now referring to Figure 2B FIG. , a cross-sectional view of package substrate 210 is shown in accordance with an additional embodiment. As shown in the figure, Figure 2B package substrate 210 in Figure 2AIn the encapsulation substrate 210, except for the structure of the first cavity 230A. Instead of having a bottom surface provided within the thickness of the stacked layer 214, the first cavity 230A completely penetrates the thickness of the stacked layer 214. That is, the first cavity 230A has a bottom surface that exposes the top surface of the core 212. In some instances, the bottom pad 225 of the first bridge die 220A can be coupled to the via 205 through the interconnect 226 and pad 215 that are not embedded in the stacked layer 214.

[0039] Now referring to Figures 3A - 3D , according to various embodiments, several cross-sectional views depicting an example of the bridge die 320 in the cavity 330 are shown. In the illustrated embodiment, a single cavity 330 and bridge die 320 are shown. However, it should be understood that a given encapsulation substrate 310 can include two or more pairs of cavities 330 and bridge dies 320. In such instances, each pair can have a different structure. For example, the depths of different cavities can be different from each other. However, the sidewall structures of different cavities can be similar to each other. That is, using the same manufacturing process, different cavities can be formed. In other embodiments, different cavities can have different sidewall structures. In these instances, using different manufacturing processes, different cavities can be formed.

[0040] Now referring to Figure 3A , according to an embodiment, a cross-sectional view of a portion of the encapsulation substrate 310 is shown. The encapsulation substrate 310 can include a core 312 and a stacked layer 314 over the core 312. Although not shown, a stacked layer 314 can also be provided below the core 312. The core 312 can also include vias (not shown). The core 312 and the stacked layer 314 can be similar to any of the core structures or stacked layer structures described in more detail below.

[0041] In an embodiment, the cavity 330 can be formed in the top surface of the stacked layer 314. The cavity 330 can have sidewalls 331. In an embodiment, the sidewalls 331 can have a substantially vertical profile. As used herein, "substantially vertical" can refer to a surface within approximately 10 degrees orthogonal to the top surface of the stacked layer 314. Such a sidewall 331 profile can be formed by using an etching process, a drilling process, or any other suitable manufacturing process.

[0042] In an embodiment, the bridge die 320 can be inserted into the cavity 330. The bridge die 320 can include a via 324 that connects the pad 325 to the pad 323. However, other embodiments can include a bridge die 320 without the via 324 or the bottom pad 325. In Figure 3A the case shown, the pad 325 can be coupled to the pad 315 through an interconnect 326 (e.g., solder, etc.). Although not shown, underfill or molding material can at least partially fill the remainder of the cavity 330.

[0043] Now referring to Figure 3B , according to another embodiment, a cross-sectional view of a portion of the encapsulation substrate 310 is shown. In the embodiment, the encapsulation substrate 310 may be substantially similar to Figure 3A the encapsulation substrate 310 in

[0044] Now referring to Figure 3C , according to another embodiment, a cross-sectional view of a portion of the encapsulation substrate 310 is shown. As shown in the figure, the encapsulation substrate 310 may be substantially similar to Figure 3A the encapsulation substrate 310 in

[0045] Now referring to Figure 3D , according to another embodiment, a cross-sectional view of a portion of the encapsulation substrate 310 is shown. Figure 3D The encapsulation substrate 310 in Figure 3A may be substantially similar to the encapsulation substrate 310 in

[0046] Now referring to Figures 4A - 4K, according to an embodiment, a series of cross-sectional views depicting a process for forming a packaged substrate 410 having a non-uniform cavity 430 depth are shown. Although one process flow is shown, it should be understood that other methods and processes may also be used to form the cavity 430.

[0047] Now refer to Figure 4A , according to an embodiment, a cross-sectional view of a portion of the packaged substrate 410 in a manufacturing stage is shown. In an embodiment, the packaged substrate 410 may include a core 412 and a build-up layer 414 over the core 412. Although not shown, a build-up layer 414 may also be provided under the core 412. The core 412 may be similar to any of the core structures described in more detail herein. The build-up layer 414 may also be similar to any of the build-up layers described in more detail herein. In an embodiment, vias 405 through the thickness of the core 412 may be provided. Electrical wiring may be provided in the build-up layer 414. For example, in some embodiments, pads 415 and vias 413 may be provided in the build-up layer 414.

[0048] Now refer to Figure 4B , according to an embodiment, cross-sectional views of the packaged substrate 410 at different manufacturing stages are shown. The packaged substrate 410 may have a surface finish 451 plated on some of the pads 415 in the pads 415. In particular, the pads 415 that will be provided in the deepest cavity may be covered by the surface finish 451. The surface finish 451 may include any suitable surface finish material, such as gold, silver, platinum, etc. The surface finish 451 may be used for antioxidant, diffusion barrier layer, etc.

[0049] Now refer to Figure 4C , according to an embodiment, a cross-sectional view of the packaged substrate 410 in a subsequent manufacturing stage is shown. As shown in the figure, a layer 461 is applied over the top surface of the build-up layer 414. The layer 461 may be a photoimageable dielectric (PID), etc. Using any suitable process, such as lamination, spin coating, etc., the layer 461 may be deposited. The layer 461 may cover the exposed top pads 415 and any associated surface finish 451.

[0050] Now refer to Figure 4D , according to another embodiment, a cross-sectional view of the packaged substrate 410 in a manufacturing stage is shown. As shown in the figure, the layer 461 is patterned to form an exposed area 462. For example, a photolithography process, etc. may be used to create a latent image in the layer 461. The exposed area 462 may be crosslinked or otherwise resistant to the etching process that will be used in subsequent patterning operations. In an embodiment, the layer 461 remains around the pads 415 covered by the surface finish 451. This area will ultimately become part of the cavity.

[0051] Now refer to Figure 4E, according to an embodiment, a cross-sectional view of the package substrate 410 in the advanced manufacturing stage is shown. As shown in the figure, electrical wiring is provided through the exposed area 462 and above the exposed area 462. For example, vias 413 through the thickness of the exposed area 462 can be provided, and above the exposed area 462, pads 415 can be provided. Using conventional patterning and plating processes used in package substrate manufacturing, the electrical wiring can be formed.

[0052] Now refer to Figure 4F , according to an embodiment, a cross-sectional view of the package substrate 410 in different manufacturing stages is shown. As shown in the figure, a surface plating 451 can be provided above one or more of the pads 415 in the pad 415 at the top of the exposed area 462. These pads 415 can be the pads to be provided at the bottom of the second cavity in the package substrate 410. As can be understood, compared with the pads 415 covered by the surface plating 451 in Figure 4B , the pads 415 covered by the surface plating 451 in this operation are at different levels of the package substrate 410. Thus, the depth of the subsequently formed cavity will be different.

[0053] Now refer to Figure 4G , according to an embodiment, a cross-sectional view of the package substrate 410 in another manufacturing stage is shown. As shown in the figure, an additional layer 461 is applied above the first exposed area 462. The additional layer 461 can also be a PID, and the PID is patterned to have an exposed area 462 and a layer 461. In an embodiment, repeated exposure of each layer can cause unexposed segments of the layer 461 to stack on top of each other to form a latent image of the cavity region. In the illustrated embodiment, the latent images of the cavity regions are perfectly aligned. However, in other instances, some misalignment can exist along the edges of the latent image.

[0054] Now refer to Figure 4H , according to an embodiment, a cross-sectional view of the package substrate 410 after a plurality of layers 461 and exposed areas 462 are stacked on top of each other is shown. Additionally, electrical wiring (e.g., vias 413, pads 415, etc.) through the exposed area 462 can be provided. Above the topmost pad 415, solder 447 can be provided. As shown in the figure, the latent image of the layer 461 on the left is three layers deep, and the latent image of the layer 461 on the right is two layers deep. Thus, the subsequently formed cavity will have different depths.

[0055] Now refer to Figure 4I, according to an embodiment, a cross-sectional view of the package substrate 410 after the cavity 430 is formed is shown. As shown in the figure, the first cavity 430A is deeper than the second cavity 430B. By using an etching process, the cavities 430A and 430B can be formed. The etching process can selectively remove the layer 461, leaving the exposed area 462. However, in some instances, other subtractive processes can be used.

[0056] Now refer to Figure 4J , according to an embodiment, a cross-sectional view of the package substrate 410 in a further manufacturing stage is shown. In an embodiment, the bridge die 420A can be inserted into the first cavity 430A, and the bridge die 420B can be inserted into the second cavity 430B. In some embodiments, the bridge die 420A and / or 420B can include vias (not shown) to route power and / or signals through the thickness of the bridge die 420A and / or 420B. The bridge dies 420A and 420B can be coupled to the build-up layer 414 by interconnects, such as solder. In some cases where the bridge die 420 does not have electrical wiring through its thickness, the bottom of the bridge 420 can be coupled to a metal etch stop layer or the like.

[0057] Now refer to Figure 4K , according to an embodiment, a cross-sectional view of the package substrate 410 after the die 445 is attached is shown. As shown in the figure, three dies 445A, 445B, and 445C are attached to the package substrate 410 by interconnects 447. The bridge die 420A can communicatively couple the die 445A to the die 445B, and the bridge die 420B can communicatively couple the die 445B to the die 445C. The die 445 can be any type of die, such as the die described in more detail herein.

[0058] Now refer to Figure 5 , according to an embodiment, a cross-sectional view of the package substrate 510 is shown. As shown in the figure, the package substrate 510 includes a core 512 and a build-up layer 514. The core 512 and the build-up layer 514 can be similar to any core or build-up layer structure described in more detail herein. In an embodiment, an exposed area 562 can be provided on the build-up layer 514. The exposed area 562 can include PID material or the like, similar to the embodiments described in more detail herein.

[0059] In an embodiment, a first cavity 530A through the entire thickness of the exposed region 562 is provided. Additionally, the first cavity 530A may be located at the edge of the package substrate 510. The first cavity 530A may have an open or exposed side. That is, in some embodiments, at least one sidewall of the first cavity 530A may be omitted. In an embodiment, a second cavity 530B through one or more layers of the exposed region 562 may be provided. For example, the depth of the second cavity 530B may be shallower compared to the depth of the first cavity 530A.

[0060] In an embodiment, a first bridge die 520A is inserted into the first cavity 530A, and a second bridge die 520B is inserted into the second cavity 530B. The first bridge die 520A may be an optical component. For example, a photoelectric transducer 575 (having one or more of a photodiode, a laser, a circuit, a lens, etc.) may be integrated in the first bridge die 520A. The transducer 575 allows an optical signal from a cable 577 (e.g., an optical fiber cable, etc.) to be converted into an electrical signal, and the electrical signal can be propagated to the first die 545A. Similarly, the transducer 575 may allow an electrical signal from the first die 545A to be converted into an optical signal and delivered to the cable 577. In an embodiment, the second bridge die 520B may communicatively couple the first die 545A to the second die 545B.

[0061] Now referring Figure 6 , a cross-sectional view of an electronic system 690 is shown according to an embodiment. In an embodiment, the electronic system 690 includes a board 691, such as a printed circuit board (PCB), a motherboard, etc. The board 691 may be coupled to the package substrate 610 through an interconnect 692. The interconnect 692 may be any suitable second-level interconnect (SLI) architecture, such as solder balls, sockets, pins, etc.

[0062] In an embodiment, the package substrate 610 may be similar to any of the package substrate architectures described in more detail herein. For example, the package substrate 610 may include a core 612 and build-up layers 614. In an embodiment, a first cavity 630A and a second cavity 630B may be provided in the build-up layers 614. The first cavity 630A may have a different depth from the second cavity 630B. A first bridge die 620A may be located in the first cavity 630A, and a second bridge die 620B may be located in the second cavity 630B. One or both of the first bridge die 620A or the second bridge die 620B may have vias 624 through at least a portion of the first bridge die 620A or the second bridge die 620B.

[0063] In an embodiment, one or more die 645 may be coupled to a package substrate 610 via an interconnect 694. The interconnect 694 may be any suitable first-level interconnect (FLI) architecture. For example, the interconnect 694 may include solder, copper bumps, hybrid bonding architectures, and the like. A first bridge die 620A may communicatively couple a first die 645A to a second die 645B, and a second bridge die 620B may communicatively couple the second die 645B to a third die 645C. The die 645 may be similar to any of the die described in more detail herein.

[0064] Figure 7 FIG. illustrates a computing device 700 in accordance with one implementation of the present disclosure. The computing device 700 houses a board 702. The board 702 may include a number of components including, but not limited to, a processor 704 and at least one communication chip 706. The processor 704 is physically and electrically coupled to the board 702. In some implementations, the at least one communication chip 706 is also physically and electrically coupled to the board 702. In additional implementations, the communication chip 706 is part of the processor 704.

[0065] These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, crypto-processors, chip sets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard disk drives, compact disks (CDs), digital versatile disks (DVDs), and the like).

[0066] The communication chip 706 can implement wireless communication for transferring data to and from the computing device 700. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that can transfer data through the use of modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated devices do not contain any wires, but in some embodiments, they may not contain any wires. The communication chip 706 can implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and higher. The computing device 700 can include multiple communication chips 706. For example, a first communication chip 706 can be dedicated to shorter-range wireless communication (such as Wi-Fi and Bluetooth), and a second communication chip 706 can be dedicated to longer-range wireless communication (such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others).

[0067] The processor 704 of the computing device 700 includes an integrated circuit die encapsulated within the processor 704. In some implementations of the present disclosure, in accordance with the embodiments described herein, the integrated circuit die of the processor can be part of an electronic package that includes a first cavity having a first depth and a second cavity having a second depth, the second depth being different from the first depth. The term "processor" can refer to any device or part of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0068] The communication chip 706 also includes an integrated circuit die encapsulated within the communication chip 706. In another implementation of the present disclosure, the integrated circuit die of the communication chip can be part of an electronic package that includes a first cavity having a first depth and a second cavity having a second depth, the second depth being different from the first depth.

[0069] In an embodiment, the computing device 700 can be part of any device. For example, the computing device can be part of a personal computer, server, mobile device, tablet computer, automobile, etc. That is, the computing device 700 is not limited to being used in any particular type of system, and the computing device 700 can be included in any device that can benefit from computing capabilities.

[0070] The above description of the illustrated implementations of the present disclosure (including what is described in the abstract) is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Although specific implementations and examples of the present disclosure have been described herein for illustrative purposes, as will be appreciated by those skilled in the art, various equivalent modifications are possible within the scope of the present disclosure.

[0071] In view of the foregoing detailed description, these modifications can be made to the present disclosure. The terms used in the following claims should not be construed as limiting the present disclosure to the specific implementations disclosed in the specification and claims. Instead, the scope of the present disclosure should be determined solely by the following claims, which should be interpreted in accordance with established principles of claim interpretation.

[0072] Example 1: A device, comprising: a substrate; a first cavity located in the substrate, wherein the first cavity has a first depth; a second cavity located in the substrate, wherein the second cavity has a second depth different from the first depth; a first die located in the first cavity, wherein the first die has a first thickness; and a second die located in the second cavity, wherein the second die has a second thickness different from the first thickness.

[0073] Example 2: The device according to Example 1, wherein the first die includes vias that at least partially penetrate the thickness of the first die.

[0074] Example 3: The device according to Example 2, further comprising: a metal layer embedded in the substrate below the second cavity, wherein the second die is coupled to the metal layer.

[0075] Example 4: The device according to Examples 1-3, wherein the sidewall of the first cavity is substantially orthogonal to the top surface of the substrate.

[0076] Example 5: The device according to Examples 1-4, wherein the sidewall of the first cavity is not orthogonal to the top surface of the substrate.

[0077] Example 6: The device according to Examples 1-5, wherein the sidewall of the first cavity has a stepped profile.

[0078] Example 7: The device according to Example 6, wherein the vertical portion of the stepped profile has a slope.

[0079] Example 8: The device according to Examples 1-7, wherein the first depth is at least approximately 10 μm deeper than the second depth.

[0080] Example 9: The device according to Examples 1-8, wherein the first cavity completely penetrates the thickness of the substrate.

[0081] Example 10: The device as described in Examples 1 - 9 further includes: a second substrate located below the substrate, wherein the second substrate includes a solid glass layer having a rectangular prism form factor.

[0082] Example 11: A device includes: a core, wherein the core includes a solid glass layer; a layer located above the core, wherein the layer includes an organic dielectric; a first cavity located in the layer; a second cavity located in the layer; a first die located in the first cavity; and a second die located in the second cavity, wherein a first distance between the core and a bottom surface of the first cavity is less than a second distance between the core and a bottom surface of the second cavity.

[0083] Example 12: The device as described in Example 11, wherein the first die includes: a via passing through at least a portion of the thickness of the first die, wherein the via is conductive.

[0084] Example 13: The device as described in Example 12 further includes: a second via passing through the core, wherein the via is electrically coupled to the second via through one or more conductive structures between a bottom of the first cavity and a top of the core.

[0085] Example 14: The device as described in Examples 11 - 13, wherein a bottom surface of the second cavity includes a metal layer.

[0086] Example 15: The device as described in Examples 11 - 14, wherein sidewalls of the first cavity and the second cavity have a stepped profile.

[0087] Example 16: The device as described in Examples 11 - 15, wherein sidewalls of the first cavity and the second cavity have an inclined profile.

[0088] Example 17: A device includes: a board; a package substrate coupled to the board, wherein the package substrate includes: a core; a layer located above the core; a first bridge located in the layer having a first thickness; and a second bridge located in the layer having a second thickness different from the first thickness; and a die coupled to the package substrate, wherein the die is electrically coupled to the first bridge and the second bridge.

[0089] Example 18: The device as described in Example 17, wherein the first bridge includes a via passing at least partially through the thickness of the first bridge.

[0090] Example 19: The device as described in Example 17 or Example 18, wherein the core includes a solid glass layer having a thickness of at least 25 μm.

[0091] Example 20: The apparatus as described in Examples 17 - 19, wherein the apparatus is part of a personal computer, a server, a mobile device, a tablet computer, or an automobile.

Claims

1. A device comprising: substrate; a first cavity disposed in the substrate, wherein the first cavity has a first depth; a second cavity disposed in the substrate, wherein the second cavity has a second depth different from the first depth; a first die located in the first cavity, wherein the first die has a first thickness; and A second die is located in the second cavity, wherein the second die has a second thickness different from the first thickness. 2 . The apparatus of claim 1 , wherein the first die comprises a via extending at least partially through a thickness of the first die.

3. The apparatus of claim 2, further comprising: A metal layer is embedded in the substrate below the second cavity, wherein the second die is coupled to the metal layer.

4. The apparatus of claim 1, 2 or 3, wherein a sidewall of the first cavity is substantially normal to a top surface of the substrate.

5. The apparatus of claim 1, 2 or 3, wherein a sidewall of the first cavity is not orthogonal to a top surface of the substrate.

6. The apparatus of claim 1, 2 or 3, wherein a side wall of the first cavity has a stepped profile.

7. The apparatus of claim 6, wherein a vertical portion of the step profile has a slope.

8. The apparatus of claim 1, 2 or 3, wherein the first depth is at least approximately 10 μm deeper than the second depth.

9. The apparatus of claim 1, 2 or 3, wherein the first cavity extends completely through the thickness of the substrate.

10. The apparatus of claim 1, 2 or 3, further comprising: A second substrate is disposed below the substrate, wherein the second substrate comprises a solid glass layer having a rectangular prism form factor.

11. A device comprising: a core, wherein the core comprises a solid glass layer; a layer disposed over the core, wherein the layer comprises an organic dielectric; a first cavity located in the layer; a second cavity located in the layer; A first tube core is located in the first cavity; and A second tube core is located in the second cavity, wherein a first distance between the core and a bottom surface of the first cavity is smaller than a second distance between the core and a bottom surface of the second cavity.

12. The apparatus of claim 11, wherein the first die comprises: A via passes through at least a portion of a thickness of the first die, wherein the via is electrically conductive.

13. The apparatus of claim 12, further comprising: A second via passes through the core, wherein the via is electrically coupled to the second via through one or more conductive structures between a bottom of the first cavity and a top of the core.

14. The apparatus of claim 11, 12 or 13, wherein a bottom surface of the second cavity comprises a metal layer.

15. The apparatus of claim 11, 12 or 13, wherein the side walls of the first cavity and the second cavity have a stepped profile.

16. The apparatus of claim 11, 12 or 13, wherein the side walls of the first cavity and the second cavity have an inclined profile.

17. A device comprising: plate; a packaging substrate coupled to the board, wherein the packaging substrate comprises: core; a layer located on the core; a first bridge, located in the layer, having a first thickness; and a second bridge, located in the layer, having a second thickness different from the first thickness; and A die is coupled to the package substrate, wherein the die is electrically coupled to the first bridge and the second bridge.

18. The apparatus of claim 17, wherein the first bridge comprises a via at least partially passing through a thickness of the first bridge.

19. A device as claimed in claim 17 or 18, wherein the core comprises a solid glass layer having a thickness of at least 25 μm.

20. The apparatus of claim 17 or 18, wherein the apparatus is part of a personal computer, a server, a mobile device, a tablet computer, or a car.

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