Package substrate and manufacturing method thereof

Abstract

The invention discloses a package substrate and a manufacturing method thereof. The package substrate comprises a core layer, a first dielectric layer, a second dielectric layer, an outer circuit layer, a circuit structure and a wiring structure, wherein the first dielectric layer and the second dielectric layer are respectively formed on two opposite sides of the core layer; the outer circuit layer is embedded in the first dielectric layer; according to the invention, the wiring structure in the RDL form is formed on the first dielectric layer and the outer circuit layer, so that the problem of warping of the asymmetric packaging substrate due to uneven stress distribution can be avoided while the requirement of a thin circuit is considered.

Description

Technical Field

[0001] The present invention relates to a packaging substrate for carrying a chip, and more particularly to a packaging substrate capable of preventing warping and improving reliability and a manufacturing method thereof. Background Art

[0002] With the vigorous development of the electronics industry, electronic products tend to be thinner, lighter, shorter and smaller in form, and in terms of functions, they are developed towards high performance, high functionality and high speed. Therefore, various packaging processes are also innovated accordingly. To meet the requirements of the fan-out package for thinning and high density, in the packaging process, the RDL (Redistribution Layer) technology is often used to change the routing and the pad assembly and interconnection positions to accommodate more input / output (I / O) contacts, so as to achieve the multi-functionality and miniaturization of electronic devices.

[0003] However, in the existing manufacturing method of the package, due to the mismatch between the thermal expansion coefficients of the redistribution layer (RDL) and the substrate material, the substrate is prone to warping under the thermal stress during the processing. Especially when manufacturing a packaging substrate with a high-density RDL layer, the substrate is easily deformed due to the asymmetric structure generated by the RDL layer, resulting in poor dimensional stability and reliability of the packaging substrate.

[0004] Therefore, how to overcome the problems of the above-mentioned prior art has actually become an urgent issue to be solved currently. Summary of the Invention

[0005] In view of the above-mentioned various deficiencies of the prior art, the present invention provides a packaging substrate, including: a core board body having a core layer, and the core layer having opposite first and second sides; a first dielectric layer formed on the first side of the core layer; a second dielectric layer formed on the second side of the core layer; an outer circuit layer embedded in the first dielectric layer on the first side of the core layer; a circuit structure formed on the second dielectric layer on the second side of the core layer and electrically connected to the outer circuit layer; and a wiring structure formed on the first dielectric layer and the outer circuit layer on the first side of the core layer and electrically connected to the outer circuit layer.

[0006] The present invention also provides a manufacturing method of a packaging substrate, including: providing a plurality of core board bodies, wherein each core board body has a core layer, and each core layer has opposite first and second sides, and providing a carrier having outer circuit layers provided on opposite sides thereof; bonding the first sides of the core layers of the two core board bodies to the opposite sides of the carrier through the first dielectric layer, so that the outer circuit layers on the carrier are embedded in the first dielectric layer on the first side of the core layer, and a second dielectric layer is bonded to the second sides of the two core layers; forming a circuit structure on the second dielectric layer on the second side of the core layer; removing the carrier; and forming a wiring structure on the first dielectric layer and the outer circuit layer on the first side of the core layer and electrically connecting the wiring structure to the outer circuit layer.

[0007] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the material of the core layer is glass, ceramic, silicon carbide (SiC), AlO2, or a high-rigidity composite material with a modulus of 50 to 100 GPa.

[0008] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the first dielectric layer and the second dielectric layer include a prepreg (PP) with glass fibers.

[0009] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the wiring structure includes at least one insulating layer, at least one wiring layer formed on the insulating layer, and at least one conductive blind via disposed in the insulating layer for electrically connecting the wiring layer and the outer circuit layer.

[0010] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the material of the insulating layer is different from the materials of the first dielectric layer and the second dielectric layer.

[0011] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the insulating layer includes an Ajinomoto build-up film (ABF) or a photosensitive polyimide (PSPI).

[0012] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the core board further includes at least one through hole penetrating the opposite first side and second side of the core layer, and conductive posts correspondingly formed in the through holes, and inner circuit layers are respectively formed on the first side and the second side, and wherein, the conductive posts are hollow conductive posts, and the inside of the hollow conductive posts is filled with plugging hole materials.

[0013] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the material for forming the conductive posts includes a barrier layer formed in contact with the core layer and a seed layer formed between the barrier layer and the plugging hole materials.

[0014] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the material for forming the inner circuit layer includes a barrier layer, a seed layer, and copper.

[0015] In a specific embodiment of the foregoing encapsulation substrate and its manufacturing method, the manufacturing of the conductive pillars and the inner circuit layer includes forming at least one through-hole penetrating the opposite first side and second side of the core layer; sequentially forming a barrier layer and a seed layer on the opposite first side and second side of the core layer and on the wall of the through-hole; filling the through-hole with a plugging material; performing plating and patterning processes on the opposite first side and second side of the core layer to form the inner circuit layer, and removing the barrier layer and the seed layer not covered by the inner circuit layer to expose the surfaces of the first side and the second side of a part of the core layer.

[0016] In a specific embodiment of the foregoing encapsulation substrate and its manufacturing method, the core layer bonded to the opposite two sides of the carrier has at least one through-hole penetrating the opposite first side and second side of the core layer, and the first dielectric layer and / or the second dielectric layer is filled into the through-hole. The manufacturing method may further include, after bonding a second dielectric layer on the second side of the two core layers, forming a conductive pillar penetrating the first dielectric layer, the through-hole, and the second dielectric layer corresponding to the through-hole to electrically connect the outer circuit layer and the circuit structure, and then forming the circuit structure on the second dielectric layer on the second side of the core layer.

[0017] In a specific embodiment of the foregoing encapsulation substrate and its manufacturing method, the conductive pillar is a conical solid conductive pillar, and the diameter of the end of the conductive pillar connected to the outer circuit layer is smaller than the diameter of the end connected to the circuit structure.

[0018] As can be seen from the above, for the encapsulation substrate and its manufacturing method of the present invention, by forming a wiring structure in the form of RDL on the first dielectric layer and the outer circuit layer, that is, on the other side opposite to the circuit structure, the problem of warping of the asymmetric encapsulation substrate due to uneven stress distribution can be avoided. Therefore, the present invention can maintain the substrate reliability while meeting the requirements of high-density RDL and fine circuits, which is beneficial to improving the yield of end products.

[0019] Furthermore, since the material for forming the core layer is a high-rigidity material such as glass, ceramic, silicon carbide (SiC), AlO2, etc., the coefficient of thermal expansion (CTE) of the core layer is relatively low. Therefore, compared with the existing organic substrates, the core board body of the present invention has excellent dimensional stability and can avoid problems such as warping and deformation during the process.

[0020] In addition, the present invention uses an insulating layer with a material different from that of the first dielectric layer and the second dielectric layer as the material of the RDL layer. By matching the coefficients of thermal expansion (CTE) of different materials, it is beneficial to disperse thermal stress, and the encapsulation substrate of the present invention can also effectively avoid the problem of warping in subsequent processes.

[0021] In addition, the present invention can simultaneously manufacture multiple encapsulation substrates with embedded outer circuit layers by forming outer circuit layers on both opposite sides of the carrier, greatly improving the production efficiency and reducing the manufacturing cost. Description of the Drawings

[0022] Figures 1A to 1F A cross-sectional schematic diagram of the first embodiment of the method for manufacturing the packaging substrate of the present invention.

[0023] Figures 2A to 2F A cross-sectional schematic diagram of the second embodiment of the method for manufacturing the packaging substrate of the present invention.

[0024] Among them, the reference numerals are described as follows:

[0025] 1, 2: Packaging substrate

[0026] 1a, 2a: Core board body

[0027] 10, 20: Core layer

[0028] 10a, 20a: First side

[0029] 10b, 20b: Second side

[0030] 11, 21: Perforation

[0031] 121: Barrier layer

[0032] 122: Seed layer

[0033] 13: Plugging material

[0034] 14: Inner circuit layer

[0035] 15, 25: Conductive post

[0036] 16, 26: First dielectric layer

[0037] 161, 261: Outer circuit layer

[0038] 163, 173, 183, 193, 283, 293: Conductive blind hole

[0039] 17, 27: Second dielectric layer

[0040] 171, 271, 91: Copper foil

[0041] 18, 28: Circuit structure

[0042] 181, 281: Circuit layer

[0043] 182, 282: Third dielectric layer

[0044] 19, 29: Wiring structure

[0045] 191, 291: Wiring layer

[0046] 192, 292: Insulating layer

[0047] 22: Through hole

[0048] 9: Carrier

[0049] 90: Plate body Detailed implementation manners

[0050] The following illustrates the implementation manners of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0051] It should be noted that the structures, ratios, sizes, etc. shown in the attached drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented. Therefore, they do not have technical essential meanings. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope that the technical content disclosed by the present invention can cover. At the same time, the terms such as "upper", "first", "second", "one", etc. cited in this specification are only for the convenience of clear narration, and are not used to limit the scope under which the present invention can be implemented. The change or adjustment of their relative relationships, without substantial change of the technical content, should also be regarded as the scope under which the present invention can be implemented.

[0052] Figures 1A to 1F It is a schematic cross-sectional view of the manufacturing method of the packaging substrate 1 of the present invention.

[0053] As Figure 1A shown, a core layer 10 having opposite first side 10a and second side 10b is provided, and at least one through hole 11 penetrating the opposite first side 10a and second side 10b of the core layer 10 is formed. Then, a barrier layer 121 and a seed layer 122 are sequentially formed on the opposite first side 10a and second side 10b of the core layer 10 and the wall surface of the through hole 11, and a plugging material 13 is filled in the at least one through hole 11.

[0054] In this embodiment, the material for forming the core layer 10 can be glass, ceramic, silicon carbide (SiC), AlO2, or a highly rigid composite material with a modulus of 50 to 100 GPa. The through hole 11 can be formed by means of laser ablation, hydrofluoric acid (HF) etching, plasma etching, mechanical drilling, etc.

[0055] Furthermore, the barrier layer 121 and the seed layer 122 can be formed by means such as sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). Among them, the barrier layer 121 can be a conductive barrier layer or a dielectric barrier layer. Materials for forming the conductive barrier layer include tantalum, titanium nitride, tantalum nitride, tungsten nitride, or other metal nitrides, but are not limited thereto; materials for forming the dielectric barrier layer include silicon nitride, silicon oxynitride, silicon carbonitride, or diamond-like carbon (DLC), but are not limited thereto. Materials for forming the seed layer 122 include copper, manganese-doped copper, or ruthenium, but are not limited thereto.

[0056] In addition, the via filling material 13 is an ink material that can be formed by filling methods such as injection, plugging, or coating. For example, the ink material mainly includes epoxy ink composites, which have physical properties such as a viscosity of 25 to 55 Pa·s, a glass transition temperature (Tg) of 145 to 180 °C, and / or a Young's modulus of 3 to 10 GPa.

[0057] As Figure 1B As shown, inner circuit layers 14 are formed on opposite first side 10a and second side 10b of the core layer 10 to fabricate the core board body 1a. And the barrier layer 121 and the seed layer 122 on the wall surface of the via 11 together form at least one conductive pillar 15, wherein the conductive pillar 15 connects the first side 10a and the second side 10b of the core layer 10.

[0058] In this embodiment, the inner circuit layer 14 is formed by plating a metal such as copper on the barrier layer 121 and the seed layer 122 to perform a patterned circuit process, and the barrier layer 121 and the seed layer 122 not covered by the inner circuit layer 14 are removed to expose the surfaces of the first side 10a and the second side 10b of a part of the core layer 10.

[0059] Furthermore, the conductive pillar 15 is hollow, so that the via filling material 13 is filled inside the conductive pillar 15 formed by the barrier layer 121 and the seed layer 122 on the wall surface of the via 11.

[0060] As Figure 1C As shown, a carrier 9 is provided, and outer circuit layers 161 are respectively provided on opposite sides thereof. Each of the two core board bodies 1a is bonded to opposite sides of the carrier 9 through a first dielectric layer 16, such that the outer circuit layer 161 on the carrier 9 is embedded in the first dielectric layer 16 on the first side 10a of the core layer 10, that is, the outer circuit layer 161 is embedded inside the surface of the first dielectric layer 16 relative to contacting the core layer 10 and the inner circuit layer 14, and a second dielectric layer 17 is bonded to the second side 10b of the two core layers 10.

[0061] In this embodiment, the carrier 9 can be a sticky temporary carrier plate, and its plate body 90 can be an organic polymer plate such as bismaleimide triazine (BT), prepreg with glass fiber (PP), etc., or a copper foil substrate. For example, the carrier 9 is a plate with metal layers such as copper foils 91 on opposite sides of a plate body 90.

[0062] Furthermore, a patterning process is performed on the copper foils 91 on opposite sides of the carrier 9 to form the outer circuit layer 161. In one embodiment, a dry film is attached to opposite sides of the carrier 9, and then the outer circuit layer 161 is fabricated through exposure, development, and electroplating by the patterning process, and the material forming the outer circuit layer 161 is copper. Also, a ring-shaped alignment portion (not shown) can be formed on the copper foil 91 first as an alignment mark for subsequent laser drilling to facilitate the formation of a small-sized laser aperture.

[0063] In addition, the first dielectric layer 16 can be formed between the carrier 9 and the core plate body 1a by lamination or other means to cover the outer circuit layer 161 on the carrier 9, so that the outer circuit layer 161 has better adhesion to avoid delamination problems. The second dielectric layer 17 can also be combined on the second side 10b of the core layer 10 by lamination. Among them, one side of the second dielectric layer 17 that does not contact the core plate body 1a can have a metal layer to facilitate subsequent circuit fabrication, such as a copper foil 171 is attached to the second dielectric layer 17.

[0064] In addition, the first dielectric layer 16 and the second dielectric layer 17 can be of the same or different materials. For example, they can include prepreg with glass fiber (PP), Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), etc., or other dielectric materials.

[0065] As Figure 1D shown, a circuit structure 18 is formed on the second dielectric layer 17 on the second side 10b of the core layer 10.

[0066] In this embodiment, the circuit structure 18 includes a circuit layer 181 formed on the second dielectric layer 17, a third dielectric layer 182 formed on the second dielectric layer 17 and covering the circuit layer 181, and conductive blind vias 183 formed in the third dielectric layer 182. For example, first, laser, etching, or mechanical drilling is performed in the second dielectric layer 17 and plating is carried out to form the conductive blind vias 173 to electrically connect the circuit structure 18 to the inner circuit layer 14. Then, the circuit structure 18 is fabricated by a build-up process, such as electroplating a metal (such as copper) or other means, including fabricating the circuit layer 181 by means of a copper foil 171.

[0067] It should be understood that the number of build-up layers of the circuit structure 18 can be designed according to requirements and is not limited to the above, and the material of the third dielectric layer 182 can be the same as or different from the materials of the first dielectric layer 16 and the second dielectric layer 17.

[0068] As Figure 1E shown, the carrier 9 is removed to expose the outer circuit layer 161.

[0069] In this embodiment, by means of laser, etching, mechanical drilling, etc., an opening is made in the first dielectric layer 16 using the annular alignment portion, and a plating process is carried out to form small-diameter conductive blind vias 163 to electrically connect the outer circuit layer 161 to the inner circuit layer 14. Then, the surface of the outer circuit layer 161 is subjected to flash etching to etch away the excess thin copper layer, making the outer circuit layer 161 flush or coplanar with the surface of the first dielectric layer 16.

[0070] In addition, since this step only requires a plating process on the first dielectric layer 16 on the first side 10a of the core layer 10, after the opening is formed, a dry film can be attached to the circuit structure 18 on the second side 10b of the core layer 10 to cover the circuit structure 18. After the plating and flash etching processes on the first side 10a of the core layer 10 are completed, the dry film is then removed (figure omitted).

[0071] As Figure 1F shown, a wiring structure 19 is formed on the first dielectric layer 16 and the outer circuit layer 161 on the first side 10a of the core layer 10 to fabricate the packaging substrate 1, wherein the wiring structure 19 is electrically connected to the outer circuit layer 161.

[0072] In this embodiment, the wiring structure 19 adopts the Rewiring Layer (RDL) specification. The wiring structure 19 includes at least one insulating layer 192, at least one wiring layer 191 formed on the insulating layer 192, and at least one conductive blind via 193 provided in the insulating layer 192 for electrically connecting the wiring layer 191 to the outer circuit layer 161.

[0073] Furthermore, the material of the insulating layer 192 is different from that of the first dielectric layer 16 and the second dielectric layer 17. For example, the insulating layer 192 may include Ajinomoto build-up film (ABF) or Photosensitive Polyimide (PSPI).

[0074] It should be understood that the number of wiring layers of the wiring structure 19 can be designed according to requirements and is not limited to the two wiring layers 191 shown in the figure. Also, the material of the insulating layer 192 can be selected according to the line width / line pitch (L / S) requirements. For example, photosensitive polyimide (PSPI) with high resolution can form high-density patterns, which is beneficial to the design of miniaturized circuits.

[0075] Therefore, the manufacturing method of this embodiment mainly electrically connects the outer wiring layer 161 on the first side 10a of the core layer 10 and the wiring structure 18 on the second side 10b of the core layer 10 through the hollow conductive column 15 that connects the first side 10a and the second side 10b of the core layer 10.

[0076] Figures 2A to 2F It is a cross-sectional schematic diagram of the manufacturing method of the packaging substrate 2 of the present invention.

[0077] As Figure 2A shown, a core layer 20 having opposite first side 20a and second side 20b is provided, and at least one through hole 21 penetrating the opposite first side 20a and second side 20b of the core layer 20 is formed to manufacture the core board body 2a.

[0078] In this embodiment, the material for forming the core layer 20 can be glass, ceramic, silicon carbide (SiC), AlO2, or a highly rigid composite material with a modulus of 50 to 100 GPa. The through hole 21 can be formed by laser ablation, hydrofluoric acid (HF) etching, plasma etching, mechanical drilling, etc.

[0079] As Figure 2B shown, a carrier 9 is provided, and outer wiring layers 261 are respectively provided on opposite sides thereof. Each of the two core board bodies 2a is bonded to opposite sides of the carrier 9 through the first dielectric layer 26, so that the outer wiring layers 261 on the carrier 9 are embedded in the first dielectric layer 26 on the first side 20a of the core layer 20, that is, the outer wiring layers 261 are embedded in the surface of the first dielectric layer 26 relative to contacting the core layer 20, and a second dielectric layer 27 is bonded to the second side 20b of the two core layers 20.

[0080] In this embodiment, the carrier 9 can be a sticky temporary carrier plate, and its plate body 90 can be an organic polymer plate such as bismaleimide triazine (BT), prepreg with glass fiber (PP), etc., or a copper foil substrate. For example, the carrier 9 is a plate body 90 with metal layers such as copper foils 91 on opposite sides thereof.

[0081] Furthermore, a patterning process is performed on the copper foils 91 on opposite sides of the carrier 9 to form the outer circuit layer 261. In one embodiment, a dry film is attached to opposite sides of the carrier 9, and then the outer circuit layer 261 is fabricated through exposure, development, and electroplating by the patterning process, and the material forming the outer circuit layer 261 is copper. And a ring-shaped alignment portion (not shown) can be formed on the copper foil 91 first as an alignment mark for subsequent laser drilling.

[0082] In addition, the first dielectric layer 26 can be formed between the carrier 9 and the core plate body 2a by lamination or other means to cover the outer circuit layer 261 on the carrier 9, so that the outer circuit layer 261 has better adhesion to avoid delamination problems. The second dielectric layer 27 can also be combined on the second side 20b of the core layer 20 by lamination. Among them, one side of the second dielectric layer 27 not in contact with the core plate body 2a can have a metal layer to facilitate subsequent circuit fabrication, such as attaching a copper foil 271.

[0083] In addition, the first dielectric layer 26 and the second dielectric layer 27 can be of the same or different materials. For example, they can include prepreg with glass fiber (PP), Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), etc., or other dielectric materials.

[0084] As Figure 2C shown, the first dielectric layer 26 and / or the second dielectric layer 27 are filled into the vias 21, and via holes 22 passing through the first dielectric layer 26, the vias 21, and the second dielectric layer 27 are formed corresponding to the vias 21.

[0085] In this embodiment, methods such as laser, etching, or mechanical drilling are used to form the via holes 22 by using the ring-shaped alignment portion (not shown) to penetrate the first dielectric layer 26, the first dielectric layer 26 and / or the second dielectric layer 27 in the vias 21, and the second dielectric layer 27.

[0086] As Figure 2DAs shown, a conductive post 25 is formed in the via hole 22, and a circuit structure 28 is formed on the second dielectric layer 27 on the second side 20b of the core layer 20, so that the circuit structure 28 and the external circuit layer 261 are electrically connected by the conductive post 25.

[0087] In this embodiment, a seed layer (not shown) is formed on the wall surface of the via hole 22, and the conductive post 25 is formed by plating on the seed layer in the via hole 22. Among them, the conductive post 25 is a tapered solid post, and the via hole 22 is formed in the direction from the second dielectric layer 27 to the first dielectric layer 26. Therefore, the conductive post 25 is V-shaped, that is, the diameter of the end of the conductive post 25 connected to the external circuit layer 261 is smaller than the diameter of the other end connected to the circuit structure 28.

[0088] Furthermore, the circuit structure 28 includes a circuit layer 281 formed on the second dielectric layer 27, a third dielectric layer 282 formed on the second dielectric layer 27 and covering the circuit layer 281, and conductive blind vias 283 formed in the third dielectric layer 282. For example, the circuit structure 28 is fabricated by a build-up process such as electroplating a metal (such as copper) or other methods, including fabricating the circuit layer 281 by using a copper foil 271.

[0089] It should be understood that the number of build-up layers of the circuit structure 28 can be designed according to requirements and is not limited to the above, and the material of the third dielectric layer 282 can be the same as or different from the materials of the first dielectric layer 26 and the second dielectric layer 27.

[0090] As Figure 2E shown, the carrier 9 is removed to expose the external circuit layer 261.

[0091] In this embodiment, the surface of the external circuit layer 261 is flash-etched to etch away the excess thin copper layer, so that the external circuit layer 261 is flush or coplanar with the surface of the first dielectric layer 26.

[0092] In addition, since this step only requires flash-etching the first dielectric layer 26 on the first side 20a of the core layer 20, after removing the carrier 9, a dry film can be first attached to the circuit structure 28 on the second side 20b of the core layer 20 to cover the circuit structure 28, and after the flash-etching process on the first side 20a of the core layer 20 is completed, the dry film is removed (not shown).

[0093] As Figure 2F shown, a wiring structure 29 is formed on the first dielectric layer 26 and the external circuit layer 261 on the first side 20a of the core layer 20 to fabricate the package substrate 2, wherein the wiring structure 29 is electrically connected to the external circuit layer 261.

[0094] In this embodiment, the wiring structure 29 adopts the Rewiring Layer (RDL) specification. The wiring structure 29 includes at least one insulating layer 292, at least one wiring layer 291 formed on the insulating layer 292, and at least one conductive blind via 293 disposed in the insulating layer 292 for electrically connecting the wiring layer 291 and the external wiring layer 261.

[0095] Furthermore, the material of the insulating layer 292 is different from that of the first dielectric layer 26 and the second dielectric layer 27. For example, the insulating layer 292 may include Ajinomoto build-up film (ABF) or Photosensitive Polyimide (PSPI).

[0096] It should be understood that the number of layers of the wiring structure 29 can be designed according to requirements and is not limited to the two wiring layers 291 shown in the figure. Also, the material of the insulating layer 292 can be selected according to the line width / line pitch (L / S) requirements. For example, Photosensitive Polyimide (PSPI) with high resolution can form high-density patterns, which is beneficial to the design of miniaturized circuits.

[0097] Therefore, the manufacturing method of this embodiment mainly electrically connects the external wiring layer 261 on the first side 20a of the core layer 20 and the wiring structure 28 on the second side 20b through the tapered solid conductive column 25 that penetrates the first dielectric layer 26, the via 21, and the second dielectric layer 27.

[0098] The present invention also provides a packaging substrate 1, 2, including: a core board body 1a, 2a; a first dielectric layer 16, 26, a second dielectric layer 17, 27, an external wiring layer 161, 261, a wiring structure 18, 28, and a wiring structure 19, 29.

[0099] The core board body 1a, 2a has a core layer 10, 20, and the core layer 10, 20 has opposite first sides 10a, 20a and second sides 10b, 20b.

[0100] The first dielectric layer 16, 26 is formed on the first side 10a, 20a of the core layer 10, 20.

[0101] The second dielectric layer 17, 27 is formed on the second side 10b, 20b of the core layer 10, 20.

[0102] The external wiring layer 161, 261 is embedded in the first dielectric layer 16, 26 on the first side 10a, 20a of the core layer 10, 20.

[0103] The described circuit structures 18, 28 are formed on the second dielectric layers 17, 27 on the second sides 10b, 20b of the core layers 10, 20, and are electrically connected to the outer circuit layers 161, 261.

[0104] The described wiring structures 19, 29 are formed on the first dielectric layers 16, 26 and the outer circuit layers 161, 261 on the first sides 10a, 20a of the core layers 10, 20, and are electrically connected to the outer circuit layers 161, 261.

[0105] In one embodiment, the materials of the core layers 10, 20 are glass, ceramic, silicon carbide (SiC), AlO2, or a highly rigid composite material with a modulus of 50 to 100 Gpa.

[0106] In one embodiment, the first dielectric layers 16, 26 and the second dielectric layers 17, 27 include prepregs (PP) with glass fibers.

[0107] In one embodiment, the wiring structures 19, 29 include at least one insulating layer 192, 292, at least one wiring layer 191, 291 formed on the insulating layer 192, 292, and at least one conductive blind via 193, 293 disposed in the insulating layer 192, 292 and electrically connecting the wiring layer 191, 291 to the outer circuit layer 161, 261.

[0108] In one embodiment, the material of the insulating layer 192, 292 is different from the materials of the first dielectric layers 16, 26 and the second dielectric layers 17, 27.

[0109] In one embodiment, the insulating layer 192, 292 includes Ajinomoto build-up film (ABF) or Photosensitive Polyimide (PSPI).

[0110] In one embodiment, the core board 1a includes at least one perforation 11 penetrating the opposite first side 10a and second side 10b of the core layer 10, and conductive posts 15 correspondingly formed in the perforation 11. And inner circuit layers 14 are respectively formed on the first side 10a and the second side 10b. And wherein, the conductive posts 15 are hollow conductive posts 15, and the inside of the hollow conductive posts 15 is filled with plugging material 13.

[0111] In one embodiment, the material for forming the conductive posts 15 includes a barrier layer 121 formed in contact with the core layer 10 and a seed layer 122 formed between the barrier layer 121 and the plugging material 13.

[0112] In one embodiment, the material for forming the inner circuit layer 14 includes a barrier layer 121, a seed layer 122, and copper.

[0113] In one embodiment, the core layer 20 has at least one through hole 21 penetrating opposite first and second sides 20a and 20b of the core layer 20, and conductive posts 25 formed in the through holes 21 and electrically connecting to the outer circuit layer 261; and the first dielectric layer 26 and / or the second dielectric layer 27 are filled between the through holes 21 and the conductive posts 25, so that the conductive posts 25 penetrate through the first dielectric layer 26, the through holes 21, and the second dielectric layer 27.

[0114] In one embodiment, the conductive post 25 is a conical solid conductive post 25, and the diameter of the end of the conductive post 25 connected to the outer circuit layer 261 is smaller than the diameter of the other end connected to the circuit structure 28.

[0115] In summary, for the packaging substrate and its manufacturing method of the present invention, by forming a wiring structure with the specification of the redistribution layer (RDL) on the first dielectric layer and the outer circuit layer on the first side of the core layer, the problem of warping caused by uneven stress distribution due to the asymmetrically arranged outer circuit layers and circuit structures on both sides of the core board body can be avoided. Therefore, the present invention can maintain the reliability of the substrate while meeting the requirements of high-density RDL and fine lines, which is beneficial to improving the yield of end products.

[0116] Furthermore, since the material for forming the core layer is a high-rigidity material such as glass, ceramic, silicon carbide (SiC), or AlO2, the core layer has advantages such as low coefficient of thermal expansion (CTE), good heat resistance, and high mechanical strength. Therefore, the core board body of the present invention has excellent dimensional stability and can avoid problems such as warping and deformation during the process.

[0117] In addition, the present invention uses an insulating layer with a different material from that of the first dielectric layer and the second dielectric layer as the material of the RDL layer. By matching the coefficients of thermal expansion (CTE) of different materials, it is beneficial to disperse thermal stress, and the packaging substrate of the present invention can also effectively avoid the problem of warping in subsequent processes.

[0118] In addition, by forming outer circuit layers on both opposite sides of the carrier, the present invention can simultaneously manufacture multiple packaging substrates with embedded outer circuit layers, greatly improving production efficiency and reducing manufacturing costs.

[0119] The above embodiments are used to illustratively explain the principles and effects of the present invention, rather than to limit the present invention. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the rights protection of the present invention should be as listed in the claims.

Claims

1. A packaging substrate, characterized in that: include: The core board has a core layer, and the core layer has a first side and a second side opposite to each other; a first dielectric layer formed on a first side of the core layer; a second dielectric layer formed on a second side of the core layer; an outer circuit layer embedded in the first dielectric layer on the first side of the core layer; A circuit structure formed on the second dielectric layer on the second side of the core layer and electrically connected to the outer circuit layer; as well as The wiring structure is formed on the first dielectric layer on the first side of the core layer and the outer circuit layer, and is electrically connected to the outer circuit layer.

2. The packaging substrate according to claim 1, wherein: The core layer is made of glass, ceramic, silicon carbide, AlO2 or a composite material with high rigidity and a modulus of 50 to 100 GPa, and the first dielectric layer and the second dielectric layer include prepreg with glass fiber.

3. The packaging substrate according to claim 1, wherein: The wiring structure includes at least one insulating layer, at least one wiring layer formed on the insulating layer, and at least one conductive blind hole in the insulating layer electrically connecting the wiring layer and the outer circuit layer, and the material of the insulating layer is different from that of the first dielectric layer and the second dielectric layer.

4. The packaging substrate according to claim 3, characterized in that: The insulating layer includes an Ajinomoto build-up layer film or a photosensitive polyimide.

5. The packaging substrate according to claim 1, wherein: The core board also includes at least one through-hole penetrating the first side and the second side opposite to each other of the core layer, and a conductive column correspondingly formed in the through-hole, and an inner circuit layer is formed on the first side and the second side respectively, and wherein the conductive column is a hollow conductive column, and the interior of the hollow conductive column is filled with plugging material.

6. The packaging substrate according to claim 5, characterized in that The material forming the conductive column includes a barrier layer formed on the core layer and a seed layer formed between the barrier layer and the plug material, and the material forming the inner circuit layer includes the barrier layer, the seed layer and copper.

7. The packaging substrate according to claim 1, wherein: The core layer has at least one through-hole penetrating through the first and second sides of the core layer, and a conductive column electrically connected to the outer circuit layer formed in the through-hole; and the first dielectric layer and / or the second dielectric layer are filled between the through-hole and the conductive column so that the conductive column penetrates the first dielectric layer, the through-hole and the second dielectric layer.

8. The packaging substrate according to claim 7, wherein: The conductive column is a conical solid conductive column, and the diameter of one end of the conductive column connected to the outer circuit layer is smaller than the diameter of the other end connected to the circuit structure.

9. The packaging substrate according to claim 1, wherein: The outer circuit layer is coplanar with the surface of the first dielectric layer.

10. A method for manufacturing a packaging substrate, characterized in that: include: A plurality of core boards are provided, wherein each core board has a core layer, each core layer has a first side and a second side opposite to each other, and a carrier having outer circuit layers respectively disposed on two opposite sides thereof is provided; The first side of each core layer of each of the two core boards is bonded to the opposite sides of the carrier through a first dielectric layer, so that the outer circuit layer on the carrier is embedded in the first dielectric layer on the first side of the core layer, and a second dielectric layer is bonded to the second side of the two core layers; forming a circuit structure on the second dielectric layer on the second side of the core layer; removing the carrier; and A wiring structure is formed on the first dielectric layer on the first side of the core layer and the outer circuit layer, and the wiring structure is electrically connected to the outer circuit layer.

11. The method for manufacturing a packaging substrate according to claim 10, wherein: The core layer is made of glass, ceramic, silicon carbide, AlO2 or a composite material with high rigidity and a modulus of 50 to 100 GPa, and the first dielectric layer and the second dielectric layer include prepreg with glass fiber.

12. The method for manufacturing a packaging substrate according to claim 10, wherein: The wiring structure includes at least one insulating layer, at least one wiring layer formed on the insulating layer, and at least one conductive blind hole in the insulating layer electrically connecting the wiring layer and the outer circuit layer, and the material of the insulating layer is different from that of the first dielectric layer and the second dielectric layer.

13. The method for manufacturing a packaging substrate according to claim 12, wherein: The insulating layer includes an Ajinomoto build-up layer film or a photosensitive polyimide.

14. The method for manufacturing a packaging substrate according to claim 10, wherein: The core board includes at least one conductive column connecting the first side and the second side of the core layer to electrically connect the outer circuit layer and the circuit structure, and an inner circuit layer is formed on the first side and the second side respectively, and wherein the conductive column is a hollow conductive column, and the interior of the hollow conductive column is filled with plugging material.

15. The method for manufacturing a packaging substrate according to claim 14, wherein: The material forming the conductive column includes a barrier layer formed on the core layer and a seed layer formed between the barrier layer and the plug material, and the material forming the inner circuit layer includes the barrier layer, the seed layer and copper.

16. The method for manufacturing a packaging substrate according to claim 14, wherein: The production of the conductive column and the inner circuit layer includes forming at least one through-hole penetrating the first and second opposite sides of the core layer; sequentially forming a barrier layer and a seed layer on the first and second opposite sides of the core layer and on the wall surface of the through-hole; filling the at least one through-hole with a plugging material; performing plating and patterning processes on the first and second opposite sides of the core layer to form the inner circuit layer, and removing the barrier layer and the seed layer not covered by the inner circuit layer to expose a portion of the surface of the first and second sides of the core layer.

17. The method for manufacturing a packaging substrate according to claim 10, wherein: The core layer combined on the opposite sides of the carrier has at least one through hole penetrating the opposite first side and second side of the core layer, and the first dielectric layer and / or the second dielectric layer are filled in the through hole.

18. The method for manufacturing a packaging substrate according to claim 17, wherein: The manufacturing method also includes forming a conductive column corresponding to the through-hole that penetrates the first dielectric layer, the through-hole and the second dielectric layer after combining the second dielectric layer on the second side of the two core layers to electrically connect the outer circuit layer and the circuit structure, and then forming the circuit structure on the second dielectric layer on the second side of the core layer.

19. The method for manufacturing a packaging substrate according to claim 18, wherein: The conductive column is a conical solid conductive column, and the diameter of one end of the conductive column connected to the outer circuit layer is smaller than the diameter of the other end connected to the circuit structure.

20. The method for manufacturing a packaging substrate according to claim 10, wherein: The outer circuit layer is coplanar with the surface of the first dielectric layer.

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