Low profile die terminal with ball drop solder

Abstract

The invention relates to a low profile die terminal with ball drop solder. An electronic device (100) includes: a semiconductor die (122) having a surface layer (106); a metallization structure (108) on the surface layer (106); a conductive terminal (114, 116) having a metal post (116) and having a first side (117) contacting a side (111) of a conductive feature (110) of the metallization structure (108); and a solder cap (118) on a second side of the conductive terminals (114, 116). A method includes forming a copper layer (114) on a portion of a conductive feature (110) of a metallized structure (108) of a wafer; forming a metal pillar (116) on a first portion of the copper layer (114); etching a second portion of the copper layer (114); performing a solder ball dripping process, the solder ball dripping process forming a solder cap (118) on one side of the metal post (116); and separating from the wafer a die (122) including the metal pillar (116) and the solder cap (118).

Description

Technical Field

[0001] This application generally relates to semiconductors, and more particularly, to low-profile die terminals with ball-drop solder. Background Art

[0002] Power conversion components and other high-power electronic devices are used in various applications that increasingly require a compact form factor and higher power density, such as cellular phones, mobile device chargers, industrial power conversion systems, and the like. Wafer chip scale packages (WCSPs) typically provide die interconnects through large solder balls, but this inhibits the ability to reduce die height and the size of the resulting packaged electronic device. Summary of the Invention

[0003] In one aspect, an electronic device includes: a semiconductor die having a semiconductor surface layer; a metallization structure on one side of the semiconductor surface layer and including conductive features; a conductive terminal having metal pillars, the conductive terminal having a first side that contacts one side of the conductive features; and a solder cap on a second side of the conductive terminal.

[0004] In another aspect, a system includes a circuit board and an electronic device attached to the circuit board. The electronic device includes: a semiconductor die having a semiconductor surface layer; a metallization structure on one side of the semiconductor surface layer and including conductive features; a conductive terminal having metal pillars, the conductive terminal having a first side that contacts one side of the conductive features; and a solder cap on a second side of the conductive terminal; wherein the second side of the conductive terminal is soldered to a lead frame or a substrate, and the lead frame or the substrate is electrically connected to the circuit board.

[0005] In another aspect, a method of manufacturing an electronic device includes: forming a copper layer on a portion of the conductive features of a metallization structure of a wafer; performing an electroplating process (700) that forms metal pillars on a first portion of the copper layer; etching a second portion of the copper layer; performing a solder ball drop process that forms a solder cap on one side of the metal pillars; and separating a die including the metal pillars and the solder cap from the wafer. Brief Description of the Drawings

[0006] Figure 1 is a partial side view of an electronic device having low-profile metal pillar terminals with ball-drop solder balls on metallized conductive features.

[0007] Figure 1A is having mounted to a circuit board Figure 1 of the system of the electronic device is a partial side view.

[0008] Figure 2 is a flowchart of a method of manufacturing an electronic device.

[0009] Figure 3-11 is a partial cross-sectional side view of a wafer processed according to the method of Figure 2 .

[0010] Figure 12 and 12A are a partial side view and a perspective view of a wafer processed by die separation according to the method of Figure 2 .

[0011] Figure 13-16 is a partial cross-sectional side view of a packaging process according to the method of Figure 2 . DETAILED DESCRIPTION

[0012] In the figures, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. Also, the terms "couple" or "couples" include indirect or direct electrical or mechanical connections or combinations thereof. For example, if a first device is coupled to or coupled with a second device, the connection may be a direct electrical connection or an indirect electrical connection via one or more intervening devices and connections. The following describes one or more operating characteristics of various circuits, systems, and / or components in the context of their functions, which in some cases are produced by the configuration and / or interconnection of various structures when the circuit system is powered on and operating. In the following discussion and claims, the terms "including", "includes", "having", "has", "with", or variations thereof are intended to be inclusive in a manner similar to the term "comprising" and should therefore be interpreted to mean "including but not limited to".

[0013] Unless otherwise stated, "about", "approximately", or "substantially" preceding a value means + / - 10% of the stated value. The following describes one or more operating characteristics of various circuits, systems, and / or components in the context of their functions, which in some cases are produced by the configuration and / or interconnection of various structures when the circuit system is powered on and operating. For ease of description in conjunction with a particular figure, one or more structures, features, aspects, components, etc. may be referred to herein as first, second, third, etc., such as first and second terminals, first, second, and third wells, etc., where such descriptions should not be construed as limiting the claims. The various disclosed structures and methods of the present disclosure may be advantageously applied to the manufacture of electronic devices such as integrated circuits. While it may be desirable for such examples to provide various improvements, the present disclosure does not require specific results unless explicitly recited in the particular claims.

[0014] First, refer to Figure 1 and1A , the disclosed examples include an electronic device 100 having a semiconductor die 122 ( Figure 1A ), the semiconductor die having a low electronic device height to facilitate compact form factor power converters and other electronic system applications. Figure 1 is shown as part of the electronic device 100 during processing as a wafer 102 before the die 122 is separated, and Figure 1A shows the electronic device 100 including the separated die 122 in a package structure mounted on a system circuit board. As Figure 1 shown, the electronic device 100 has a silicon substrate layer 104 and a semiconductor surface layer 106 on the substrate layer 104. In one example, the semiconductor surface layer 106 is or includes gallium nitride (GaN) having an upper or top side 107. In another example, the semiconductor surface layer 106 is or includes a different type of semiconductor material, such as silicon. One or more electronic components, such as transistors, diodes, resistors, etc. (not shown), may be formed on and / or in the semiconductor surface layer 106 to provide the electronic components and / or circuitry of the electronic device.

[0015] As Figure 1 further shown, the electronic device 100 includes a single-level or multi-level metallization structure 108 that includes one or more conductive features. The metallization structure 108 may include one or more patterned conductive metal traces and / or conductive metal vias, such as aluminum, copper, or other suitable conductive metal or its alloy, with a dielectric material formed around the conductive metal structure. In the illustrated example, the metallization structure 108 includes a conductive feature 110 connected to a metal trace feature in the uppermost level of the metallization structure 108. In one embodiment, the conductive feature 110 is or includes aluminum. In another embodiment, the conductive feature 110 may be a different conductive metal.

[0016] The electronic device 100 includes conductive metal terminals that provide electrical and mechanical interconnections for the circuits or components of the device 100, one of these circuits or components being shown in Figure 1 . Figure 1A An example system 130 is shown where the semiconductor die 122 of the electronic device 100 includes a plurality of terminals soldered to conductive features in the upper level of a multi-level package substrate 120. In this example, the conductive features or leads along the bottom level of the multi-level package substrate 120 are soldered to conductive metal pads on a printed circuit board 132. Figure 1AThe encapsulated electronic device 100 therein further includes a molded or ceramic encapsulation structure 124 which, in the illustrated example, surrounds all or part of the semiconductor die 122 and extends onto an upper portion of the multi-level package substrate 120. In one example, the die terminals of the electronic device 100 are or include copper pillars (e.g., studs) with solder caps. Additionally, in one example, the solder caps are formed by a solder ball drop process, as further discussed in connection with Figure 2 Further discussion.

[0017] In one example, a polyimide layer 112 extends over a portion of the conductive features 110 of the metallization structure 108 and contacts and covers an outer portion of the top side 111 of the conductive features 110, as Figure 1 Shown in. Figure 1 The conductive terminals illustrated in include a metal pillar 116 having a bottom or first side 117 which contacts a portion of the top side 111 of the conductive features 110. In one example, the metal pillar 116 is or includes copper. In another example, a different conductive metal may be used. In one example, the conductive terminal includes a sputtered titanium or titanium-tungsten layer as a barrier layer alloy, followed by a copper layer 114 extending between the metal pillar 116 and the conductive features 110 of the metallization structure 108, referred to as a seed layer. In one example, the copper layer 114 and any included barrier layer alloy are much thinner than the metal pillar 116, but any suitable thickness may be used. In this example, the bottom surface of the copper layer 114 (and any included barrier layer) forms the bottom side 117 of the conductive terminal and contacts a portion of the top side 111 of the conductive features 110 of the metallization structure 108. In this example, the polyimide layer 112 contacts a portion of the copper layer 114 and contacts a portion of the metal pillar 116, but this is not a strict requirement for all possible embodiments.

[0018] A solder cap 118 extends over the top or second side of the conductive terminals 114, 116. The vertical height of the metal pillar 116 can be any suitable thickness to provide thermal insulation for the semiconductor die 122, e.g., in one example using a gallium nitride semiconductor surface layer 106, approximately 35 to 50 μm. Significantly higher metal pillars 116 may be used, but this creates difficulties for the coplanarity of the top or second sides of multiple terminals of a given die 122. In this regard, a lower terminal height can advantageously contribute to a small form factor semiconductor die 122 and help reduce the overall height of the encapsulated electronic device 100 to accommodate small form factor applications.

[0019] Unlike wafer chip scale packaging methods using large solder ball terminals, the metal pillar contacts of the electronic device 100 provide small form factor solder capped conductive metal terminals for mechanically and electrically interconnecting the die 122 to a body structure, such as Figure 1AThe multi-level package substrate 120. In another example, the electronic device 100 may include conductive metal features of a starting lead frame (not shown), and the solder-capped conductive metal terminals 114, 116, 118 of the conductive metal features are connected to corresponding conductive features of the starting lead frame during the electronic device packaging operation. Additionally, the use of metal pillars (e.g., vias) 116 facilitates a lateral reduction in the size of the semiconductor die 122 by enabling the inclusion of more terminals in a given area compared to larger solder ball terminals.

[0020] Furthermore, in one example, the solder cap 118 of the conductive terminal is formed by the solder ball drop process further described below, which facilitates cost-effective manufacturing compared to plated solder caps. In this example or another example, the solder cap 118 includes copper (Cu), tin (Sn), and silver (Ag) (e.g., sometimes referred to as "SAC" solder). In contrast, the plated solder method cannot provide solder containing copper. In the illustrated example, the solder ball drop manufacturing of the solder cap 118 provides a more uniform solder material composition than the plated solder method. Additionally, the ball drop solder cap 118 has better electromigration performance and is thus convenient for use in higher voltage circuit and system applications, especially in combination with high-voltage or medium-voltage transistors or other power conversion components (e.g., GaN transistors, etc.) of the semiconductor die 122. In one example, the solder cap 118 includes SAC305 / 396 solder having a non-zero copper composition as well as tin and silver, while the plated solder has little or no copper in the solder (especially in the topmost portion after being soldered to the main structure).

[0021] Additionally, the example conductive terminal structure of this example does not include an intervening separate copper layer (e.g., sometimes referred to as a "copper over anything (COA) layer"), where the bottom side 117 of the terminal (the metal pillar 116 with or without a seed layer 114 alone) contacts the top side 111 of the conductive feature 110 to provide a low-profile compact terminal structure for power delivery and other small form factor system applications, such as Figure 1A the example system 130.

[0022] Also refer to Figure 2-16 , Figure 2 which shows a method 200 of manufacturing an electronic device, Figure 3-11 shows a wafer processed according to the method of Figure 2 to form the conductive terminals described above, and Figure 12-16 shows the semiconductor die 122 separated from the starting wafer and encapsulated in one example to produce Figure 1A the packaged electronic device 100.

[0023] Method 200 begins at Figure 2202 therein, where the wafer has previously undergone various manufacturing steps to form one or more electronic components in each unit area of the starting wafer. In one example, the wafer includes a gallium nitride (GaN) semiconductor surface layer 106. In Figure 2 202 therein forms a single-level or multi-level metallization structure having one or more upper or top-level conductive features in each unit area. Figure 3 Shows an example where a metallization process 300 is performed on the processed wafer 102. The metallization process 300 forms the metallization structure 108 described above, including one or more conductive metal trace features, via features (not shown), and one or more intervening dielectric material levels. Process 300 and Figure 3 includes forming an aluminum conductive feature 110 (e.g., aluminum) having a top side 111, as described above in connection with Figure 1 described.

[0024] The example illustrated also includes forming one or more protective layers, such as a polyimide (PI) layer, in Figure 2 204. Figure 4 and 4A Shows an example where a process 400 is performed to form a polyimide layer 112 that extends over the top side of the metallization structure 108, including covering the top side 111 of the conductive metal feature 110. In one example, process 400 includes blanket polyamide deposition to initially form the polyimide layer 112, as shown in Figure 4 shown. In this example, process 400 also includes a patterning operation to form openings in the polyimide layer 112 that expose a portion of the top side 111 of the conductive feature 110, as shown in Figure 4A shown.

[0025] Method 200 continues in Figure 2 206 - 214 to form conductive metal terminals that contact the exposed portions of the conductive features 110 of the metallization structure 108. The example illustrated begins at 206 with copper seed layer deposition. Figure 5 Shows an example where a sputtering or other deposition process 500 is performed to form an initial copper seed layer 114 that extends over the top side of the polyimide layer 112. In this example, the copper seed layer also extends over the patterned sidewalls of the openings in the polyimide layer 112 and onto the exposed portions of the top side 111 of the conductive features 110 of the metallization structure 108. In one example, the seed layer deposition process 500 is a chuck deposition process that deposits the copper seed layer 114, e.g., including an initial titanium layer of about or a titanium-tungsten layer of about and a copper layer of about .

[0026] InFigure 2 In 208, the illustrated example continues to form and pattern a mask having openings that expose a portion of the seed layer 114 above the top-level conductive features 110 in each unit area of the processed wafer. Figure 6 and 6A shows an example where a process 600 of depositing a plating mask layer 602 on the top side of the wafer is performed. In one example, the mask 602 is a photoresist layer (e.g., CE7000). In another example, any suitable non-conductive mask layer material can be used to facilitate subsequent electroplating processes. The mask layer 602 initially covers the entire copper seed layer 114, including the seed layer 114 on the conductive features 110 in the opening of the polyimide layer 112, as Figure 6 shown in. Process 600 continues in Figure 6A where the mask layer 602 is patterned to create openings in each intended terminal area of each unit area of the processed wafer, the openings exposing the copper seed layer 114 in the opening of the polyimide layer 112.

[0027] Method 200 continues in Figure 2 at 210 where electroplating is performed to form metal pillars 116 (e.g., via pillars) above a first portion of the copper seed layer 114. Figure 7 shows an example where an electroplating process 700 of forming metal pillars 116 in the openings of the plating mask 602 is performed. In one example, the electroplating process 700 continues until the height of the conductive metal pillars 116 exceeds the desired final terminal height, e.g., about 35 to 50 μm, where the additional thickness typically corresponds to the thickness of the copper seed layer 114. This allows subsequent copper etching to remove the remaining portion of the copper seed layer 114, resulting in the desired final height of the metal pillars 116 for a given electronic device design.

[0028] Then, in Figure 2 at 212 the plating mask layer is removed. Figure 8 shows an example where a photoresist stripping or cleaning process 800 of removing the remaining portion of the plating mask is performed.

[0029] Method 200 continues in Figure 2 at 214 with seed layer etching. Figure 9 shows an example where an etching process 900 of etching the exposed portion of the copper seed layer 114 and the metal pillars 116 is performed. The etching process 900 is performed until the exposed first portion of the copper seed layer 114 is removed from the top side of the polyimide layer, and the process 900 can remove a corresponding amount of the plated metal pillars 116 while retaining the first portion of the copper seed layer 114 below the metal pillars 116, including the bottom side 117 of the metal terminal structure.

[0030] Method 200 continues at 216, where solder caps 118 are formed along the top side or tip of the metal pillars 116 in each unit area of the processed wafer. At Figure 2 in 216, a solder cap is formed on the top side of the metal pillar 116 using a solder ball dropping process. Figure 10 And 10A shows an example where a solder ball dropping process 1000 of dropping solder balls 118 on the top side of the illustrated metal pillar 116 is performed using any suitable processing techniques and equipment (not shown). In one example, the solder balls comprise copper, tin, and silver. Each dropped solder ball 118 is initially dropped from a dispenser (not shown) ( Figure 10 ), and lands on one side of the metal pillar 116 ( Figure 10A ).

[0031] At Figure 2 in 218, the formation of the solder cap continues with a thermal solder reflow process. Figure 11 shows an example where a thermal reflow process 1100 of reflowing the solder cap 118 on the top side of the metal pillar 116 is performed.

[0032] Method 200 continues at Figure 2 in 220 to 228 with die separation and packaging operations. At 220, a die separation process is performed to separate individual processed semiconductor dies 122 from the processed wafer 102. Figure 12 And 12A shows an example where individual die regions 122 of the wafer 102 are separated from each other along the Figure 12 lines 1202 shown in. In one example, laser scribing is used, where a laser (not shown) is translated along the scribe lanes between adjacent rows and columns of the unit regions 122 along one side of the wafer 102 (e.g., in one example, from the bottom side or back side). Laser scribing creates cracks and fissures in the wafer 102, and the wafer 102 is mounted on a carrier or tape structure. Then, as Figure 12A shown in, the tape is radially outwardly stretched to separate the individual processed semiconductor dies 122 from each other and from the starting wafer structure, where each individual semiconductor die 122 includes one or more of the metal pillars 116 and associated solder caps 118, as described and depicted above.

[0033] Then, at Figure 2 in 222 to 228, the separated semiconductor dies 122 are used as components in a packaging operation to produce a packaged electronic device 100. In the illustrated example, the semiconductor dies 122 are flip-chip bonded (e.g., soldered) to a substrate at Figure 2 in 222 and 224. Figure 13Shows an example where a flip-chip die bonding process 1300 is performed, which bonds the metal pillars 116 of individual semiconductor dies 122 to corresponding top-side conductive metal features on the upper level of a starting multi-level package substrate 120 in the form of a panel array having rows and columns of individual unit areas 1301. In one example, the die bonding process 1300 uses an automated pick-and-place device (not shown) that places the individual semiconductor dies 122 in the corresponding unit areas 1301 of the panel array.

[0034] Method 200 continues at Figure 2 224, where the solder caps 118 of the corresponding die terminals are reflowed to form solder connections between the die terminals (e.g., metal pillars 116) and the associated conductive features along the top side of the multi-level package substrate 100 in each unit area 1301 of the panel array structure. Figure 14 Shows an example where a thermal reflow process 1400 is performed, which reflows the solder caps 118 at a suitable temperature (e.g., approximately 240 °C) for a sufficient amount of time to reflow the solder and form solder joints that electrically and mechanically interconnect the semiconductor die 122 with the corresponding unit areas 1301 of the multi-level package substrate 120.

[0035] At Figure 2 226, method 200 continues with a molding process. Figure 15 Shows an example where a molding process 1500 is performed to form a molded package structure 124 that surrounds the semiconductor chip die and extends to the exposed top side of the multi-level package substrate 120. In the illustrated example, a single mold cavity can be used to create an integral molded structure 124 in all unit areas 1301 of the panel array structure. In another embodiment (not shown), multiple cavities can be used, each containing one or more of the unit areas 1301.

[0036] At Figure 2 228, method 200 includes a package separation process to separate the individual packaged electronic devices 100 from the panel array structure. Figure 16 Shows an example where a die separation process 1600 is performed to separate the individual packaged electronic devices along a line 1602 between adjacent unit areas 1301. In one example, the die separation process 1600 includes a cutting operation using any suitable technique and equipment (not shown), such as sawing, laser cutting, etching, etc., to produce the multiple examples of the packaged electronic devices 100 described and illustrated above in connection with Figure 1 and 1A The individual electronic devices 100 can then be mounted in a host system, such as Figure 1A system 1300 in

[0037] Within the scope of the claims, modifications are possible in the described examples, and other embodiments are possible.

Claims

1. An electronic device, comprising: a semiconductor die having a semiconductor surface layer; a metallization structure on one side of the semiconductor surface layer and comprising conductive features; a conductive terminal having a metal post, the conductive terminal having a first side contacting one side of the conductive feature; as well as A solder cap is on the second side of the conductive terminal. The electronic device of claim 1 , wherein the metal pillar comprises copper.

3. The electronic device of claim 2, wherein the solder cap comprises copper, tin, and silver. The electronic device of claim 2 , wherein the conductive features of the metallization structure comprise aluminum.

5. The electronic device of claim 2, wherein the conductive terminal comprises a copper layer extending between the metal post and the conductive feature of the metallization structure. The electronic device of claim 1 , wherein the solder cap comprises copper, tin, and silver.

7. The electronic device of claim 1, wherein the conductive features of the metallization structure comprise aluminum.

8. The electronic device of claim 1, wherein the conductive terminal comprises a copper layer extending between the metal post and the conductive feature of the metallization structure.

9. The electronic device of claim 1, wherein the semiconductor surface layer comprises gallium nitride.

10. The electronic device of claim 1, further comprising a polyimide layer on a portion of the conductive feature of the metallization structure, the polyimide layer contacting a portion of the metal post.

11. The electronic device of claim 1, wherein the second side of the conductive terminal is soldered to a lead frame or a substrate.

12. A system comprising: Circuit boards; as well as An electronic device attached to the circuit board and comprising: Lead frame or substrate; a semiconductor die having a semiconductor surface layer; a metallization structure on one side of the semiconductor surface layer and comprising conductive features; a conductive terminal having a metal post, a first side, and an opposing second side, the first side of the conductive terminal contacting the first side of the conductive feature; and a solder cap on a second side of the conductive terminal; The second side of the conductive terminal is soldered to the lead frame or substrate, and the lead frame or substrate is electrically connected to the circuit board.

13. The system of claim 12, wherein the solder cap comprises copper, tin, and silver.

14. The system of claim 12, wherein the conductive features of the metallization structure comprise aluminum.

15. The system of claim 12, wherein the conductive terminal comprises a copper layer extending between the metal post and the conductive feature of the metallization structure.

16. A method of manufacturing an electronic device, the method comprising: forming a copper layer on a portion of a conductive feature of a metallization structure of the wafer; performing an electroplating process, the electroplating process forming a metal post on the first portion of the copper layer; etching a second portion of the copper layer; performing a solder ball dropping process, the solder ball dropping process forming a solder cap on one side of the metal pillar; as well as Dies including the metal pillars and the solder caps are separated from the wafer. The method of claim 16 , wherein the solder cap comprises copper, tin, and silver. The method of claim 16 , wherein the metal pillar comprises copper.

19. The method of claim 16, wherein the wafer comprises a gallium nitride semiconductor surface layer.

20. The method of claim 16, wherein the conductive features of the metallization structure comprise aluminum.

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