Support plate mother board, support plate, preparation method of support plate mother board and chip packaging structure

Abstract

The invention provides a carrier mother board, a carrier and a preparation method thereof, and a chip packaging structure. The carrier comprises a substrate, a first conductive layer, a second conductive layer and a conductive filling layer. The substrate includes a through hole. The first conductive layer covers a sidewall of the via. The second conductive layer is located on the side, away from the side wall of the through hole, of the first conductive layer and covers at least part of the first conductive layer, and the thickness of at least part of the second conductive layer is larger than that of the first conductive layer. The conductive filling layer is located on the side, away from the side wall of the through hole, of the second conductive layer and fills the through hole. In the carrier plate, the first conductive layer with good coverage is arranged to cover the side wall of the through hole with high aspect ratio, and the second conductive layer with good conductivity is arranged to improve the long-range conductivity of the surface of the large-size substrate and the uniformity of large-area electroplating in the process of forming the conductive filling layer; therefore, the filling quality of the conductive filling layer of the through hole with the high aspect ratio on the substrate is improved, and the risks of cavities and stripping problems of the conductive filling layer in the carrier plate are reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to a carrier motherboard, a carrier and a preparation method thereof, and a chip packaging structure. Background Art

[0002] With the demand for high performance of semiconductor chip (Integrated Circuit, IC) packaging, the substrate in semiconductor packaging, as the key medium for realizing high-density interface lead-out of IC and docking with printed circuit board (PCB), faces higher requirements for connection line density and substrate size. To this end, through-glass-via technology (TGV) came into being. It replaces traditional organic substrates by realizing electrical connection and signal transmission on the upper and lower surfaces of substrates such as glass substrates, and has become a key technology for realizing high functional density integration of chips.

[0003] In TGV technology, after etching a hole with a high aspect ratio on a glass substrate, it is necessary to fill the hole with a conductive material to achieve vertical electrical connection between the upper and lower surfaces of the glass substrate. Therefore, how to improve the filling quality of the conductive material in the deep hole has become the key point of TGV technology. Summary of the invention

[0004] The present disclosure provides a carrier motherboard, a carrier and a method for preparing the same, and a chip packaging structure. By arranging a first conductive layer and a second conductive layer of different thicknesses on the side walls of a through hole on a substrate of the carrier, the filling quality of a conductive filling layer and the bonding strength with the side walls of the through hole are improved, thereby reducing the risk of voids occurring when filling the conductive filling layer and the risk of peeling of the conductive filling layer.

[0005] The first aspect of the present disclosure provides a carrier motherboard, which includes a substrate, a first conductive layer, a second conductive layer and a conductive filling layer. An opening is formed on one side surface of the substrate. The first conductive layer covers the substrate surface and the inner wall of the opening. The second conductive layer is located on the side of the first conductive layer away from the substrate surface or the inner wall of the opening, and covers at least part of the first conductive layer, and the thickness of at least part of the second conductive layer on the first conductive layer is greater than the thickness of the first conductive layer; the conductive filling layer is located on the side of the second conductive layer away from the side wall of the opening, and fills the opening.

[0006] In the above scheme, the cooperation between the first conductive layer and the second conductive layer in the opening of the carrier motherboard can not only increase the bonding strength between the second conductive layer and the inner wall of the opening, but also make up for the poor covering effect of the second conductive layer, thereby improving the filling effect of the filling layer, i.e., the conductive filling layer, filled into the opening in the subsequent process, while reducing the risk of the conductive filling layer peeling off from the side wall of the opening.

[0007] In a specific embodiment of the first aspect of the present disclosure, the first conductive layer covers one side surface of the substrate, and the thickness of the first conductive layer is uniformly distributed.

[0008] Optionally, the second conductive layer covers one side of the surface of the first conductive layer facing away from the substrate, the thickness of the second conductive layer is uniformly distributed on one side surface of the substrate, and the thickness of the second conductive layer at the opening of the opening is greater than the thickness of the second conductive layer at the opening away from the opening.

[0009] Optionally, the thickness of the second conductive layer on one side surface of the substrate is greater than the thickness of the first conductive layer on one side surface of the substrate.

[0010] Optionally, the thickness of the second conductive layer at the opening of the opening is greater than the thickness of the first conductive layer at the opening of the opening.

[0011] Optionally, the second conductive layer includes a uniform portion, a gradient portion, and a transition portion. The uniform portion is located on one side surface of the substrate, the gradient portion is located on the inner wall of the opening, the transition portion connects the uniform portion and the gradient portion, and the transition portion has an arc-shaped transition surface.

[0012] Optionally, the opening is a blind hole, and the thickness of the second conductive layer gradually decreases in the direction from the opening of the blind hole to the bottom wall of the blind hole.

[0013] Optionally, it further includes at least one adhesion layer. The adhesion layer is located between the first conductive layer and the substrate, and the adhesion layer covers one side surface of the substrate and the inner wall of the opening.

[0014] Optionally, the thickness of the adhesion layer is uniformly distributed.

[0015] Optionally, the density of the adhesion layer is greater than the density of the second conductive layer.

[0016] The second aspect of the present disclosure provides a carrier plate, which includes a substrate, a first conductive layer, a second conductive layer, and a conductive filling layer. The substrate includes a through hole. The first conductive layer covers the side wall of the through hole, and the thickness of the first conductive layer is uniformly distributed. The second conductive layer is located on one side of the surface of the first conductive layer facing away from the substrate or the inner wall of the opening, and covers at least part of the first conductive layer. The thickness of at least part of the second conductive layer is greater than the thickness of the first conductive layer; the conductive filling layer is located on one side of the second conductive layer facing away from the side wall of the through hole, and fills the through hole.

[0017] In the above solution, the first conductive layer with uniform thickness can not only enhance the bonding strength between it and the sidewall of the through hole, but also provide a good interface for the formation of the second conductive layer, improving the quality of the second conductive layer. In addition, the first conductive layer can completely cover the sidewall of the through hole to improve the continuity of the electroplating seed layer during the formation of the conductive filling layer, increasing the effect of electroplating metal filling the hole. At the same time, the thicker second conductive layer, on the one hand, has a strong bonding force with the first conductive layer, which can reduce the risk of peeling of the subsequently formed conductive filling layer. On the other hand, it has good electrical conductivity, which can improve the filling quality of the subsequently formed conductive filling layer and reduce the risk of voids appearing during the filling of the above conductive filling layer.

[0018] In a specific implementation manner of the second aspect of the present disclosure, the substrate includes a first surface and a second surface arranged opposite to each other. The through hole includes a first opening located on the first surface and a second opening located on the second surface. The thickness of the second conductive layer at the first opening is greater than the thickness at the second opening of the second conductive layer.

[0019] In the above solution, the thickness change of the second conductive layer can change the electric field distribution during the filling process of the subsequently formed conductive filling layer, improving the uniformity of the electric field distribution and the regional consistency of the electroplating rate during the filling process, so as to ensure that the hole electroplating filling speeds in different regions of the substrate are consistent, and improving the hole filling quality, that is, the uniformity of the conductive filling layer.

[0020] Optionally, the thickness of the second conductive layer gradually decreases in the direction from the first opening to the second opening. In this way, the second conductive layer can more effectively improve the filling quality of the conductive filling layer.

[0021] Optionally, the second conductive layer covers a part of the first conductive layer.

[0022] Optionally, the thickness of the second conductive layer at the first opening is greater than the thickness of the first conductive layer at the first opening.

[0023] Optionally, the density of the first conductive layer is greater than the density of the second conductive layer. In this way, the risk of peeling of the conductive filling layer from the sidewall of the through hole can be effectively reduced.

[0024] Optionally, the carrier plate further includes at least one adhesion layer. The adhesion layer is located between the first conductive layer and the sidewall of the through hole, and the adhesion layer covers the sidewall of the through hole. The adhesion layer is used to more effectively enhance the bonding strength between the first conductive layer and the sidewall of the through hole.

[0025] Optionally, the thickness of the adhesion layer is uniformly distributed. In this way, the bonding strength between the first conductive layer and the sidewall of the through hole is effectively increased.

[0026] Optionally, the density of the adhesion layer is greater than the density of the second conductive layer.

[0027] Optionally, the adhesion layer is at least one of a titanium metal layer, a titanium nitride layer, a chromium metal layer, a ruthenium metal layer, an aluminum oxide layer, a silicon oxide layer, a silicon nitride layer, a tantalum metal layer, or a tantalum nitride metal layer.

[0028] Optionally, the first conductive layer is any one of a titanium metal layer, a chromium metal layer, an aluminum metal layer, a copper metal layer, a nickel metal layer, a tungsten metal layer, a tantalum metal layer, a ruthenium metal layer, a palladium metal layer, or a platinum metal layer.

[0029] Optionally, the second conductive layer is one of a copper metal layer or a nickel metal layer.

[0030] Optionally, the substrate is a glass substrate.

[0031] Optionally, the carrier plate further includes metal contact points, which include a first metal contact point and a second metal contact point. The first metal contact point is located on the first surface and is in direct contact with one surface of the conductive filling layer exposed by the first opening, and the second metal contact point is located on the second surface and is in direct contact with the other surface of the conductive filling layer exposed by the second opening.

[0032] In the above solution, the metal contact points in the carrier plate can not only achieve electrical connection, specifically connect different circuit elements or chip achievements, and realize functions such as signal transmission and power supply, but also increase the reliability of electrical connection compared to only connecting through the conductive filling layer.

[0033] The third aspect of the present disclosure provides a method for manufacturing a carrier plate, which includes: forming an opening on one side surface of a substrate, forming a first conductive layer by atomic deposition, the first conductive layer covering the inner wall of the opening, forming a second conductive layer by magnetron sputtering, the second conductive layer covering at least part of the inner surface of the first conductive layer, and at least part of the thickness of the second conductive layer being greater than the thickness of the first conductive layer; electroplating to form a conductive filling layer, and the conductive filling layer filling the opening.

[0034] In the above solution, for the carrier plate prepared by this method, the first conductive layer in the opening of the carrier plate can not only enhance the bonding strength between it and the side wall of the through hole, but also provide a good interface for the formation of the second conductive layer. In addition, it can cooperate with the second conductive layer to improve the continuity of the conductive area in the opening, improve the uniformity of the conductive filling layer in the subsequent process, and at the same time reduce the risk of its peeling.

[0035] In a specific embodiment of the third aspect of the present disclosure, in the step of forming the first conductive layer by atomic deposition, the formed first conductive layer has a uniform thickness distribution and covers one side surface of the substrate.

[0036] In the above solution, the density of the first conductive layer formed by the process of forming the first conductive layer using atomic deposition is greater than that of the second conductive layer, further reducing the risk of the conductive filling layer peeling off from the side wall of the opening.

[0037] Optionally, the opening is a blind hole, and the ratio of the thickness difference between the thickness of the first conductive layer at the opening of the blind hole and the thickness of the first conductive layer on the bottom wall of the blind hole to the thickness of the first conductive layer on the bottom wall of the blind hole is less than a preset value, and the preset value is less than or equal to 20%.

[0038] Optionally, the preset value is less than or equal to 10%.

[0039] Optionally, the thickness of the first conductive layer on one side surface of the substrate is 10 nm - 200 nm.

[0040] Optionally, the thickness of the first conductive layer at the opening of the blind hole is less than the thickness of the second conductive layer at the opening of the blind hole.

[0041] In a specific embodiment of the third aspect of the present disclosure, in the step of forming the second conductive layer using magnetron sputtering, the second conductive layer covers one side of the surface of the first conductive layer facing away from the substrate, and the thickness of the second conductive layer at the opening of the opening is greater than the thickness of the second conductive layer at a position far from the opening of the opening.

[0042] In the above solution, the process of forming the second conductive layer using magnetron sputtering is relatively mature, and it is easy to control the thickness change of the second conductive layer on the side wall of the opening, saving production costs.

[0043] Optionally, the opening is a blind hole, and the thickness of the second conductive layer gradually decreases in the direction from the opening of the blind hole to the bottom wall of the blind hole.

[0044] Optionally, the second conductive layer covers a part of the first conductive layer.

[0045] Optionally, the thickness of the second conductive layer on one side surface of the substrate is 50 nm - 2000 nm.

[0046] Optionally, the second conductive layer includes a uniform part, a gradient part, and a transition part. The uniform part is located on one side surface of the substrate, the gradient part is located on the inner wall of the opening, the transition part connects the uniform part and the gradient part, and the transition part has an arc-shaped transition surface.

[0047] In a specific embodiment of the second aspect of the present disclosure, before forming the first conductive layer using atomic deposition, it further includes: forming at least one adhesion layer on the inner wall of the opening using atomic deposition, and the adhesion layer covers the inner wall of the opening.

[0048] Optionally, the thickness of the adhesion layer is evenly distributed and covers one side surface of the substrate.

[0049] Optionally, the density of the adhesion layer is greater than that of the second conductive layer.

[0050] Optionally, the adhesion layer is at least one of a titanium metal layer, a titanium nitride layer, a chromium metal layer, a ruthenium metal layer, an aluminum oxide layer, a silicon oxide layer, a silicon nitride layer, a tantalum metal layer, or a tantalum nitride metal layer.

[0051] Optionally, the first conductive layer is any one of a titanium metal layer, a chromium metal layer, an aluminum metal layer, a copper metal layer, a nickel metal layer, a tungsten metal layer, a tantalum metal layer, a ruthenium metal layer, a palladium metal layer, or a platinum metal layer.

[0052] Optionally, the second conductive layer is one of a copper metal layer or a nickel metal layer.

[0053] Optionally, the substrate is a glass substrate.

[0054] In a specific embodiment of the third aspect of the present disclosure, the opening is a blind hole, and the manufacturing method further includes removing the film layer structure on one side surface of the substrate to obtain the first surface of the substrate, processing the other side surface of the substrate corresponding to the bottom wall of the blind hole, removing a part of the bottom wall of the blind hole to form a through hole filled with a conductive filling layer, and obtaining the second surface of the substrate.

[0055] Optionally, the manufacturing method further includes forming a first metal contact point on the first surface, the first metal contact point being in direct contact with one surface of the conductive filling layer exposed on the first surface, and forming a second metal contact point on the second surface, the second metal contact point being in direct contact with the other surface of the conductive filling layer exposed on the second surface.

[0056] In a specific embodiment of the third aspect of the present disclosure, the opening is a through hole, and the manufacturing method further includes removing the film layer structure on one side surface of the substrate to obtain the first surface of the substrate, processing the other side surface of the substrate corresponding to the other opening of the through hole, removing a part of the substrate and the corresponding film layer to form a second surface, the second surface being a smooth plane, so that the thickness of the second conductive layer in the through hole near the first surface is less than the thickness of the second conductive layer near the second surface.

[0057] Optionally, the thickness of the second conductive layer gradually decreases in the direction from the first surface to the second surface.

[0058] Optionally, the manufacturing method further includes forming a first metal contact point on the first surface, the first metal contact point being in direct contact with one surface of the conductive filling layer exposed on the first surface, and forming a second metal contact point on the second surface, the second metal contact point being in direct contact with the other surface of the conductive filling layer exposed on the second surface.

[0059] The fourth aspect of the present disclosure provides a chip packaging structure, which includes a carrier board according to any one of the second aspect above or a carrier board prepared by the preparation method according to any one of the third aspect above. Description of the Drawings

[0060] Figure 1a It is a schematic plan view of a carrier board mother board or a carrier board provided by an embodiment of the present disclosure.

[0061] Figure 1b Provided by an embodiment of the present disclosure Figure 1a It is a schematic cross-sectional view of a carrier board mother board or a carrier board provided by an embodiment of the present disclosure in the M1N1 direction.

[0062] Figure 2 Provided by an embodiment of the present disclosure Figure 1b It is an enlarged view of part A in the cross-sectional view of a carrier board mother board or a carrier board provided by an embodiment of the present disclosure.

[0063] Figure 3 Provided by an embodiment of the present disclosure Figure 1b It is an enlarged view of part A in the cross-sectional view of another carrier board mother board provided by an embodiment of the present disclosure.

[0064] Figure 4 Provided by an embodiment of the present disclosure Figure 1b It is an enlarged view of part A in the cross-sectional view of another carrier board mother board provided by an embodiment of the present disclosure.

[0065] Figure 5 Provided by an embodiment of the present disclosure Figure 1b It is an enlarged view of part A in the cross-sectional view of another carrier board mother board provided by an embodiment of the present disclosure.

[0066] Figure 6 Provided by an embodiment of the present disclosure Figure 1b It is an enlarged view of part A in the cross-sectional view of a carrier board provided by an embodiment of the present disclosure.

[0067] Figure 7 Provided by an embodiment of the present disclosure Figure 1b It is an enlarged view of part A in the cross-sectional view of another carrier board provided by an embodiment of the present disclosure.

[0068] Figure 8 Provided by an embodiment of the present disclosure Figure 1b It is an enlarged view of part A in the cross-sectional view of another carrier board provided by an embodiment of the present disclosure.

[0069] Figure 9 Provided by an embodiment of the present disclosure Figure 1b It is an enlarged view of part A in the cross-sectional view of another carrier board provided by an embodiment of the present disclosure.

[0070] Figure 10 Provided by an embodiment of the present disclosure Figure 1b It is an enlarged view of part A in the cross-sectional view of another carrier board provided by an embodiment of the present disclosure.

[0071] Figure 11 Another enlarged view of portion A in the cross-sectional schematic diagram of another carrier board provided by an embodiment of the present disclosure Figure 1b in the cross-sectional schematic diagram of another carrier board provided by an embodiment of the present disclosure

[0072] Figure 12 Another enlarged view of portion A in the cross-sectional schematic diagram of another carrier board provided by an embodiment of the present disclosure Figure 1b in the cross-sectional schematic diagram of another carrier board provided by an embodiment of the present disclosure

[0073] Figure 13 Another cross-sectional schematic diagram of another carrier board in the M1N1 direction provided by an embodiment of the present disclosure Figure 1a in the cross-sectional schematic diagram of another carrier board provided by an embodiment of the present disclosure

[0074] Figure 14 Schematic diagram of a method for manufacturing a carrier board provided by an embodiment of the present disclosure

[0075] Figure 15 Partial cross-sectional schematic diagram of an intermediate product obtained by a method for manufacturing a carrier board provided by an embodiment of the present disclosure

[0076] Figure 16 Schematic flow diagram of a method for manufacturing a carrier board provided by an embodiment of the present disclosure

[0077] Figure 17 Schematic flow diagram of another method for manufacturing a carrier board provided by an embodiment of the present disclosure

[0078] Figure 18 Partial cross-sectional schematic diagram of an intermediate product obtained by another method for manufacturing a carrier board provided by an embodiment of the present disclosure

[0079] Figure 19 Partial schematic flow diagram of a method for manufacturing a carrier board provided by an embodiment of the present disclosure

[0080] Figure 20 Partial schematic flow diagram of another method for manufacturing a carrier board provided by an embodiment of the present disclosure

[0081] Figure 21 Partial schematic flow diagram of another method for manufacturing a carrier board provided by an embodiment of the present disclosure

[0082] Reference numerals:

[0083] 100 - Substrate; 100A - TGV structure; 110 - Through - hole; 111 - Side wall of the through - hole; 112 - First opening; 113 - Second opening; 120 - First surface; 130 - Second surface; 140 - Opening; 140a - Inner wall of the opening; 140b - Blind hole; 141 - Side wall of the blind hole; 142 - Bottom wall of the blind hole; 200 - First conductive layer; 300 - Second conductive layer; 310 - Uniform part; 320 - Gradient part; 330 - Transition part; 400 - Conductive filling layer; 500 - Adhesion layer; 510 - Inner adhesion layer; 520 - Outer adhesion layer; 600 - Metal contact point; 610 - First metal contact point; 620 - Second metal contact point. Detailed implementation mode

[0084] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure.

[0085] The TGV technology is to drill vertical through - holes, that is, holes with a high aspect ratio, on a carrier board such as a glass carrier board, and then fill the through - holes with a conductive material (usually a metal, such as copper). For example, it can be achieved by electroplating, so as to realize the vertical electrical connection between different layers of the chip. These vertical electrical connections can replace traditional organic carrier boards, improve the interconnection wire density and signal transmission speed, and reduce signal delay and high - frequency loss. Therefore, the TGV technology is a key technology for realizing three - dimensional integration of chips.

[0086] In the actual process, when filling the through - holes with a high aspect ratio with a conductive material, it is necessary to ensure uniform deposition of the conductive material in the through - holes. For example, when using the electroplating filling method, the phenomenon of incomplete filling at the bottom of the hole, that is, the so - called "void" problem, is likely to occur. These voids will seriously affect the electrical performance of the TGV structure, such as increasing resistance and reducing the reliability of the TGV structure. At the same time, the difference in the coefficient of thermal expansion between the filling material and the material of the glass carrier board, such as glass, will generate stress in the TGV structure. During the manufacturing, packaging, and use of the chip, temperature changes are inevitable. This thermal stress may cause damage to the TGV structure, such as cracks at the interface between the TGV structure and the glass carrier board, such as glass, or the filling material peeling off from the hole wall, thereby affecting the overall performance and reliability of the chip.

[0087] In view of this, embodiments of the present disclosure provide a carrier mother board, a carrier, a preparation method thereof, and a chip packaging structure to at least solve the above technical problems. The carrier mother board includes a substrate, a first conductive layer, and a second conductive layer. An opening is formed by recessing one side surface of the substrate. The first conductive layer covers the inner wall of the opening. The second conductive layer is located inside the first conductive layer and covers at least part of the first conductive layer, and the thickness of at least part of the second conductive layer on the first conductive layer is greater than the thickness of the first conductive layer. In this way, the first conductive layer and the second conductive layer in the opening of the carrier mother board cooperate with each other. The thicker second conductive layer has a good conductive effect. At the same time, the thinner first conductive layer covers all the inner walls of the opening, which can not only increase the bonding strength between the second conductive layer and the inner wall of the opening, but also make up for the poor covering effect of the second conductive layer, which affects the electric field distribution when filling the subsequent conductive filling layer. Therefore, the structure of the carrier mother board improves the filling effect of the filling layer, that is, the conductive filling layer, filled into the opening in the subsequent process, and at the same time reduces the risk of the conductive filling layer peeling off from the side wall of the opening.

[0088] Next, the carrier mother board, the carrier, the preparation method thereof, and the chip packaging structure according to at least one embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0089] Exemplarily, as Figure 1a , Figure 1b and Figure 2 shown, the carrier mother board includes a substrate 100, a first conductive layer 200, and a second conductive layer 300. An opening 140 is formed by recessing one side surface of the substrate 100. The substrate 100 is a glass substrate, and the carrier mother board can also be called a glass carrier mother board. Specifically, the glass substrate not only has advantages in terms of material properties such as high modulus, high flatness, wide thermal expansion coefficient, and good chemical and high-temperature tolerance, but also has advantages in terms of optics and mechanics, which not only facilitates the smooth progress of the laser processing process, but also can meet the requirements of semiconductor devices for high-precision manufacturing, and avoid affecting the performance and packaging quality of the chip due to size deviation and / or damage of the carrier during chip stacking and other processes.

[0090] The first conductive layer 200 covers the inner wall of the opening 140. The second conductive layer 300 is located inside the first conductive layer 200 and covers at least part of the first conductive layer 200, and the thickness of at least part of the second conductive layer 300 on the first conductive layer 200 is greater than the thickness of the first conductive layer 200.

[0091] In the carrier mother board provided by at least one embodiment of the present disclosure, as Figure 2 and Figure 3 shown, the first conductive layer 200 covers one side surface of the substrate 100, and the thickness of the first conductive layer 200 is evenly distributed.

[0092] In the carrier motherboard provided by at least one embodiment of the present disclosure, as Figure 2 and Figure 3 shown, the second conductive layer 300 covers one side surface of the first conductive layer 200 facing away from the substrate 100. The thickness of the second conductive layer 300 is uniformly distributed on one side surface of the substrate 100, and the thickness of the second conductive layer 300 at the opening of the opening 140 is greater than the thickness of the second conductive layer 300 at the opening away from the opening 140 of the opening 140.

[0093] For example, the thickness of the second conductive layer 300 on one side surface of the substrate 100 is greater than the thickness of the first conductive layer 200 on one side surface of the substrate 100.

[0094] For example, the thickness of the second conductive layer 300 at the opening of the opening 140 is greater than the thickness of the first conductive layer 200 at the opening of the opening 140.

[0095] In the carrier motherboard provided by at least one embodiment of the present disclosure, as Figure 4 shown, the second conductive layer 300 includes a uniform portion 310, a gradient portion 320, and a transition portion 330. The uniform portion 310 is located on one side surface of the substrate 100, the gradient portion 320 is located on the inner wall of the opening 140, the transition portion 330 connects the uniform portion 310 and the gradient portion 320, and the transition portion 330 has an arc-shaped transition surface.

[0096] For example, the opening 140 is a blind hole 140b, and the thickness of the second conductive layer 300 gradually decreases in the direction from the opening of the blind hole 140b to the bottom wall 142 of the blind hole.

[0097] In the carrier motherboard provided by at least one embodiment of the present disclosure, as Figure 5 shown, the carrier motherboard further includes at least one adhesion layer 500. The adhesion layer 500 is located between the first conductive layer 200 and the substrate 100, and the adhesion layer 500 covers one side surface of the substrate 100 and the inner wall of the opening 140.

[0098] For example, the thickness of the adhesion layer 500 is uniformly distributed.

[0099] For example, the density of the adhesion layer 500 is greater than the density of the second conductive layer 300.

[0100] In the carrier motherboard provided by at least one embodiment of the present disclosure, the carrier motherboard further includes a conductive filling layer 400. The conductive filling layer 400 is located on the side of the second conductive layer 300 facing away from the first conductive layer 200 and fills the opening 140.

[0101] An embodiment of the present disclosure further provides a carrier plate, which includes a substrate, a first conductive layer, and a second conductive layer. The substrate includes a through hole, the first conductive layer covers the side wall of the through hole, and the thickness of the first conductive layer is evenly distributed. The second conductive layer is located inside the first conductive layer and covers at least part of the first conductive layer. The thickness of at least part of the second conductive layer is greater than that of the first conductive layer. In this way, a first conductive layer with a relatively thin thickness and a second conductive layer with a relatively large thickness are respectively formed on the side wall of the through hole. The relatively thin first conductive layer is well combined with the side wall of the through hole, and at the same time, it can provide a good adhesion interface for the second conductive layer, thereby reducing the risk of the conductive filling layer formed in the subsequent process peeling off from the side wall of the through hole. At the same time, the relatively thick second conductive layer serves as a transition layer, which can reduce the contact between the electroplating solution and the side wall of the through hole during the electroplating process of the above-mentioned conductive filling layer, promote the electroplating efficiency, and thus reduce the risk of void formation. Therefore, the first conductive layer and the second conductive layer formed on the side wall of the through hole, that is, the composite film layer metal conductive layer, cooperate with each other to improve the filling quality of the conductive filling layer in the TGV technology.

[0102] It should be noted that the material of the conductive filling layer can be metal.

[0103] Exemplarily, as Figure 1a 、 Figure 1b and Figure 6 shown, the carrier plate includes a substrate 100, a first conductive layer 200, and a second conductive layer 300. A through hole 110 is provided on the substrate 100. The first conductive layer 200, the second conductive layer 300, and the conductive filling layer 400 located in the through hole 110 form a TGV structure 100A.

[0104] The substrate 100 is a glass substrate, and specific reference can be made to the above embodiments for introduction, which will not be elaborated here. The substrate 100 includes a through hole 110, and the ratio of the depth to the diameter of the through hole 110 is relatively large. For example, in some advanced chip manufacturing, the aspect ratio may reach 10:1 or even higher. This design with a high aspect ratio is to achieve more vertical connections within a limited chip plane area, increasing the functional density and integration of the chip. However, it is precisely this design with a high aspect ratio of the through hole 110 that causes problems such as poor filling quality, such as voids or uneven filling, during the subsequent filling process, thereby affecting the stability and speed of signal transmission.

[0105] The first conductive layer 200 covers the side wall 111 of the through hole, and the thickness of the first conductive layer 200 is uniformly distributed, that is, the thickness difference of the first conductive layer 200 at various locations is less than 20% of the average thickness, and the thickness of the first conductive layer 200 can be considered to be uniformly distributed. The first conductive layer 200 can have good adhesion and buffering properties, not only having good adhesion with the side wall 111 of the through hole, but also alleviating the peeling problem caused by factors such as thermal stress. At the same time, the first conductive layer 200 with uniform thickness not only provides a consistent and good adhesion interface for the second conductive layer 300, but also helps to enhance the mechanical connection strength of the second conductive layer 300 and the conductive filling layer 400. The good adhesion between the two can keep the conductive filling layer 400 and the through hole 110 tightly connected, reducing the risk of damage or even peeling caused by external forces.

[0106] The second conductive layer 300 is located on the inner side of the first conductive layer 200, that is, the side away from the sidewall 111 of the through hole, and covers at least a portion of the first conductive layer 200. The thickness of at least a portion of the second conductive layer 300 is greater than the thickness of the first conductive layer 200. Figure 2 As shown, the second conductive layer 300 covers the entire first conductive layer 200, and the thickness of the second conductive layer 300 is greater than the thickness of the first conductive layer 200. First, there is a stronger bonding force between the thicker second conductive layer 300 and the relatively thinner first conductive layer 200, which can further improve the peeling problem. Secondly, in the subsequent process of preparing the conductive filling layer 400, the thicker second conductive layer 300 can not only reduce the resistance and improve the uniformity of current distribution, but also serve as a transition layer to improve the subsequent electroplating process conditions such as the electric field distribution, the contact between the electroplating solution and the side wall 111 of the through hole, and provide a relatively uniform electroplating starting surface, which is conducive to the stable flow of the electroplating solution from top to bottom, forming a uniform conductive filling layer 400, and reducing the risk of forming voids during the electroplating process.

[0107] It should be noted that the structure of the carrier board is not limited to the above examples and Figure 1a , Figure 1b and Figure 6 The structural limitations, for example, the number of through holes 110 on the carrier, the aspect ratio of the through holes 110, and the specific thicknesses of the first conductive layer 200 and the second conductive layer 300 can be selected according to actual needs and will not be elaborated herein.

[0108] Based on the thickness relationship between the first conductive layer 200 and the second conductive layer 300 in the above embodiments, the embodiment of the present disclosure further specifically defines the thickness variation of the second conductive layer 300 on the sidewall of the through hole 110 .

[0109] For example, in the carrier provided by at least one embodiment of the present disclosure, Figure 7As shown, the substrate 100 includes a first surface 120 and a second surface 130 that are oppositely arranged, for example, oppositely arranged along the length direction of the substrate 100. The through hole 110 includes a first opening 112 located on the first surface 120 and a second opening 113 located on the second surface 130. The thickness of the second conductive layer 300 at the first opening 112 is greater than the thickness of the second conductive layer 300 at the second opening 113, that is, the thickness of the second conductive layer 300 on the sidewall 111 of the through hole becomes smaller in the direction from the first opening 112 to the second opening 113.

[0110] In this way, the second conductive layer 300 in this form can be deposited by using a conventional magnetron sputtering device, without using an expensive device dedicated to deep hole coating, reducing the requirements for the device. The thickness of the second conductive layer 300 is relatively large. During the formation of the subsequent conductive filling layer 400, that is, during the electroplating process, the distribution of the electric field lines has an important influence on the deposition of metal ions in the electroplating solution. The setting of the second conductive layer 300 makes the potential difference on the surface of the relatively large substrate 100 small, and the electric field distribution is relatively uniform. The electroplating rates of the through holes 110 at the center and edge positions of the substrate 100 that need to be filled by the conductive filling layer 400 are close, so that the metal ions in the electroplating solution are uniformly deposited on the inner walls of the through holes 110 at the center and edge positions of the substrate 100, that is, on the surface of the second conductive layer 300 facing away from the first conductive layer 200.

[0111] As Figure 8 shown, the thickness of the second conductive layer 300 gradually becomes smaller in the direction from the first opening 112 to the second opening 113. Here, the thickness of the second conductive layer 300 refers to the thickness of the second conductive layer 300 on the sidewall 111 of the through hole. In this way, when the diameter of the through hole 110 corresponding to the second conductive layer 300 gradually becomes larger, the electric field distribution can be gradually and continuously optimized during the electroplating process, preventing the problem of uneven electroplating caused by sudden changes in the electric field, that is, it is more conducive to realizing the uniformity of the subsequent formed conductive filling layer 400.

[0112] Based on the above embodiments, in the carrier board provided by at least one embodiment of the present disclosure, as Figure 9 shown, the second conductive layer 300 covers a part of the first conductive layer 200.

[0113] Based on the above embodiments, in the carrier board provided by at least one embodiment of the present disclosure, as Figure 10 shown, the thickness of the second conductive layer 300 at the first opening 112 is greater than the thickness of the first conductive layer 200 at the first opening 112.

[0114] Exemplarily, as Figure 9 and Figure 10As shown, the aspect ratio of the through-hole 110 on the substrate 100 is relatively large. The first conductive layer 200 covers the sidewall 111 of the through-hole. The second conductive layer 300 covers the surface of a part of the first conductive layer 200 facing away from the sidewall 111 of the through-hole. That is to say, in the direction from the first opening 112 to the second opening 113, the second conductive layer 300 changes from having a certain thickness to having no thickness. At this time, the thickness of the second conductive layer 300 on the sidewall 111 of the through-hole near the first opening 112 is greater than the thickness of the first conductive layer 200 on the sidewall 111 of the through-hole at the corresponding position. Near the second opening 113, as Figure 9 shown, there is no second conductive layer 300 on the surface of the first conductive layer 200 facing away from the sidewall 111 of the through-hole, or as Figure 10 shown, the corresponding thickness of the second conductive layer 300 gradually becomes zero at the second opening 113.

[0115] It should be noted that the structure of the carrier board in the embodiments of the present disclosure is not limited to the limitations in the above examples. For example, the thickness change of the second conductive layer 300 on the sidewall 111 of the through-hole may not be limited to Figure 7 shown in the figure. Specifically, multiple stepped structures can be formed, and the stepped structures on the opposite sidewalls are arranged opposite to each other or staggered. For example, the thickness change of the second conductive layer 300 on the sidewall 111 of the through-hole is not limited to Figure 8 and Figure 9 shown in the figure, and its gradually changing surface can be a wavy surface. All of the above can be adjusted according to actual requirements and process conditions, and will not be elaborated here.

[0116] In the carrier board provided in at least one embodiment of the present disclosure, the density of the first conductive layer 200 is greater than the density of the second conductive layer 300. In this way, the change range of the thermal expansion coefficient of the first conductive layer 200 is smaller, and the thermal expansion matching with the inner wall of the through-hole 110 is stronger, thereby reducing the risk of problems such as peeling and damage of the first conductive layer 200 due to stress concentration between the through-hole 110 and the first conductive layer 200 during the temperature cycle.

[0117] Based on the above embodiments, in the carrier board provided in one embodiment of the present disclosure, as Figure 11 and Figure 12 shown, the carrier board further includes at least one adhesion layer 500. The adhesion layer 500 is located between the first conductive layer 200 and the sidewall 111 of the through-hole, and the adhesion layer 500 covers the sidewall 111 of the through-hole. In this way, by forming a stable chemical bond or physical adsorption with the sidewall 111 of the through-hole, the adhesion layer 500 can strengthen the peeling of the subsequent conductive filling layer 400 from the sidewall 111 of the through-hole, thereby improving the integrity and long-term reliability of the TGV structure in the carrier board.

[0118] Exemplarily, as Figure 11As shown in the figure, the carrier board includes a substrate 100, an adhesion layer 500, a first conductive layer 200, a second conductive layer 300, and a conductive filling layer 400. The substrate 100 includes a through hole 110. The adhesion layer 500, the first conductive layer 200, and the second conductive layer 300 are sequentially covered on the side wall 111 of the through hole. The conductive filling layer 400 is located on the side of the second conductive layer 300 away from the first conductive layer 200 and fills the through hole 110. Specifically, the adhesion layer 500 is one of a titanium metal layer, a titanium nitride metal layer, a tantalum metal layer, or a tantalum nitride metal layer.

[0119] Exemplarily, as Figure 12 shown in the figure, the carrier board includes a substrate 100, an inner adhesion layer 510, an outer adhesion layer 520, a first conductive layer 200, a second conductive layer 300, and a conductive filling layer 400. The substrate 100 includes a through hole 110. The inner adhesion layer 510, the outer adhesion layer 520, the first conductive layer 200, and the second conductive layer 300 are sequentially covered on the side wall 111 of the through hole. The conductive filling layer 400 is located on the side of the second conductive layer 300 away from the first conductive layer 200 and fills the through hole 110. Specifically, the inner adhesion layer 510 is a titanium metal layer, the outer adhesion layer 520 is a titanium nitride metal layer, or the inner adhesion layer 510 is a tantalum metal layer, and the outer adhesion layer 520 is a tantalum nitride metal layer.

[0120] In the carrier board provided by at least one embodiment of the present disclosure, the thickness of the adhesion layer 500 is evenly distributed, that is, the adhesion layer 500 is evenly distributed on the side wall 111 of the through hole. If the thickness difference of the adhesion layer 500 at each place is less than 20% of the average thickness, it can be considered that the thickness of the adhesion layer 500 is evenly distributed. In this way, the adhesion layer 500 can not only improve the bonding strength between the first conductive layer 200 and the side wall 111 of the through hole, making the connection between the two more stable, but also provide a good interface for subsequent film layers such as the first conductive layer 200, thereby improving the film forming uniformity of the first conductive layer 200 and improving the quality of the carrier board.

[0121] In the carrier board provided by at least one embodiment of the present disclosure, the density of the adhesion layer 500 is greater than the density of the second conductive layer 300.

[0122] Based on the above embodiments, the present disclosure embodiments also introduce the adhesion relationship between the film layers in the through hole 110.

[0123] For example, in the carrier provided by at least one embodiment of the present disclosure, the adhesive layer 500 includes an inner adhesive layer 510 and an outer adhesive layer 520, the outer adhesive layer 520 is located on the side of the inner adhesive layer 510 away from the side wall 111 of the through hole, the adhesion between the outer adhesive layer 520 and the inner adhesive layer 510 and the adhesion between the outer adhesive layer 520 and the first conductive layer 200 are greater than the adhesion between the inner adhesive layer 510 and the first conductive layer 200, and the adhesion between the inner adhesive layer 510 and the first conductive layer 200 is greater than the adhesion between the first conductive layer 200 and the side wall 111 of the through hole, and the adhesion between the first conductive layer 200 and the side wall 111 of the through hole is greater than the adhesion between the second conductive layer 300 and the side wall 111 of the through hole. In this way, the problem of the film layer in the through hole 110 peeling off from the side wall 111 of the through hole can be effectively improved.

[0124] It should be noted that the adhesion between different film layers mentioned in the above embodiments may refer to the adhesion between two film layers per unit area.

[0125] In addition, the embodiments of the present disclosure also introduce the materials of the first conductive layer 200 , the second conductive layer 300 , and the adhesive layer 500 in the carrier.

[0126] For example, in the carrier provided in at least one embodiment of the present disclosure, the adhesion layer 500 is at least one of a titanium metal layer, a titanium nitride layer, a chromium metal layer, a ruthenium metal layer, an aluminum oxide layer, a silicon oxide layer, a silicon nitride layer, a tantalum metal layer or a tantalum nitride metal layer.

[0127] For example, in the carrier provided in at least one embodiment of the present disclosure, the first conductive layer 200 is any one of a copper metal layer, a nickel metal layer, a chromium metal layer, a tungsten metal layer, a tantalum metal layer, a ruthenium metal layer, a palladium metal layer or a platinum metal layer.

[0128] For example, in the carrier provided in at least one embodiment of the present disclosure, the second conductive layer 300 is a metal layer, such as a copper metal layer or a nickel metal layer.

[0129] Based on the above embodiments, the carrier board in the embodiments of the present disclosure may further include other structures, and the specific solutions are as follows.

[0130] For example, in the carrier provided by at least one embodiment of the present disclosure, Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12As shown, the carrier board further includes a conductive filling layer 400. For example, the conductive filling layer 400 is an electroplated copper layer located on the side of the second conductive layer 300 away from the side wall 111 of the through hole and fills the through hole 110. In this carrier board, the first conductive layer 200 completely covers the conductive layer on the side wall 111 of the through hole, which is beneficial to the uniformity of the coating formation during the electroplating process. At the same time, with the mutual cooperation between the first conductive layer 200 and the second conductive layer 300, the conductive filling layer 400 is evenly distributed in the through hole 110 and has a high bonding strength with the side wall of the through hole 110, thereby improving the stability of the electrical connection performance of the carrier board in the vertical direction and the reliability of chip packaging.

[0131] For example, in the carrier board provided in at least one embodiment of the present disclosure, as Figure 13 shown, the carrier board further includes metal contact points 600. The metal contact points 600 include a first metal contact point 610 and a second metal contact point 620. The first metal contact point 610 is located on the first surface 120 and is in direct contact with one surface of the conductive filling layer 400 exposed by the first opening 112, and the second metal contact point 620 is located on the second surface 130 and is in direct contact with the other surface of the conductive filling layer 400 exposed by the second opening 113.

[0132] The embodiment of the present disclosure provides a method for manufacturing a carrier board, as Figure 14 shown, the manufacturing method includes forming an opening 140 by recessing on one side surface of the substrate 100, forming the first conductive layer 200 by atomic deposition method. The first conductive layer 200 covers the inner wall 140a of the opening, such as the side wall 141 and the bottom wall 142 of the blind hole, forming the second conductive layer 300 by magnetron sputtering method. The second conductive layer 300 covers at least part of the inner surface of the first conductive layer 200, that is, the surface of the first conductive layer 200 away from the inner wall 140a of the opening, such as the side wall 141 of the blind hole, and the thickness of at least part of the second conductive layer 300 is greater than the thickness of the first conductive layer 200.

[0133] It should be noted that the embodiment of the present disclosure does not limit the specific parameters and operations of this manufacturing method, which can be designed according to actual needs. For example, during the process of forming the first conductive layer 200 by atomic deposition method and forming the second conductive layer 300 by magnetron sputtering method, physical shielding or the method of forming a sacrificial layer on one side surface of the substrate 100 can be used to avoid forming the first conductive layer 200 and the second conductive layer 300 on one side surface of the substrate 100 in the above steps. In addition, conventional methods can also be used to form the first conductive layer 200 and the second conductive layer 300 on one side surface of the substrate and in the opening 140 respectively. For details, reference can be made to the following embodiments, which will not be elaborated here.

[0134] For the specific distribution of the first conductive layer 200 and the second conductive layer 300, reference may be made to the above embodiments, which will not be elaborated here.

[0135] Exemplarily, as Figure 14 shown, the method for preparing the carrier board includes the following steps S100 to S300.

[0136] Step S100: Provide a substrate 100, and a through hole 140 is formed by recessing one side surface of the substrate 100.

[0137] Step S200: Form a first conductive layer 200 by atomic deposition method. The first conductive layer 200 covers the inner wall 140a of the through hole, specifically, the side wall 141 and the bottom wall 142 of the blind hole.

[0138] Step S300: Form a second conductive layer 300 by magnetron sputtering method. The second conductive layer 300 covers the inner side of the first conductive layer 200, that is, the first conductive layer 200 facing away from the inner wall 140a of the through hole. Specifically, the surface of the side wall 141 of the blind hole and the surface of the first conductive layer 200 facing away from the bottom wall 142 of the blind hole. And at least part of the thickness of the second conductive layer 300 on one side surface of the substrate 100 is greater than the thickness of the first conductive layer 200 on one side surface of the substrate 100. The thickness of the second conductive layer on the bottom wall 142 of the blind hole is less than the thickness of part of the second conductive layer on the side wall 141 of the blind hole.

[0139] In the above method for preparing the carrier board, the first conductive layer 200 processed by atomic layer deposition method can completely cover the side wall 141 of the blind hole to improve the continuity of the electroplating seed layer during the formation of the conductive filling layer 400 in the subsequent process, making up for the part not covered by the second conductive layer 300, which is beneficial to improving the uniformity of the electric field distribution during electroplating and increasing the effect of electroplating metal filling holes. At the same time, on the one hand, the thicker second conductive layer has a strong bonding force with the first conductive layer, which can reduce the risk of peeling of the above-mentioned conductive filling layer. On the other hand, the thicker second conductive layer can reduce the resistance and improve the uniformity of the distribution of the electroplating solution, thereby improving the filling quality of the conductive filling layer and reducing the risk of voids appearing during the filling of the conductive filling layer.

[0140] It should be noted that in the above preparation method, the second conductive layer 300 in step S300 can be as Figure 9 shown, covering the surface of the side of the first conductive layer 200 facing away from the substrate 100, or as Figure 10 shown, covering the surface of part of the first conductive layer 200 facing away from the inner wall 140a of the through hole, such as the side wall 111 of the through hole. Specifically, reference may be made to the above embodiments, which will not be elaborated here.

[0141] In a method for manufacturing a carrier board provided by an embodiment of the present disclosure, in step S200 where the first conductive layer 200 is formed by atomic deposition, the thickness of the formed first conductive layer 200 is evenly distributed and covers one side surface of the substrate 100. Specifically, the first conductive layer 200 formed in step S200 covers one side surface of the substrate 100 and is evenly distributed. At the same time, the first conductive layer 200 also covers the inner wall 140a of the opening and is evenly distributed. For the understanding of the uniform thickness distribution, reference can be made to the description of the above embodiments, which will not be elaborated here.

[0142] For example, the thickness of the first conductive layer 200 on one side surface of the substrate 100 is 10 nm - 200 nm. Specifically, for example, the thickness of the first conductive layer 200 on one side surface of the substrate 100 can be any one of 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, etc.

[0143] In a method for manufacturing a carrier board provided by at least one embodiment of the present disclosure, the opening 140 is a blind hole 140b. The ratio of the thickness difference between the thickness of the first conductive layer 200 at the opening of the blind hole 140b and the thickness of the first conductive layer 200 on the bottom wall 142 of the blind hole to the thickness of the first conductive layer 200 on the bottom wall 142 of the blind hole is less than a preset value, and the preset value is less than or equal to 20%. In a method for manufacturing a carrier board provided by at least one embodiment of the present disclosure, the preset value is less than or equal to 10%.

[0144] Exemplarily, the thickness of the first conductive layer 200 at the opening of the blind hole 140b is A, and the thickness of the first conductive layer 200 on the bottom wall 142 of the blind hole is B, (A - B) / B = preset value, and the preset value is less than or equal to 20% or less than or equal to 10%. That is, the thickness of the first conductive layer 200 at the opening of the blind hole 140b is equal to or approximately equal to the thickness of the first conductive layer 200 on the bottom wall 142 of the blind hole.

[0145] In a method for manufacturing a carrier board provided by at least one embodiment of the present disclosure, the opening 140 is a blind hole 140b, and the thickness of the first conductive layer 200 at the opening of the blind hole 140b is less than the thickness of the corresponding second conductive layer 300 at the opening of the blind hole.

[0146] In a method for manufacturing a carrier board provided by an embodiment of the present disclosure, in the step of forming the second conductive layer 300 by magnetron sputtering, that is, in step S300, the second conductive layer 300 covers one side surface of the first conductive layer 200 facing away from the substrate 100. The formed second conductive layer 300 has a uniform thickness distribution on one side surface of the substrate 100, and the thickness of the second conductive layer 300 at the opening of the opening is greater than the thickness of the second conductive layer 300 at the opening far away from the opening 140.

[0147] In a method for manufacturing a carrier board provided by an embodiment of the present disclosure, the opening 140 is a blind hole 140b, and the thickness of the second conductive layer 300 on the side wall 141 of the blind hole gradually decreases in the direction from the opening of the blind hole 140b to the bottom wall 142 of the blind hole.

[0148] Exemplarily, as Figure 15 shown, the second conductive layer 300 has a uniform thickness distribution on one side surface of the substrate 100. The second conductive layer 300 covers the surface of the first conductive layer 200 facing away from the side wall 141 of the blind hole and the surface of the first conductive layer 200 facing away from the bottom wall 142 of the blind hole, and the thickness of the second conductive layer 300 decreases in the direction from the opening of the blind hole 140b to the bottom wall 142 of the blind hole. The thickness of the second conductive layer 300 on the bottom wall 142 of the blind hole is less than the local thickness of the second conductive layer 300 on the side wall 141 of the blind hole.

[0149] In a method for manufacturing a carrier board provided by an embodiment of the present disclosure, continue to refer to Figure 15 , the thickness of the second conductive layer 300 on the side wall 141 of the blind hole gradually decreases in the direction from the opening of the blind hole 140b to the bottom wall 142 of the blind hole.

[0150] In a method for manufacturing a carrier board provided by an embodiment of the present disclosure, as Figure 2 and Figure 9 shown, the second conductive layer 300 covers a part of the first conductive layer 200.

[0151] In a method for manufacturing a carrier board provided by an embodiment of the present disclosure, as Figure 15 , the thickness of the second conductive layer 300 at the opening of the blind hole 140b is greater than the thickness of the corresponding first conductive layer 200 at the opening of the blind hole 140b. Regarding the thickness change of the second conductive layer 300 on the side wall 141 of the blind hole, reference can be made to the description of the above embodiments, and details are not described herein.

[0152] In a method for manufacturing a carrier board provided by an embodiment of the present disclosure, the thickness of the second conductive layer 300 on one side surface of the substrate 100 is 50 nm - 2000 nm.

[0153] Exemplarily, the thickness of the second conductive layer 300 on one side surface of the substrate 100 is any one of 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, 300 nm, 310 nm, 320 nm, 330 nm, 340 nm, 350 nm, 360 nm, 370 nm, 380 nm, 390 nm, 400 nm, 420 nm, 440 nm, 460 nm, 480 nm, 500 nm, 550 nm, 600 nm, 700 nm, 850 nm, 1000 nm, 1200 nm, 1400 nm, 1600 nm, 1800 nm, and the thickness of the second conductive layer 300 on one side surface of the substrate 100 is greater than the thickness of the first conductive layer 200 on one side surface of the substrate 100.

[0154] In a method for preparing a carrier board provided in an embodiment of the present disclosure, reference may be made to Figure 5 As shown, the second conductive layer 300 includes a uniform portion 310, a gradual change portion 320, and a transition portion 330. The uniform portion 310 is located on one side surface of the substrate 100, that is, the first surface 120 of the subsequent formed carrier board. The gradual change portion 320 is located on the side wall 141 and the bottom wall 142 of the opening. The transition portion 330 connects the uniform portion 310 and the gradual change portion 320, and the transition portion 330 has an arc-shaped transition surface. For example, the line of the transition portion 330 is arc-shaped.

[0155] It should be noted that the carrier board structure prepared by the method for preparing a carrier board provided in the embodiment of the present disclosure is not limited to the limitations in the above embodiments. For example, the thicknesses of the first conductive layer 200 and the second conductive layer 300 on the first surface 120 can be designed according to actual needs on the premise that the thickness of the second conductive layer 300 is greater than the thickness of the first conductive layer 200, and is not limited to the parameters provided in the above embodiments. For example, the transition portion 330 in the second conductive layer 300 can also be set to other structures, such as Figure 15 As shown, the transition portion 330 is a chamfer. For another example, in addition to being linearly changed, the gradual change portion 320 in the second conductive layer 300 can also show a wavy change or a stepped change. All of the above can be designed according to actual needs and will not be elaborated here.

[0156] Based on the above embodiments, the method for preparing a carrier board provided in the embodiment of the present disclosure may also have other steps, and the specific content is as follows.

[0157] In a specific embodiment of the second aspect of the present disclosure, before forming the first conductive layer by atomic deposition, at least one adhesion layer is formed on the inner wall of the opening by atomic deposition, and the adhesion layer covers the inner wall of the opening.

[0158] Exemplarily, a method for preparing a carrier plate includes steps S100 to S400 as Figure 16 shown, specifically as follows.

[0159] S100, a recessed opening is formed on one side surface of the substrate.

[0160] S200, at least one adhesion layer is formed on the inner wall of the opening by atomic deposition, and the adhesion layer covers the inner wall of the opening.

[0161] S300, a first conductive layer is formed by atomic deposition, and the first conductive layer covers the inner wall of the opening.

[0162] S400, a second conductive layer is formed by magnetron sputtering, the second conductive layer covers at least a part of the inner surface of the first conductive layer, and the thickness of at least a part of the second conductive layer is greater than the thickness of the first conductive layer.

[0163] Thus, in the above method for preparing a carrier plate, before preparing the first conductive layer, in the carrier plate obtained by preparing at least one adhesion layer on the inner wall of the opening, the adhesion layer can further improve the bonding strength between the subsequent filling material, i.e., the conductive filling layer, and the opening, and reduce the risk of peeling of the conductive filling layer.

[0164] In a specific embodiment of the second aspect of the present disclosure, as Figure 17 shown, the preparation method further includes step S500: electroplating to form a conductive filling layer, and the conductive filling layer fills the opening. For example, the conductive filling layer fills a blind hole.

[0165] Based on the above preparation method, there are various design schemes for the structure of the intermediate product of the obtained carrier plate.

[0166] For example, as Figure 5 shown, based on Figure 17The structure of an intermediate product of a carrier board obtained by the shown preparation method includes a substrate 100, an adhesion layer 500, a first conductive layer 200, a second conductive layer 300, and a conductive filling layer 400. A blind hole 140b is formed by recessing one side surface of the substrate 100. The adhesion layer 500 and the first conductive layer 200 are sequentially disposed on one side surface of the substrate 100, covering the side wall 141 and the bottom wall 142 of the blind hole. The second conductive layer 300 is disposed on one side of the side surface of the first conductive layer 200 facing away from the substrate 100 and covers the first conductive layer 200. The conductive filling layer 400 is filled in the blind hole 140b. The sum of the thicknesses of the adhesion layer 500 and the first conductive layer 200 on one side surface of the substrate 100 is less than the sum of the thicknesses of the second conductive layer 300 on one side surface of the substrate 100.

[0167] For another example, as Figure 18 shown, based on Figure 17 Another structure of an intermediate product of a carrier board obtained by the shown preparation method includes a substrate 100, an inner adhesion layer 510, an outer adhesion layer 520, a first conductive layer 200, a second conductive layer 300, and a conductive filling layer. The inner adhesion layer 510, the outer adhesion layer 520, and the first conductive layer 200 are sequentially disposed on the first surface 120 of the substrate 100 and cover the side wall 141 and the bottom wall 142 of the blind hole of the substrate 100. The second conductive layer 300 is disposed on one side of the side surface of the first conductive layer 200 facing away from the first surface 120 of the substrate 100 and covers the first conductive layer 200. The conductive filling layer 400 is filled in the blind hole 140b. The sum of the thicknesses of the inner adhesion layer 510, the outer adhesion layer 520, and the first conductive layer 200 on the first surface 120 of the substrate 100 is less than the sum of the thicknesses of the second conductive layer 300 on the first surface 120 of the substrate 100.

[0168] In at least one embodiment of the present disclosure, as Figure 18 shown, in step S200, while the adhesion layer covers the inner wall of the opening, it also covers one side surface of the substrate, and the adhesion layer is evenly distributed on the first surface and the inner wall of the opening.

[0169] In at least one embodiment of the present disclosure, the density of the adhesion layer is greater than the density of the second conductive layer.

[0170] In at least one embodiment of the present disclosure, the adhesion layer is at least one of a titanium metal layer, a titanium nitride layer, a chromium metal layer, a ruthenium metal layer, an aluminum oxide layer, a silicon oxide layer, a silicon nitride layer, a tantalum metal layer, or a tantalum nitride metal layer.

[0171] In at least one embodiment of the present disclosure, the first conductive layer is any one of a titanium metal layer, a chromium metal layer, an aluminum metal layer, a copper metal layer, a nickel metal layer, a tungsten metal layer, a tantalum metal layer, a ruthenium metal layer, a palladium metal layer, or a platinum metal layer.

[0172] In at least one embodiment of the present disclosure, the second conductive layer is one of a copper metal layer or a nickel metal layer.

[0173] In at least one embodiment of the present disclosure, the substrate is a glass substrate.

[0174] It should be noted that the method for preparing the carrier board in the embodiments of the present disclosure is not limited to the above examples and illustrations, and it may also include other solutions. For example, the opening mentioned in the above method for preparing the carrier board is not limited to the blind hole mentioned in the figure and the example, and it may also be a through hole. According to the design of the through hole, the corresponding operations of forming the adhesive layer, the first conductive layer, and the second conductive layer in the through hole can be adjusted accordingly. At the same time, compared with the design of the through hole, the design of the blind hole can simplify the process steps of the method for preparing the carrier board, thereby reducing the production difficulty and increasing the production cost. The above can be designed according to actual needs and will not be elaborated here.

[0175] In one embodiment of the present disclosure, the opening mentioned in the method for preparing the carrier board is a blind hole, and the preparation method further includes steps S700 to S800 as shown in Figure 19 as follows.

[0176] S700, removing the film layer structure on one side surface of the substrate to obtain the first surface of the substrate.

[0177] For example, removing the first conductive layer and the second conductive layer on one side surface of the substrate, or removing at least one adhesive layer, the first conductive layer, and the second conductive layer on one side surface of the substrate.

[0178] S800, processing the other side surface of the substrate corresponding to the bottom wall of the blind hole, removing a part of the bottom wall of the blind hole to form a through hole filled with a conductive filling layer, and obtaining the second surface of the substrate.

[0179] In at least one embodiment of the present disclosure, in the direction from the first surface to the new second surface, the thickness of the second conductive layer on the side wall of the through hole gradually decreases.

[0180] In another embodiment of the present disclosure, the opening mentioned in the method for preparing the carrier board is a through hole, and the preparation method further includes steps S700a to S800a as shown in Figure 20 as follows.

[0181] S700a, removing the film layer structure on one side surface of the substrate to obtain the first surface of the substrate.

[0182] For example, removing the first conductive layer and the second conductive layer on one side surface of the substrate, or removing at least one adhesive layer, the first conductive layer, and the second conductive layer on one side surface of the substrate.

[0183] S800a, process the other surface corresponding to the other opening of the through hole in the processing substrate, remove part of the substrate and the corresponding film layer to form a second surface, and the second surface is a smooth plane, so that the thickness of the second conductive layer in the through hole near the first surface is less than the thickness of the second conductive layer near the second surface.

[0184] In at least one embodiment of the present disclosure, in the direction from the first surface to the new second surface, the thickness of the second conductive layer on the sidewall of the through hole gradually decreases.

[0185] In at least one embodiment of the present disclosure, the method for preparing the carrier plate further includes steps S910 to S920 as shown in Figure 21 as follows.

[0186] S910, form a first metal contact point on the first surface, and the first metal contact point is in direct contact with one surface of the conductive filling layer exposed on the first surface.

[0187] S920, form a second metal contact point on the new second surface, and the second metal contact point is in direct contact with the other surface of the conductive filling layer exposed on the first surface.

[0188] The embodiment of the present disclosure also provides a chip packaging structure, and the chip packaging structure includes the carrier plate in any one of the above embodiments or the carrier plate prepared by the preparation method in any one of the above embodiments.

[0189] In at least one embodiment of the present disclosure, the chip packaging structure can be assembled in an electronic device, such as a display device, and the display device can be an organic light-emitting diode display device, a liquid crystal display device, an electronic paper display device, etc.

[0190] For example, the display device in the embodiment of the present disclosure can be any product or component with a display function, such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, a navigator, etc.

[0191] It should be noted that the embodiment of the present disclosure does not describe all the structures of the above-mentioned carrier plate. To achieve the necessary functions of the carrier plate, those skilled in the art can set other structures according to specific application scenarios. The carrier plate in the embodiment of the present disclosure can be used for semiconductor devices. Specifically, the semiconductor device includes a semiconductor chip and the carrier plate described in any one of the above embodiments, and the semiconductor chip is mounted on the carrier plate.

[0192] The above are only the preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A carrier motherboard, characterized in that: include: A substrate, wherein an opening is formed on one side surface of the substrate; a first conductive layer, covering the inner wall of the opening; a second conductive layer, located on the inner side of the first conductive layer and covering at least a portion of the first conductive layer, wherein a thickness of at least a portion of the second conductive layer on the first conductive layer is greater than a thickness of the first conductive layer; as well as A conductive filling layer is located on a side of the second conductive layer away from the sidewall of the opening and fills the opening.

2. The carrier motherboard according to claim 1, characterized in that: The first conductive layer covers a surface of one side of the substrate, and the thickness of the first conductive layer is evenly distributed; Preferably, the second conductive layer covers a side of the first conductive layer away from the surface of the substrate, the thickness of the second conductive layer is uniformly distributed on the surface of the substrate, and the thickness of the second conductive layer at the opening of the opening is greater than the thickness of the second conductive layer at the opening away from the opening; Preferably, the thickness of the second conductive layer on one side surface of the substrate is greater than the thickness of the first conductive layer on one side surface of the substrate; Preferably, the thickness of the second conductive layer at the opening of the opening is greater than the thickness of the first conductive layer at the opening of the opening; Preferably, the second conductive layer comprises a uniform portion, a gradual portion and a transition portion, the uniform portion is located on one side surface of the substrate, the gradual portion is located on the inner wall of the opening, the transition portion connects the uniform portion and the gradual portion, and the transition portion has an arc-shaped transition surface; Preferably, the opening is a blind hole, and the thickness of the second conductive layer gradually decreases in a direction from the opening of the blind hole to the bottom wall of the blind hole; Preferably, it further comprises at least one adhesive layer, wherein the adhesive layer is located between the first conductive layer and the substrate, and the adhesive layer covers a side surface of the substrate and an inner wall of the opening; Preferably, the thickness of the adhesive layer is uniformly distributed; Preferably, the density of the adhesion layer is greater than the density of the second conductive layer.

3. A carrier board, characterized in that: include: a substrate including a through hole; A first conductive layer covers the sidewall of the through hole, and the thickness of the first conductive layer is uniformly distributed; a second conductive layer, located on the inner side of the first conductive layer and covering at least a portion of the first conductive layer, wherein a thickness of at least a portion of the second conductive layer is greater than a thickness of the first conductive layer; as well as A conductive filling layer is located on a side of the second conductive layer away from the sidewall of the through hole and fills the through hole.

4. The carrier board according to claim 3, characterized in that: The substrate comprises a first surface and a second surface arranged opposite to each other, the through hole comprises a first opening located on the first surface and a second opening located on the second surface, and the thickness of the second conductive layer at the first opening is greater than the thickness of the second conductive layer at the second opening; Preferably, the thickness of the second conductive layer gradually decreases in a direction from the first opening to the second opening; Preferably, the second conductive layer covers a portion of the first conductive layer; Preferably, the thickness of the second conductive layer at the first opening is greater than the thickness of the first conductive layer at the first opening; Preferably, the density of the first conductive layer is greater than the density of the second conductive layer; Preferably, it further comprises at least one adhesive layer, wherein the adhesive layer is located between the first conductive layer and the side wall of the through hole, and the adhesive layer covers the side wall of the through hole; Preferably, the thickness of the adhesive layer is uniformly distributed; Preferably, the density of the adhesion layer is greater than the density of the second conductive layer; Preferably, the adhesion layer is at least one of a titanium metal layer, a titanium nitride layer, a chromium metal layer, a ruthenium metal layer, an aluminum oxide layer, a silicon oxide layer, a silicon nitride layer, a tantalum metal layer or a tantalum nitride metal layer; Preferably, the first conductive layer is any one of a titanium metal layer, a chromium metal layer, an aluminum metal layer, a copper metal layer, a nickel metal layer, a tungsten metal layer, a tantalum metal layer, a ruthenium metal layer, a palladium metal layer or a platinum metal layer; Preferably, the second conductive layer is one of a copper metal layer or a nickel metal layer; Preferably, the substrate is a glass substrate; Preferably, it also includes a metal contact point, which includes a first metal contact point and a second metal contact point, the first metal contact point is located on the first surface and is in direct contact with one surface of the conductive filling layer exposed by the first opening, and the second metal contact point is located on the second surface and is in direct contact with another surface of the conductive filling layer exposed by the second opening.

5. A method for preparing a carrier plate, characterized in that: include: An opening is formed on one side surface of the substrate; forming a first conductive layer by atomic deposition, wherein the first conductive layer covers the inner wall of the opening; Forming a second conductive layer by magnetic sputtering, wherein the second conductive layer covers at least a portion of the surface of the inner wall of the opening of the first conductive layer, and the thickness of at least a portion of the second conductive layer is greater than the thickness of the first conductive layer; A conductive filling layer is formed by electroplating, and the conductive filling layer fills the opening.

6. The method for preparing a carrier plate according to claim 5, characterized in that: In the step of forming the first conductive layer by atomic deposition, the thickness of the formed first conductive layer is uniformly distributed and covers one side surface of the substrate; Preferably, the opening is a blind hole, and a ratio of a thickness difference between a thickness of the first conductive layer at the opening of the blind hole and a thickness of the first conductive layer on the bottom wall of the blind hole to a thickness of the first conductive layer on the bottom wall of the blind hole is less than a preset value, and the preset value is less than or equal to 20%; Preferably, the preset value is less than or equal to 10%; Preferably, the thickness of the first conductive layer on one side surface of the substrate is 10nm-200nm; Preferably, the thickness of the first conductive layer at the opening of the blind hole is smaller than the thickness of the second conductive layer at the opening of the blind hole.

7. The method for preparing a carrier according to claim 5, characterized in that: In the step of forming the second conductive layer by magnetic sputtering, the second conductive layer covers a side of the first conductive layer that is away from the surface of the substrate, and the thickness of the second conductive layer at the opening of the opening is greater than the thickness of the second conductive layer at the opening away from the opening of the opening; Preferably, the opening is a blind hole, and the thickness of the second conductive layer gradually decreases in a direction from the opening of the blind hole to the bottom wall of the blind hole; Preferably, the second conductive layer covers a portion of the first conductive layer; Preferably, the thickness of the second conductive layer on one side surface of the substrate is 50nm-2000nm; Preferably, the second conductive layer comprises a uniform portion, a gradual portion and a transition portion, the uniform portion is located on one side surface of the substrate, the gradual portion is located on the inner wall of the opening, the transition portion connects the uniform portion and the gradual portion, and the transition portion has an arc-shaped transition surface; Preferably, before forming the first conductive layer by using the atomic deposition method, the method further comprises: Forming at least one adhesion layer on the inner wall of the opening by atomic deposition, wherein the adhesion layer covers the inner wall of the opening; Preferably, the thickness of the adhesive layer is evenly distributed and covers one side surface of the substrate; Preferably, the density of the adhesion layer is greater than the density of the second conductive layer; Preferably, the adhesion layer is at least one of a titanium metal layer, a titanium nitride layer, a chromium metal layer, a ruthenium metal layer, an aluminum oxide layer, a silicon oxide layer, a silicon nitride layer, a tantalum metal layer or a tantalum nitride metal layer; Preferably, the first conductive layer is any one of a titanium metal layer, a chromium metal layer, an aluminum metal layer, a copper metal layer, a nickel metal layer, a tungsten metal layer, a tantalum metal layer, a ruthenium metal layer, a palladium metal layer or a platinum metal layer; Preferably, the second conductive layer is one of a copper metal layer or a nickel metal layer; Preferably, the substrate is a glass substrate.

8. The method for preparing a carrier plate according to claim 7, characterized in that: The opening is a blind hole, and the preparation method further comprises: Removing the film layer structure on one side surface of the substrate to obtain a first surface of the substrate; Processing the other side surface of the substrate corresponding to the bottom wall of the blind hole, removing part of the bottom wall of the blind hole to form a through hole filled with the conductive filling layer, and obtaining the second surface of the substrate; Preferably, the preparation method further comprises: forming a first metal contact point on the first surface, wherein the first metal contact point is in direct contact with a surface of the conductive filling layer exposed on the first surface; A second metal contact point is formed on the second surface, and the second metal contact point is in direct contact with another surface of the conductive filling layer exposed by the second surface.

9. The method for preparing a carrier according to claim 7, characterized in that: The opening is a through hole, and the preparation method further comprises: Removing the film layer structure on one side surface of the substrate to obtain a first surface of the substrate; Processing the other side surface of the substrate corresponding to the other opening of the through hole, removing part of the substrate and the corresponding film layer, and forming a second surface, wherein the second surface is a smooth plane, so that the thickness of the second conductive layer in the through hole near the first surface is smaller than the thickness of the second conductive layer near the second surface; Preferably, the thickness of the second conductive layer gradually decreases in a direction from the first surface to the second surface; Preferably, the preparation method further comprises: forming a first metal contact point on the first surface, wherein the first metal contact point is in direct contact with a surface of the conductive filling layer exposed on the first surface; A second metal contact point is formed on the second surface, and the second metal contact point is in direct contact with another surface of the conductive filling layer exposed by the second surface.

10. A chip packaging structure, characterized in that: A carrier motherboard comprising the carrier motherboard according to any one of claims 1-2, or the carrier board according to any one of claims 3-4, or the carrier board prepared by the preparation method according to any one of claims 5-9.

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