Semiconductor device, manufacturing method thereof and storage system
By providing an insulating portion at the end of the wire structure to define the pattern and obtaining the wire structure by substitution, the pattern unevenness and deformation problems caused by the etching load effect are solved, and the production accuracy and stability of the wire structure are improved.
Patent Information
- Application Number
- CN202311765488.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-20
- Publication Date
- 2025-06-20
AI Technical Summary
When preparing wire structures with different lengths, due to the etching load effect, uneven pattern and deformation of the wire structure are easily caused.
By providing a first insulating portion and a second insulating portion at the ends of the corresponding regions of the first conductor structure and the second conductor structure, the pattern of the conductor structure is defined in advance during the process, and the conductor structure is obtained by substitution to improve the problem of pattern unevenness and deformation.
The graphics production accuracy and stability of the wire structure are improved, the graphics defects caused by the etching load effect are avoided, and the space of semiconductor devices is saved.
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Figure CN120184142A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular, to a semiconductor device, a manufacturing method thereof, and a storage system. Background Art
[0002] The patterning process can produce patterns with a target pitch, as well as a preset shape and size. However, currently, when preparing wire structures with different lengths, due to the etching loading effect, it is easy to cause uneven and deformed patterns of the obtained wire structures. Summary of the Invention
[0003] Embodiments of this application provide a semiconductor device, a manufacturing method thereof, and a storage system, which can improve the pattern manufacturing accuracy and stability of a first wire structure and a second wire structure with different lengths.
[0004] Embodiments of this application provide a semiconductor device, which includes:
[0005] A substrate;
[0006] A first wire structure disposed in the substrate;
[0007] A second wire structure disposed in the substrate, wherein the length of the first wire structure is greater than the length of the second wire structure;
[0008] Wherein, the semiconductor device further includes an insulating structure disposed in the substrate, the insulating structure includes a first insulating portion connected to an end of the first wire structure, and a second insulating portion connected to an end of the second wire structure, and the insulating structure includes a first material, the substrate includes a second material, and the first material and the second material are different.
[0009] In some embodiments of this application, the first wire structure and the second wire structure both extend along a first direction and are arranged along a second direction, and the first direction and the second direction intersect, and both the first direction and the second direction are perpendicular to the thickness direction of the substrate;
[0010] Wherein, the first insulating portion is connected to the end of the first wire structure along the first direction, and the second insulating portion is connected to the end of the second wire structure along the first direction.
[0011] In some embodiments of this application, the semiconductor device includes a plurality of the first wire structures and a plurality of the second wire structures, and the plurality of the first wire structures and the plurality of the second wire structures are alternately arranged along the second direction;
[0012] The insulating structure further includes a third insulating portion, which is connected between the first insulating portion and the second insulating portion between an adjacent first wire structure and an adjacent second wire structure.
[0013] In some embodiments of the present application, between an adjacent first wire structure and an adjacent second wire structure, the first insulating portion, the second insulating portion, and the third insulating portion are an integral structure.
[0014] In some embodiments of the present application, between an adjacent first wire structure and an adjacent second wire structure, the first wire structure, the first insulating portion connected to the first wire structure, the second wire structure, the second insulating portion connected to the second wire structure, and the third insulating portion connected between the first insulating portion and the second insulating portion form a ring.
[0015] In some embodiments of the present application, the third insulating portion extends along the second direction.
[0016] In some embodiments of the present application, the length of the first insulating portion along the first direction is less than the length of the second insulating portion along the first direction.
[0017] In some embodiments of the present application, the sum of the lengths of the first wire structure and the first insulating portion connected to the end of the first wire structure along the first direction is equal to the sum of the lengths of the second wire structure and the second insulating portion connected to the end of the second wire structure along the first direction.
[0018] In some embodiments of the present application, the insulating structure includes a filling oxide layer and a covering oxide layer located between the filling oxide layer and the substrate, and the second material includes a silicon material.
[0019] Based on the above object of the present application, embodiments of the present application further provide a method for manufacturing a semiconductor device, which includes the following steps:
[0020] Form a first sacrificial portion, a second sacrificial portion, and an insulating structure in a substrate. A first insulating portion connected to the end of the first sacrificial portion and a second insulating portion connected to the end of the second sacrificial portion are formed in the insulating structure. The insulating structure includes a first material, the substrate includes a second material, and the first material and the second material are different;
[0021] Remove the first sacrificial portion to form a first groove in the substrate, and remove the second sacrificial portion to form a second groove in the substrate;
[0022] A first wire structure is formed in the first groove, and a second wire structure is formed in the second groove. The first insulating portion is connected to an end of the first wire structure, the second insulating portion is connected to an end of the second wire structure, and the length of the first wire structure is greater than the length of the second wire structure.
[0023] In some embodiments of the present application, the step of forming the first sacrificial portion, the second sacrificial portion, and the insulating structure in the substrate includes:
[0024] Forming a first intermediate groove and a second intermediate groove in the substrate;
[0025] Forming a first sacrificial layer in the first intermediate groove and forming a second sacrificial layer in the second intermediate groove;
[0026] Removing a part of the first sacrificial layer to form a first isolation groove, and removing a part of the second sacrificial layer to form a second isolation groove. The remaining first sacrificial layer forms the first sacrificial portion, the first isolation groove is formed at an end of the first sacrificial portion, the remaining second sacrificial layer forms the second sacrificial portion, and the second isolation groove is formed at an end of the second sacrificial portion;
[0027] Forming a first insulating portion in the first isolation groove and forming a second insulating portion in the second isolation groove.
[0028] In some embodiments of the present application, the step of forming the first intermediate groove and the second intermediate groove in the substrate includes:
[0029] Forming a plurality of the first intermediate grooves extending in a first direction and arranged in a second direction, a plurality of the second intermediate grooves extending in the first direction and arranged in the second direction, and a plurality of third intermediate grooves extending in the second direction in the substrate. The first direction and the second direction intersect, both the first direction and the second direction are perpendicular to the thickness direction of the substrate, and the plurality of the first intermediate grooves and the plurality of the second intermediate grooves are alternately arranged in the second direction;
[0030] Wherein, the third intermediate groove is connected between the first intermediate groove and the second intermediate groove, and an adjacent first intermediate groove and a second intermediate groove, and two third intermediate grooves connected between an adjacent first intermediate groove and a second intermediate groove form an annular groove.
[0031] In some embodiments of the present application, the step of forming the first sacrificial layer in the first intermediate groove and forming the second sacrificial layer in the second intermediate groove further includes:
[0032] A third sacrificial layer is formed in the third intermediate groove, and the third sacrificial layer is connected between the first sacrificial layer and the second sacrificial layer.
[0033] In some embodiments of the present application, the steps of removing a part of the first sacrificial layer to form a first isolation groove and removing a part of the second sacrificial layer to form a second isolation groove include:
[0034] Removing a part of the first sacrificial layer, a part of the second sacrificial layer, and the third sacrificial layer to form the first isolation groove, the second isolation groove, and the third isolation groove respectively, and the third isolation groove is connected between the first isolation groove and the second isolation groove.
[0035] In some embodiments of the present application, the steps of forming a first insulating portion in the first isolation groove and forming a second insulating portion in the second isolation groove further include:
[0036] Forming a third insulating portion in the third isolation groove, and the third insulating portion is connected between the first insulating portion and the second insulating portion to constitute the insulating structure.
[0037] For the above object of the present application, an embodiment of the present application further provides a storage system, which includes a controller and the semiconductor device, or a semiconductor device manufactured by using the manufacturing method of the semiconductor device, and the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.
[0038] The present application provides a semiconductor device, its manufacturing method, a storage system, and an electronic device. By providing a first insulating portion and a second insulating portion at the ends of corresponding regions of a first wire structure and a second wire structure, the patterns of the first wire structure and the second wire structure can be pre-defined during the manufacturing process, and the first wire structure and the second wire structure can be obtained by replacement, so as to improve the non-uniformity and deformation of the wire structure patterns caused by the etching load effect and other adverse phenomena. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] The following will make the technical solutions and other beneficial effects of the present application obvious by describing the specific embodiments of the present application in detail with reference to the accompanying drawings.
[0040] Figure 1 It is a schematic structural diagram of a semiconductor device in an embodiment;
[0041] Figure 2 It is another schematic structural diagram of a semiconductor device in an embodiment;
[0042] Figure 3 It is a top view of the semiconductor device provided by the embodiment of the present application;
[0043] Figure 4 A schematic cross-sectional structure diagram of the semiconductor device provided by the embodiment of the present application along Figure 3 the A-A line in;
[0044] Figure 5 A schematic cross-sectional structure diagram of the semiconductor device provided by the embodiment of the present application along Figure 3 the B-B line in;
[0045] Figure 6 A flowchart of the manufacturing method of the semiconductor device provided by the embodiment of the present application;
[0046] Figure 7 A schematic structural diagram of a manufacturing process of the semiconductor device provided by the embodiment of the present application;
[0047] Figure 8 A schematic cross-sectional structure diagram of the semiconductor device provided by the embodiment of the present application along Figure 7 the C-C line in;
[0048] Figure 9 A schematic structural diagram of a manufacturing process of the semiconductor device provided by the embodiment of the present application;
[0049] Figure 10 A schematic cross-sectional structure diagram of the semiconductor device provided by the embodiment of the present application along Figure 9 the D-D line in;
[0050] Figure 11 A schematic structural diagram of a manufacturing process of the semiconductor device provided by the embodiment of the present application;
[0051] Figure 12 A schematic cross-sectional structure diagram of the semiconductor device provided by the embodiment of the present application along Figure 11 the E-E line in;
[0052] Figure 13 A schematic structural diagram of a manufacturing process of the semiconductor device provided by the embodiment of the present application;
[0053] Figure 14 A schematic cross-sectional structure diagram of the semiconductor device provided by the embodiment of the present application along Figure 13 the F-F line in;
[0054] Figure 15 A schematic cross-sectional structure diagram of the semiconductor device provided by the embodiment of the present application along Figure 13 the G-G line in;
[0055] Figure 16 A schematic structural diagram of a manufacturing process of the semiconductor device provided by the embodiment of the present application;
[0056] Figure 17 A schematic cross-sectional structure diagram of the semiconductor device provided by the embodiment of the present application along Figure 16 the H-H line in
[0057] Figure 18 A schematic cross-sectional structure diagram of the semiconductor device provided by the embodiment of the present application along Figure 16 the I-I line in
[0058] Figure 19 A schematic structure diagram of the manufacturing process of the semiconductor device provided by the embodiment of the present application;
[0059] Figure 20 A schematic cross-sectional structure diagram of the semiconductor device provided by the embodiment of the present application along Figure 19 the J-J line in
[0060] Figure 21 A schematic cross-sectional structure diagram of the semiconductor device provided by the embodiment of the present application along Figure 19 the K-K line in
[0061] Figure 22 A schematic structure diagram of the manufacturing process of the semiconductor device provided by the embodiment of the present application;
[0062] Figure 23 A schematic cross-sectional structure diagram of the semiconductor device provided by the embodiment of the present application along Figure 22 the L-L line in
[0063] Figure 24 A schematic cross-sectional structure diagram of the semiconductor device provided by the embodiment of the present application along Figure 22 the M-M line in
[0064] Figure 25 A schematic structure diagram of the manufacturing process of the semiconductor device provided by the embodiment of the present application;
[0065] Figure 26 A schematic cross-sectional structure diagram of the semiconductor device provided by the embodiment of the present application along Figure 25 the N-N line in
[0066] Figure 27 A schematic cross-sectional structure diagram of the semiconductor device provided by the embodiment of the present application along Figure 25 the O-O line in
[0067] Figure 28 A schematic structure diagram of the manufacturing process of the semiconductor device provided by the embodiment of the present application;
[0068] Figure 29 A schematic cross-sectional structure diagram of the semiconductor device provided by the embodiment of the present application along Figure 28 the P-P line in
[0069] Figure 30 A cross-sectional structure schematic diagram of the semiconductor device provided by the embodiment of the present application along Figure 28 the Q-Q line in
[0070] Figure 31 A manufacturing process structure schematic diagram of the semiconductor device provided by the embodiment of the present application;
[0071] Figure 32 A structure schematic diagram of the storage system provided by the embodiment of the present application;
[0072] Figure 33 A structure schematic diagram of the electronic device provided by the embodiment of the present application. Detailed implementation manners
[0073] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.
[0074] The following disclosure provides many different implementation manners or examples for implementing different structures of the present application. To simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present application. In addition, the present application may repeat reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various implementation manners and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those skilled in the art can be aware of the application of other processes and / or the use of other materials.
[0075] Please refer to Figure 1 and Figure 2, in a semiconductor device of the related art, a multiple patterning process is usually adopted to form a first trace 2 and a second trace 3 in an etching layer 1 to be etched, and the length of the first trace 2 is greater than that of the second trace 3. Among them, since it is necessary to form the first trace 2 and the second trace 3 with different lengths, the distribution density of the etching pattern is different. Under the action of the etching load effect, the first trace 2 and the second trace 3 are prone to pattern unevenness and deformation. For example, the end of the first trace 2 with a larger length is prone to deformation such as drift, while the end of the second trace 3 with a shorter length is prone to the phenomenon of increased width, and the etching depths of the first trace 2 and the second trace 3 in different regions are different. In the related art, virtual traces are often set as buffer patterns so that pattern unevenness and deformation occur in the virtual traces. However, the virtual traces will occupy the space of the semiconductor device, reducing the space utilization rate of the semiconductor device.
[0076] Please combine Figure 3 , Figure 4 and Figure 5 , embodiments of the present application provide a semiconductor device, which includes a substrate 10, a first wire structure 21, a second wire structure 22, and an insulating structure 30.
[0077] The first wire structure 21 is disposed in the substrate 10, the second wire structure 22 is disposed in the substrate 10, and the length of the first wire structure 21 is greater than that of the second wire structure 22.
[0078] Further, the insulating structure 30 is disposed in the substrate 10. The insulating structure 30 includes a first insulating portion 31 connected to the end of the first wire structure 21 and a second insulating portion 32 connected to the end of the second wire structure 22, and the insulating structure 30 includes a first material, and the substrate 10 includes a second material, and the first material and the second material are different.
[0079] In the embodiments of the present application, by providing the first insulating portion 31 and the second insulating portion 32 at the ends of the corresponding regions of the first wire structure 21 and the second wire structure 22, the patterns of the first wire structure 21 and the second wire structure 22 can be pre-defined in the manufacturing process, and the first wire structure 21 and the second wire structure 22 can be obtained by replacement, so as to improve the adverse phenomena such as pattern unevenness and deformation of the wire structure caused by the etching load effect.
[0080] Specifically, please continue to combine Figure 3 , Figure 4 and Figure 5 , the semiconductor device includes a substrate 10, a first wire structure 21, a second wire structure 22, and an insulating structure 30 disposed in the substrate 10.
[0081] Among them, the substrate 10 includes a base layer 11 and a cover layer 12 disposed on one side of the base layer 11. The first wire structure 21 and the second wire structure 22 both pass through the cover layer 12 and a part of the base layer 11, and the insulating structure 30 passes through the cover layer 12 and a part of the base layer 11.
[0082] In some embodiments, the material of the base layer 11 may include a semiconductor material. For example, the semiconductor material may include, but is not limited to, silicon (such as single-crystalline silicon, polycrystalline silicon, doped polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any suitable combination thereof. And the material of the cover layer 12 may include a silicon nitride material.
[0083] The insulating structure 30 includes a first insulating portion 31 connected to the end of the first wire structure 21 and a second insulating portion 32 connected to the end of the second wire structure 22.
[0084] In some embodiments, the semiconductor device includes a plurality of first wire structures 21 and a plurality of second wire structures 22. The plurality of first wire structures 21 extend along a first direction X and are arranged along a second direction Y. The first direction X intersects the second direction Y, and both the first direction X and the second direction Y are perpendicular to the thickness direction of the substrate 10. The plurality of second wire structures 22 extend along the first direction X and are arranged along the second direction Y.
[0085] In some embodiments, the first direction X is perpendicular to the second direction Y.
[0086] The first insulating portion 31 is connected to the end of the first wire structure 21 along the first direction X, and the second insulating portion 32 is connected to the end of the second wire structure 22 along the first direction X. Specifically, both opposite ends of the first wire structure 21 along the first direction X are connected to the first insulating portion 31, and both opposite ends of the second wire structure 22 along the first direction X are connected to the second insulating portion 32.
[0087] Further, the length of the first wire structure 21 is greater than the length of the second wire structure 22, that is, the length of the first wire structure 21 along the first direction X is greater than the length of the second wire structure 22 along the first direction X. In some embodiments, the length of the first insulating portion 31 along the first direction X is less than the length of the second insulating portion 32 along the first direction X, and the sum of the lengths of the first wire structure 21 and the first insulating portion 31 connected to the end of the first wire structure 21 along the first direction X is equal to the sum of the lengths of the second wire structure 22 and the second insulating portion 32 connected to the end of the second wire structure 22 along the first direction X.
[0088] In some embodiments, a plurality of first wire structures 21 and a plurality of second wire structures 22 are arranged alternately along the second direction Y, that is, one second wire structure 22 is disposed between two adjacent first wire structures 21, and one first wire structure 21 is disposed between two adjacent second wire structures 22.
[0089] The insulating structure 30 further includes a third insulating portion 33. Between an adjacent first wire structure 21 and an adjacent second wire structure 22, the third insulating portion 33 is connected between the first insulating portion 31 and the second insulating portion 32; the third insulating portion 33 may extend along the second direction Y.
[0090] Between an adjacent first wire structure 21 and an adjacent second wire structure 22, the first wire structure 21, the first insulating portion 31 connected to the first wire structure 21, the second wire structure 22, the second insulating portion 32 connected to the second wire structure 22, and the third insulating portion 33 connected between the first insulating portion 31 and the second insulating portion 32 form a ring, for example Figure 3 a square ring in the figure.
[0091] In some embodiments, between an adjacent first wire structure 21 and an adjacent second wire structure 22, the first insulating portion 31, the second insulating portion 32, and the third insulating portion 33 are an integral structure.
[0092] In some embodiments, the materials of the first wire structure 21 and the second wire structure 22 may include conductive materials, such as conductive metal materials, while the insulating structure 30 includes a first material, the substrate 10 includes a second material, and the first material and the second material are different. The first material may include oxide materials or nitride materials, and the second material may include silicon (such as single-crystalline silicon, polycrystalline silicon, doped polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any suitable combination thereof, or silicon nitride materials.
[0093] In some embodiments, the insulating structure 30 includes a filled oxide layer 301 embedded in the substrate 10 and a capping oxide layer 302 located between the filled oxide layer 301 and the substrate 10. Among them, the filled oxide layer 301 may be a high-temperature oxide layer (HT Ox), and the capping oxide layer 302 may be a low-temperature oxide layer (LT Ox).
[0094] Continuing from the above, when fabricating the first wire structure 21 and the second wire structure 22 with different lengths in the embodiments of the present application, by providing the first insulating portion 31 and the second insulating portion 32 at the ends of the corresponding regions of the first wire structure 21 and the second wire structure 22, the patterns of the first wire structure 21 and the second wire structure 22 can be pre-defined during the manufacturing process, and the first wire structure 21 and the second wire structure 22 can be obtained by replacement, thus avoiding the occurrence of poor patterns caused by directly etching the substrate 10 with uneven pattern distribution density, and improving the poor phenomena such as uneven patterns and deformation of the wire structure caused by the etching load effect; and compared with the related art, there is no need to set up dummy traces, which can save the space of the semiconductor device, reduce the spacing between adjacent wire structures, and increase the number of wire structures that can be fabricated.
[0095] In addition, the embodiments of the present application further provide a method for manufacturing a semiconductor device, and the method for manufacturing the semiconductor device includes the following steps:
[0096] Form a first sacrificial portion, a second sacrificial portion, and an insulating structure in the substrate. A first insulating portion connected to the end of the first sacrificial portion and a second insulating portion connected to the end of the second sacrificial portion are formed in the insulating structure, and the insulating structure includes a first material, the substrate includes a second material, and the first material and the second material are different;
[0097] Remove the first sacrificial portion to form a first groove in the substrate, and remove the second sacrificial portion to form a second groove in the substrate;
[0098] Form a first wire structure in the first groove and a second wire structure in the second groove. The first insulating portion is connected to the end of the first wire structure, the second insulating portion is connected to the end of the second wire structure, and the length of the first wire structure is greater than the length of the second wire structure.
[0099] Before fabricating the first wire structure and the second wire structure with different lengths in the embodiments of the present application, by forming the first insulating portion and the second insulating portion at the ends of the corresponding regions of the first wire structure and the second wire structure, the patterns of the first wire structure and the second wire structure can be pre-defined during the manufacturing process, and the first wire structure and the second wire structure can be obtained by replacing the first sacrificial portion and the second sacrificial portion, so as to improve the poor phenomena such as uneven patterns and deformation of the wire structure caused by the etching load effect.
[0100] Specifically, please refer to Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figures 7 to 30 , and the method for manufacturing the semiconductor device includes the following steps:
[0101] Step S10: Form a first sacrificial portion 51, a second sacrificial portion 52, and an insulating structure 30 in the substrate 10. A first insulating portion 31 connected to the end of the first sacrificial portion 51 and a second insulating portion 32 connected to the end of the second sacrificial portion 52 are formed in the insulating structure 30. The insulating structure 30 includes a first material, and the substrate 10 includes a second material, and the first material and the second material are different.
[0102] Step S20: Remove the first sacrificial portion 51 to form a first groove 210 in the substrate 10, and remove the second sacrificial portion 52 to form a second groove 220 in the substrate 10.
[0103] Step S30: Form a first wire structure 21 in the first groove 210 and a second wire structure 22 in the second groove 220. The first insulating portion 31 is connected to the end of the first wire structure 21, and the second insulating portion 32 is connected to the end of the second wire structure 22. The length of the first wire structure 21 is greater than the length of the second wire structure 22.
[0104] Specifically, in step S10, the substrate 10 is provided, and the substrate 10 includes a base layer 11 and a covering layer 12 provided on one side of the base layer 11. The material of the base layer 11 may include a semiconductor material. For example, the semiconductor material may include but is not limited to silicon (such as single-crystalline silicon, polycrystalline silicon, doped polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any suitable combination thereof. The material of the covering layer 12 may include a silicon nitride material.
[0105] As Figure 7 and Figure 8 shown, a multiple patterning process can be used to pattern the substrate 10. For example, a first patterning layer 41, a second patterning layer 42, and a third patterning layer 43 can be sequentially formed on the side of the covering layer 12 away from the base layer 11. Among them, the first patterning layer 41 can be in a "day" - shaped structure in a top view, which can be regarded as two connected "square" - shaped structures. The second patterning layer 42 covers the first patterning layer 41, and when the second patterning layer 42 covers the two "square" - shaped structures, corresponding two grooves will be formed. The third patterning layer 43 fills the two grooves and covers the side of the second patterning layer 42 away from the first patterning layer 41.
[0106] In some embodiments, the third patterning layer 43 outside the grooves can be removed first, and then the second patterning layer 42 extending in the thickness direction of the substrate 10 and the second patterning layer 42 located on the side of the first patterning layer 41 away from the substrate 10 are removed. Then, the first patterning layer 41 and the remaining third patterning layer 43 form Figure 7The same rectangular structure is used, and the first patterning layer 41 and the remaining third patterning layer 43 are used as masks to pattern the substrate 10 to form a first intermediate groove 101 and a second intermediate groove 102 in the substrate 10.
[0107] In some embodiments, the step of forming the first intermediate groove 101 and the second intermediate groove 102 further includes: forming a third intermediate groove 103 in the substrate 10, and the third intermediate groove 103 is connected between the first intermediate groove 101 and the second intermediate groove 102.
[0108] An adjacent first intermediate groove 101 and a second intermediate groove 102 are connected to two third intermediate grooves 103 located between the adjacent first intermediate groove 101 and the second intermediate groove 102.
[0109] Specifically, a plurality of first intermediate grooves 101 extending along the first direction X and arranged along the second direction Y, a plurality of second intermediate grooves 102 extending along the first direction X and arranged along the second direction Y, and a plurality of third intermediate grooves 103 extending along the second direction Y are formed in the substrate 10. The first direction X and the second direction Y intersect, both the first direction X and the second direction Y are perpendicular to the thickness direction of the substrate 10, and the plurality of first intermediate grooves 101 and the plurality of second intermediate grooves 102 are alternately arranged along the second direction Y.
[0110] As Figure 9 and Figure 10 shown, the third intermediate groove 103 is connected between the first intermediate groove 101 and the second intermediate groove 102. An adjacent first intermediate groove 101 and a second intermediate groove 102, and two third intermediate grooves 103 connected between the adjacent first intermediate groove 101 and the second intermediate groove 102 form an annular groove, such as a rectangular groove.
[0111] It should be noted that the first intermediate groove 101, the second intermediate groove 102, and the third intermediate groove 103 penetrate through the covering layer 12 and part of the base layer 11.
[0112] Next, a first sacrificial layer 501 is formed in the first intermediate groove 101, and a second sacrificial layer 502 is formed in the second intermediate groove 102.
[0113] In some embodiments, as Figure 11 and Figure 12 shown, the step of forming the first sacrificial layer 501 and the second sacrificial layer 502 further includes: forming a third sacrificial layer 503 in the third intermediate groove 103, and the third sacrificial layer 503 is connected between the first sacrificial layer 501 and the second sacrificial layer 502.
[0114] Then, a spacer layer and a photoresist layer 61 are sequentially deposited on the side of the cover layer 12 away from the base layer 11, and the photoresist layer 61 covers a part of the first sacrificial layer 501 and a part of the second sacrificial layer 502, and the length of the covered first sacrificial layer 501 along the first direction X is greater than the length of the covered second sacrificial layer 502 along the first direction X.
[0115] In some embodiments, as Figure 13 , Figure 14 and Figure 15 shown, the spacer layer includes a first spacer layer 65, a second spacer layer 64, a third spacer layer 63, and a fourth spacer layer 62 that are sequentially disposed on the side of the cover layer 12 away from the base layer 11; wherein, the material of the first spacer layer 65 may include an oxide material, the material of the second spacer layer 64 may include a silicon nitride material, the material of the third spacer layer 63 may include a spin-on carbon material, and the material of the fourth spacer layer 62 may include a silicon oxynitride material.
[0116] It should be noted that the first spacer layer 65 and the second spacer layer 64 can be used to form a mask for the next patterning process, and the third spacer layer 63 and the fourth spacer layer 62 can enable the first spacer layer 65 and the second spacer layer 64 to form a better film morphology during the patterning process.
[0117] Then, the first spacer layer 65 and the second spacer layer 64 are etched through the pattern of the photoresist layer 61 to form a mask as Figure 16 , Figure 17 and Figure 18 shown; wherein, the first spacer layer 65 and the second spacer layer 64 cover a part of the first sacrificial layer 501 and a part of the second sacrificial layer 502, and the length of the covered first sacrificial layer 501 along the first direction X is greater than the length of the covered second sacrificial layer 502 along the first direction X.
[0118] Next, a part of the first sacrificial layer 501 is removed to form a first isolation groove 104, and a part of the second sacrificial layer 502 is removed to form a second isolation groove 105, and the remaining first sacrificial layer 501 forms a first sacrificial portion 51, the first isolation groove 104 is formed at the end of the first sacrificial portion 51, the remaining second sacrificial layer 502 forms a second sacrificial portion 52, and the second isolation groove 105 is formed at the end of the second sacrificial portion 52.
[0119] In some embodiments, as Figure 19 , Figure 20 and Figure 21 shown, the steps of forming the first isolation groove 104 and the second isolation groove 105 further include: removing the third sacrificial layer 503 to form a third isolation groove 106, and the third isolation groove 106 is connected between the first isolation groove 104 and the second isolation groove 105.
[0120] It should be noted that while forming the first isolation groove 104, the second isolation groove 105, and the third isolation groove 106, the second isolation layer 64 is also removed.
[0121] Then, a first insulating portion 31 is formed in the first isolation groove 104, and a second insulating portion 32 is formed in the second isolation groove 105.
[0122] The steps of forming the first insulating portion 31 and the second insulating portion 32 further include: forming a third insulating portion 33 in the third isolation groove 106, and the third insulating portion 33 is connected between the first insulating portion 31 and the second insulating portion 32 to constitute the insulating structure 30. Wherein, the insulating structure 30 includes a first material, the substrate 10 includes a second material, and the first material and the second material are different. The first material may include an oxide material or a nitride material, and the second material may include silicon (such as single-crystalline silicon, polycrystalline silicon, doped polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI) or any suitable combination thereof, or a silicon nitride material.
[0123] Specifically, as Figure 22 、 Figure 23 and Figure 24 shown, a covering oxide material layer 3021 is formed on the inner walls of the first isolation groove 104, the second isolation groove 105, and the third isolation groove 106, and the covering oxide material layer 3021 may be a low-temperature oxide layer.
[0124] Then, as Figure 25 、 Figure 26 and Figure 27 shown, a filling oxide material layer 3011 is formed on the side of the first isolation layer 65 away from the substrate 10, and the filling oxide material layer 3011 fills the first isolation groove 104, the second isolation groove 105, and the third isolation groove 106, and covers the side of the first isolation layer 65 away from the substrate 10, and the filling oxide material layer 3011 may be a high-temperature oxide layer.
[0125] Next, as Figure 28 、 Figure 29 and Figure 30As shown, the first spacer layer 65, the filling oxide material layer 3011, and the covering oxide material layer 3021 on the side of the covering layer 12 away from the base layer 11 are removed, and specifically, a chemical mechanical polishing process can be used for removal; then the remaining filling oxide material layer 3011 and the covering oxide material layer 3021 form a filling oxide layer 301 and a covering oxide layer 302, and the filling oxide layer 301 and the covering oxide layer 302 located in the first isolation groove 104 constitute a first insulating portion 31, the filling oxide layer 301 and the covering oxide layer 302 located in the second isolation groove 105 constitute a second insulating portion 32, the filling oxide layer 301 and the covering oxide layer 302 located in the third isolation groove 106 constitute a third insulating portion 33, and the first insulating portion 31, the second insulating portion 32, and the third insulating portion 33 constitute an insulating structure 30.
[0126] In step S20, as Figure 31 shown, the first sacrificial portion 51 is removed to form a first groove 210 in the substrate 10, and the second sacrificial portion 52 is removed to form a second groove 220 in the substrate 10, wherein the length of the first groove 210 along the first direction X is greater than the length of the second groove 220 along the first direction X.
[0127] In step S30, as Figure 3 、 Figure 4 and Figure 5 shown, the first groove 210 and the second groove 220 are filled with a conductive material to form a first wire structure 21 in the first groove 210 and a second wire structure 22 in the second groove 220. The first insulating portion 31 is connected to the end of the first wire structure 21, the second insulating portion 32 is connected to the end of the second wire structure 22, and the length of the first wire structure 21 is greater than the length of the second wire structure 22.
[0128] The sum of the lengths of the first wire structure 21 and the first insulating portion 31 connected to the end of the first wire structure 21 along the first direction X is equal to the sum of the lengths of the second wire structure 22 and the second insulating portion 32 connected to the end of the second wire structure 22 along the first direction X; between an adjacent first wire structure 21 and a second wire structure 22, the first wire structure 21, the first insulating portion 31 connected to the first wire structure 21, the second wire structure 22, the second insulating portion 32 connected to the second wire structure 22, and the third insulating portion 33 connected between the first insulating portion 31 and the second insulating portion 32 form a ring, for example Figure 3 is a square ring in
[0129] Continuing from the above, when preparing the first wire structure 21 and the second wire structure 22 with different lengths in the embodiments of the present application, by providing the first insulating portion 31 and the second insulating portion 32 at the ends of the corresponding regions of the first wire structure 21 and the second wire structure 22, the patterns of the first wire structure 21 and the second wire structure 22 can be pre-defined during the manufacturing process, and the first wire structure 21 and the second wire structure 22 can be obtained by replacement, avoiding the occurrence of poor patterns caused by directly etching the substrate 10 with uneven pattern distribution density, so as to improve the poor phenomena such as uneven and deformed wire structure patterns caused by the etching load effect; and compared with the related art, there is no need to set up dummy traces, which can save the space of semiconductor devices, reduce the spacing between adjacent wire structures, and increase the number of wire structures that can be fabricated.
[0130] For the above object of the present application, embodiments of the present application further provide a storage system. Please refer to Figure 32 , the storage system 70 includes the semiconductor device 71 described in the above embodiments, and the semiconductor device 71 can be a memory or a part of a memory. In the embodiments of the present application, the semiconductor device 71 is taken as an example of a memory for illustration.
[0131] Furthermore, the storage system 70 further includes a controller 72. The controller 72 is coupled to the semiconductor device 71 and is used to control the semiconductor device 71 to store data, and the semiconductor device 71 is a semiconductor device manufactured by the manufacturing method of the semiconductor device described in the above embodiments or the semiconductor device described in the above embodiments.
[0132] Specifically, the controller 72 can control the semiconductor device 71 through the channel CH, and the semiconductor device 71 can perform operations in response to requests from the host 80 based on the control of the controller 72. The semiconductor device 71 can receive a command CMD and an address ADDR from the controller 72 through the channel CH and access the area selected from the storage array in response to the address. In other words, the semiconductor device 71 can perform internal operations corresponding to the command on the area selected by the address.
[0133] In some embodiments, the storage system 70 can be implemented as including but not limited to storage devices such as universal flash storage (UFS) devices, solid state drives (SSD), multimedia cards in the form of MMC, eMMC, RS-MMC, and micro MMC, secure digital cards in the form of SD, mini SD, and micro SD, storage devices of the personal computer memory card international association (PCMCIA) card type, storage devices of the peripheral component interconnect (PCI) type, high-speed PCI (PCI-E) type storage devices, compact flash (CF) cards, smart media cards, or memory sticks, etc.
[0134] Specifically, the above storage system 70 can be applied to terminal products such as computers, televisions, set-top boxes, in-vehicle devices, etc.
[0135] Further, please refer to Figure 33 , some embodiments of the present application further provide an electronic device 90. The electronic device 90 includes the storage system 70, and the storage system 70 is the storage system described in the above embodiments of the present application. Specifically, the electronic device 90 may include, but is not limited to, any device capable of storing data such as mobile phones, desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, wearable devices, mobile power supplies, etc.
[0136] An electronic device provided by some embodiments of the present application, due to the provision of the storage system provided by some embodiments of the present application, has the same beneficial effects as the above storage system.
[0137] In the above embodiments, the descriptions of the various embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.
[0138] The above has introduced in detail a semiconductor device, its manufacturing method, and a storage system provided by the embodiments of the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A semiconductor device, characterized in that, Comprising: A substrate; A first wire structure disposed in the substrate; A second wire structure disposed in the substrate, the length of the first wire structure being greater than the length of the second wire structure; Wherein, the semiconductor device further includes an insulating structure disposed in the substrate, the insulating structure includes a first insulating portion connected to an end of the first wire structure and a second insulating portion connected to an end of the second wire structure, and the insulating structure includes a first material, the substrate includes a second material, and the first material and the second material are different.
2. The semiconductor device according to claim 1, characterized in that, Both the first wire structure and the second wire structure extend in a first direction and are arranged in a second direction, and the first direction and the second direction intersect, and both the first direction and the second direction are perpendicular to the thickness direction of the substrate; Wherein, the first insulating portion is connected to the end of the first wire structure along the first direction, and the second insulating portion is connected to the end of the second wire structure along the first direction.
3. The semiconductor device according to claim 2, characterized in that, The semiconductor device includes a plurality of the first wire structures and a plurality of the second wire structures, and the plurality of the first wire structures and the plurality of the second wire structures are alternately arranged along the second direction; The insulating structure further includes a third insulating portion, and between an adjacent first wire structure and a second wire structure, the third insulating portion is connected between the first insulating portion and the second insulating portion.
4. The semiconductor device according to claim 3, characterized in that, Between an adjacent first wire structure and a second wire structure, the first insulating portion, the second insulating portion and the third insulating portion are an integral structure.
5. The semiconductor device according to claim 3, characterized in that, Between an adjacent first wire structure and a second wire structure, the first wire structure, the first insulating portion connected to the first wire structure, the second wire structure, the second insulating portion connected to the second wire structure, and the third insulating portion connected between the first insulating portion and the second insulating portion form a ring.
6. The semiconductor device according to claim 3, characterized in that, The third insulating portion extends in the second direction.
7. The semiconductor device according to claim 2, characterized in that, The length of the first insulating portion along the first direction is less than the length of the second insulating portion along the first direction.
8. The semiconductor device according to claim 2, characterized in that, The sum of the lengths of the first wire structure and the first insulating portion connected to the end of the first wire structure along the first direction is equal to the sum of the lengths of the second wire structure and the second insulating portion connected to the end of the second wire structure along the first direction.
9. The semiconductor device according to claim 1, characterized in that, The insulating structure includes a filling oxide layer and a covering oxide layer between the filling oxide layer and the substrate, and the second material includes a silicon material.
10. A method for manufacturing a semiconductor device, characterized in that, Including the following steps: Forming a first sacrificial portion, a second sacrificial portion, and an insulating structure in the substrate, the insulating structure is formed with a first insulating portion connected to an end of the first sacrificial portion and a second insulating portion connected to an end of the second sacrificial portion, and the insulating structure includes a first material, the substrate includes a second material, and the first material and the second material are different; Remove the first sacrificial portion to form a first groove in the substrate, and remove the second sacrificial portion to form a second groove in the substrate; Form a first wire structure in the first groove and a second wire structure in the second groove. The first insulating portion is connected to the end of the first wire structure, the second insulating portion is connected to the end of the second wire structure, and the length of the first wire structure is greater than the length of the second wire structure.
11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, The steps of forming the first sacrificial portion, the second sacrificial portion, and the insulating structure in the substrate include: Form a first intermediate groove and a second intermediate groove in the substrate; Form a first sacrificial layer in the first intermediate groove and a second sacrificial layer in the second intermediate groove; Remove part of the first sacrificial layer to form a first isolation groove and remove part of the second sacrificial layer to form a second isolation groove. The remaining first sacrificial layer forms the first sacrificial portion, the first isolation groove is formed at the end of the first sacrificial portion, the remaining second sacrificial layer forms the second sacrificial portion, and the second isolation groove is formed at the end of the second sacrificial portion; Form a first insulating portion in the first isolation groove and a second insulating portion in the second isolation groove.
12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, The steps of forming the first intermediate groove and the second intermediate groove in the substrate include: Form a plurality of the first intermediate grooves extending in a first direction and arranged in a second direction, a plurality of the second intermediate grooves extending in the first direction and arranged in the second direction, and a plurality of third intermediate grooves extending in the second direction in the substrate. The first direction and the second direction intersect, both the first direction and the second direction are perpendicular to the thickness direction of the substrate, and the plurality of the first intermediate grooves and the plurality of the second intermediate grooves are alternately arranged in the second direction; Wherein, the third intermediate groove is connected between the first intermediate groove and the second intermediate groove, and an adjacent first intermediate groove, an adjacent second intermediate groove, and two of the third intermediate grooves connected between the adjacent first intermediate groove and the adjacent second intermediate groove form an annular groove.
13. The method for manufacturing a semiconductor device according to claim 12, wherein, The steps of forming the first sacrificial layer in the first intermediate groove and the second sacrificial layer in the second intermediate groove further include: Form a third sacrificial layer in the third intermediate groove, and the third sacrificial layer is connected between the first sacrificial layer and the second sacrificial layer.
14. The method for manufacturing a semiconductor device according to claim 13, wherein, The steps of removing part of the first sacrificial layer to form the first isolation groove and removing part of the second sacrificial layer to form the second isolation groove include: Remove part of the first sacrificial layer, part of the second sacrificial layer, and the third sacrificial layer to form the first isolation groove, the second isolation groove, and the third isolation groove respectively, and the third isolation groove is connected between the first isolation groove and the second isolation groove.
15. The method for manufacturing a semiconductor device according to claim 14, wherein, The steps of forming the first insulating portion in the first isolation groove and the second insulating portion in the second isolation groove further include: A third insulating portion is formed in the third isolation groove, and the third insulating portion is connected between the first insulating portion and the second insulating portion to constitute the insulating structure.
16. A storage system, wherein, The storage system includes a controller and a semiconductor device according to any one of claims 1 to 9, or a semiconductor device manufactured by a manufacturing method of a semiconductor device according to any one of claims 10 to 15. The controller is coupled to the semiconductor device and is configured to control the semiconductor device to store data.