Package structure, package system, and method of forming package structure

Abstract

The disclosure provides a package structure, a package system, and a method of forming a package structure. A package structure may include a first layer having at least one transistor, a second layer on a first side of the first layer, the second layer including a signal layer. The third layer may be on a second side of the first layer, the second side being opposite the first side of the first layer, the third layer may include a power supply layer. A stack may be coupled to the second layer, the stack including a first device row and a second device row. Each of the first and second device rows may include at least one device, such as a computing device. The second device row may be mounted on the first device row, the devices in the first device row may be different from the devices of the second device row.

Description

Technical Field

[0001] The subject matter disclosed herein relates to microelectronic packaging and integrated circuit (IC) packaging. More specifically, the subject matter disclosed herein relates to modular packaging architectures. Background Art

[0002] Semiconductor devices can be connected to additional devices and circuits on different substrates. Forming connections between substrates can provide increased computing. However, forming connections between substrates can lead to complications. Packaging describes a general method for connecting multiple computing components together and integrating them in an integrated unit, and can involve various different types of integrated circuits on multiple substrates that can be combined into a single unit. Packaging can also describe methods for protecting multiple computing components within a single unit by using various techniques that provide thermal protection, physical protection, and electrical protection. The concepts of the background art discussed herein are for informational purposes only and are not intended to limit the present disclosure. The background art or field described herein should also not be intended to limit the present disclosure to a particular use or concept. Summary of the Invention

[0003] Example embodiments provide a packaging structure that includes a first layer having at least one transistor, a second layer on a first side of the first layer, the second layer including a signal layer. A third layer can be on a second side of the first layer, the second side being opposite the first side of the first layer, the third layer can include a power layer. A stack can be coupled to the second layer, the stack including a first device row and a second device row. Each of the first device row and the second device row can include at least one device, such as a computing device. The second device row can be mounted on the first device row, and the devices in the first device row can be different from the devices in the second device row. The first device row can include processing devices. The second device row can include storage devices. The storage devices in the second device row can be mounted on top of the processing devices or another type of device. The storage devices can be dynamic random access memory devices. The first device row can include at least one type of device. The first device row can include at least one device other than storage devices or processing devices. The stack can be mounted on the signal layer.

[0004] An exemplary embodiment provides a packaging system that includes a substrate including a logic layer. A first layer including a first row of devices may be on the substrate. A second layer including a second row of devices may be disposed on the first layer, and the second row of devices may be coupled to the first row of devices. A third layer including a third row of devices may be disposed on the second layer, and the third row of devices may be coupled to the second row of devices. Each of the first row of devices, the second row of devices, and the third row of devices may include at least one device. The device composition of the first row of devices may be different from the device composition of the second row of devices. The device composition of the third row of devices may be substantially the same as the device composition of the second row of devices. The substrate may include a power layer and a signal layer, the power layer being coupled to the logic layer and the logic layer being coupled to the signal layer. The power layer and the signal layer may be coupled to the first layer. The first row of devices may include processing devices. The second row of devices may include storage devices.

[0005] An exemplary embodiment provides a method of forming a packaging structure, the method including: forming a transistor layer including at least one transistor on a first side of a first substrate; forming a signal layer on the transistor layer, the signal layer being communicatively coupled to the transistor layer; forming a power layer on a second side of the first substrate, the second side of the first substrate being opposite the first side, the power layer being electrically coupled to the transistor layer; bonding a first row of devices to the signal layer; and bonding a second row of devices to the first row of devices. In some embodiments, bonding the first row of devices to the signal layer may include depositing a dielectric layer, patterning vias in the dielectric layer, and heating the first row of devices and the signal layer together to bond the first row of devices and the signal layer. In some embodiments, the device composition of the second row of devices may be different from the device composition of the first row of devices. In some embodiments, a third row of devices may be bonded to the second row of devices, the third row of devices having the same device composition as the second row of devices. In some embodiments, forming a signal layer on the transistor layer includes forming a redistribution layer on a surface of the signal layer, and bonding the first row of devices to the signal layer includes: depositing a first dielectric layer over the redistribution layer; patterning the first dielectric layer to expose an exposed portion of the redistribution layer; mounting conductive contacts of the first row of devices on the exposed portion of the redistribution layer; and performing a thermal process to bond the exposed portion of the redistribution layer to the conductive contacts of the first row of devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the following sections, aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments shown in the drawings, in which:

[0007] Figure 1A Cross-sectional views of exemplary embodiments of a packaging structure according to various embodiments of the subject matter disclosed herein are drawn;

[0008] Figure 1BDraw an enlarged cross-sectional view of an exemplary embodiment of a packaging structure according to various embodiments of the subject matter disclosed herein;

[0009] Figure 2 Draw an enlarged cross-sectional view of an exemplary embodiment of a packaging structure according to various embodiments of the subject matter disclosed herein;

[0010] Figure 3 Draw a cross-sectional view of an exemplary embodiment of a component of a packaging structure according to various embodiments of the subject matter disclosed herein;

[0011] Figure 4A Draw a cross-sectional view of an exemplary embodiment of a component of a packaging structure at a first time according to various embodiments of the subject matter disclosed herein;

[0012] Figure 4B Draw a cross-sectional view of an exemplary embodiment of a component of a packaging structure at a second time according to various embodiments of the subject matter disclosed herein;

[0013] Figure 4C Draw a cross-sectional view of an exemplary embodiment of a component of a packaging structure at a third time according to various embodiments of the subject matter disclosed herein;

[0014] Figure 4D Draw a cross-sectional view of an exemplary embodiment of a component of a packaging structure at a fourth time according to various embodiments of the subject matter disclosed herein;

[0015] Figure 4E Draw a cross-sectional view of an exemplary embodiment of a component of a packaging structure at a fifth time according to various embodiments of the subject matter disclosed herein;

[0016] Figure 4F Draw a cross-sectional view of an exemplary embodiment of a component of a packaging structure at a sixth time according to various embodiments of the subject matter disclosed herein;

[0017] Figure 4G Draw a cross-sectional view of an exemplary embodiment of a component of a packaging structure at a seventh time according to various embodiments of the subject matter disclosed herein;

[0018] Figure 4H Draw a cross-sectional view of an exemplary embodiment of an assembled packaging structure at an eighth time according to various embodiments of the subject matter disclosed herein;

[0019] Figure 4I Draw a cross-sectional view of an exemplary embodiment of a component of a packaging structure at a ninth time according to various embodiments of the subject matter disclosed herein;

[0020] Figure 4JDraw a cross-sectional view of an example embodiment of a package structure component at the tenth time according to various embodiments of the subject matter disclosed herein;

[0021] Figure 4K Draw a cross-sectional view of an example embodiment of a package structure component at the eleventh time according to various embodiments of the subject matter disclosed herein;

[0022] Figure 4L Draw a cross-sectional view of an example embodiment of a package structure component at the twelfth time according to various embodiments of the subject matter disclosed herein;

[0023] Figure 5 Draw an example embodiment of a method of forming a package structure according to various embodiments of the subject matter disclosed herein;

[0024] Figure 6A Draw a cross-sectional view of an example embodiment of a package structure component according to various embodiments of the subject matter disclosed herein; and

[0025] Figure 6B Draw an enlarged cross-sectional view of an example embodiment of a package structure component according to various embodiments of the subject matter disclosed herein. Detailed Description

[0026] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, those skilled in the art will understand that the aspects disclosed herein may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the subject matter disclosed herein.

[0027] References to "one embodiment" or "an embodiment" in the present specification mean that a particular feature, structure, or characteristic described in connection with that embodiment can be included in at least one embodiment disclosed herein. Thus, the phrases "in one embodiment," "in an embodiment," "according to one embodiment" (or other phrases with similar meanings) that appear throughout the present specification may not necessarily all refer to the same embodiment. In addition, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" should not be construed as necessarily being preferred or advantageous over other embodiments. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Further, depending on the context discussed herein, singular terms may include the corresponding plural forms, and plural terms may include the corresponding singular forms. Similarly, hyphenated terms (e.g., "two-dimensional," "pre-determined," etc.) may occasionally be used interchangeably with their corresponding non-hyphenated versions (e.g., "two dimensional," "predetermined," etc.), and capitalized entries (e.g., "Integrated Circuit," "First Substrate," "CMOS," etc.) may be used interchangeably with their corresponding non-capitalized versions (e.g., "integrated circuit," "first substrate," "cmos," etc.). Such occasional interchangeable use should not be considered inconsistent with each other.

[0028] In addition, depending on the context discussed herein, singular terms may include the corresponding plural forms, and plural terms may include the corresponding singular forms. It should also be noted that the various figures (including component diagrams) shown and discussed herein are for illustrative purposes only and are not drawn to scale. For example, for clarity, the dimensions of some elements may be exaggerated relative to other elements. Additionally, if deemed appropriate, reference numerals are repeated among the figures to indicate corresponding and / or similar elements.

[0029] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the claimed subject matter. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprises" and / or "comprising" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0030] It will be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, directly connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. The same reference numerals always refer to the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used herein, coupling may refer to electrical coupling, communication coupling, physical coupling, and / or thermal coupling of objects.

[0031] As used herein, the terms "first", "second", etc. are used as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless explicitly so defined. Additionally, the same reference numerals may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functionality. However, such use is merely for the purpose of simplifying the illustration and facilitating discussion; it does not mean that the construction or architectural details of such components or units are the same in all embodiments, or that such commonly referenced parts / modules are the only way to implement some of the example embodiments disclosed herein.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted as having an idealized or overly formal meaning unless expressly so defined herein.

[0033] As used herein, a substrate may refer to a variety of materials and structures, including wafers using silicon, wafers using silicon-on-insulator (SOI) (such as glass), wafers of other semiconductor materials (such as germanium), and other semiconductor materials on an insulator. In some embodiments, the substrate may include organic materials. In some embodiments, the substrate may be referred to as a wafer, die, and chip individually or in combination. Thus, in some embodiments, a bonding substrate may be referred to as die-to-die (D2D) bonding, wafer-to-wafer (W2W) bonding, or die-to-wafer (D2W) bonding. In some embodiments, the substrate may contain circuitry, such as integrated circuits, including a central processing unit (CPU), logic chips, memory (such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate DRAM or DDR DRAM), application processor (AP), graphics processing unit (GPU), other forms of auxiliary processing units (xPU), artificial intelligence (AI) chips, high bandwidth memory (HBM) interfaces, and other application specific integrated circuits (ASIC). In some embodiments, a combination of circuitry may be present on the substrate. In some embodiments, the substrate may include packaged chips.

[0034] As used herein, packaging refers to the process of forming interconnections between substrates. In some embodiments, the interconnections may be between direct surfaces and involve W2W, D2D, and D2W bonding. In other embodiments, techniques including wire bonding and other forms of indirect bonding may be performed individually or in combination with W2W, D2D, and D2W bonding. In some embodiments, the circuits may be bonded directly facing each other, while in other embodiments, flip chip bonding may be used. In some embodiments, the interconnections may be made between substrates on the front side or circuit side of the substrate. In other embodiments, the interconnections may be made on the back side or rear side of the substrate opposite the circuit structure. In some embodiments, the interconnections may include through-silicon vias (TSV) or other forms of through-chip vias, where one or more substrates may be connected using vias extending through an interposer (such as another substrate or chip). In some embodiments, the interconnections may be formed using connections (such as pads) on the surface of the substrate, and additional materials (such as solder) may be used between the pads to form the interconnections.

[0035] As used herein, a conductor can refer to various conductive materials, including materials that can be used alone or in combination with other materials (such as in the form of an alloy). In some embodiments, the conductor is copper (Cu). In some embodiments, the copper (Cu) can be in the form of Cu(II), Cu(III), or other forms of copper, alone or in combination with other elements (including cobalt (Co) and ruthenium (Ru)). Such a list of elements is not intended to be exhaustive, and in other embodiments, any other known type of conductive material can be used.

[0036] As used herein, a dielectric can refer to various materials, including various forms of silicon, such as silicon oxide including SiO2, silicon nitride including SiN, and silicon carbonitride including SiCN. In some embodiments, the dielectric material can be referred to as an electrical insulating material, an insulating region, or an insulator. In some embodiments, the amount of insulation provided can be relative to another material (which can be referred to as a conductive material or a conductor).

[0037] As used herein, a chiplet can refer to an integrated circuit with a well-defined function, such as a microprocessor, a memory device, or other computing functions; modular design is achieved using chiplets, and multiple chiplets can be combined with a larger package, sharing a substrate or an interposer to form a larger device. A core can refer to a single unit of a multi-core device, where multiple devices form a larger device, and each device can independently function to enable multiple operation streams. In some embodiments, a core can take the form of a chiplet, or a chiplet can take the form of a core. However, in other embodiments, a chiplet can take the form of any other suitable integrated circuit. Devices, computing devices, and dies can be used herein to refer to chiplets, or vice versa.

[0038] Various embodiments of apparatuses, systems, and methods related to a packaging architecture are disclosed herein for modularly creating stacked logic and a building block architecture using hybrid bonding. The stacked logic and building block architecture can include a base die that provides logic, wiring, and power delivery to a memory stack. As used herein, a stack can refer to a certain combination of processing devices, memory devices, and support circuit architectures, such as chiplets and dies containing individual elements, memory dies, support processing units, I / O circuits, and other forms of integrated chips. As used herein, device composition can refer to which devices are used within a row, a system, or other objects. A stack can also be referred to as a device stack, a die stack, or a chiplet stack.

[0039] In some embodiments, a backside power delivery network (BSPDN) can be formed on the backside of a substrate, and a signal network can be formed on the front side of the same substrate. In some embodiments, the layer containing the BSPDN can be referred to as a power layer. In some embodiments, the BSPDN and the signal network can be formed on separate substrates and transferred to the same substrate. The BSPDN and the signal network can be separated by a transistor layer. The transistor layer can include a plurality of transistors. The transistors can provide different functions and take different forms, including a logic layer. The BSPDN and the signal network can form a single monolithic structure on the same die in a semiconductor foundry process. The stacked module can be formed in a separate semiconductor foundry process, or it can be formed as other components in the same semiconductor foundry process, or it can have multiple components formed in multiple semiconductor foundry processes and assembled in a package assembly process.

[0040] Figure 1A An exemplary embodiment of a package architecture 100 is depicted that integrates a base die 104 using backside power delivery with a die stack 102. In the package architecture 100, the die stack 102, which consists of multiple layers of devices or dies, is coupled to the base die 104 having a power layer and a signal layer and is mounted in a stacked form on a support substrate 106, as Figure 1B shown. The devices in the die stack 102 can include computing devices, processing devices, network devices, storage devices, and other types of devices. In some embodiments, the base die 104 can be a silicon die, while in other embodiments, various semiconductor materials can be used.

[0041] The die stack 102 can include multiple layers, including a first stacked layer 110, a second stacked layer 120, and a third stacked layer 130. Each of the first stacked layer 110, the second stacked layer 120, and the third stacked layer 130 can include one or more devices. The number of stacked layers and the number of devices in each stacked layer can vary. Although in Figure 1A and Figure 1B the exemplary embodiments, the first stacked layer 110, the second stacked layer 120, and the third stacked layer 130 are shown as being the same, in other embodiments, the number and / or type of devices in at least one stacked layer can be different from the number and / or type of devices in another stacked layer.

[0042] The first stacked layer 110 includes a first device 112, a second device 114, and a third device 116. The second stacked layer 120 includes a fourth device 122, a fifth device 124, and a sixth device 126. The third stacked layer 130 includes a seventh device 132, an eighth device 134, and a ninth device 136. The devices within each stacked layer can include dies (such as chips) and support circuitry (such as other forms of ICs, which can also be in the form of dies or devices). For example, dies (such as processors, processing cores, processor devices, or memory dies) and power distribution, wiring, and I / O dies for the die stack 102 can be included within the stacked layers. The devices used within each stacked layer can be relatively thin, having a thickness of, for example, 20 - 30 microns, up to 50 microns. In some embodiments, the devices in each stacked layer can be even thinner, but in some embodiments, the thickness can be greater or smaller.

[0043] In some embodiments, the first stacked layer 110 can include a first support dielectric layer 174, which can form the sides of the first stacked layer 110. The first support dielectric layer 174 can include a dielectric material and can form a structural and thermal support as part of the first stacked layer 110. In some embodiments, the second stacked layer 120 can include a second support dielectric layer 176, which can form the sides of the second stacked layer 120. The second support dielectric layer 176 can include a dielectric material and can form a structural and thermal support as part of the second stacked layer 120. In some embodiments, the third stacked layer 130 can include a third support dielectric layer 178, which can form the sides of the third stacked layer 130. The third support dielectric layer 178 can include a dielectric material and can form a structural and thermal support as part of the third stacked layer 130.

[0044] The small chip stack 102 may include multiple bonding layers to connect the stacked layers and provide mechanical, electrical, and thermomechanical connections between the stacked layers. The bonding layers may include a variety of materials, including dielectric materials, and may also include metallic materials. In some embodiments, the bonding layers may include bonds between conductive materials at the surface layers and bonds between dielectric materials at the surface layers. In some embodiments, the bonding process may be a hybrid bonding process in which both dielectric regions and conductive regions are bonded together between the stacked layers. In some embodiments, fusion bonding may be used to bond the dielectric regions together. In some embodiments, hybrid bonding may bond the conductive regions at high temperature conditions while the dielectric portions may be bonded at a temperature closer to room temperature. In some embodiments, the material surrounding the thin die / device may include a dielectric layer having a thickness of, for example, 20 - 30 microns and may extend up to 50 microns (the same or similar thickness as the die / device), but in other embodiments, the dielectric layer may vary in size. In some embodiments, the thickness of the stacked layers and the thickness of the bonding layers may be substantially the same, while in other embodiments, they may vary.

[0045] The first bonding layer 118 may form the substrate of the small chip stack 102, and the first stacked layer 110 is held fixed to the substrate chip 104 using the first bonding layer 118. The first bonding layer 118 may include a first set of conductive contacts 119 that provide interconnection between the devices of the substrate chip 104 and the first stacked layer 110. In some embodiments, the first set of conductive contacts 119 may be aligned with TSVs or other forms of vias passing through the first stacked layer 110.

[0046] The second bonding layer 128 may form the substrate of the second stacked layer 120, hold the second stacked layer 120 in place, and connect it to the first stacked layer 110. The second bonding layer 128 may include a second set of conductive contacts 129 that provide interconnection between the devices of the first stacked layer 110 and the devices of the second stacked layer 120. In some embodiments, the second set of conductive contacts 129 may be aligned with TSVs or other forms of vias passing through the second stacked layer 120.

[0047] The third bonding layer 138 may form the substrate of the third stacked layer 130, hold the third stacked layer 130 in place, and connect it to the second stacked layer 120. The third bonding layer 138 may include a third set of conductive contacts 139 that provide interconnection between the devices of the second stacked layer 120 and the devices of the third stacked layer 130. In some embodiments, the third set of conductive contacts 139 may be aligned with TSVs or other forms of vias passing through the third stacked layer 130.

[0048] In addition, the first bonding layer 118 couples the die stack 102 to the base die 104 at the redistribution layer 150. The redistribution layer 150 is coupled to the signal network layer 152, which in turn is coupled to the transistor layer 154. The redistribution layer 150 may include a series of pads, lines, traces, and other forms of connections that form the top surface of the base die 104. The redistribution layer 150 allows the connections between the die stack 102 and the base die 104 to spread from where the lines and vias may appear on the surface of the signal section, allowing for the formation of additional space for connections and providing additional space to prevent unintentional connections.

[0049] The signal network layer 152 may include a network-on-chip (NOC) and may provide interconnections to transmit signals to and from the die stack 102. In some embodiments, the signal network layer 152 may provide packet routing. In some embodiments, the signal network layer 152 may include multiple layers, including multiple layers that provide signal routing. In some embodiments, the signal network layer 152 may include a plurality of conductive channels within a dielectric material, the plurality of conductive channels may be arranged in multiple layers, and the size of the conductive channels decreases as they approach the transistor layer 154. In some embodiments, the signal network layer 152 may have a plurality of conductive channels and may include 15 - 20 signal layers that include the conductive channels. In some embodiments, the conductive channels may be a conductive material, such as a metal, including copper. In some embodiments, the size of the conductive channels in the top layer of the signal network layer 152 may increase as the distance from the transistor layer 154 increases, while in other embodiments, the size of the conductive channels may be constant.

[0050] The transistor layer 154 separates the signal network layer 152 from the BSPDN layer 158 and includes a plurality of transistors. As used herein, the transistor layer 154 can be used to refer to both the layer containing the plurality of transistors and the plurality of transistors. In some embodiments, the transistor layer 154 can serve as the underlying logic for both the signal network layer 152 and the BSPDN layer 158. In other embodiments, the transistor layer 154, together with the signal network layer 152 and the BSPDN layer 158, provides the underlying logic for the die stack 102. The BSPDN layer 158 provides a power delivery network for routing the power lines 156 on the back side of the transistor layer 154 and can supply both a power supply voltage and a reference voltage to the transistors in the transistor layer 154. The BSPDN layer 158 can include multiple different layers of power lines 156 for power routing within an insulating material. In some embodiments, the insulating material can include a dielectric material. In some embodiments, the BSPDN layer 158 can include 4 to 6 layers of power lines 156. In some embodiments, the size of the power lines 156 can decrease as they approach the transistor layer 154. The power lines 156 can be composed of a conductive material, including various forms of low-resistance metals such as copper, and optionally or additionally, the conductive material can include various forms of other conductive materials, including doped carbon. The support substrate dielectric layer 172 can form the sides of the base die 104. The support substrate dielectric layer 172 can be composed of a dielectric material and can extend from the support substrate 106 to the first stack layer 110.

[0051] The dielectric layer 160 forms the bottom of the BSPDN layer 158 and, in some embodiments, may include vias with plugs to couple the BSPDN layer 158 to the support substrate 106 using the interconnect 108. In some embodiments, multiple plugs and vias may be used to couple the BSPDN layer 158 to the support substrate 106. The interconnect 108 may include, individually or in combination, pads, bumps, micro-bumps, pillars, balls, and other forms (such as controlled collapse chip connection (C4) bumps). As used herein, a C4 bump refers to a form of solder bump on a pad on the top surface of a substrate before flipping the substrate to form a flip chip. In some embodiments, the interconnect 108 may also include a dielectric material, which may include materials such as adhesives, resins, or elastomers, which may form a connection between the BSPDN layer 158 and the support substrate 106 in addition to the conductive connection. In some embodiments, a combination of conductive and dielectric connections may form a hybrid bond. The support substrate 106 may in turn be connected to other devices and dies, and in some embodiments, may take the form of an interposer. In some embodiments, an underfill material 180 may be injected between the dielectric layer 160 and the support substrate 106. In some embodiments, the underfill material 180 may be a dielectric material and may form a hybrid bond along one or more of the conductive connections in the interconnect 108.

[0052] Figure 2 An example embodiment of a package structure 200 depicting a package that includes multiple device arrays integrated in one package is shown. In Figure 2 this case, Figure 1A unlike Figure 1B above, multiple packages (including a first package 210 and a second package 220) may be provided on the support substrate 106. The first package 210 and the second package 220 may take the form of any package disclosed herein, including the package architecture 100. The first package 210 and the second package 220 may be assembled separately or together, and then the first package 210 may be connected to the support substrate 106 using a first interconnect 212, and the second package 220 may be connected to the support substrate 106 using a second interconnect 222. The first interconnect 212 and the second interconnect 222 may include, individually or in combination, pads, bumps, micro-bumps, pillars, balls, and other forms (such as C4 bumps). In some embodiments, the first interconnect 212 and the second interconnect 222 may also include one or more dielectric materials, such as an underfill material or any other suitable material.

[0053] In Figure 2In this case, an encapsulation structure 202 is formed over and around a first package 210 and a second package 220. The encapsulation structure 202 can be made of, for example, a nickel-plated copper lid or a heat slug or additive manufacturing. An additional layer of thermal interface material 204 can be used to directly bond the encapsulation structure 202 to the first package 210 and the second package 220 for thermal dissipation purposes. In some embodiments, the encapsulation structure 202 can additionally seal the first package 210 and the second package 220. In some embodiments, the encapsulation structure 202 can be partially or fully open, and the partially open form of the encapsulation structure 202 can, for example, allow air flow to transfer heat from the first package 210 and the second package 220. In some embodiments, the encapsulation structure 202 can provide mechanical support for the first package 210 and the second package 220 and can provide protection against mechanical deformation, drop impact, etc. In some embodiments, an underfill material 230 can be injected between the first package 210, the second package 220, and the support substrate 106. In some embodiments, the underfill material 230 can be a dielectric material and can be used to form a dielectric bond. In some embodiments, a hybrid bond can be formed by a combination of a metal bond and a dielectric bond, such as one or more of the first interconnect 212, the second interconnect 222, and the underfill material 230 and other suitable materials.

[0054] Figure 3 An example embodiment of a supported interposer structure 300 is depicted. In Figure 3 this case, a plurality of packages, including a third package 310 and a fourth package 320, are provided on a support substrate 106 via an interposer 308. The third package 310 and the fourth package 320 can take the form of any of the packages disclosed herein, including the package architecture 100. The third package 310 and the fourth package 320 can be assembled separately or together, and then the third package 310 can be connected to the interposer 308 using a third interconnect 312 and the fourth package 320 can be connected to the interposer 308 using a fourth interconnect 322. The third interconnect 312 and the fourth interconnect 322 can individually or in combination include pads, bumps, micro-bumps, pillars, balls, and other forms (such as C4 bumps). The interposer 308 can take the form of a substrate having additional interconnects, traces, and circuits on which the third package 310 and the fourth package 320 are mounted. Additionally, stiffeners, shown in the form of a first stiffener 302 and a second stiffener 304, can be provided on the support substrate 106 to provide additional mechanical support. In some embodiments, an underfill material 230 can be injected between the third package 310, the fourth package 320, and the interposer 308.

[0055] Figures 4A to 4LIllustrate an illustrative embodiment of the encapsulation process of the stacked component 400. Figure 5 Illustrate a process 500 for forming a stack of illustrative embodiments corresponding to Figures 4A to 4L The stacked component 400 may take the form of the encapsulation architecture 100.

[0056] Figure 4A Illustrate forming a transistor layer 402 on the first substrate 404 at S510 in Figure 5 In some embodiments, the transistor layer 402 may be the transistor layer 154. The transistor layer 402 may be formed using complementary metal oxide semiconductor (CMOS) processes such as deposition, lithography, etching, passivation, etc. In some embodiments, the first substrate 404 may be a silicon wafer, and in other embodiments, the first substrate 404 may include other semiconductor materials such as germanium, or may take the form of other substrates such as organic substrates or even SOI substrates such as glass. In some embodiments, the first substrate 404 may be a sacrificial substrate. The transistor layer 402 and the structures directly built on the transistor layer 402 may be referred to as the front-side layer.

[0057] Figure 4B Illustrate Figure 5 forming a signal network layer 406 on the transistor layer 402 at S515 in

[0058] Figure 4C Illustrate Figure 5 bonding a first carrier wafer 412 to the signal network layer 406 at S520 in Figure 4C Then the first substrate 404 may be completely or partially removed, Figure 4C showing the remaining portion of the first substrate 404 present on the transistor layer 402, also referred to herein as the remaining substrate layer. The first substrate 404 may be completely or partially removed using various processes, including grinding, polishing, etching, and lift-off processes, including chemical mechanical polishing (CMP). Any remaining portion of the first substrate 404 (e.g., as Figure 4CAs shown, it can be planarized to provide a flat surface suitable for additional CMOS processing. The first carrier wafer 412 can be bonded, for example, using an adhesive layer to directly bond to the signal network layer 406. In some embodiments, the first carrier wafer 412 can be used as a carrier wafer and can be suitable for use at temperatures up to a threshold temperature. In some embodiments, the threshold temperature can be about 400 °C, while in other embodiments, the threshold temperature can be greater or less.

[0059] Figure 4D Shown at Figure 5 S525 in forms the BSPDN layer 410 on the back side of the transistor layer 402. In some embodiments, the BSPDN layer 410 is formed using CMOS processing. The BSPDN layer 410 can be formed by directly building on the back side of the transistor layer 402 by depositing additional materials on the remaining substrate layer, or can be formed in the first substrate 404 by performing patterning steps (such as lithography and etching) to build trenches, vias, and holes within the remaining substrate layer. In some embodiments, the BSPDN layer 410 can be formed by directly building on the first substrate 404 and performing patterning steps to build both within the first substrate 404. In some embodiments, multiple power layers can be formed, each layer stacked on the previous layer. In some embodiments, the BSPDN layer 410 can be fabricated on a separate substrate and transferred to the back side of the transistor layer 402. In some embodiments, the BSPDN layer 410 can be provided as a multi-layer structure. In some embodiments, the BSPDN layer 410 can be provided as the aforementioned BSPDN layer 158. In some embodiments, the BSPDN layer 410, the transistor layer 402, and the signal network layer 406 can together form a base chip 420, which can be substantially similar to Figure 1A and Figure 1B the base chip 104 in.

[0060] Figure 4E Shown at Figure 5At S530 therein, the first carrier wafer 412 is separated from the substrate chip 420, which can be done, for example, by using one or more of layer peeling, chemical peeling, thermal peeling, and photo peeling techniques to peel the adhesive layer that bonds the first carrier wafer 412 to the substrate chip 420. Additionally, on top of the substrate chip 420, a first dielectric layer 430 and a first conductive layer 432 are formed using CMOS processing steps. The CMOS processing steps can include deposition, etching, patterning, lithography, and any other suitable steps. The first dielectric layer 430 can directly contact the signal network layer 406, and the first conductive layer 432 can form a redistribution layer that includes pads, vias, and other suitable forms of interconnections for additional mounting. In some embodiments, a portion of the surface of the first dielectric layer 430 can be patterned to expose the exposed portion of the first conductive layer 432.

[0061] Figure 4F Shown at Figure 5 At S535 therein, the substrate chip 420 is bonded to the second carrier wafer 422. The second carrier wafer 422 can be a silicon wafer, a glass substrate, or any other form of substrate suitable for the processing conditions. In some embodiments, the second carrier wafer 422 can have a release layer deposited on the surface of the second carrier wafer 422 before bonding the substrate chip 420. The substrate chip 420 can be bonded such that the BSPDN layer 410 contacts the second carrier wafer 422 or the release layer. In some embodiments, the second carrier wafer 422 can be bonded to the substrate chip 420 at S535 before the separation of the first carrier wafer 412 at S530.

[0062] Figure 4G Shown at Figure 5 At S540 therein, a first insulating layer 434 is deposited on top of the second carrier wafer 422. The first insulating layer 434 can be thick enough to extend the vertical height of the substrate chip 420. In some embodiments, the first insulating layer 434 can cover the first dielectric layer 430, and some or all of the first insulating layer 434 can be removed from the surface of the first dielectric layer 430, for example, by patterning, grinding, etching, and other forms of CMOS processing.

[0063] Figure 4H Shown at Figure 5At S545 therein, the first device row 435 is mounted on the surfaces of the first dielectric layer 430 and the first conductive layer 432. The first device row 435 includes a first device 436, a second device 437, and a third device 439, which may be memory devices or core processing dies, as well as other forms of die and circuitry as described herein. The first device row 435 is bonded to the base die 420 via a hybrid bonding process. In the hybrid bonding process, the first dielectric layer 430 is bonded to corresponding dielectric components within the first device 436, the second device 437, and the third device 439 via fusion bonding, while the first conductive layer 432 provides a metal bond between the conductive material of the first conductive layer 432 and the corresponding pads, vias, and other metal contacts of the first device row 435. Thermal processes or heat treatments may use heat in the hybrid bonding process to allow the dielectric portions and / or conductive portions to bond. One or more of the devices in the first device row 435 may have TSVs or other forms of vias that extend vertically along the entire height of the first device row 435. The vias may be formed before the placement of the devices in the first device row 435, after the placement of the devices in the first device row 435, or in some combination thereof.

[0064] Figure 4I Shown at Figure 5 At S550 therein, a second insulating layer 444 is deposited over the first insulating layer 434. The second insulating layer 444 may have substantially the same thickness as the first device row 435. In some embodiments, the second insulating layer 444 may cover the first device row 435, and some or all of the second insulating layer 444 may be removed, for example, by patterning, grinding, etching, and other forms of CMOS processing, so as not to cover the first device row 435.

[0065] Figure 4J Shown at Figure 5 At S555 therein, the process for the second device row 445 is shown, where a second dielectric layer 440 and a second conductive layer 442 are deposited on the first device row 435. The second dielectric layer 440 and the second conductive layer 442 may be subjected to CMOS processing steps to create the interconnects for the second device row 445 to be mounted thereon, where a fourth device 446, a fifth device 447, and a sixth device 449 are mounted and coupled to the first device row 435. The devices of the second device row 445 may be memory devices or core processing dies, as well as other forms of die and circuitry as described herein. One or more of the devices in the second device row 445 may have TSVs or other forms of vias that extend vertically along the entire height of the second device row 445. The vias may be formed before the placement of the devices in the second device row 445, after the placement of the devices in the second device row 445, or in some combination thereof.

[0066] In some embodiments, the second device row 445 can be bonded to the first device row 435 via a hybrid bonding process (e.g., where the second dielectric layer 440 is bonded to corresponding dielectric components within the fourth device 446, fifth device 447, and sixth device 449 via fusion bonding, and the second conductive layer 442 provides a metal bond between the conductive material of the second conductive layer 442 and the corresponding pads, vias, and other metal contacts of the second device row 445). A thermal process or heat treatment can use heat in the hybrid bonding process to allow the dielectric portions and / or conductive portions to bond. A third insulating layer 454 can be deposited over the second insulating layer 444. In some embodiments, the third insulating layer 454 can have a thickness substantially the same as that of the second device row 445. In some embodiments, the third insulating layer 454 can cover the second device row 445, and some or all of the third insulating layer 454 can be removed from the surface of the second device row 445, for example, by patterning, grinding, etching, and other forms of CMOS processing.

[0067] Figure 4K Illustrated at Figure 5 S560 in the process for the third device row 455, which is substantially similar to the process at S555, where the third dielectric layer 450 and the third conductive layer 452 are deposited on the second device row 445. The third dielectric layer 450 and the third conductive layer 452 can be subjected to CMOS processing steps to create the interconnects for the third device row 455 to be mounted thereon, where the seventh device 456, eighth device 457, and ninth device 459 are mounted and coupled to the second device row 445. The devices of the third device row 455 can be memory devices or core processing dies and other forms of dies and circuits as described herein. One or more of the devices in the third device row 455 can have TSVs or other forms of vias that extend vertically along the entire height of the third device row 455. The vias can be formed before the placement of the devices in the third device row 455, after the placement of the devices in the third device row 455, or in some combination thereof.

[0068] The third device row 455 can be bonded to the second device row 445 via a hybrid bonding process, where the third dielectric layer 450 is bonded to corresponding dielectric components within the seventh device 456, the eighth device 457, and the ninth device 459 via fusion bonding, while the third conductive layer 452 provides a metal bond between the conductive material of the third conductive layer 452 and the corresponding pads, vias, and other metal contacts of the third device row 455. A thermal process or heat treatment can use heat in the hybrid bonding process to allow the dielectric and / or conductive portions to bond. A fourth insulating layer 464 can be deposited over the third insulating layer 454. In some embodiments, the fourth insulating layer 464 can have substantially the same thickness as the third device row 455. In some embodiments, the fourth insulating layer 464 can cover the third device row 455, and some or all of the fourth insulating layer 464 can be removed, for example, by patterning, grinding, etching, and other forms of CMOS processing, without covering the third device row 455.

[0069] Figure 4L Shown at Figure 5 S565 in the substrate chip 420 to peel (or separate) the second carrier wafer 422. The second carrier wafer 422 can be separated, for example, by using one or more of layer peeling, chemical peeling, thermal peeling, and photo peeling techniques to peel the adhesive layer that couples the second carrier wafer 422 to the BSPDN layer 410. For example, in some embodiments, the chemical peeling technique can use a solvent to directly dissolve the adhesive, the thermal peeling technique can apply heat to the carrier wafer to melt the adhesive, and the photo peeling technique can use a laser to directly apply energy to the adhesive layer to reduce the bond strength.

[0070] Figure 4L Also shown at Figure 5 S570 in the individual device 470 can be separated and removed from a larger set of devices. For example, previous steps may have been performed using a combination of front-end-of-line (FEOL) and back-end-of-line (BEOL) processes, where multiple devices are assembled on a common carrier wafer. After the individual devices are completed, the devices can then be singulated into individual devices. The processes for singulation can vary and can include physical cutting, laser cutting, scribing and breaking, and processes that cut before grinding. Any other suitable method can be used.

[0071] Figure 6A and Figure 6B An exemplary embodiment of the package architecture 600 is shown. Compared to the package architecture 100, the package architecture 600 includes additional structural supports. The package architecture 600 includes Figure 1A and Figure 1Bcomponents of the packaging architecture 100 and includes a set of insulating layers and a structural dummy layer 610. The set of insulating layers includes a first insulating layer 602, a second insulating layer 604, a third insulating layer 606, and a fourth insulating layer 608, although the number of insulating layers can vary. The first insulating layer 602 can be substantially coplanar with the base die 104 and have a thickness substantially the same as the base die 104. The first insulating layer 602 can contact a support substrate (if provided for the base die 104). The second insulating layer 604 can be mounted on the first insulating layer 602 and be substantially coplanar with the first stack layer 110 and have a thickness substantially the same as the first stack layer 110. The third insulating layer 606 can be mounted on the second insulating layer 604 and be substantially coplanar with the second stack layer 120 and have a thickness substantially the same as the second stack layer 120. The fourth insulating layer 608 can be mounted on the third insulating layer 606 and be substantially coplanar with the third stack layer 130 and have a thickness substantially the same as the third stack layer 130. The structural dummy layer 610 can be mounted on top of the third stack layer 130 and the fourth insulating layer 608. In some embodiments, the structural dummy layer 610 can be a dielectric material and can be fusion bonded to the fourth insulating layer 608. A thermal process or heat treatment can use heat in the hybrid bonding process to allow the dielectric portion and / or the conductive portion to bond. In other embodiments, the structural dummy layer 610 can be, for example, a silicon layer and can be held in place, for example, using an adhesive such as a resin or an epoxy resin to hold the structural dummy layer 610 in place. In some embodiments, the structural dummy layer 610 and the insulating layers can provide mechanical support and stability for the devices of the packaging architecture 600. In some embodiments, the structural dummy layer 610 and the insulating layers can provide thermal support and stability for the devices of the packaging architecture 600, for example, by providing a thermal path for heat to flow from the device stack to the cooling surface on the structural dummy layer 610.

[0072] In some embodiments, the devices used within the above-described stack can be selected from known good dies and chips. In some embodiments, the selection of known good dies can be used to improve the yield of the process. In some embodiments, the base die can be selected from known good chips or known good dies.

[0073] In some embodiments, the packaging architecture presented herein can provide a stacked packaging architecture by using hybrid bonding to stack known good dies and chips (i.e., DRAM, processors, ASICs) onto known good logic dies to meet the growing demands for chip computing for AI, high-performance computing (HPC), and data centers. The packaging architecture presented herein can provide a configurable stack on the logic die to bring flexibility for computing and matching, such as for the number of cores, capacity, and bandwidth for mixing and matching.

[0074] Although this specification may contain many specific implementation details, the implementation details should not be construed as limiting the scope of any claimed subject matter, but rather as descriptions of features specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments may also be implemented combinatorially in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Additionally, although features may be described above as acting in certain combinations and even initially claimed as such, in some cases one or more features from a claimed combination may be deleted from the combination, and the claimed combination may be directed to a sub-combination or a variation of a sub-combination.

[0075] Similarly, although operations are depicted in the figures in a particular order, this should not be construed as requiring that the operations be performed in the particular order shown or in sequential order, or that all of the illustrated operations be performed, to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Additionally, the separation of various system components in the above-described embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0076] Accordingly, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the appended claims. In some cases, the acts recited in the claims may be performed in a different order and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain implementations, multitasking and parallel processing may be advantageous.

[0077] As those skilled in the art will recognize, the innovative concepts described herein can be modified and varied over a wide range of applications. Accordingly, the scope of the claimed subject matter should not be limited to any of the specific exemplary teachings discussed above, but is defined by the appended claims.

[0078] This application claims the benefit of priority of U.S. Provisional Patent Application Serial No. 63 / 612,353, filed on December 19, 2023, and U.S. Patent Application Serial No. 18 / 810,393, filed on August 20, 2024, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. A packaging structure, comprising: A first layer including at least one transistor; a second layer on the first side of the first layer, the second layer comprising a signal layer; a third layer on a second side of the first layer, the second side being opposite to the first side, the third layer comprising a power layer; and a stack coupled to the second layer, the stack comprising a first device row and a second device row, wherein each of the first device row and the second device row comprises at least one device, wherein the second device row is mounted on the first device row, and The devices in the first device row are different from the devices in the second device row. 2 . The package structure of claim 1 , wherein the first device row comprises processing devices. The package structure of claim 1 , wherein the second device row comprises memory devices. The package structure according to claim 3 , wherein the memory device is mounted above the processing device. 5 . The package structure according to claim 3 , wherein the memory device is mounted on a device other than a processing device. The package structure according to claim 3 , wherein the memory device is a dynamic random access memory device. The package structure according to claim 1 , wherein the first device row comprises at least one device. 8 . The package structure of claim 1 , wherein the first device row includes devices other than memory devices or processing devices. 9 . The package structure of claim 1 , wherein the stack is mounted on the signal layer.

10. A packaging system, comprising: a substrate, the substrate comprising a logic layer; a first layer, the first layer comprising a first device row, the first layer being on the substrate; a second layer, the second layer comprising a second device row, wherein the second layer is disposed above the first layer, wherein the second device row is coupled to the first device row; as well as a third layer, the third layer comprising a third device row, wherein the third layer is arranged above the second layer, wherein the third device row is coupled to the second device row, wherein each of the first device row, the second device row, and the third device row includes at least one device, and The device composition of the first device row is different from the device composition of the second device row. 11 . The packaging system of claim 10 , wherein a device composition of the third device row is the same as the device composition of the second device row. 12 . The packaging system of claim 10 , wherein the substrate comprises a power layer and a signal layer, wherein the power layer is coupled to the logic layer, and wherein the logic layer is coupled to the signal layer.

13. The packaging system of claim 12, wherein the power layer and the signal layer are coupled to the first layer. The packaging system of claim 10 , wherein the first device row comprises processing devices.

15. The packaging system of claim 10, wherein the second device row comprises memory devices.

16. A method for forming a package structure, comprising: forming a transistor layer on a first side of a first substrate, the transistor layer comprising at least one transistor; forming a signal layer on the transistor layer, the signal layer being communicatively coupled to the transistor layer; forming a power layer on a second side of the first substrate, the second side being opposite to the first side, the power layer being electrically coupled to the transistor layer; bonding a first device row to the signal layer; as well as A second device row is bonded to the first device row.

17. The method of claim 16, wherein bonding the first device row to the signal layer comprises: A dielectric layer is deposited, vias are patterned in the dielectric layer, and the first device row and the signal layer are heated together to form a bond between the first device row and the signal layer.

18. The method of claim 16, wherein a device composition of the second device row is different from a device composition of the first device row.

19. The method of claim 16, further comprising bonding a third device row to the second device row, the device composition of the third device row being the same as the device composition of the second device row.

20. The method according to claim 16, wherein forming the signal layer on the transistor layer comprises forming a redistribution layer on a surface of the signal layer, and Wherein bonding the first device row to the signal layer comprises: A first dielectric layer is deposited over the redistribution layer, the first dielectric layer is patterned to expose exposed portions of the redistribution layer, conductive contacts of the first device row are mounted on the exposed portions of the redistribution layer, and a thermal process is performed to bond the exposed portions of the redistribution layer to the conductive contacts of the first device row.

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