Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. A semiconductor device may include: a substrate including a chip region and a pad region; a first bonding pad in the chip region; a second bonding pad on the first bonding pad and having a front surface connected to the first bonding pad; a first probe pad in the pad region, extending to the chip region, and connected to a rear surface of at least one of the second bonding pads; and a second probe pad positioned adjacent to the first probe pad and connected to a rear surface of at least one of the second bonding pads.

Description

Technical Field

[0001] The present disclosure relates to an electronic device and a method of manufacturing the electronic device, and more particularly, to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] The integration degree of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, a semiconductor device in which memory cells are formed as a single layer on a substrate has reached its limit in terms of integration degree. Accordingly, a three-dimensional semiconductor device in which memory cells are stacked on a substrate has been developed. In addition, in order to improve the operation reliability of a semiconductor device, various structures and manufacturing methods are being developed. Summary of the Invention

[0003] According to an embodiment of the present disclosure, a semiconductor device may include: a substrate including a chip region and a pad region; a first bonding pad located in the chip region; a second bonding pad located on the first bonding pad and having a front surface connected to the first bonding pad; a first probing pad located in the pad region, extending into the chip region, and connected to a rear surface of at least one of the second bonding pads; and a second probing pad positioned adjacent to the first probing pad and connected to a rear surface of at least one of the second bonding pads.

[0004] According to an embodiment of the present disclosure, a semiconductor device may include: a first test structure including a first lower bonding pad and a first upper bonding pad electrically connected to the first lower bonding pad; a second test structure including a second lower bonding pad and a second upper bonding pad electrically connected to the second lower bonding pad and positioned adjacent to the first test structure in a first direction; a first probing pad electrically connected to the first test structure and extending in the first direction; and a second probing pad electrically connected to the second test structure and extending in the first direction.

[0005] According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include: forming a first wafer including a first substrate and a first bonding pad; forming a second wafer including a second substrate and a second bonding pad; bonding the first wafer and the second wafer such that a front surface of the first bonding pad and a front surface of the second bonding pad are connected; forming probing pads respectively connected to rear surfaces of the second bonding pads; and detecting a bonding defect by applying different voltages to a pair of the probing pads.

[0006] These and other features and advantages of the present invention will become apparent from the following drawings and the detailed description of exemplary embodiments of the invention. Brief Description of the Drawings

[0007] Figures 1A to 1C is a simplified diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0008] Figures 2A to 2C is a simplified diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0009] Figures 3A to 3C 、 Figures 4A to 4C 、and Figures 5A to 5C is a simplified diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Detailed Embodiments

[0010] Various embodiments of the present disclosure provide a semiconductor device having a stable structure and improved performance characteristics, and a method of manufacturing the semiconductor device.

[0011] According to the present invention, a semiconductor device having a stable structure and improved reliability can be provided.

[0012] Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

[0013] Figures 1A to 1C is a simplified diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 1A is a plan view, Figure 1B which may be a cross-sectional view taken along line A-A' of Figure 1A and may be a cross-sectional view taken along B-B' of Figure 1C and may be a cross-sectional view taken along B-B' of Figure 1A of.

[0014] Referring to Figures 1A to 1C , the semiconductor device may include at least one of a substrate 100, a first interlayer insulating layer IL1, a second interlayer insulating layer IL2, a third interlayer insulating layer IL3, a gate structure 180, a channel structure CH, a first bonding pad 120, a second bonding pad 130, a probe pad 170, and a test pattern. The semiconductor device may further include a first line 110A, a first contact via 110B, a second line 140A, a second contact via 140B, a third line 160A, a third contact via 160B, a contact plug 150, and a source structure 190.

[0015] The substrate 100 may include a chip region CHR and a pad region PAR. The chip region CHR may include a planar region PLR. Each planar region PLR may include a first peripheral circuit region PR1 and a cell region CR. The first peripheral circuit region PR1 and the cell region CR may be stacked. A second peripheral circuit region PR2 may be located between the planar regions PLR.

[0016] The peripheral circuit PC may be located in the first peripheral circuit region PR1. The peripheral circuit PC may include at least one of a page buffer and a decoder. Alternatively, the peripheral circuit PC may include transistor 1. Transistor 1 may include junctions 1A and 1B, gate electrode 1D, and gate insulating layer 1C.

[0017] For example, the gate insulating layer 1C may be located between the gate electrode 1D and the substrate 100. The peripheral circuit PC may also include at least one of a page buffer and a decoder. The gate structure 180 may be located in the cell region CR. The gate structure 180 may be formed between the second interlayer insulating layer IL2 and the third interlayer insulating layer IL3.

[0018] In addition, the channel structure CH extending through the gate structure 180 and connected to the peripheral circuit PC may be located in the cell region CR. The probe pad 170 may be located in the pad region PAR. For example, the probe pad 170 may be used to detect bonding defects.

[0019] The first bonding pad 120 may be above or on the substrate 100 in the first interlayer insulating layer ILl. The first bonding pad 120 may be located in the chip region CHR of the substrate 100. For example, the first bonding pad 120 may be located in at least one of the first peripheral circuit region PR1, the second peripheral circuit region PR2, and the cell region CR. The first bonding pad 120 may be located in the first interlayer insulating layer IL1. For example, the first interlayer insulating layer IL1 may be located on the substrate 100. The first bonding pad 120 may be connected to the first wire 110A. The first wire 110A and the first bonding pad 120 may be connected through the first contact via 110B. In addition, at least one of the first contact vias 110B may connect the first wire 110A and the peripheral circuit PC. The first wire 110A and the first contact via 110B may be located in the first interlayer insulating layer IL1. The first bonding pad 120 may include a conductive material such as copper or tungsten. In an embodiment, for example, the first bonding pad 120 may include copper. The first wire 110A and the first contact via 110B may include a conductive material such as tungsten. The first interlayer insulating layer IL1 may include an insulating material such as an oxide.

[0020] The second bonding pad 130 may be located on the first bonding pad 120 and may be in direct contact with the first bonding pad 120. The second bonding pad 130 may be located in the second interlayer insulating layer IL2. For example, the second interlayer insulating layer IL2 may be located on the first interlayer insulating layer IL1. The second bonding pad 130 may be bonded and connected to the first bonding pad 120. For example, the front surface of the second bonding pad 130 may be connected to the front surface of the first bonding pad 120. The second bonding pad 130 may include a conductive material such as copper or tungsten. In an embodiment, for example, the second bonding pad 130 may include copper.

[0021] The contact plug 150 may be located above the second bonding pad 130. The contact plug 150 may extend through the second interlayer insulating layer IL2 into the third interlayer insulating layer IL3. For example, the third interlayer insulating layer IL3 may be located on the second interlayer insulating layer IL2. The contact plug 150 may be connected to the second wire 140A. The contact plug 150 and the second wire 140A may be connected through the second contact via 140B. The second wire 140A and the second contact via 140B may be located in the second interlayer insulating layer IL2. The contact plug 150, the second wire 140A, and the second contact via 140B may include a conductive material such as tungsten.

[0022] The channel structure CH may be located above the second bonding pad 130. The channel structure CH and the second bonding pad 130 may be connected through the second wire 140A and the second contact via 140B. The channel structure CH may extend through the gate structure 180 including alternately stacked insulating layers 180A and conductive layers 180B. The channel structure CH may extend through the gate structure 180 into the source structure 190. For example, the source structure 190 may be located on the gate structure 180. Each channel structure CH may include at least one of a channel layer CHA, a memory layer CHB surrounding the channel layer CHA, and an insulating core CHC located in the channel layer CHA.

[0023] The probe pad 170 may be located in the pad region PAR. At least one of the probe pads 170 may extend from the pad region PAR into the chip region CHR. For example, at least one of the probe pads 170 may extend from the pad region PAR into the chip region CHR and may be connected to the rear surface of at least one of the second bonding pads 130 among the second bonding pads 130. The probe pad 170 and the second bonding pad 130 may be connected through the third wire 160A, the third contact via 160B, and the contact plug 150. For example, the third wire 160A and the third contact via 160B may be located on the contact plug 150 and may be located in the third interlayer insulating layer IL3.

[0024] During the process of joining the first bonding pad 120 and the second bonding pad 130 or in a subsequent process, the first bonding pad 120 and the second bonding pad 130 may deteriorate. For example, delamination may occur between the first bonding pad 120 and the second bonding pad 130, and copper migration may occur between the delaminated positions. Therefore, it is necessary to detect whether there is a bonding defect by monitoring whether the first bonding pad 120 and the second bonding pad 130 deteriorate for each step.

[0025] According to an embodiment of the present disclosure, the probe pads 170 can be electrically connected to the bonding pads 120 and 130. Bonding defects can be detected by applying different voltages to a pair of the probe pads 170 connected to the bonding pads 120 and 130. For example, a pair of probe pads 170 can be adjacent to each other and close. For example, a pair of probe pads 170 can be positioned adjacent to each other in the first direction I. Alternatively, at least one probe pad 170 not connected to the bonding pads 120 and 130 can be located between the pair of probe pads 170. By not performing subsequent processes when bonding defects are detected, the manufacturing cost can be reduced.

[0026] According to the above structure, in the semiconductor device, the bonding pads 120 and 130 can be located in the chip region CHR. Additionally, in the semiconductor device, the probe pads 170 can be located in the pad region PAR. By applying different voltages to at least a pair of the probe pads 170, it can be detected whether there is a bonding defect between the bonding pads 120 and 130. Therefore, when there is a defect in the bonding, by abandoning subsequent processes without performing subsequent processes, the manufacturing cost can be reduced.

[0027] Figures 2A to 2C is a simplified diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Hereinafter, the content repeated with the above is omitted.

[0028] Referring to Figure 2A , the semiconductor device can include at least one of a first test structure TS1, a second test structure TS2, a first probe pad 270A, and a second probe pad 270B.

[0029] The first test structure TS1 can include a first lower bonding pad 220A1 and a first upper bonding pad 230A1 located on the first lower bonding pad 220A1. The first test structure TS1 can also include at least one of a first lower test line 210A1, a first lower test via 210B1, a first upper test line 240A1, and a first upper test via 240B1.

[0030] The first lower bonding pad 220A1 can be arranged in a second direction II that intersects the first direction I. For example, the first lower bonding pad 220A1 can be arranged to be spaced apart in the second direction II. The first lower bonding pad 220A1 can be electrically connected to the first upper bonding pad 230A1. For example, the first lower bonding pad 220A1 can be respectively connected to the first upper bonding pad 230A1. At least one of the first lower bonding pad 220A1 and the first upper bonding pad 230A1 can include a conductive material such as copper or tungsten.

[0031] The first lower test line 210A1 can extend in the second direction II. The first lower test line 210A1 can be connected to the first lower bonding pad 220A1. For example, the first lower test line 210A1 and the first lower bonding pad 220A1 can be connected through the first lower test via 210B1. For example, the first lower test via 210B1 can be located between the first lower test line 210A1 and the first lower bonding pad 220A1. At least one of the first lower test line 210A1 and the first lower test via 210B1 can include a conductive material such as copper or tungsten.

[0032] The first upper test line 240A1 can extend in the second direction II. The first upper test line 240A1 can be connected to the first upper bonding pad 230A1. For example, the first upper test line 240A1 and the first upper bonding pad 230A1 can be connected through the first upper test via 240B1. For example, the first upper test via 240B1 can be located between the first upper test line 240A1 and the first upper bonding pad 230A1. At least one of the first upper test line 240A1 and the first upper test via 240B1 can include a conductive material such as copper or tungsten.

[0033] The second test structure TS2 can be positioned adjacent to the first test structure TS1 in the first direction I. The second test structure TS2 can include a second lower bonding pad 220B1 and a second upper bonding pad 230B1 located on the second lower bonding pad 220B1. The second test structure TS2 can also include at least one of a second lower test line 210A2, a second lower test via 210B2, a second upper test line 240A2, and a second upper test via 240B2.

[0034] The second lower bonding pad 220B1 can be arranged in the second direction II. The second lower bonding pad 220B1 can be electrically connected to the second upper bonding pad 230B1. At least one of the second lower bonding pad 220B1 and the second upper bonding pad 230B1 can include a conductive material such as copper or tungsten.

[0035] The second lower test line 210A2 can extend in the second direction II and can be connected to the second lower bonding pad 220B1. The second lower test line 210A2 and the second lower bonding pad 220B1 can be connected through the second lower test via 210B2. At least one of the second lower test line 210A2 and the second lower test via 210B2 can include a conductive material such as copper or tungsten.

[0036] The second upper test line 240A2 can extend in the second direction II and can be connected to the second upper bonding pad 230B1. The second upper test line 240A2 and the second upper bonding pad 230B1 can be connected through the second upper test via 240B2. At least one of the second upper test line 240A2 and the second upper test via 240B2 can include a conductive material such as copper or tungsten.

[0037] The probe pads 270A and 270B can be located above the bonding pads 220A1, 230A1, 220B1, and 230B1. The probe pads 270A and 270B can extend in the first direction I. The first probe pad 270A can extend in the first direction I and can be electrically connected to the first test structure TS1. The second probe pad 270B can extend in the first direction I and can be electrically connected to the second test structure TS2. For example, the probe pads 270A and 270B and the test structures TS1 and TS2 can be connected through the connection via 260B.

[0038] Bonding defects can be detected by applying different voltages to the first probe pad 270A and the second probe pad 270B. For example, the bonding defects can include bridging that occurs between the bonding pads 220A1, 230A1, 220B1, and 230B1. In other words, bonding defects can be detected by applying a first voltage to the first probe pad 270A and a second voltage different from the first voltage to the second probe pad 270B. For example, the second voltage can be greater than the first voltage.

[0039] For example, a ground voltage V SS can be applied to the first probe pad 270A, and an operating voltage V cc can be applied to the second probe pad 270B. For example, the operating voltage V cc can be an external operating voltage. For example, the ground voltage V SS can be 0V, and as an external voltage for detecting bonding defects, the operating voltage V ccIt can be approximately 3.3V. A bonding defect can be detected by measuring the breakdown voltage of a pair of probe pads 270A and 270B at a specific current or by measuring the leakage current of at least one of a pair of probe pads 270A and 270B at a specific voltage. When the breakdown voltage is less than the reference voltage or when the leakage current is greater than the reference value, a defect in the bonding can be detected. For example, the voltage in the case of normal bonding can be used as the reference voltage, and the leakage current in the case of normal bonding can be used as the reference current.

[0040] Referring to Figure 2B , at least one of the first lower bonding pad 220A2 and the second lower bonding pad 220B2 can extend in the second direction II. At least one of the first upper bonding pad 230A2 and the second upper bonding pad 230B2 can extend in the second direction II. In other words, the bonding pads 220A2, 220B2, 230A2, and 230B2 can have a linear shape.

[0041] The lower bonding pads 220A2 and 220B2 can be connected to the lower test lines 210A1 and 210A2 through the lower test vias 210B1 and 210B2. The upper bonding pads 230A2 and 230B2 can be connected to the upper test lines 240A1 and 240A2 through the upper test vias 240B1 and 240B2.

[0042] Referring to Figure 2C , multiple upper test lines 240A11, 240A12, 240A21, and 240A22 and multiple upper test vias 240B11, 240B12, 240B21, and 240B22 can be located between the upper bonding pads 230A1 and 230B1 and the probe pads 270A and 270B. The upper test lines 240A11 and 240A12 can be connected to each other through the upper test vias 240B11 and 240B12. The upper test lines 240A21 and 240A22 can be connected to each other through the upper test vias 240B21 and 240B22. In an embodiment, multiple lower test lines 210A1 and 210A2 and multiple lower test vias 210B1 and 210B2 can be respectively located below the lower bonding pads 220A1 and 220B1. In other words, the shapes, connection relationships, etc. of the test lines 210A1, 210A2, 240A11, 240A12, 240A21, and 240A22, the test vias 210B1, 210B2, 240B11, 240B12, 240B21, and 240B22, the bonding pads 220A1, 230A1, 220B1, and 230B1, and the probe pads 270A and 270B are not limited to Figure 2C the embodiment shown, but they can be modified and combined.

[0043] According to the above structure, by applying different voltages to the detection pads 270A and 270B, bonding defects can be detected. In addition, the bonding pads 220A1, 230A1, 220B1 and 230B1 and the detection pads 270A and 270B can be electrically connected through various shapes of test wires 210A1, 210A2, 240A11, 240A12, 240A21 and 240A22 and test through holes 210B1, 210B2, 240B11, 240B12, 240B21 and 240B22 and combinations thereof.

[0044] Figures 3A to 5C is a simplified diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 3A , Figure 4A and Figure 5A It can be a floor plan, Figure 3B , Figure 4B and Figure 5B It can be along Figure 3A , Figure 4A and Figure 5A The AA′ extracted cross-section in Figure 3C , Figure 4C and Figure 5C It can be along Figure 3A , Figure 4A and Figure 5A In the following, the contents overlapping with the above contents are omitted.

[0045] Reference Figures 3A to 3C , a first wafer 300A including a first substrate S1 may be formed. The first wafer 300A may include a first peripheral circuit region PR1 and a second peripheral circuit region PR2 between the first peripheral circuit region PR1. First, a peripheral circuit PC may be formed on the first substrate S1. For example, the peripheral circuit PC may be formed in the first peripheral circuit region PR1. The peripheral circuit PC may include at least one of a transistor 1, a page buffer, and a decoder. The transistor 1 may include junctions 1A and 1B, a gate insulating layer 1C, or a gate electrode 1D. An isolation insulating layer ISO may be formed in the first substrate S1, and an active region of the transistor 1 may be defined by the isolation insulating layer ISO.

[0046] Subsequently, a first bonding pad 320 can be formed on the first substrate S1. At least one of the first bonding pads 320 can be connected to the peripheral circuit PC through the first line 310A and the first contact via 310B. In other words, some of the first bonding pads 320 may not be connected to the peripheral circuit PC. The first bonding pad 320 can include a conductive material such as copper or tungsten. The first bonding pad 320, the first line 310A, and the first contact via 310B can be formed in the first interlayer insulating layer IL1. For example, the first interlayer insulating layer IL1 can be formed on the first substrate S1 and can include an insulating material such as an oxide.

[0047] Referring Figures 4A to 4C , a second wafer 300B including a second substrate S2 can be formed. The second wafer 300B can include a cell region CR. First, a stack 380 can be formed by alternately laminating a first material layer 380A and a second material layer 380B on the second substrate S2. For example, the first material layer 380A can include an insulating material such as an oxide, and the second material layer 380B can include a sacrificial material such as a nitride. A channel structure CH extending into the second substrate S2 can be formed through the stack 380. The channel structure CH can be formed in the cell region CR of the second substrate S2. Each channel structure CH can include at least one of a channel layer CHA, a memory layer 130B surrounding the channel layer 130A, and an insulating core 130C in the channel layer 130A. Subsequently, a slit extending through the stack 380 can be formed, and the second material layer 380B can be replaced with a third material layer 380C through the slit. For example, the third material layer 380C can include a conductive material such as tungsten, molybdenum, or polysilicon. Thus, a gate structure 380G including alternately laminated first material layers 380A and third material layers 380C can be formed. As a reference, when the second material layer 380B includes a conductive material, the replacement process can be omitted. In this case, the stack 380 can be used as the gate structure 380G. Subsequently, a slit structure can be formed by forming an insulating material or a semiconductor material in the slit.

[0048] A contact plug 350 can be formed on the second substrate S2. The contact plug 350 can extend through the second interlayer insulating layer IL2 into the second substrate S2. The contact plug 350 can include a conductive material such as tungsten. For example, the second interlayer insulating layer IL2 can be formed on the second substrate S2 and can include an insulating material such as an oxide.

[0049] The second bonding pad 330 may be formed above the second substrate S2. At least one of the second bonding pads 330 may be connected to the contact plug 350 through the second wire 340A and the second contact via 340B. Alternatively, at least one of the second bonding pads 330 may be connected to at least one of the channel structures CH through the second wire 340A and the second contact via 340B. The second bonding pad 330 may include a conductive material such as copper or tungsten. The second bonding pad 330, the second wire 340A, and the second contact via 340B may be formed in the second interlayer insulating layer IL2.

[0050] Referring Figures 5A to 5C , the first wafer 300A and the second wafer 300B may be bonded. For example, the front surfaces of the first bonding pad 320 and the second bonding pad 330 may be bonded. The first wafer 300A and the second wafer 300B may be bonded such that the first peripheral circuit region PR1 of the first wafer 300A and the cell region CR of the second wafer 300B are stacked.

[0051] During the process of bonding the first wafer 300A and the second wafer 300B and in subsequent processes, the bonding pads 320 and 330 may deteriorate. For example, delamination may occur between the first bonding pad 320 and the second bonding pad 330, and copper migration may occur between the delaminated positions. Therefore, it is necessary to detect the presence of bonding defects by monitoring whether the first bonding pad 320 and the second bonding pad 330 deteriorate.

[0052] Subsequently, the second substrate S2 of the second wafer 300B may be removed. Subsequently, a source structure 390 connected to the channel structure CH may be formed on the gate structure 380G. The source structure 390 may include a semiconductor material. Subsequently, a third interlayer insulating layer IL3 may be formed. The third interlayer insulating layer IL3 may be formed on the second interlayer insulating layer IL2. Alternatively, the third interlayer insulating layer IL3 may be formed on the source structure 390.

[0053] Subsequently, a probe pad 370 may be formed above the bonding pads 320 and 330. At least one of the probe pads 370 may be formed in a region other than the region where the first peripheral circuit region PRl of the first wafer 300A and the cell region CR of the second wafer 300B are stacked. For example, the probe pad 370 may be formed in the pad region PAR.

[0054] A probe pad 370 can be formed to connect to the back surface of the second bonding pad 330. For example, at least one of the probe pads 370 can extend from the pad region PAR to the chip region CHR and can be connected to the back surface of the second bonding pad 330. The probe pad 370 can be formed in the third interlayer insulating layer IL3. At least one of the probe pads 370 can be connected to at least one of the contact plugs 350 through a third wire 360A and a third contact via 360B. Accordingly, the probe pad 370 can be electrically connected to the bonding pads 320 and 330. The third wire 360A and the third contact via 360B can be formed in the third interlayer insulating layer IL3.

[0055] Bonding defects can be detected by applying different voltages to a pair of the probe pads 370 among the probe pads 370. For example, the bonding defects can include a bridge formed between the bonding pads 320 and 330. First, a first voltage can be applied to one of the pair of probe pads 370, and a second voltage greater than the first voltage can be applied to the remaining probe pad 370. For example, the first voltage can be 0V as a ground voltage V SS , and the second voltage can be approximately 3.3V as an external voltage (i.e., an operating voltage V cc ) for detecting bonding defects. Subsequently, the breakdown voltage of each of the pair of probe pads 370 can be measured. Alternatively, the leakage current of the remaining probe pad 370 can be measured. For example, the remaining probe pad 370 can refer to the probe pad 370 to which a relatively large voltage is applied. Subsequently, when the breakdown voltage measured through the probe pad 370 is lower than a reference voltage, it can be determined that there is a defect in the bonding. Alternatively, when the leakage current measured through the remaining probe pad 370 is higher than a reference current, it can be determined that there is a defect in the bonding. For example, the reference voltage or the reference current can refer to the voltage value or the current value when the bonding is normal.

[0056] Although embodiments according to the scope of the present disclosure have been described with reference to the accompanying drawings, the scope of the present disclosure is not limited to the above-described embodiments and drawings. It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the scope of the present disclosure.

[0057] Cross-reference to related applications

[0058] This application claims priority to Korean Patent Application No. 10-2023-0184746, filed on December 18, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: A substrate, the substrate comprising a chip area and a pad area; a first bonding pad, the first bonding pad being located in the chip region; a second bonding pad located on the first bonding pad and having a front surface connected to the first bonding pad; a first detection pad, the first detection pad being located in the pad region, extending to the chip region, and connected to a rear surface of at least one second bonding pad among the second bonding pads; as well as A second probing pad is positioned adjacent to the first probing pad and connected to a rear surface of at least one second bonding pad among the second bonding pads.

2. The semiconductor device according to claim 1, wherein A bonding defect is detected by applying a first voltage to the first probing pad and applying a second voltage different from the first voltage to the second probing pad.

3. The semiconductor device according to claim 2, wherein: The bonding defect includes a bridge occurring between the first bonding pad and the second bonding pad.

4. The semiconductor device according to claim 1, wherein The chip region includes a planar region in which a peripheral circuit region and a cell region are stacked.

5. The semiconductor device according to claim 4, further comprising: a peripheral circuit, the peripheral circuit being located in the peripheral circuit area; A gate structure, the gate structure is located in the cell region; as well as A channel structure extends through the gate structure and is connected to the peripheral circuit.

6. The semiconductor device according to claim 5, further comprising: A source structure is located on the gate structure.

7. The semiconductor device according to claim 1, wherein At least one of the first bonding pad and the second bonding pad includes copper.

8. A semiconductor device, comprising: a first test structure including a first lower bonding pad and a first upper bonding pad electrically connected to the first lower bonding pad; a second test structure including a second lower bonding pad and a second upper bonding pad electrically connected to the second lower bonding pad and positioned adjacent to the first test structure in a first direction; a first probing pad electrically connected to the first test structure and extending in the first direction; as well as A second probing pad is electrically connected to the second test structure and extends in the first direction.

9. The semiconductor device according to claim 8, wherein: A ground voltage is applied to the first probing pad, and an operating voltage is applied to the second probing pad.

10. The semiconductor device according to claim 8, wherein The first test structure comprises: a first lower test line connected to the first lower bonding pad and extending in a second direction crossing the first direction; and A first upper test line is connected to the first upper bonding pad and extends along the second direction.

11. The semiconductor device according to claim 8, wherein The first test structure includes a plurality of first lower bonding pads arranged in a second direction crossing the first direction.

12. The semiconductor device according to claim 8, wherein The first test structure includes a plurality of first upper bonding pads arranged in a second direction crossing the first direction.

13. The semiconductor device according to claim 8, wherein At least one of the first lower bonding pad and the second lower bonding pad extends in a second direction crossing the first direction.

14. The semiconductor device according to claim 8, wherein: At least one of the first upper bonding pad and the second upper bonding pad extends in a second direction crossing the first direction.

15. The semiconductor device according to claim 8, wherein The second test structure comprises: a second lower test line connected to the second lower bonding pad and extending in a second direction crossing the first direction; and A second upper test line is connected to the second upper bonding pad and extends in the second direction.

16. The semiconductor device according to claim 8, wherein The second test structure includes a plurality of second lower bonding pads arranged in a second direction crossing the first direction.

17. The semiconductor device according to claim 8, wherein: The second test structure includes a plurality of second upper bonding pads arranged in a second direction crossing the first direction.

18. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a first wafer including a first substrate and a first bonding pad; forming a second wafer including a second substrate and a second bonding pad; bonding the first wafer and the second wafer such that the front surface of the first bonding pad is connected to the front surface of the second bonding pad; forming probing pads connected to rear surfaces of the second bonding pads, respectively; and A bonding defect is detected by applying different voltages to a pair of the probing pads among the probing pads.

19. The method according to claim 18, wherein: The step of detecting the bonding defect comprises the following steps: applying a first voltage to one of the pair of probing pads, and applying a second voltage greater than the first voltage to the remaining probing pads; and A breakdown voltage of the pair of probing pads is measured.

20. The method according to claim 19, wherein: When the breakdown voltage is lower than a reference voltage, the bonding defect exists.

21. The method according to claim 18, wherein: The step of detecting the bonding defect comprises the following steps: applying a first voltage to one of the pair of detection pads; applying a second voltage greater than the first voltage to the remaining probing pads; and The leakage current of the remaining detection pads is measured.

22. The method according to claim 21, wherein: When the leakage current is higher than a reference current, the bonding defect exists.

23. The method according to claim 18, wherein: The first wafer includes a peripheral circuit region, the second wafer includes a cell region, and the first wafer and the second wafer are bonded such that the peripheral circuit region and the cell region are stacked.

24. The method according to claim 23, wherein: The peripheral circuit area includes a peripheral circuit, and The unit region includes a stack and a channel structure extending through the stack.

25. The method according to claim 24, further comprising the steps of: After the bonding step, removing the second substrate; as well as A source structure is formed connected to the channel structure.

26. The method of claim 23, wherein: The probing pad is formed in a pad region, and the pad region is a region spaced apart from the peripheral circuit region and the cell region.

27. The method according to claim 26, wherein: The probing pads extend from the pad region and are connected to rear surfaces of the second bonding pads, respectively.

28. The method of claim 18, wherein: The first bonding pad or the second bonding pad includes copper.

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