Semiconductor package, method of manufacturing same, and electronic system including same

Abstract

The invention provides a semiconductor package, a method of manufacturing the same, and an electronic system including the same. The semiconductor package includes a silicon substrate including a through silicon via, a first build-up layer on a first surface of the silicon substrate, a second build-up layer on a second surface of the silicon substrate, and a stack capacitor including at least one integration in at least one of the silicon substrate, the first build-up layer, and the second build-up layer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method and apparatus for manufacturing a semiconductor package having a silicon interposer and an integrated stacked capacitor (ISC). Background Art

[0002] As electronic devices become smaller and smaller, semiconductor packages used in electronic devices also need to become smaller and have high reliability, high performance, and high capacity. Therefore, the importance of the structure of a semiconductor package for responding to the size and performance of a semiconductor package and supplying power to the semiconductor package more stably is increasing.

[0003] The information disclosed in this background art section has been known to the inventor before the implementation of the present application or is technical information obtained during the implementation of the present disclosure. Therefore, it may include information that does not form the prior art known to the public. Summary of the Invention

[0004] One or more embodiments provide a method and apparatus for manufacturing a semiconductor package having a silicon interposer and an integrated stacked capacitor.

[0005] One or more embodiments provide a semiconductor package including an integrated stacked capacitor having a relatively small size to reduce the vertical size and improve the power distribution network (PDN) and signal integration of a semiconductor device.

[0006] According to an aspect of an embodiment, there is provided a semiconductor package including: a silicon substrate including a through-silicon via, a first stacked layer on a first surface of the silicon substrate, a second stacked layer on a second surface of the silicon substrate, and at least one capacitor included in at least one of the silicon substrate, the first stacked layer, and the second stacked layer.

[0007] According to another aspect of an embodiment, there is provided a method of manufacturing a semiconductor package, the method including providing a silicon substrate including a through-silicon via, providing a first stacked layer on a first surface of the silicon substrate, providing a second stacked layer on a second surface of the silicon substrate, providing a capacitor in at least one of the silicon substrate, the first stacked layer, and the second stacked layer, and providing a semiconductor chip.

[0008] According to another aspect of the embodiment, an electronic system is provided, which includes at least one memory configured to store computer-readable instructions and a plurality of data, and at least one processor configured to execute the computer-readable instructions and implement a plurality of computing operations using the plurality of data, wherein the at least one processor includes a semiconductor package, the semiconductor package includes a silicon substrate including through-silicon vias, a first stack layer on a first surface of the silicon substrate, a second stack layer on a second surface of the silicon substrate, and at least one capacitor, and the at least one capacitor is included in at least one of the silicon substrate, the first stack layer, and the second stack layer. Description of the Drawings

[0009] Through the following description in conjunction with the drawings, the above and / or other aspects, features, and advantages of one or more embodiments of the present disclosure will become more apparent, wherein:

[0010] Figure 1 A semiconductor package according to one or more embodiments is shown;

[0011] Figure 2A A cross-sectional view showing the provision of a laser groove on a silicon substrate according to one or more embodiments is shown, Figure 2B A cross-sectional view showing the provision of one or more ISCs on the groove according to one or more embodiments is shown, Figure 2C A cross-sectional view showing the provision of a stacked insulating layer on the silicon substrate and the groove according to one or more embodiments is shown, Figure 2D A cross-sectional view showing the provision of a through-silicon tunnel according to one or more embodiments is shown, Figure 2E A cross-sectional view showing the provision of a metal material in the through-silicon tunnel to form a through-silicon via in the semiconductor package according to one or more embodiments is shown;

[0012] Figure 3A A cross-sectional view showing the provision of a silicon substrate having through-silicon vias according to one or more other embodiments is shown, Figure 3B A cross-sectional view showing the provision of one or more ISCs according to one or more other embodiments is shown, Figure 3C A cross-sectional view showing the provision of a stacked insulating layer on the silicon substrate according to one or more other embodiments is shown, Figure 3D A cross-sectional view showing the provision of a via on the stacked insulating layer in the semiconductor package according to one or more other embodiments is shown;

[0013] Figure 4A Shows Figure 3D An enlarged cross-sectional view of region A in Figure 4B Shows Figure 3D An enlarged cross-sectional view of region B in

[0014] Figure 5A Shows a cross-sectional view of a silicon substrate with through-silicon vias according to another embodiment, Figure 5B Shows a cross-sectional view of providing one or more ISCs according to another embodiment, Figure 5C Shows a cross-sectional view of providing a stacked insulating layer on a silicon substrate according to another embodiment, Figure 5D Shows a cross-sectional view of providing vias on a stacked insulating layer in a semiconductor package according to another embodiment;

[0015] Figure 6A Shows Figure 5D an enlarged cross-sectional view of region C in Figure 6B Shows Figure 5D an enlarged cross-sectional view of region D in;

[0016] Figure 7 Shows a semiconductor package according to one or more other embodiments;

[0017] Figure 8 Shows a semiconductor package according to one or more other embodiments;

[0018] Figure 9 Shows a semiconductor package according to one or more other embodiments;

[0019] Figure 10 Shows a semiconductor package according to one or more other embodiments;

[0020] Figure 11 Shows a semiconductor package according to one or more other embodiments;

[0021] Figure 12 Shows a flowchart of a method of manufacturing a semiconductor package according to one or more embodiments;

[0022] Figure 13 Shows a semiconductor package architecture that can be incorporated with a semiconductor package according to one or more embodiments; and

[0023] Figure 14 Shows a schematic block diagram of an electronic system according to one or more embodiments. Detailed Description

[0024] The embodiments described herein are examples, and thus, the present disclosure is not limited thereto and can be implemented in various other forms. Each embodiment provided in the following description does not exclude being associated with one or more features of another example or one or more other embodiments that are also provided herein or not provided herein but consistent with the present disclosure. For example, even if a matter described in a particular example or embodiment is not described in a different example or embodiment, that matter can be understood to be related to or combined with that different example or embodiment, unless otherwise mentioned in its description.

[0025] In addition, it should be understood that all descriptions of principles, aspects, examples, and embodiments are intended to cover their structural and functional equivalents. In addition, these equivalents should be understood to include not only currently known equivalents but also equivalents to be developed in the future, that is, all devices invented to perform the same function, regardless of their structure.

[0026] It will be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as "element") of a semiconductor device is referred to as being "on", "above", "over", "under", "below", "beneath", "connected to", or "coupled to" another element of the semiconductor device, it can be directly on, above, over, under, below, beneath, connected to, or coupled to the other element, or there can be intervening elements. In contrast, when an element of a semiconductor device is referred to as being "directly on", "directly above", "directly over", "directly under", "directly below", "directly beneath", "directly connected to", or "directly coupled to" another element of the semiconductor device, there are no intervening elements. Throughout the present disclosure, the same reference numerals refer to the same elements.

[0027] For ease of description, spatial relationship terms such as "above", "over", "on", "upper", "below", "beneath", "under", "lower", "top", and "bottom" may be used herein to describe the relationship of one element to another as shown in the figures. It will be understood that the spatial relationship terms are intended to encompass different orientations of the semiconductor device in addition to the orientation depicted in the figures during use or operation. For example, if the semiconductor device in the figures is flipped, an element described as "below" or "beneath" another element will be oriented "above" the other element. Thus, the term "below" can encompass both an upper and a lower orientation. The semiconductor device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used herein are to be interpreted accordingly.

[0028] As used herein, a statement such as "at least one of" when preceding a list of elements modifies the entire list of elements and not individual elements of the list. For example, the statement "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. Here, when the term "same" is used to compare the sizes of two or more elements, the term may encompass "substantially the same" sizes.

[0029] It should be understood that although the terms "first", "second", "third", "fourth", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0030] It will also be understood that even if a particular step or operation of manufacturing a device or structure is described as later than another step or operation, that step or operation may be performed later than the other step or operation, unless the other step or operation is described as being performed after that step or operation. It will be understood that any one of the components or any combination of components described herein can be used to perform one or more operations of the flowchart. Additionally, all operations are exemplary operations and may include various additional steps.

[0031] Embodiments are described with reference to cross-sectional illustrations, which are schematic illustrations of the embodiments (and intermediate structures). As such, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the embodiments are not to be construed as limited to the specific shapes of regions shown herein but include, for example, shape deviations resulting from manufacturing. For example, an implantation region shown as rectangular typically has rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to depict the actual shape of regions of the device and are not intended to limit the scope of the present disclosure. Additionally, in the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity.

[0032] For simplicity, general elements of a semiconductor device may or may not be described in detail herein.

[0033] Due to high computational performance requirements in various applications such as artificial intelligence (AI) applications, larger semiconductor package sizes are needed to integrate a greater number of central processing units (CPUs), graphics processing units (GPUs), high bandwidth memories (HBMs), AI chips, etc. in a single semiconductor package. As the thermal design power (TDP) required by CPUs and GPUs increases, larger packages with a relatively low impedance power distribution network (PDN) across multiple frequency ranges, particularly in the high frequency domain, are needed.

[0034] A silicon (Si) interposer with through-silicon vias (TSVs) enables heterogeneous integration of CPUs, GPUs, and HBMs. However, due to the relatively low resistivity of silicon (Si), which is approximately 5 - 10 Ω·cm, a silicon interposer with TSVs may experience signal loss, electromagnetic interference, crosstalk, and coupling issues in the relatively high frequency domain. Additionally, due to manufacturing and cost issues, it may be difficult to produce packages larger than 100 mm × 100 mm.

[0035] A semiconductor package according to one or more embodiments provides an integrated stacked capacitor embedded in a groove of a build-up layer, a redistribution layer, or a silicon substrate of the semiconductor package. Accordingly, the vertical size of the semiconductor package and the impedance of the power distribution network (PDN) for multiple frequency ranges, particularly the relatively high frequency range, can be reduced to improve the performance of the semiconductor package.

[0036] Figure 1 A semiconductor package according to one or more embodiments is shown.

[0037] Reference Figure 1, the semiconductor package 1 may include a first semiconductor chip 10, a second semiconductor chip 20, a first build-up layer 100, a silicon interposer 200, and a second build-up layer 300.

[0038] Here, the direction parallel to the main surface of the first build-up layer 100 may be referred to as the horizontal direction (X direction and / or Y direction), and the direction perpendicular to the horizontal direction (X direction and / or Y direction) and orthogonal to the main surface of the first build-up layer 100 may be referred to as the vertical direction (Z direction).

[0039] The first build-up layer 100 may include one or more first build-up insulating layers 110, a first wiring pattern 120, and a first through-via 130. The first wiring pattern 120 and the first through-via 130 may be included or contained in the first build-up insulating layer 110. The first build-up insulating layer 110 may include an organic insulating material such as an Ajinomoto build-up film (ABF), an oxide, a nitride, a photoimageable dielectric (PID) resin prepared by combining an epoxy resin and a photoinitiator, and may further include a photosensitive polyimide and / or an inorganic filler, etc. However, the embodiments are not limited thereto. For example, instead of the build-up layer, a redistribution layer including one or more redistribution insulating layers, wiring patterns, and vias may be provided.

[0040] The first wiring pattern 120 and the first through-via 130 may be provided as conductive patterns, and the conductive patterns may be located in the first build-up insulating layer 110. The first wiring pattern 120 may extend in the horizontal direction (X direction and / or Y direction) and be provided at different vertical levels within the first build-up insulating layer 110. The first through-via 130 may penetrate one or more first build-up insulating layers 110 in the vertical direction (Z direction) to interconnect the first wiring pattern 120 and electrically connect the first wiring pattern 120.

[0041] According to one or more embodiments, at least some of the first wiring pattern 120 may be provided integrally with some of the first through-via 130. For example, the first wiring pattern 120 and the first through-via 130 that are in contact with each other may be integrally formed as a single structure.

[0042] According to one or more embodiments, the first through-via 130 may have any suitable shape, including for example a tapered shape, where the horizontal width of the first through-via 130 decreases in the vertical direction (Z direction) away from the first semiconductor chip 10 and the second semiconductor chip 20, depending on the manufacturing conditions. However, the embodiments are not limited thereto.

[0043] The first wiring pattern 120 and the first through-via 130 may include, for example, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), and alloys thereof, but is not limited thereto.

[0044] The semiconductor package 1 may further include a passivation layer, an under-bump metal (UBM) layer 150, and a conductive layer. For example, the passivation layer may have a single-layer structure and may be provided on the lower surface of the first stacked insulating layer 110. In another embodiment, the passivation layer may have a multi-layer structure. The passivation layer may at least partially cover the exposed upper surface and side surfaces of the conductive layer and may expose the lower surface of the conductive layer. In addition, the UBM layer 150 may be provided on a part of the upper surface of the passivation layer.

[0045] The passivation layer may include an insulating material such as ABF, silicon oxide, silicon nitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), and combinations thereof.

[0046] The UBM layer 150 may electrically connect the conductive layer to other components of the semiconductor package 1 such as the external connection terminals 170. Additionally, the UBM layer 150 may prevent the external connection terminals 170 from cracking due to thermal shock between the external connection terminals 170 and the first stacked layer 100, thereby improving the reliability of the semiconductor package 1. The UBM layer 150 may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and combinations thereof.

[0047] The conductive layer may be provided on the passivation layer, and the lower surface of the conductive layer may be exposed from the lower surface of the passivation layer. The conductive layer may include conductive patterns spaced apart in a first horizontal direction (X direction) or a second horizontal direction (Y direction). For example, the conductive layer is shown as a single-layer conductive pattern provided at a single vertical level. However, the embodiment is not limited thereto, and the conductive layer may be provided as a multi-layer conductive pattern provided at different vertical levels, depending on the embodiment. The conductive layer may include, for example, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), and ruthenium (Ru), and alloys thereof, but is not limited thereto.

[0048] The external connection terminals 170 may be provided on the lower surface of the UBM layer 150. The external connection terminals 170 may connect the first semiconductor chip 10 and the second semiconductor chip 20 to devices external to the semiconductor package 1, such as, for example, a module substrate, a system board, and a printed circuit board. The external connection terminals 170 may be configured to electrically and / or physically connect the first stacked layer 100 and an external device. According to one or more embodiments, the external connection terminals 170 may include, for example, solder balls, conductive bumps, and flip-chip connection structures having a grid array such as a pin grid array, a ball grid array, and a land grid array. The external connection terminals 170 may be electrically connected to the UBM layer 150 and may be electrically connected to external devices such as a module substrate, a system board, and a printed circuit board.

[0049] The silicon interposer 200 may be provided on the upper surface of the first stacked layer 100. The silicon interposer 200 may include a silicon substrate 210 and through-silicon vias (TSVs) 220 that vertically penetrate the silicon substrate 210. As another embodiment, instead of through-silicon vias, the silicon interposer 200 may include through-organic vias (TOVs), coaxial vias (COVs), or copper (Cu) vias-in-via.

[0050] The through-silicon vias 220 may be provided between the first stacked layer 100 and the second stacked layer 300 and provide an electrical connection path between the first stacked layer 100 and the second stacked layer 300. The through-silicon vias 220 may include a conductive material that includes, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and combinations thereof.

[0051] The through-silicon vias 220 may have an upper surface and a lower surface that are spaced apart from each other in the vertical direction (Z direction). The upper surface of the through-silicon vias 220 may be coplanar with the upper surface of the silicon substrate 210, and the lower surface of the through-silicon vias 220 may be coplanar with the lower surface of the silicon substrate 210. The through-silicon vias 220 may at least partially contact the first through-via 130 and the first wiring pattern 120 exposed on the upper surface of the uppermost first stacked insulating layer 110. For example, the lower surface of the through-silicon vias 220 may be joined and connected to the upper surface of the first through-via 130 and the first wiring pattern 120.

[0052] Each through-silicon via 220 can have any suitable shape, including, for example, a cylindrical shape. The diameter of each through-silicon via 220 in the horizontal direction (X or Y direction) can be constant along the vertical direction (Z direction). In another embodiment, a plurality of through-silicon vias 220 can have a tapered shape, which has a diameter that varies along the vertical direction (Z direction) in the horizontal direction (X or Y direction), depending on manufacturing conditions.

[0053] The second build-up layer 300 can be located on the silicon interposer 200. The second build-up layer 300 can include one or more second build-up insulating layers 310, second wiring patterns 320, and second through-vias 330. The second wiring patterns 320 and the second through-vias 330 can be included or contained in the second build-up insulating layer 310. However, the embodiments are not limited thereto. For example, instead of the build-up layer, a redistribution layer including one or more redistribution insulating layers, wiring patterns, and vias can be provided.

[0054] The second build-up insulating layers 310 can be stacked in the vertical direction (Z direction). The second build-up insulating layers 310 can include insulating materials such as ABF, oxides, and nitrides, photoimageable dielectrics (PID) resins prepared by combining epoxy resins and photoinitiators, and can further include photosensitive polyimides and / or inorganic fillers, etc., without being limited thereto.

[0055] The second wiring patterns 320 and the second through-vias 330 can be provided as conductive patterns, and the conductive patterns can be located in the second build-up insulating layer 310. The second wiring patterns 320 can extend in the horizontal direction (X direction and / or Y direction) and are provided at different vertical levels within the second build-up insulating layer 310. The second through-vias 330 can penetrate one or more second build-up insulating layers 310 in the vertical direction (Z direction) to interconnect the second wiring patterns 320 and electrically connect the second wiring patterns 320.

[0056] According to an embodiment, at least some of the second wiring patterns 320 can be provided integrally with some of the second through-vias 330. For example, the second wiring patterns 320 and the second through-vias 330 that are in contact with each other can be integrally formed as a single and continuous structure without an interface therebetween.

[0057] According to an embodiment, the second through-vias 330 can have any suitable shape, including, for example, a tapered shape, where the horizontal width of the second through-vias 330 decreases in the vertical direction (Z direction) away from the first semiconductor chip 10 and the second semiconductor chip 20, depending on manufacturing conditions.

[0058] The second wiring pattern 320 and the second vias 330 may include, for example, metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), and alloys thereof, but are not limited thereto.

[0059] The first semiconductor chip 10 and the second semiconductor chip 20 may be provided on the upper surface of the second stacked layer 300.

[0060] The first semiconductor chip 10 and the second semiconductor chip 20 may be, for example, a high bandwidth memory (HBM) and a system on chip (SOC). However, the embodiments are not limited thereto, and semiconductor chips other than SOC or HBM may be provided, such as, for example, logic chips (such as a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), an application specific integrated circuit (ASIC)) or memory chips (such as a dynamic random access memory (DRAM) chip and a NAND chip).

[0061] The connection member 11 may be provided between the lower surface of the first semiconductor chip 10 and the upper surface of the second stacked layer 300. The lower surface of the first semiconductor chip 10 may include connection pads. The connection pads of the first semiconductor chip 10 may be electrically connected to the second stacked layer 300 through the connection member 11. The underfill layer 12 may be provided adjacent to and surrounding the connection member 11 between the first semiconductor chip 10 and the second stacked layer 300. The connection member 11 may be provided between the active lower surface of the second semiconductor chip 20 and the upper surface of the second stacked layer 300. In one example, the connection member 11 may contact a capacitor among at least one capacitor. The lower surface of the second semiconductor chip 20 may include connection pads. The connection pads of the second semiconductor chip 20 may be electrically connected to the second stacked layer 300 through the connection member 11. The underfill layer 12 may be provided adjacent to and surrounding the connection member 11 between the second semiconductor chip 20 and the second stacked layer 300. The underfill layer 12 may include an inclined outer surface. The underfill layer 12 may include an epoxy resin or a mixture of two or more silicone materials.

[0062] The semiconductor package 1 may further include one or more integrated stacked capacitors (ISC) 500. Each of the one or more ISCs 500 may be a silicon-based ISC 500, which includes a concave array having capacitive vias with a vertical cylindrical shape respectively on a silicon backplane. The thickness of the ISC 500 in the Z direction may range from less than 2 μm to 780 μm. However, the embodiments are not limited thereto. For example, the vertical cylindrical array may have a size of 2×2 μm 2 and the ISC 500 may include a concave array. For example, the capacitance value of the ISC 500 may be about several hundreds of nF / mm 2 . Therefore, compared with, for example, a multilayer ceramic capacitor (MLCC), the ISC 500 may have a relatively small size and a relatively high capacitance density.

[0063] Due to the relatively small size of the ISC 500 having a thickness that may be equal to or less than 2 μm in the vertical direction (Z direction), the ISC 500 may be provided at various positions in the semiconductor package 1. For example, referring to Figure 1 , since the thickness of the stacked layer may range from about 10 μm to 25 μm and is greater than the thickness of the ISC 500, one or more ISCs 500 may be embedded in the first stacked insulating layer 110 and the second stacked insulating layer 310. One or more ISCs 500 may be placed at the surface layer of the first stacked insulating layer 110 as a ground-side capacitor (LSC) and placed at the surface layer of the second stacked layer 300 as a die-side capacitor (DSC). In addition, one or more ISCs 500 may be provided in a shallow groove or cavity formed on the surface of the silicon substrate 210. As described in more detail below, during a laser grooving process for manufacturing the through-silicon vias 220 in the silicon substrate 210, a shallow groove having a depth (thickness) of about 3 μm to 25 μm in the vertical direction (Z direction) may be manufactured in at least one of the upper surface and the lower surface of the silicon substrate 210. Therefore, when the ISC 500 is placed in the shallow groove of the silicon substrate 210, a separate step of providing space to include the ISC 500 in the silicon substrate 210 may be omitted, and the manufacturing process may be more simplified. However, the embodiments are not limited thereto, and the thickness of one or more ISCs 500 may be adjusted to be the same as the thickness of the silicon substrate 210 in the vertical direction (Z direction).

[0064] Figures 2A to 2E is a cross-sectional view showing a method of manufacturing a silicon interposer and a stacked insulating layer included in a semiconductor package according to one or more embodiments. For the sake of brevity, descriptions overlapping with the previous drawings will be omitted, and the differences will be mainly described. The silicon interposer and the stacked layer manufactured by the method described below may be or correspond to Figure 1The silicon interposer 200 and the stacked layers 100 and 300 shown in [reference], thus, the same reference numerals as shown below can be used. Figure 1 as shown in [reference].

[0065] Referring Figure 2A to [reference], one or more shallow grooves 41 having a depth of 3 to 25 μm in the vertical direction (Z direction) are formed in the silicon substrate 210 by a laser grooving process, and a groove 42 penetrating the silicon substrate 210 is formed. The groove 42 can be provided to form a through-silicon via (TSV) 220, and the shallow groove 41 can be provided to embed an ISC 500 therein.

[0066] Referring Figure 2B to [reference], one or more ISCs 500 can be provided in the one or more shallow grooves 41 provided in the silicon substrate 210. For example, the ISC 500 can be embedded in the upper surface and / or the lower surface of the silicon substrate 210. However, the embodiments are not limited thereto, and additional ISCs 500 can be embedded inside the silicon substrate 210.

[0067] Referring Figure 2C to [reference], a first stacked insulating layer 110 can be provided to cover the lower surface of the silicon substrate 210, and a second stacked insulating layer 310 can be provided to cover the upper surface of the silicon substrate 210 and the groove 42. The first stacked insulating layer 110 and the second stacked insulating layer 310 can be integrally formed as a single structure and can be used interchangeably in the present disclosure. The second stacked insulating layer 310 can cover the upper surface of the one or more ISCs 500.

[0068] Referring Figure 2D to [reference], a through-silicon tunnel 221 can be formed, for example, by a laser process, wet etching, or dry etching. Additionally, based on a via-in-via process in the through hole, a trench 33 is formed on the upper surface of the second stacked insulating layer 310 to expose a part of the upper surface of the ISC 500.

[0069] Referring Figure 2E, a metal material is filled in the through-silicon via 221 to form a through-silicon via 220, and a metal material is filled in the trench 33 to form a second through-via 330. A first wiring pattern 120 can be formed on the lower surface of the silicon substrate 210 and a second wiring pattern 320 can be formed on the upper surface of the silicon substrate 210 to contact the through-silicon via 220 and the second through-via 330. The metal materials filled in the through-silicon via 221 and the trench 33 can include a conductive material, which includes, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and combinations thereof. The upper surface of the through-silicon via 220 can be coplanar with the upper surface of the second stacked insulating layer 310 on the silicon substrate 210, and the lower surface of the through-silicon via 220 can be coplanar with the lower surface of the first stacked insulating layer 110 under the silicon substrate 210.

[0070] Additional components (e.g., components as shown in Figure 2E ) can be provided on the silicon interposer and the stacked insulating layer as shown in Figure 1 .

[0071] Figures 3A to 3D FIG. is a cross-sectional view showing a method of manufacturing a silicon interposer and a stacked layer included in a semiconductor package according to one or more other embodiments. For the sake of brevity, descriptions overlapping with the previous figures will be omitted, and the differences will be mainly described. The silicon interposer and the stacked layer manufactured by the method described below can be or correspond to the silicon interposer 200 and the stacked layers 100 and 300 shown in Figure 1 , and thus, the same reference numerals shown in Figure 1 can be used below.

[0072] Referring to Figure 3A , the silicon substrate 210 can include a through-silicon via 220 formed by a laser grooving process for forming a shallow groove 41 on the silicon substrate, a wet etching process for forming a through-silicon via, and a metallization process for filling the through-silicon via with a metal material, as described above with reference to Figures 2A to 2D . Compared with Figure 2A , one or more shallow grooves 41 for embedding one or more ISCs 500 may not be formed. The second wiring pattern 320 and the first wiring pattern 120 can be provided on the upper surface and the lower surface of the silicon substrate 210, respectively. A part of the second wiring pattern 320 and a part of the first wiring pattern 120 are directly provided on the upper surface and the lower surface of the through-silicon via 220, respectively, and a circuit path can be provided together with the through-silicon via 220.

[0073] Referring to Figure 3B, one or more ISCs 500 may be provided on at least two adjacent second wiring patterns 320. For example, each of the one or more ISCs 500 may contact the upper surfaces of at least two adjacent second wiring patterns 320 spaced apart from each other and connect the adjacent second wiring patterns 320.

[0074] Reference Figure 3C , an additional first stacked insulating layer 110 may be laminated on the lower surface of the silicon substrate 210, and a second stacked insulating layer 310 may be laminated on the upper surface of the silicon substrate 210. The second stacked insulating layer 310 may cover the second wiring pattern 320 and the ISC 500, and the first stacked insulating layer 110 may cover the lower surface of the silicon substrate 210 and the first wiring pattern 120. According to one or more embodiments, instead of the first stacked insulating layer 110 and the second stacked insulating layer 310, one or more redistribution layers may be laminated on the upper surface and the lower surface of the silicon substrate 210.

[0075] Reference Figure 3D , a first through-via 130 may be formed in the first stacked insulating layer 110, and a second through-via 330 may be formed in the second stacked insulating layer 310. One or more second through-vias 330 may penetrate one or more second stacked insulating layers 310 and contact the upper surface of the ISC 500, and the other side of the one or more second through-vias 330 may contact the second wiring pattern 320, as Figure 1 shown. The first through-via 130 may penetrate one or more first stacked insulating layers 110. In addition, the first through-via 130 may interconnect the first wiring patterns 120 provided at different vertical levels, and the second through-via 330 may interconnect the second wiring patterns 320 provided at different vertical levels, also as Figure 1 shown. The first through-via 130 and the second through-via 330 may include, for example, metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), and their alloys, but are not limited thereto. Additional first stacked insulating layers 110, first wiring patterns 120, and first through-vias 130 may be provided, and additional second stacked insulating layers 310, second wiring patterns 320, and second through-vias 330 may be provided.

[0076] Additional elements (e.g., elements as shown in Figure 3D ) may be provided on the silicon interposer and the stacked layer as shown in Figure 1 .

[0077] Figure 4A ShowsFigure 3D An enlarged cross-sectional view of region A in Figure 4B shows Figure 3D an enlarged cross-sectional view of region B in

[0078] Figure 4A shows Figure 3D region A of , which shows the ISC 500 embedded in the second stacked insulating layer 310. The lower surface of the ISC 500 can contact the upper surfaces of two adjacent second wiring patterns 320.

[0079] Figure 4B shows Figure 3D region B of , which shows the ISC 500 embedded in the second stacked insulating layer 310. The lower surface of the ISC 500 can contact the upper surface of an adjacent second wiring pattern 320, and the upper surface of the ISC 500 can contact the lower surface of the second via 330.

[0080] As Figure 4A and Figure 4B shown, the thickness of the ISC 500 equal to or less than 2 μm can be less than the thickness of the second stacked insulating layer 310, and the thickness of the second stacked insulating layer 310 can be in the range from 10 μm to 25 μm in the vertical direction (Z direction). Therefore, the ISC 500 can be embedded in the second stacked insulating layer 310, and the vertical size of the semiconductor package 1 can be reduced.

[0081] Figures 5A to 5D is a cross-sectional view showing a method of manufacturing a silicon interposer and stacked layers included in a semiconductor package according to one or more other embodiments. For the sake of brevity, descriptions overlapping with the previous drawings will be omitted, and the differences will be mainly described. The silicon interposer and stacked layers manufactured in the method described below can be or correspond to Figure 1 the silicon interposer 200 and stacked layers 100 and 300 shown in , and thus, the same reference numerals as shown in Figure 1 can be used below.

[0082] Referring to Figure 5A , the silicon substrate 210 can include through-silicon vias 220 formed by a laser grooving process for forming shallow grooves on the silicon substrate, a wet etching process for forming through-silicon tunnels, and a metallization process for filling the through-silicon tunnels with a metal material, as described above with reference to Figures 2A to 2D . The second wiring pattern 320 can be provided on the upper surface of the silicon substrate 210. A part of the second wiring pattern 320 is directly provided on the upper surface of the through-silicon via 220, and can provide a circuit path together with the through-silicon via 220.

[0083] Referring to Figure 5B, one or more ISCs 500 can be directly provided on the upper surface of the second stacked insulating layer 310 on the silicon substrate 210 and adjacent to one or more second wiring patterns 320 provided on the upper surface of the silicon substrate 210. For example, the lower surface of the ISC 500 can be coplanar with the upper surface of the second stacked insulating layer 310 on the silicon substrate 210 and the lower surface of the adjacent second wiring pattern 320. However, the embodiments are not limited thereto, and additional ISCs 500 can be embedded in the silicon substrate 210 and / or different layers for the first stacked insulating layer 110 and the second stacked insulating layer 310.

[0084] Reference Figure 5C , the first stacked insulating layer 110 can be laminated on the lower surface of the silicon substrate 210, and the second stacked insulating layer 310 can be laminated on the upper surface of the silicon substrate 210. The second stacked insulating layer 310 can cover the second wiring pattern 320 and the ISC 500, and the first stacked insulating layer 110 can cover the lower surface of the silicon substrate 210 and the first wiring pattern 120. According to an embodiment, instead of the first stacked insulating layer 110 and the second stacked insulating layer 310, one or more redistribution layers can be laminated on the upper and lower surfaces of the silicon substrate 210.

[0085] Reference Figure 5D , the first via 130 can be formed in the first stacked insulating layer 110, and the second via 330 can be formed in the second stacked insulating layer 310. The first via 130 can penetrate one or more first stacked insulating layers 110, and the second via 330 can penetrate one or more second stacked insulating layers 310. The first via 130 can interconnect the first wiring patterns 120 provided at different vertical levels, and the second via 330 can interconnect the second wiring patterns 320 provided at different vertical levels, as Figure 1 shown. In addition, one or more second vias 330 can be provided to contact one or more ISCs 500. For example, the lower surface of the one or more second vias 330 can directly contact the upper surface of the ISC 500. The first via 130 and the second via 330 can include, for example, metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), and their alloys, but are not limited thereto. Additional first stacked insulating layers 110, first wiring patterns 120, and first vias 130 can be provided, and additional second stacked insulating layers 310, second wiring patterns 320, and second vias 330 can be provided.

[0086] Additional elements (e.g., the elements as shown in Figure 1 ) can be provided on the silicon interposer and the build-up layer, as shown in Figure 5D .

[0087] Figure 6A shows an enlarged cross-sectional view of region C in Figure 5D , and Figure 6B shows an enlarged cross-sectional view of region D in Figure 5D .

[0088] Figure 6A shows region C of Figure 5D , which shows that the ISC 500 is embedded in the second build-up insulating layer 310 and connected to adjacent second vias 330. The upper surface of the ISC 500 can contact the lower surfaces of two adjacent second vias 330, and the lower surface of the ISC 500 can contact the second build-up insulating layer 310 on the silicon substrate 210.

[0089] Figure 6B shows region D of Figure 5D , which shows that the ISC 500 is embedded in the second build-up insulating layer 310 and connected to adjacent second vias 330. The upper surface of the ISC 500 can contact the lower surfaces of three adjacent second vias 330, and the lower surface of the ISC 500 can contact the second build-up insulating layer 310 on the silicon substrate 210. As shown in Figure 6A and Figure 6B , the thickness of the ISC500 that is equal to or less than 2μm can be less than the thickness of the second build-up insulating layer 310, and the thickness of the second build-up insulating layer 310 can be in the range of 10μm to 25μm in the vertical direction (Z direction). Therefore, since the ISC 500 can be embedded in the second build-up insulating layer 310, the vertical size of the semiconductor package 1 can be reduced.

[0090] Figure 7 shows a semiconductor package according to one or more other embodiments. For the sake of brevity, the description overlapping with the previous figures will be omitted, and the differences will be mainly described.

[0091] Referring to Figure 7 , as compared with Figure 1Compared with the semiconductor package 1 shown in [reference], in addition to the first semiconductor chip 10 and the second semiconductor chip 20 provided on the upper surface of the second stacking layer 300, the semiconductor package 2 may include a third semiconductor chip 30 and a fourth semiconductor chip 40 embedded in the silicon substrate 210. For example, the third semiconductor chip 30 and the fourth semiconductor chip 40 may be provided in cavities adjacent to the through-silicon vias 220 in the silicon substrate 210. The upper surfaces of the third semiconductor chip 30 and the fourth semiconductor chip 40 may be coplanar with the upper surface of the silicon substrate 210. Connection pads may be provided on the surfaces of the third semiconductor chip 30 and the fourth semiconductor chip 40. One or more of the first through-via 130 and the second through-via 330 may be connected to the connection pads on the surfaces of the third semiconductor chip 30 and the fourth semiconductor chip 40. The first semiconductor chip 10 and the second semiconductor chip 20 may be, for example, high bandwidth memory (HBM) chips and the third semiconductor chip 30 and the fourth semiconductor chip 40 may be system-on-chip (SOC). However, the embodiments are not limited thereto, and semiconductor chips other than SOC or HBM may be provided, such as, for example, logic chips (such as central processing unit (CPU), graphics processing unit (GPU), field programmable gate array (FPGA), digital signal processor (DSP), application specific integrated circuit (ASIC)) or memory chips (such as dynamic random access memory (DRAM) chips and NAND chips).

[0092] As Figure 7 shown, the ISC 500 may be provided at various positions in the semiconductor package 2. For example, since the thicknesses of the first stacking layer 100 and the second stacking layer 300 may be in the range from about 10 μm to 25 μm, one or more ISC500 may be placed at the surface layer of the first stacked insulating layer 110 as a ground-side capacitor (LSC), and placed at the surface layer of the second stacking layer 300 as a die-side capacitor (DSC). In addition, one or more ISC 500 may be provided in shallow grooves or cavities formed on the surface of the silicon substrate 210. The thickness of each of the one or more ISC 500 embedded in the silicon substrate 210 may be less than or equal to the thickness of the silicon substrate 210 in the vertical direction (Z direction).

[0093] Reference Figure 7, since the ISC 500 can be embedded in the first stacked insulating layer 110, the second stacked insulating layer 310, and the silicon substrate 210, the ISC 500 can be provided closer to the first semiconductor chip 10, the second semiconductor chip 20, the third semiconductor chip 30, and the fourth semiconductor chip 40 compared to a semiconductor package including, for example, a multilayer ceramic capacitor (MLCC). Therefore, the vertical size of the semiconductor package 2 can be reduced, and the impedance of the power distribution network (PDN) for multiple frequency ranges (especially relatively high frequency ranges) can be reduced, and the performance of the semiconductor package 2 can be improved.

[0094] Figure 8 A semiconductor package according to one or more other embodiments is shown. For the sake of brevity, descriptions overlapping with the previous figures will be omitted, and the differences will be mainly described.

[0095] Reference Figure 8 , Figure 1 Compared with the semiconductor package 1 shown in

[0096] As Figure 8 shown, the ISC 500 can be provided at various positions in the semiconductor package 3. For example, since the thicknesses of the first stacked layer 100 and the second stacked layer 300 can be in the range from about 10 μm to 25 μm, one or more ISC500s can be placed at the surface layer of the first stacked insulating layer 110 as a ground-side capacitor (LSC), and placed at the surface layer of the second stacked layer 300 as a die-side capacitor (DSC). In addition, one or more ISC 500s can be provided in shallow grooves or cavities formed on the surface of the silicon substrate 210. The thickness of each of the one or more ISC 500s embedded in the silicon substrate 210 can be less than or equal to the thickness of the silicon substrate 210 in the vertical direction (Z direction).

[0097] Reference Figure 8 , since the ISC 500 can be embedded in the first stacked insulating layer 110, the second stacked insulating layer 310, and the silicon substrate 210, the ISC 500 can be provided closer to the first semiconductor chip 10, the second semiconductor chip 20, the third semiconductor chip 30, and the fourth semiconductor chip 40 compared to a semiconductor package including, for example, a multilayer ceramic capacitor (MLCC). Therefore, the vertical size of the semiconductor package 3 can be reduced, and the impedance of the power distribution network (PDN) for multiple frequency ranges (especially relatively high frequency ranges) can be reduced, and the performance of the semiconductor package 3 can be improved.

[0098] Figure 9 Shows a semiconductor package according to one or more other embodiments. For the sake of brevity, descriptions overlapping with the previous figures will be omitted, and the differences will be mainly described.

[0099] Reference Figure 9 , compared with the semiconductor package 1 shown in Figure 1 , in addition to the first semiconductor chip 10 and the second semiconductor chip 20, the semiconductor package 4 may include a third semiconductor chip 30 and a fourth semiconductor chip 40 similar to those shown in Figure 7 embedded in the silicon substrate 210, and a fifth semiconductor chip 50 and a sixth semiconductor chip 60 similar to those shown in Figure 8 on the lower surface of the first stacked layer 100. For example, the third semiconductor chip 30 and the fourth semiconductor chip 40 may be provided in cavities adjacent to the through-silicon vias 220 in the silicon substrate 210. The upper surfaces of the third semiconductor chip 30 and the fourth semiconductor chip 40 may be coplanar with the upper surface of the silicon substrate 210. Connection pads may be provided on the surfaces of the third semiconductor chip 30 and the fourth semiconductor chip 40. One or more of the first through-via 130 and the second through-via 330 may be connected to the connection pads on the surfaces of the third semiconductor chip 30 and the fourth semiconductor chip 40.

[0100] As Figure 9 shown, one or more ISCs 500 may be provided at various positions in the semiconductor package 4. For example, since the thicknesses of the first stacked layer 100 and the second stacked layer 300 may be in the range from about 10 μm to 25 μm, the one or more ISCs 500 may be placed as ground-side capacitors (LSCs) at the surface layer of the first stacked insulating layer 110 and as die-side capacitors (DSCs) at the surface layer of the second stacked layer 300. In addition, one or more ISCs 500 may be provided in shallow grooves or cavities formed on the surface of the silicon substrate 210. The thickness of each of the one or more ISCs 500 embedded in the silicon substrate 210 may be less than or equal to the thickness of the silicon substrate 210 in the vertical direction (Z direction).

[0101] Reference Figure 9, since the ISC 500 can be embedded in the first stacked insulating layer 110, the second stacked insulating layer 310, and the silicon substrate 210, the ISC 500 can be provided closer to the first semiconductor chip 10, the second semiconductor chip 20, the third semiconductor chip 30, the fourth semiconductor chip 40, the fifth semiconductor chip 50, and the sixth semiconductor chip 60 compared to a semiconductor package including, for example, a multilayer ceramic capacitor (MLCC). Therefore, the vertical size of the semiconductor package 4 can be reduced, the impedance of the power distribution network (PDN) for multiple frequency ranges (especially relatively high frequency ranges) can be reduced, and the performance of the semiconductor package 4 can be improved.

[0102] Figure 10 A semiconductor package according to one or more other embodiments is shown. For the sake of brevity, descriptions overlapping with the previous figures will be omitted, and the differences will be mainly described.

[0103] Reference Figure 10 , compared with Figure 9 the semiconductor package 4 shown, in addition to the first semiconductor chip 10, the second semiconductor chip 20, the third semiconductor chip 30, the fourth semiconductor chip 40, the fifth semiconductor chip 50, and the sixth semiconductor chip 60, the semiconductor package 5 may include at least one additional silicon substrate 210 stacked on the silicon substrate 210. In addition, similar to the third semiconductor chip 30 and the fourth semiconductor chip 40, the seventh semiconductor chip 70 and the eighth semiconductor chip 80 may be embedded in the silicon substrate 210'.

[0104] As Figure 10 shown, the ISC 500 can be provided at various positions in the semiconductor package 5. For example, since the thicknesses of the first stacked layer 100 and the second stacked layer 300 can be in the range from about 10 μm to 25 μm, one or more ISC500s can be placed at the surface layer of the first stacked insulating layer 110 as a ground-side capacitor (LSC), and placed at the surface layer of the second stacked layer 300 as a die-side capacitor (DSC). Additionally, one or more ISC 500s can be provided in shallow grooves or cavities formed on the surface of the silicon substrate 210. The thickness of each of the one or more ISC 500s embedded in the silicon substrate 210 can be less than or equal to the thickness of the silicon substrate 210 in the vertical direction (Z direction).

[0105] Reference Figure 10, since the ISC 500 can be embedded in the first stacked insulating layer 110, the second stacked insulating layer 310, and the silicon substrates 210 and 210', compared with a semiconductor package including, for example, a multilayer ceramic capacitor (MLCC), the ISC 500 can be provided closer to the first semiconductor chip 10, the second semiconductor chip 20, the third semiconductor chip 30, the fourth semiconductor chip 40, the fifth semiconductor chip 50, the sixth semiconductor chip 60, the seventh semiconductor chip 70, and the eighth semiconductor chip 80. Therefore, the vertical size of the semiconductor package 5 can be reduced, and the impedance of the power distribution network (PDN) for multiple frequency ranges (especially relatively high frequency ranges) can be reduced, and the performance of the semiconductor package 5 can be improved.

[0106] Figure 11 A semiconductor package according to one or more other embodiments is shown. For the sake of brevity, the description overlapping with the previous figures will be omitted, and the differences will be mainly described.

[0107] Reference Figure 11 , the semiconductor package 6 can be a three-dimensional (3D) stacked semiconductor package, which includes silicon interposers 200 stacked on top of each other. For example, Figure 11 Three stacked silicon interposers 200 are shown, but the embodiments are not limited thereto. Each silicon interposer 200 may include semiconductor chips 90, 91, and 92 embedded therein. The silicon interposer 200 may be the same as the silicon interposer described with reference to Figure 1 . The silicon interposers 200 may be connected to each other through external connection terminals 170. The semiconductor chips 90, 91, and 92 may each be a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a logic die, etc., but the embodiments are not limited thereto.

[0108] As Figure 11 shown, the ISC 500 can be provided at various positions in the semiconductor package 5. For example, since the thickness of the first stacked layer 100 and the second stacked layer 300 in each silicon interposer 200 can be in the range from about 10 μm to 25 μm, one or more ISC 500s can be placed at the surface layer of the first stacked insulating layer 110 as a ground-side capacitor (LSC) and at the surface layer of the second stacked layer 300 as a die-side capacitor (DSC). In addition, one or more ISC 500s can be provided in one or more shallow grooves or cavities formed on the surface of the silicon substrate 210. The thickness of the one or more ISC 500s embedded in the silicon substrate 210 can be less than or equal to the thickness of the silicon substrate 210 in the vertical direction (Z direction).

[0109] Reference Figure 11, since the ISC 500 can be embedded in the first stacked insulating layer 110, the second stacked insulating layer 310, and the silicon substrate 210, the ISC 500 can be provided closer to the semiconductor chips 90, 91, and 92 compared to a semiconductor package including, for example, a multilayer ceramic capacitor (MLCC). Therefore, the vertical size of the semiconductor package 6 can be reduced, and the impedance of the power distribution network (PDN) for multiple frequency ranges (especially relatively high frequency ranges) can be reduced, and the performance of the semiconductor package 6 can be improved.

[0110] Figure 12 A flowchart of manufacturing a semiconductor package according to one or more embodiments is shown.

[0111] In operation S110, a silicon interposer including a silicon substrate and through-silicon vias vertically penetrating the silicon substrate is formed. The silicon substrate is laser processed to form shallow grooves and / or cavities on the upper and lower surfaces of the silicon substrate, and a part of the shallow grooves and / or cavities is wet-etched or dry-etched to form through-silicon tunnels penetrating the silicon substrate. The through-silicon tunnels are filled with a metal material to form through-silicon vias. The metal material may include a conductive material including, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), titanium (Ti), and combinations thereof, but the embodiments are not limited thereto. One or more ISCs may be embedded in the one or more shallow grooves and / or cavities of the silicon substrate.

[0112] In operation S120, a first stacked layer is formed on the lower surface of the silicon interposer. The first stacked insulating layer is laminated on the lower surface of the silicon substrate and the one or more ISCs, and a first wiring pattern is formed on the first stacked insulating layer. First through-vias are formed to penetrate the first stacked insulating layer, and may interconnect the first wiring patterns provided at different vertical levels and connect one or more first wiring patterns to the ISCs. An additional layer of the first stacked insulating layer having the first wiring pattern and the first through-vias may be formed on the lower surface of the first stacked insulating layer. In addition, one or more ISCs may be embedded in one of the first stacked insulating layers or different levels of the first stacked insulating layer and connected to at least one of the first through-vias and the first wiring pattern. A passivation layer may be formed on the lowermost first stacked insulating layer. A under-bump metal (UBM) layer and a conductive layer may be formed, and external connection terminals may be formed on the conductive layer to connect the semiconductor package to an external device.

[0113] In operation S130, a second stacked layer is formed on the upper surface of the silicon interposer. The second stacked insulating layer is laminated on the upper surface of the silicon substrate and on the one or more ISCs embedded in the silicon substrate, and a second wiring pattern is formed on the second stacked insulating layer. Second vias are formed to penetrate the second stacked insulating layer and may interconnect the second wiring patterns provided at different vertical levels. An additional layer of the second stacked insulating layer having the second wiring pattern and the second vias may be formed on the upper surface of the second stacked insulating layer. Additionally, one or more ISCs may be embedded in one of the second stacked insulating layers or in different levels of the second stacked insulating layer and connected to at least one of the second vias and the second wiring pattern. At operation S140, one or more semiconductor chips may be provided. For example, semiconductor chips may be provided on the lower surface of the first stacked layer and on the upper surface of the second stacked layer. Connection members may be formed to connect the semiconductor chips to the first wiring pattern and the second wiring pattern included in the first stacked layer and the second stacked layer. A bottom fill layer may fill the space between the connection members. The semiconductor chips may be, for example, logic chips such as a CPU, GPU, FPGA, DSP, ASIC, SOC chip, HBM chip, DRAM chip, SRAM chip, NAND chip, etc., however, the embodiments are not limited thereto. According to one or more other embodiments, semiconductor chips may also be provided in cavities formed in the silicon substrate before forming the first stacked layer and the second stacked layer. Additionally, multiple silicon interposers may be stacked on top of each other and directly connected to each other or connected to each other through external connection terminals therebetween.

[0114] Figure 13 A semiconductor package architecture is shown that may incorporate a semiconductor package according to one or more embodiments.

[0115] Reference Figure 13 , a semiconductor package architecture 2000 according to one or more embodiments may include a processor 2200 and semiconductor devices 2300 mounted on a substrate 2100. The processor 2200 and / or the semiconductor devices 2300 may include one or more semiconductor packages described in the above embodiments.

[0116] Figure 14 A schematic block diagram of an electronic system according to one or more embodiments is shown.

[0117] Reference Figure 14, an electronic system 3000 according to one or more embodiments may include a microprocessor 3100, a memory 3200, and a user interface 3300 that perform data communication using a bus 3400. The microprocessor 3100 may include a central processing unit (CPU) or an application processor (AP). The electronic system 3000 may further include a random access memory (RAM) 3500 that communicates directly with the microprocessor 3100. The microprocessor 3100 and / or the RAM 3500 may be implemented in a single module or package. The user interface 3300 may be used to input data into the electronic system 3000 or output data from the electronic system 3000. For example, the user interface 3300 may include a keyboard, a touchpad, a touch screen, a mouse, a scanner, a voice detector, a liquid crystal display (LCD), a micro light emitting diode (LED), an organic light emitting diode (OLED) device, an active matrix organic light emitting diode (AMOLED) device, a printer, a lighting device, or various other input / output devices, but is not limited thereto. The memory 3200 may store the operating code of the microprocessor 3100, the data processed by the microprocessor 3100, or the data received from an external device. The memory 3200 may include a memory controller, a hard disk, or a solid state drive (SSD).

[0118] At least the microprocessor 3100, the memory 3200, and / or the RAM 3500 in the electronic system 3000 may include a semiconductor package as described in the above embodiments.

[0119] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered available for other similar features or aspects in other embodiments.

[0120] Although the embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims and their equivalents.

[0121] Cross - reference to related applications

[0122] This application is based on and claims the benefit of U.S. Provisional Application No. 63 / 611,535, filed on December 18, 2023, with the United States Patent and Trademark Office, the disclosure of which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor package, comprising: a silicon substrate including a through-silicon via; A first accumulation layer is disposed on a first surface of the silicon substrate; a second accumulation layer, on the second surface of the silicon substrate; as well as At least one capacitor is included in at least one of the silicon substrate, the first buildup layer, and the second buildup layer.

2. The semiconductor package according to claim 1, wherein The first stacking layer comprises: a first build-up insulating layer; a plurality of first wiring patterns; and a first through via connecting the plurality of first wiring patterns, and The second stacking layer comprises: a second build-up insulating layer; a plurality of second wiring patterns; and The second through via connects the plurality of second wiring patterns.

3. The semiconductor package according to claim 2, wherein: A capacitor among the at least one capacitor is located on at least one of a first surface of the first buildup layer and a second surface of the second buildup layer.

4. The semiconductor package according to claim 2, wherein: A capacitor among the at least one capacitor is included in at least one of the first buildup insulating layer and the second buildup insulating layer, and wherein the capacitor is connected to at least one of the plurality of first wiring patterns, the first through via, the plurality of second wiring patterns, and the second through via.

5. The semiconductor package according to claim 2, wherein: A capacitor of the at least one capacitor is included in the second buildup insulating layer, and The capacitor is located on second surfaces of two adjacent second wiring patterns among the plurality of second wiring patterns.

6. The semiconductor package according to claim 2, wherein: A capacitor of the at least one capacitor is included in the second buildup insulating layer, and Wherein, the capacitor is directly on the second surface of the silicon substrate.

7. The semiconductor package according to claim 1, wherein: The silicon substrate includes a groove on at least one of the first surface of the silicon substrate and the second surface of the silicon substrate, and Wherein, a capacitor among the at least one capacitor is provided in the groove.

8. The semiconductor package according to claim 1, further comprising: a semiconductor chip on at least one of the first surface of the first buildup layer and the second surface of the second buildup layer; as well as a connecting member between the semiconductor chip and at least one of the first buildup layer and the second buildup layer, Wherein, the connecting member contacts a capacitor among the at least one capacitor.

9. The semiconductor package according to claim 8, further comprising: a second semiconductor chip, included in the silicon substrate, Another capacitor among the at least one capacitor is included in the silicon substrate adjacent to the second semiconductor chip.

10. The semiconductor package according to claim 8, further comprising: a second silicon substrate including a through via, wherein a fourth semiconductor chip is included in the second silicon substrate, and Another capacitor among the at least one capacitor is included in the second silicon substrate.

11. The semiconductor package according to claim 2, further comprising: a third semiconductor chip, included in the silicon substrate, Wherein, a capacitor among the at least one capacitor is included in the silicon substrate adjacent to the third semiconductor chip.

12. The semiconductor package according to claim 11, wherein A second surface of the capacitor is connected to a first surface of the second through via.

13. The semiconductor package according to claim 1, wherein A capacitor of the at least one capacitor is included in the silicon substrate, and Wherein, the thickness of the capacitor is less than or equal to the thickness of the silicon substrate in the vertical direction.

14. The semiconductor package according to claim 1, wherein: A thickness of each of the at least one capacitor in a vertical direction is less than or equal to 2 μm.

15. A method for manufacturing a semiconductor package, the method comprising: providing a silicon substrate including a through-silicon via; Providing a first buildup layer on the first surface of the silicon substrate; providing a second buildup layer on the second surface of the silicon substrate; providing a capacitor in at least one of the silicon substrate, the first buildup layer, and the second buildup layer; as well as Semiconductor chips are provided.

16. The method according to claim 15, further comprising: forming a groove on at least one of the second surface of the silicon substrate and the first surface of the silicon substrate, Wherein, providing the capacitor includes providing the capacitor in the groove.

17. The method according to claim 15, wherein: Providing the second buildup layer includes providing a second buildup insulating layer, a plurality of second wiring patterns, and a second through via, and Wherein, providing the capacitor includes providing the capacitor in the second buildup insulating layer.

18. The method according to claim 15, wherein: Providing the second buildup layer includes providing a second buildup insulating layer, a plurality of second wiring patterns, and a second through via, and Wherein, providing the capacitor includes providing the capacitor in the second buildup insulating layer and directly on the second surface of the silicon substrate.

19. The method according to claim 15, wherein: The providing the semiconductor chip comprises providing the semiconductor chip in at least one of the silicon substrate, the first surface of the first buildup layer, and the second surface of the second buildup layer, The semiconductor chip overlaps with the capacitor in a vertical direction.

20. An electronic system comprising: at least one memory configured to store computer readable instructions and a plurality of data; as well as at least one processor configured to execute the computer-readable instructions and perform a plurality of computing operations using the plurality of data, Wherein, the at least one processor comprises a semiconductor package, and the semiconductor package comprises: a silicon substrate including a through-silicon via; A first accumulation layer is disposed on a first surface of the silicon substrate; A second accumulation layer is disposed on the second surface of the silicon substrate; and At least one capacitor is included in at least one of the silicon substrate, the first buildup layer, and the second buildup layer.

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