Power compensation device and method based on alternating load

Abstract

The invention relates to the technical field of power compensation, in particular to a power compensation device and method based on an alternating load. Comprising a filter and a controller, and the controller is the rear stage of the filter; the filter comprises an inductor I and a capacitor I, and the inductor I is arranged on a primary power supply positive line; one end of the first capacitor is connected with the end, close to the controller, of the first inductor, and the other end of the first capacitor is connected with a primary power supply loop. The controller comprises an FPGA, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a second inductor, a third inductor, a second capacitor and a third capacitor. The compensation method plays a key role specially aiming at the problem of input end voltage fluctuation caused when two paths of alternating loads work, and the increase of the output distortion rate is effectively controlled.

Description

Technical Field

[0001] The present invention relates to the technical field of power compensation, and particularly to a power compensation device and method based on an alternating load. Background Art

[0002] A cryogenic satellite detector requires two pulse tube cryocoolers for two-stage cooling of the detector. One is used to cool the peripheral devices of the detector, and the temperature requirement is relatively not so low (such as cooling to 70 - 80K); the other is used to cool the devices highly sensitive to temperature, such as high-performance infrared detectors that require deep cooling (cooling to below 8K).

[0003] Due to the different functional requirements of the two pulse tube cryocoolers, they need to operate at different alternating frequencies, which requires their controllers to be able to output two alternating loads with different frequencies. In such application scenarios, the dynamic change of the load power and the adjustment of the output frequency directly lead to the power demand of the front-end power supply system fluctuating within a wide range from 0W to 1000W. In view of the strict control requirements of the satellite platform for the bus current fluctuation, in order to effectively suppress the current fluctuation, a filter is usually designed in the front-end power supply system. However, although the introduction of the filter can improve the current fluctuation condition, it inevitably causes the fluctuation of the front-end power supply voltage of the controller.

[0004] The problem of the front-end power supply voltage fluctuation further has an adverse impact on the quality of the back-end output AC voltage. Specifically, the back-end output voltage fluctuation causes the distortion of the output AC voltage, resulting in an increase in the distortion rate of the output sine wave. The increase in the voltage distortion rate not only affects the stable operation of the AC load, but also may cause abnormal operation of the back-end motor, thereby affecting the performance and reliability of the entire aerospace system. Therefore, how to control the back-end output voltage distortion rate while ensuring that the front-end filter effectively suppresses the current fluctuation has become an urgent technical problem to be solved. Summary of the Invention

[0005] The present invention provides a power compensation device and method based on an alternating load, aiming to solve the problem of large distortion rate of the back-end output voltage caused by the front-end voltage fluctuation, so as to reduce the requirement for the front-end voltage stability and reduce the volume and weight of the filter.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] The present invention provides a power compensation device and method based on an alternating load, including a filter and a controller, and the controller is the subsequent stage of the filter;

[0008] The controller includes an FPGA, NMOS transistor 1, NMOS transistor 2, NMOS transistor 3, NMOS transistor 4, NMOS transistor 5, NMOS transistor 6, NMOS transistor 7, NMOS transistor 8, inductor 2, inductor 3, capacitor 2, and capacitor 3;

[0009] The drain of NMOS transistor 1 is connected to the positive line of the primary power supply, and the gate of NMOS transistor 1 is used to receive the SPWM1H signal sent by the FPGA; the drain of NMOS transistor 2 is connected to the source of NMOS transistor 1, the source of NMOS transistor 2 is connected to the return line of the primary power supply, and the gate of NMOS transistor 2 is used to receive the SPWM1L signal sent by the FPGA; the drain of NMOS transistor 3 is connected to the positive line of the primary power supply, and the gate of NMOS transistor 3 is used to receive the SPWM2H signal sent by the FPGA; the drain of NMOS transistor 4 is connected to the source of NMOS transistor 3, the source of NMOS transistor 4 is connected to the return line of the primary power supply, and the gate of NMOS transistor 4 is used to receive the SPWM2L signal sent by the FPGA; among them, the SPWM1H signal and the SPWM1L signal conduct alternately, and the two signals will not be high level at the same time; the SPWM2H signal and the SPWM2L signal conduct alternately, and the two signals will not be high level at the same time;

[0010] The drain of NMOS transistor 5 is connected to the positive line of the primary power supply, and the gate of NMOS transistor 5 is used to receive the SPWM3H signal sent by the FPGA; the drain of NMOS transistor 6 is connected to the source of NMOS transistor 5, the source of NMOS transistor 6 is connected to the return line of the primary power supply, and the gate of NMOS transistor 6 is used to receive the SPWM3L signal sent by the FPGA; the drain of NMOS transistor 7 is connected to the positive line of the primary power supply, and the gate of NMOS transistor 7 is used to receive the SPWM4H signal sent by the FPGA; the drain of NMOS transistor 8 is connected to the source of NMOS transistor 7, the source of NMOS transistor 8 is connected to the return line of the primary power supply, and the gate of NMOS transistor 8 is used to receive the SPWM4L signal sent by the FPGA; among them, the SPWM3H signal and the SPWM3L signal conduct alternately, and the two signals will not be high level at the same time; the SPWM4H signal and the SPWM4L signal conduct alternately, and the two signals will not be high level at the same time;

[0011] One end of inductor 2 is connected to the source of NMOS transistor 3, the other end of inductor 2 is connected to one end of capacitor 2, and the other end of capacitor 2 is connected to the source of NMOS transistor 1; one end of inductor 3 is connected to the source of NMOS transistor 7, the other end of inductor 3 is connected to one end of capacitor 3, and the other end of capacitor 3 is connected to the source of NMOS transistor 5.

[0012] Further, the filter includes an inductor 1 and a capacitor 1. The inductor 1 is disposed on the positive line of the primary power supply; one end of the capacitor 1 is connected to the end of the inductor 1 close to the controller, and the other end is connected to the return line of the primary power supply.

[0013] Further, the inductor 1 is a 6 mH inductor; the capacitor 1 is a 10 mF capacitor array composed of multiple capacitors in parallel.

[0014] A power compensation method based on an alternating load includes the following steps:

[0015] S1. The FPGA outputs a pulse width modulation wave of 20 KHz;

[0016] S2. Calculate the theoretical supply voltage V required by the first refrigerator from the controller: out1 :

[0017] V out1 = V in * sin(2π / n1 * m1) (1)

[0018] Then, calculate the theoretical supply voltage V required by the second refrigerator from the controller: out2 :

[0019] V out2 = V in * sin(2π / n2 * m2) (2)

[0020] Wherein, V in represents the theoretical voltage at the input end of the controller; n1 = 20000 / 42, n2 = 20000 / 18, m1 varies from 0 to n1, and m2 varies from 0 to n2;

[0021] S3. In each 20 KHz switching cycle, calculate the current output power value, and further calculate the front-end supply voltage fluctuation value ΔV caused by this output power value:

[0022] ΔV = K1 * V out1 + K2 * V out2 (3)

[0023] Wherein, K1 represents the coefficient of the change in the bus voltage caused by the first refrigerator when outputting voltage, and its value range is 0.01 to 0.1; K2 represents the coefficient of the change in the bus voltage caused by the second refrigerator when outputting voltage, and its value range is 0.01 to 0.1;

[0024] S4. Calculate the magnitude of the compensated voltage at the input end of the controller through the PID algorithm, that is, V in - ΔV;

[0025] S5. Calculate the actual output voltage of the controller at this time:

[0026] V′ out1 = (V in -ΔV) *sin(2π / n1*m1) (4)

[0027] V′ out2 = (V in -ΔV) *sin(2π / n2*m2) (5)

[0028] Among them, V′ out1 Represents the actual power supply voltage provided by the controller to the refrigerator; V' out2 Represents the actual power supply voltage provided by the controller to refrigerator 2;

[0029] S6. Adjust the values ​​of m1 and m2 according to the actual output voltage of the controller:

[0030] m′1=m1*V out1 / V′ out1 (6)

[0031] m′2=m2*V out2 / V′ out2 (7)

[0032] Among them, m′1 represents the actual value of m1, and m′2 represents the actual value of m2.

[0033] The beneficial effects achieved by the present invention are:

[0034] Power supply and filtering optimization: The technical solution disclosed in this invention significantly reduces the stability requirements for the front-end power supply voltage, thereby reducing the volume, weight and power consumption of the front-end filter. This not only reduces the cost investment of the product itself, but also reduces the transmission cost, providing strong support for the project in terms of cost control.

[0035] Compensation advantages of the method: The method disclosed in the present invention exhibits many advantages. On the one hand, it does not require too much additional hardware cost, thus controlling the cost increase from the source; on the other hand, the method eliminates the tedious steps of real-time acquisition of the input voltage, which not only reduces the stringent requirements on acquisition speed and accuracy, but also effectively avoids the risk of failure of the compensation algorithm due to acquisition anomalies, thereby greatly improving the stability of the system.

[0036] Improved debugging and load adaptability: The innovative way of achieving compensation adjustment with external instructions greatly facilitates the debugging work, allowing the equipment to easily adapt to alternating loads of different frequencies and powers. This high degree of adaptability enhances the equipment's ability to cope with complex external load environments and broadens its application range.

[0037] Solving the voltage fluctuation problem: Specifically targeting the voltage fluctuation problem at the input end caused by the operation of two alternating loads, this compensation method plays a key role and effectively controls the increase in the output distortion rate. Verified by actual tests on aerospace products, the AC voltage distortion rate at the backend output fully meets the requirements for the normal operation of the refrigerator, ensuring the stable operation of the refrigerator and the entire system, and providing a reliable guarantee for the smooth implementation of aerospace missions.

[0038] In addition, the present invention can not only be used to solve the voltage fluctuation problem at the input end caused by the operation of two alternating loads on spacecraft, but also shows a broader application prospect. Its core technical principle and compensation method can be extended to many other fields with similar alternating load voltage fluctuation problems. Whether it is the scenario of the coordinated operation of large-scale electromechanical equipment in industrial production or the complex power supply network nodes in the civilian field, as long as they are troubled by voltage fluctuations caused by alternating loads, the present invention is expected to become an effective solution to escort the stable and efficient operation of various systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0040] Figure 1 It is a schematic circuit diagram of the power compensation device disclosed by the present invention.

[0041] Figure 2 It is a schematic diagram of the principle of the power compensation device disclosed by the present invention.

[0042] In the figure, L1 is inductor one; L2 is inductor two; L3 is inductor three; C1 is capacitor one; C2 is capacitor two; C3 is capacitor three; P1 is NMOS transistor one; P2 is NMOS transistor two; P3 is NMOS transistor three; P4 is NMOS transistor four; P5 is NMOS transistor five; P6 is NMOS transistor six; P7 is NMOS transistor seven; P8 is NMOS transistor eight. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0044] It should be noted that if there are directional indications involved in the embodiments of the present invention (such as up, down, left, right, front, back...), then such directional indications are only used to explain the relative positional relationship, movement conditions, etc. between components in a specific posture (as shown in the attached drawings). If this specific posture changes, then the directional indications will also change accordingly.

[0045] In addition, if there are descriptions such as "first", "second", etc. involved in the embodiments of the present invention, then such descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second" may explicitly or implicitly include at least one such feature. In addition, the meaning of "and / or" appearing throughout the text is that it includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, or solution B, or a solution where A and B are satisfied simultaneously. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0046] The controller of the present invention outputs a sine voltage and power according to the power demand of the refrigerator. According to the characteristics of the front-end LC filter, the load characteristics of the two refrigerators at the back-end, and the currently output power value, it calculates the magnitude of the voltage fluctuation at the input end of the current controller. According to this fluctuating voltage, it calculates the voltage that needs to be adjusted for output, and finally ensures that the output voltage meets the requirements of the back-end refrigerator.

[0047] As Figures 1 - 2 shown, the present invention provides a power compensation device based on an alternating load, including a filter and a controller, and the controller is the subsequent stage of the filter;

[0048] The filter includes an inductor L1 and a capacitor C1. The inductor L1 is arranged on the positive line of the primary power supply; one end of the capacitor C1 is connected to the end of the inductor L1 close to the controller, and the other end is connected to the return line of the primary power supply;

[0049] The controller includes an FPGA (not shown in the figure, mainly used to output SPWM signals), NMOS transistor P1, NMOS transistor P2, NMOS transistor P3, NMOS transistor P4, NMOS transistor P5, NMOS transistor P6, NMOS transistor P7, NMOS transistor P8, inductor L2, inductor L3, capacitor C2, and capacitor C3;

[0050] The drain of the NMOS transistor P1 is connected to the positive line of the primary power supply. The gate of the NMOS transistor P1 is used to receive the SPWM1H signal sent by the FPGA. The drain of the NMOS transistor P2 is connected to the source of the NMOS transistor P1. The source of the NMOS transistor P2 is connected to the return line of the primary power supply. The gate of the NMOS transistor P2 is used to receive the SPWM1L signal sent by the FPGA. The drain of the NMOS transistor P3 is connected to the positive line of the primary power supply. The gate of the NMOS transistor P3 is used to receive the SPWM2H signal sent by the FPGA. The drain of the NMOS transistor P4 is connected to the source of the NMOS transistor P3. The source of the NMOS transistor P4 is connected to the return line of the primary power supply. The gate of the NMOS transistor P4 is used to receive the SPWM2L signal sent by the FPGA. Among them, the SPWM1H signal and the SPWM1L signal are alternately turned on (they are complementary. Similarly, the SPWM2H and SPWM2L, SPWM3H and SPWM3L signals are alternately turned on). The two signals will not be high level at the same time. The SPWM2H signal and the SPWM2L signal are alternately turned on. The two signals will not be high level at the same time. In addition, when outputting a sine wave, SPWM1H is turned on in the upper half cycle and SPWM2H is turned on in the lower half cycle. When the two are turned on at the same time, the output level is 0, and the refrigerator does not work, and the equipment will not be damaged. The same applies to other signals and will not be elaborated one by one.

[0051] The drain of the NMOS transistor P5 is connected to the positive line of the primary power supply. The gate of the NMOS transistor P5 is used to receive the SPWM3H signal sent by the FPGA. The drain of the NMOS transistor P6 is connected to the source of the NMOS transistor P5. The source of the NMOS transistor P6 is connected to the return line of the primary power supply. The gate of the NMOS transistor P6 is used to receive the SPWM3L signal sent by the FPGA. The drain of the NMOS transistor P7 is connected to the positive line of the primary power supply. The gate of the NMOS transistor P7 is used to receive the SPWM4H signal sent by the FPGA. The drain of the NMOS transistor P8 is connected to the source of the NMOS transistor P7. The source of the NMOS transistor P8 is connected to the return line of the primary power supply. The gate of the NMOS transistor P8 is used to receive the SPWM4L signal sent by the FPGA. Among them, the SPWM3H signal and the SPWM3L signal are alternately turned on. The two signals will not be high level at the same time. The SPWM4H signal and the SPWM4L signal are alternately turned on. The two signals will not be high level at the same time.

[0052] One end of the inductor L2 is connected to the source electrode of the NMOS transistor P3, the other end of the inductor L2 is connected to one end of the capacitor C2, and the other end of the capacitor C2 is connected to the source electrode of the NMOS transistor P1; one end of the inductor L3 is connected to the source electrode of the NMOS transistor P7, the other end of the inductor L3 is connected to one end of the capacitor C3, and the other end of the capacitor C3 is connected to the source electrode of the NMOS transistor P5. Among them, both ends of the capacitor C2 are connected to the power supply of the first refrigerator, and are used to provide 42 Hz alternating current V for the first refrigerator out1 ; both ends of the capacitor C3 are connected to the power supply of the second refrigerator, and are used to provide 18 Hz alternating current V for the second refrigerator out2 .

[0053] Among them, the FPGA is the abbreviation of Field-mProgramable GateArray, that is, a field programmable gate array, which is a programmable integrated circuit chip; NMOS is the abbreviation of N-type Metal Oxide Semiconductor Field Effect Transistor (N-typeMetal Oxide SemiconductorField Effect Transistor).

[0054] The filter is used to suppress the fluctuation of the primary bus current caused by the subsequent AC load. This filter will suppress the fluctuation of the primary bus current, but will cause the fluctuation of the output voltage V at the back end of the filter in of the filter

[0055] Furthermore, the inductor L1 is a 6 mH inductor; the capacitor C1 is a 10 mF capacitor array composed of multiple capacitors connected in parallel to improve the overall current fluctuation suppression ability

[0056] The controller converts the voltage V output by the filter in into a 42 Hz alternating current and an 18 Hz alternating current to supply power to two refrigerators at the back end. The FPGA inside the controller controls the alternating conduction of the SPWM1H signal and the SPWM1L signal and the alternating conduction of the SPWM2H signal and the SPWM2L signal according to the 20K carrier SPWM signal control requirements, controls the output of the four MOS transistor switches on the H bridge, and after filtering by the subsequent inductor L2 and capacitor C2, outputs a 42 Hz sinusoidal AC voltage V out1 , driving the first refrigerator to work. Similarly, the FPGA inside the controller controls the alternating conduction of the SPWM3H signal and the SPWM3L signal and the alternating conduction of the SPWM4H signal and the SPWM4L signal according to the 20K carrier SPWM signal control requirements, controls the output of the four MOS transistor switches on the H bridge, and after filtering by the subsequent inductor L3 and capacitor C3, outputs an 18 Hz sinusoidal AC voltage V out2, drive the second refrigerating machine to work.

[0057] Due to the two refrigerating machines working at different operating frequencies and the effect of the front-end filter, the voltage V at the input end of the controller fluctuates, which in turn causes the distortion rate of the output AC voltage to increase. According to the power output sizes of the first refrigerating machine and the second refrigerating machine at the back end, the present invention calculates the change size of the voltage V at the input end of the controller. Through the internal PID algorithm, the power supply voltages of the first refrigerating machine and the second refrigerating machine are readjusted to meet the distortion rate requirements. in Due to the two refrigerating machines working at different operating frequencies and the effect of the front-end filter, the voltage V at the input end of the controller fluctuates, which in turn causes the distortion rate of the output AC voltage to increase. According to the power output sizes of the first refrigerating machine and the second refrigerating machine at the back end, the present invention calculates the change size of the voltage V at the input end of the controller. Through the internal PID algorithm, the power supply voltages of the first refrigerating machine and the second refrigerating machine are readjusted to meet the distortion rate requirements. in Further, the FPGA is the control center of the controller, and the model of the FPGA is BQ2V3000.

[0058] The principle of the power compensation device is as follows:

[0059] First, the controller internally calculates the instantaneous power of the current two-way AC output in real time. According to the design parameters of the front-end filter and the current output power value, the bus voltage fluctuation at the input end of the controller caused by the current power value is calculated inversely; then, according to the bus voltage fluctuation at the input end of the controller, the compensation value to be calculated is calculated through the PID algorithm; finally, after adding the compensation value and the current output value, it is used as the final power output. In addition, the PID parameters can also be set through external instructions to adjust the compensation effect.

[0060] A power compensation method based on an alternating load is deployed in the system within the controller. By adjusting the duty cycle of the pulse width modulation wave to meet the power requirements of the alternating load at the back end, it specifically includes the following steps:

[0061] S1. The FPGA outputs a pulse width modulation wave of 20 KHz;

[0062] S2. Calculate the theoretical power supply voltage V that the first refrigerating machine needs the controller to provide

[0063] (that is, the target value that the normal working power supply of the first refrigerating machine needs to reach): out1 (that is, the target value that the normal working power supply of the first refrigerating machine needs to reach):

[0064] V out1 = V in *sin(2π / n1*m1) (1)

[0065] Then, calculate the theoretical power supply voltage V that the second refrigerating machine needs the controller to provide out2 (that is, the target value that the normal working power supply of the second refrigerating machine needs to reach):

[0066] V out2 = V in *sin(2π / n2*m2) (2)

[0067] Among them, V inThe theoretical voltage representing the input end of the controller is a theoretical value set in the system before the satellite leaves the factory according to the output power of the backend refrigerator and the parameters of the frontend filter, etc.;

[0068] Among them, since the pulse-width modulation wave is 20KHz, so n1 = 20000 / 42, n2 = 20000 / 18, m1 varies from 0 to n1, and m2 varies from 0 to n2; both m1 and m2 are taken according to the sine law. Before the satellite leaves the factory, a theoretical value will be set for m1 and m2 respectively for initial calculation;

[0069] S3. Within each 20KHz switching period (50us), calculate the current output power value, and then calculate the fluctuation value ΔV of the frontend supply voltage caused by this output power value:

[0070] ΔV = K1 * V out1 +K2 * V out2 (3)

[0071] Among them, K1 represents the coefficient that causes the change in the bus voltage when the first refrigerator outputs voltage. This coefficient value is related to the output power of the backend refrigerator and the parameters of the frontend filter, and the value range is between 0.01 and 0.1; K2 represents the coefficient that causes the change in the bus voltage when the second refrigerator outputs voltage. This coefficient value is related to the output power of the backend refrigerator and the parameters of the frontend filter, and the value range is between 0.01 and 0.1; K1 and K2 are the proportional coefficients in the PID parameters, which are set before the satellite leaves the factory and can also be adjusted according to ground commands after the satellite is in orbit;

[0072] S4. Calculate the compensated voltage magnitude at the input end of the controller through the PID algorithm, that is, V in -ΔV;

[0073] S5. Calculate the actual output voltage of the controller at this time as:

[0074] V′ out1 = (V in -ΔV) *sin(2π / n1*m1) (4)

[0075] V′ out2 = (V in -ΔV) *sin(2π / n2*m2) (5)

[0076] Among them, V′ out1 represents the actual supply voltage provided by the controller to the first refrigerator; V′ out2 represents the actual supply voltage provided by the controller to the second refrigerator;

[0077] S6. Adjust the values of m1 and m2 correspondingly according to the actual output voltage of the controller:

[0078] m′1 = m1 * V out1 / V′ out1 (6)

[0079] m′2 = m2 * V out2 / V′ out2 (7)

[0080] Wherein, m′1 represents the actual value of m1, and m′2 represents the actual value of m2.

[0081] After calculating m′1 and m′2 by this method, substitute m′1 and m′2 into Formula (1) and Formula (2) to directly output V′ out1 and V′ out2 , for use by Refrigerator One and Refrigerator Two. The V′ out1 and V′ out2 directly output after compensation by this method meet the distortion rate requirements; in addition, m′1 and m′2 need to be adjusted according to the output power.

[0082] The above are only optional embodiments of the present invention, and do not limit the patent scope of the present invention. Any equivalent structural transformation made under the inventive concept of the present invention, or direct / indirect application in other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. A power compensation device based on alternating load, characterized in that: It includes a filter and a controller, wherein the controller is the post-stage of the filter; The controller includes FPGA, NMOS tube 1 (P1), NMOS tube 2 (P2), NMOS tube 3 (P3), NMOS tube 4 (P4), NMOS tube 5 (P5), NMOS tube 6 (P6), NMOS tube 7 (P7), NMOS tube 8 (P8), inductor 2 (L2), inductor 3 (L3), capacitor 2 (C2) and capacitor 3 (C3); The drain of the NMOS tube 1 (P1) is connected to the primary power positive line, and the gate of the NMOS tube 1 (P1) is used to receive the SPWM1H signal sent by the FPGA; the drain of the NMOS tube 2 (P2) is connected to the source of the NMOS tube 1 (P1), the source of the NMOS tube 2 (P2) is connected to the primary power return line, and the gate of the NMOS tube 2 (P2) is used to receive the SPWM1L signal sent by the FPGA; the drain of the NMOS tube 3 (P3) is connected to the primary power positive line, and the NMOS tube 3 (P3) is connected to the primary power positive line. ) is used to receive the SPWM2H signal sent by the FPGA; the drain of the NMOS tube four (P4) is connected to the source of the NMOS tube three (P3), the source of the NMOS tube four (P4) is connected to the primary power return line, and the gate of the NMOS tube four (P4) is used to receive the SPWM2L signal sent by the FPGA; wherein the SPWM1H signal and the SPWM1L signal are alternately turned on, and the two signals will not be high at the same time; the SPWM2H signal and the SPWM2L signal are alternately turned on, and the two signals will not be high at the same time; The drain of the NMOS tube five (P5) is connected to the primary power positive line, and the gate of the NMOS tube five (P5) is used to receive the SPWM3H signal sent by the FPGA; the drain of the NMOS tube six (P6) is connected to the source of the NMOS tube five (P5), the source of the NMOS tube six (P6) is connected to the primary power return line, and the gate of the NMOS tube six (P6) is used to receive the SPWM3L signal sent by the FPGA; the drain of the NMOS tube seven (P7) is connected to the primary power positive line, and the gate of the NMOS tube seven (P7) is used to receive the SPWM3L signal sent by the FPGA. The gate of the NMOS tube eight (P7) is used to receive the SPWM4H signal sent by the FPGA; the drain of the NMOS tube eight (P8) is connected to the source of the NMOS tube seven (P7), the source of the NMOS tube eight (P8) is connected to the primary power return line, and the gate of the NMOS tube eight (P8) is used to receive the SPWM4L signal sent by the FPGA; wherein the SPWM3H signal and the SPWM3L signal are alternately turned on, and the two signals will not be high at the same time; the SPWM4H signal and the SPWM4L signal are alternately turned on, and the two signals will not be high at the same time; One end of the inductor 2 (L2) is connected to the source of the NMOS tube 3 (P3), the other end of the inductor 2 (L2) is connected to one end of the capacitor 2 (C2), the other end of the capacitor 2 (C2) is connected to the source of the NMOS tube 1 (P1); one end of the inductor 3 (L3) is connected to the source of the NMOS tube 7 (P7), the other end of the inductor 3 (L3) is connected to one end of the capacitor 3 (C3), the other end of the capacitor 3 (C3) is connected to the source of the NMOS tube 5 (P5).

2. The power compensation device based on alternating load according to claim 1, characterized in that: The filter comprises an inductor 1 (L1) and a capacitor 1 (C1), wherein the inductor 1 (L1) is arranged on a primary power positive line; one end of the capacitor 1 (C1) is connected to the end of the inductor 1 (L1) close to the controller, and the other end is connected to a primary power return line.

3. The power compensation device based on alternating load according to claim 2, characterized in that: The inductor 1 (L1) is a 6mH inductor; the capacitor 1 (C1) is a 10mF capacitor array composed of multiple capacitors connected in parallel.

4. A power compensation method under alternating load, based on the power compensation device according to any one of claims 1 to 3, characterized in that: The following steps are involved: S1.FPGA outputs 20KHz pulse width modulation wave; S2. Calculate the theoretical supply voltage V that the controller needs to provide for the refrigerator out1 : V out1 =V in *sin(2π / n1*m1) (1) Then, calculate the theoretical power supply voltage V that the controller needs to provide for the second refrigerator out2 : <h2 style=";text-align:left;direction:ltr">V<h2 style=";text-align:left;direction:ltr"> out2 <h2 style=";text-align:left;direction:ltr"> =V<h2 style=";text-align:left;direction:ltr"> in <h2 style=";text-align:left;direction:ltr"> *sin(2π / n2*m2) (2) Among them, V in Represents the theoretical voltage at the controller input; n1 = 20000 / 42, n2 = 20000 / 18, m1 varies from 0 to n1, and m2 varies from 0 to n2; S3. In each 20KHz switching cycle, calculate the current output power value, and then calculate the front-end power supply voltage fluctuation value ΔV caused by the output power value: ΔV=K1*V out1 +K2*V out2 (3) Among them, K1 represents the coefficient of bus voltage change caused by refrigerator 1 when the output voltage is low, and the value range is 0.01-0.1; K2 represents the coefficient of bus voltage change caused by refrigerator 2 when the output voltage is low, and the value range is 0.01-0.1; S4. Calculate the voltage after compensation at the controller input through the PID algorithm, that is, V in -ΔV; S5. Calculate the actual output voltage of the controller at this time: V out1 = (V in -ΔV) *sin(2π / n1*m1) (4) V′ out2 = (V in -ΔV) *sin(2π / n2*m2) (5) Among them, V′ out1 Represents the actual power supply voltage provided by the controller to the refrigerator; V' out2 Represents the actual power supply voltage provided by the controller to refrigerator 2; S6. Adjust the values ​​of m1 and m2 according to the actual output voltage of the controller: m′1=m1*V out1 / V′ out1 (6) m′2=m2*V out2 / V′ out2 (7) Among them, m′1 represents the actual value of m1, and m′2 represents the actual value of m2.

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