Isolated AC / DC voltage sampling and PWM driving control circuit

Abstract

The invention discloses an isolated AC / DC voltage sampling and PWM driving control circuit, and belongs to the technical field of integrated circuits. Comprising an analog quantity sampling circuit and a power module upper and lower bridge arm driving protection circuit. Sampled and conditioned signals are connected to the analog input end of the DSP, a PWM output pin of the DSP is connected with the input end of the isolation driving module, and an upper bridge arm and a lower bridge arm of a power tube are driven through the isolation driving module. An analog quantity acquisition processing flow is executed when analog quantity sampling is carried out, a power tube upper bridge arm processing flow is executed when an upper bridge arm power tube is controlled, and a power tube lower bridge arm processing flow is executed when a lower bridge arm power tube is controlled. According to the invention, the clamping module is arranged at the preceding stage of the analog input pin of the microcontroller, so that the analog input pin of the microcontroller can be effectively prevented from being damaged by the high voltage pulse peak of the analog input port. An isolation amplifier and a resistor are adopted for voltage reduction, and voltage bias is added in a post-stage conditioning circuit, so that sampling of alternating current and direct current voltage is realized while the size is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to an isolated AC / DC voltage sampling and PWM drive control circuit. Background Art

[0002] Currently, for isolated AC sampling, a small transformer is mostly used for step-down and then a general diode is used for rectification and filtering for analog quantity sampling. For PWM pulse drive, a small transformer coupling method is used to drive and control MOSFET, silicon carbide, or IGBT. When using a small transformer for sampling or driving a power transistor, there are problems such as large volume, heaviness, and insufficient isolation in a small volume situation. Since a large capacitor is used for filtering during the sampling process, the sampling accuracy is insufficient, which further leads to insufficient control accuracy and ultimately an unstable control system. Because the sampling is carried out using the transformer isolation method and the same sampling circuit is used, the circuit design is complex, resulting in a large PCB board area. The main problems of the current isolated AC / DC voltage sampling device: This type of isolated sampling circuit belongs to a relatively conventional method for processing AC voltage sampling, with a large volume, and multi-channel sampling will make the board card heavy; This type of circuit cannot perform both AC and DC voltage sampling simultaneously; this type of circuit has no high and low clamping design for analog quantity sampling, which may cause damage to the analog input port of the control chip due to high voltage pulse spikes.

[0003] When this type of circuit uses diode rectification, there will be a dead zone (diode forward voltage drop) in the initial sampling stage, resulting in very poor linearity; when this type of circuit uses diode rectification, there will be a dead zone (diode forward voltage drop) in the initial sampling stage, and due to the problem of the filter capacitor, the output accuracy will become worse; When this type of circuit uses a transformer to drive power devices, the volume is large and heavy, and the isolation degree is insufficient on a small-sized transformer. When this type of circuit uses a transformer to drive power devices, the rise and fall times are not easy to control; when this type of circuit uses a transformer to drive power devices, the gate of the transistor is not connected to the internal clamp. It cannot prevent false conduction caused by Miller current. Summary of the Invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and provide an isolated AC / DC voltage sampling and PWM drive control circuit.

[0005] The object of the present invention is achieved by the following technical solutions: An isolated AC / DC voltage sampling and PWM drive control circuit, comprising an analog quantity sampling circuit, a power module upper-bridge-arm drive protection circuit, and a power module lower-bridge-arm drive protection circuit; the analog quantity sampling circuit includes a high-voltage AC / DC voltage sampling input terminal module, the high-voltage AC / DC voltage sampling input terminal module is connected to an isolation amplifier module, the isolation amplifier module is connected to an output conditioning and voltage biasing module, the output conditioning and voltage biasing module is connected to a clamping module, and the clamping module is connected to a microcontroller analog quantity input module; The sampled and conditioned signal is connected to the DSP analog quantity input terminal, the DSP PWM output pin is connected to the input terminal of the isolation drive module, and the upper and lower bridge arms of the power tube are driven through the isolation drive module; when performing analog quantity sampling, an analog quantity acquisition and processing flow is executed, when controlling the upper-bridge-arm power tube, a power tube upper-bridge-arm processing flow is executed, and when controlling the lower-bridge-arm power tube, a power tube lower-bridge-arm processing flow is executed.

[0006] Preferably, the power module upper-bridge-arm drive protection circuit includes a first isolated gate driver, the input terminal of the first isolated gate driver is connected to a PWM1A pre-isolation output module and a PWM1A isolation output enable module, the output terminal of the first isolated gate driver is connected to a Q1 isolation output module, and the Q1 isolation output module is connected to a power switch module.

[0007] Preferably, the power module lower-bridge-arm drive protection circuit includes a second isolated gate driver, the input terminal of the second isolated gate driver is connected to a PWM1B pre-isolation output module and a PWM1B isolation output enable module, the output terminal of the second isolated gate driver is connected to a Q2 isolation output module, and the Q2 isolation output module is connected to a power switch module.

[0008] Preferably, the analog quantity acquisition and processing flow includes the following steps: Introduce the sampling point of the AC voltage or DC voltage through the wiring terminal J3; Step down the input signal by means of resistor voltage division, then perform RC filtering processing and input it into the isolation amplifier module for differential amplification; Input the differentially amplified signal into the output conditioning and voltage biasing module for conditioning transformation to obtain a voltage signal; Input the conditioned and transformed voltage signal into the clamping module, input the sampled and conditioned signal into the analog quantity input port of the DSP controller, subtract the voltage bias and calculate the effective value of the AC voltage or DC voltage by using the method of calculating the root mean square within a period.

[0009] Preferably, the power tube upper-bridge-arm processing flow includes the following steps: The DSP controller controls the PWM1A output pin to output a PWM control square wave; The PWM control square wave is input to the first isolated gate driver after passing through a pull-down resistor and a filter capacitor, then pull-up enabling is performed, and the on and off times of the upper-bridge power transistor are controlled through the resistor at the output end of the first isolated gate driver and the terminal block J4.

[0010] Preferably, the processing flow of the lower-bridge arm of the power transistor includes the following steps: The DSP controller controls the PWM1B output pin to output a PWM control square wave; The PWM control square wave is input to the second isolated gate driver after passing through a pull-down resistor and a filter capacitor, then pull-up enabling is performed, and the on and off times of the lower-bridge power transistor are controlled through the resistor at the output end of the second isolated gate driver and the terminal block J5.

[0011] Preferably, a power supply circuit is further included, and the power supply circuit provides multiple power supplies for powering each circuit.

[0012] The beneficial effects of the present invention are: 1) A clamping module is provided in the front stage of the analog input pin of the microcontroller, which can effectively prevent the analog input port from damaging the analog input pin of the microcontroller due to high-voltage pulse spikes.

[0013] 2) By using an isolation amplifier and resistor voltage reduction, and adding a voltage offset in the post-stage conditioning circuit, the PCB board can be made small and light, and the AC and DC voltage sampling can be realized while reducing the volume.

[0014] 3) Without using diode rectification, the linearity and sampling accuracy are greatly improved.

[0015] 4) It has a linearity sampling with a linearity up to 99.97%.

[0016] 5) It has a sampling accuracy up to 99.7%.

[0017] 6) The single-channel isolated gate driver has an isolation voltage up to 5 kVRMS.

[0018] 7) The on and off resistors of the output stage can be independently configured, and the turn-on rising edge and turn-off falling time of the controlled power device can be adjusted, which can effectively control the output efficiency of the entire device.

[0019] 8) The gate of the transistor is connected to the internal clamp, which can prevent the Miller current from causing false conduction and effectively protect the risk of damage to the power device. Description of the Drawings

[0020] Figure 1It is a schematic diagram of the principle of the analog quantity sampling circuit and the upper and lower drive protection circuit of the power module; Figure 2 It is a schematic diagram of the principle of the power supply circuit; Figure 3 It is the principle of the power supply circuit Figure 1 ; Figure 4 It is the principle of the power supply circuit Figure 2 ; Figure 5 It is the principle of the analog quantity sampling circuit and the upper and lower drive protection circuit of the power module Figure 1 ; Figure 6 It is the principle of the analog quantity sampling circuit and the upper and lower drive protection circuit of the power module Figure 2 ; Figure 7 It is the principle of the analog quantity sampling circuit and the upper and lower drive protection circuit of the power module Figure 3 ; Figure 8 It is the principle of the analog quantity sampling circuit and the upper and lower drive protection circuit of the power module Figure 4 ; Figure 9 It is the schematic diagram of the signal path of the power supply circuit Figure 1 ; Figure 10 It is the schematic diagram of the signal path of the power supply circuit Figure 2 ; Figure 11 It is the schematic diagram of the signal path of the analog quantity sampling circuit and the upper and lower drive protection circuit of the power module Figure 1 ; Figure 12 It is the schematic diagram of the signal path of the analog quantity sampling circuit and the upper and lower drive protection circuit of the power module Figure 2 ; Figure 13 It is the schematic diagram of the signal path of the analog quantity sampling circuit and the upper and lower drive protection circuit of the power module Figure 3 ; Figure 14 It is the schematic diagram of the signal path of the analog quantity sampling circuit and the upper and lower drive protection circuit of the power module Figure 4 . Specific implementation manners

[0021] Next, the technical solutions of the present invention will be clearly and completely described in conjunction with the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present invention.

[0022] First, the model descriptions of some components in the attached drawings of the present invention are as follows: J1 is a power supply plug connector (PJ-037AH); J2 is a 2.54 mm terminal block; D1-D5 are LED indicators; S1 is a DC switch (M2011SS1W01); U1 is a power module (URB2412YMD-10WR3G); U2 is a power module (URA2415YMD-10WR3); U3 is a power module (MIC39100-3.3WS-TR), U4 is a power module (URB2405YMD-10WR3G); U5 is a power module (DCH010505SN7), U10, U12 are power modules (R12P22005D); U6 is a power reference chip (REF2033); V1 is a clamping diode (MMBD7000LT1); U7 is a precision enhanced isolation amplifier (AMC1301DWVR), whose input range is ±250 mV; U9, U11 are single-channel isolated gate drivers (UCC5390S); J3 is a 2.54 mm sampling signal input interface; J4, J5 are power semiconductor gate drive terminal blocks; U8 is a precision operational amplifier (TPMCP6021T-E / OT); Referring to Figures 1 - 14 , the present invention provides a technical solution: an isolated AC-DC voltage sampling and PWM drive control circuit, including an analog sampling circuit, a power module upper bridge arm drive protection circuit, and a power module lower bridge arm drive protection circuit; the analog sampling circuit includes a high-voltage AC-DC voltage sampling input terminal module, the high-voltage AC-DC voltage sampling input terminal module is connected to an isolation amplifier module, the isolation amplifier module is connected to an output conditioning and voltage biasing module, the output conditioning and voltage biasing module is connected to a clamping module, and the clamping module is connected to a microcontroller analog input module; The sampled and conditioned signal is connected to the DSP analog input terminal, the DSP PWM output pin is connected to the input terminal of the isolation drive module, and the upper and lower bridge arms of the power transistor are driven through the isolation drive module; when performing analog sampling, an analog acquisition and processing process is executed, when controlling the upper bridge arm power transistor, a power transistor upper bridge arm processing process is executed, and when controlling the lower bridge arm power transistor, a power transistor lower bridge arm processing process is executed.

[0023] In this embodiment, as Figure 1 and Figure 2As shown, the model of the amplifier in the isolation amplifier module is AMC1301DWVR, which can achieve a linearity sampling and sampling accuracy of up to 99.97%. The model of the isolated gate driver in the upper and lower drive protection circuits of the power module is UCC5390S, which has an isolation voltage of up to 5kVRMS; the turn-on and turn-off resistances of the output stage of UCC5390S can be independently configured, and it has the function of adjusting the turn-on rising edge and turn-off falling time of the controlled power device, which can effectively control the output efficiency of the entire device; using UCC5390S to connect the gate of the transistor to the internal clamp can prevent false connection caused by Miller current. A bias voltage is added to the conditioning circuit, so that high-voltage AC and DC have the function of simultaneous sampling; the circuit design board is small and light in weight; the control chip analog input port pulse spike suppression protection overvoltage clamp protection function is realized through the clamp module.

[0024] In some embodiments, the upper-bridge-arm drive protection circuit of the power module includes a first isolated gate driver. The input end of the first isolated gate driver is connected to the PWM1A isolated pre-output module and the PWM1A isolated output enable module, and the output end of the first isolated gate driver is connected to the Q1 isolated output module, and the Q1 isolated output module is connected to the power switch module.

[0025] In some embodiments, the lower-bridge-arm drive protection circuit of the power module includes a second isolated gate driver. The input end of the second isolated gate driver is connected to the PWM1B isolated pre-output module and the PWM1B isolated output enable module, and the output end of the second isolated gate driver is connected to the Q2 isolated output module, and the Q2 isolated output module is connected to the power switch module.

[0026] In some embodiments, the analog quantity acquisition and processing process includes the following steps: Introduce the sampling points of AC voltage or DC voltage through the wiring terminal J3; Step down the input signal by means of resistor voltage division, then perform RC filtering and input it into the isolation amplifier module for differential amplification; Input the differentially amplified signal into the output conditioning and voltage bias module for conditioning transformation to obtain a voltage signal; Input the conditioned voltage signal into the clamp module, input the sampled and conditioned signal into the analog input port of the DSP controller, subtract the voltage bias and calculate the effective value of the AC voltage or DC voltage by using the method of calculating the root mean square within the period.

[0027] In this embodiment, the sampling points of high AC voltage or DC voltage (the peak voltage of this design is less than 750V) are introduced through J3 (terminal block); the voltage is stepped down by means of resistor voltage division and then processed by RC filtering and enters pins 2 and 3 of U7 (U7(AMC1301DWVR)). The input signal range of the AMC1301DWVR chip is -250mV - +250mV and it has high voltage isolation and differential amplification functions; pins 5 and 6 of U7 (U7(AMC1301DWVR)) pass through U8 (TPMCP6021T-E / OT) R11, R12, R15, R16, R18 (resistors), C51, C53, C46 (capacitors), R9 (resistor) to form an AC / DC voltage sampling output conditioning module with a voltage offset output conditioning function, so that the output voltage is about 0 - 3.3V; the generated 0 - 3.3V voltage enters V1 (MMBD7000LT1) to condition the transformed voltage. When the high voltage is 3.3V, it can be clamped to 3.3V through the internal diode of V1 to protect the DSP analog input port. When the conditioned and transformed voltage is lower than 0V, it can be clamped to 0V through the internal diode of V1 to protect the DSP analog input port, because the DSP analog sampling input port only allows a voltage input of 0 - 3.3V; the sampled and conditioned signal enters the DSP controller's analog input port, and the effective value of the AC voltage or the DC voltage value is calculated by subtracting the voltage offset and using the method of root mean square within the period.

[0028] In some embodiments, the processing flow of the upper bridge arm of the power transistor includes the following steps: The DSP controller controls the PWM1A output pin to output a PWM control square wave; The PWM control square wave is input to the first isolated gate driver after passing through a pull-down resistor and a filter capacitor, then pulled up to enable, and the on and off times of the upper bridge arm power transistor are controlled through the resistor at the output end of the first isolated gate driver and the terminal block J4.

[0029] In this embodiment, the PWM1A output pin of the DSP controller outputs a PWM control square wave; it is pulled down by R23 (resistor) and connected to the filter composed of R20 (resistor) and C61 (capacitor), and then connected to pins 2 and 3 of the U9 (UCC5390S) single-channel isolated gate driver. Through Q1 (MOS) and R24 (resistor), it is pulled up to enable the PWM output, forming the input loop of the single-channel isolated gate driver pins to prepare for controlling the subsequent power device of the output; the U9 (UCC5390S) single-channel isolated gate driver plays the role of isolating the high voltage of the power transistor from the DSP PWM control output end, as well as power amplification and protection. Pins 8 and 5 of U9 (UCC5390S) are the power supply on the output side, and the outputs of pins 7 and 6 are the output ports for the high supply level of the power transistor. R21 and R22 (resistors) play the role of controlling the turn-on and turn-off times of the power transistor, etc.; J4 (terminal block) can be connected to the gate of the power transistor to realize the turn-on and turn-off of the power, and to control the upper-bridge power transistor in the upper and lower bridges composed of power transistors.

[0030] In some embodiments, the processing flow of the lower bridge of the power transistor includes the following steps: The DSP controller controls the PWM1B output pin to output a PWM control square wave; The PWM control square wave is input to the second isolated gate driver after passing through a pull-down resistor and a filter capacitor, then pulled up to enable, and the turn-on and turn-off times of the lower-bridge power transistor are controlled through the resistors at the output end of the second isolated gate driver and the terminal block J5.

[0031] In this embodiment, corresponding to the upper bridge, the PWM1B output pin of the DSP controller of the lower bridge outputs a PWM control square wave; it is pulled down by R27 (resistor) and connected to the filter composed of R30 (resistor) and C72 (capacitor), and then connected to pins 2 and 3 of the U11 (UCC5390S) single-channel isolated gate driver. Through Q1 (MOS) and R31 (resistor), it is pulled up to enable the PWM output, forming the input loop of the single-channel isolated gate driver pins to prepare for controlling the subsequent power device of the output; the U11 (UCC5390S) single-channel isolated gate driver plays the role of isolating the high voltage of the power transistor from the DSP PWM control output end, as well as power amplification and protection; pins 8 and 5 of U11 (UCC5390S) are the power supply on the output side, and the outputs of pins 7 and 6 are the output ports for the high supply level of the power transistor. R28 and R29 (resistors) play the role of controlling the turn-on and turn-off times of the power transistor, etc.; it realizes the control of the lower-bridge power transistor in the upper and lower bridges composed of power transistors.

[0032] In some embodiments, a power supply circuit is further included, and the power supply circuit provides multiple power supplies for powering each circuit.

[0033] In this embodiment, the signal path of the power supply circuit is as Figures 9 - 10As shown, Path 1: DC24V DC input power supply input 1 loop. J1 (PJ-037AH DC input interface) passes through S1 (M2011SS1W01 DC switch), through C9, C1, C2, C3 (filter capacitors), and through pins 1 and 2 of U1 (URB2412YMD-10WR3G).

[0034] Path 2: DC24V DC input power supply input 2 loop. J2 (2.54 interface) passes through S1 (M2011SS1W01 DC switch), through C9, C1, C2, C3 (filter capacitors), and through pins 1 and 2 of U1 (URB2412YMD-10WR3G).

[0035] Path 3: DC +12V generation circuit. Pins 3 and 5 of U1 (URB2412YMD-10WR3G) pass through C10, C11, C4, C5 (filter capacitors), through L1 (30 ohm) bead, and through C6, C7, C8 (capacitors) to generate +12V.

[0036] Path 4: DC +15V generation circuit. Pins 3 and 4 of U2 (URA2415YMD-10WR3) pass through C12, C13, C14 (filter capacitors) to generate +15V.

[0037] Path 5: DC -15V generation circuit. Pins 4 and 5 of U2 (URA2415YMD-10WR3) pass through C17, C18, C19 (filter capacitors) to generate -15V.

[0038] Path 6: DC +5V and DC +3.3V generation circuit. Pin 3 of U4 (URB2405YMD-10WR3G) generates +5V. +5V passes through C22, C23, C24 (filter capacitors) to pin 1 of U3 (MIC39100-3.3WS-TR), and then through pin 3 and through C20, C21 (filter capacitors) to generate +3.3V.

[0039] Path 7: +3.3V_D generation circuit. +3.3V passes through C25, C26 (filter capacitors), through L2 (30 ohm) bead, and through C27, C28 (filter capacitors) to generate +3.3V_D.

[0040] Path 8: +12V_D generation circuit. +12V passes through C29, C30 (filter capacitors), through L3 (30 ohm) bead, and through C31, C32, (filter capacitors) C33, C34 (decoupling capacitors) to generate +12V_D.

[0041] Path 9: DGND generation circuit. GND passes through R6 (resistor) to generate DGND.

[0042] The signal paths of the analog sampling circuit and the upper and lower drive protection circuits of the power module are as follows Figures 11 - 14 shown. Path 10: 5V_N generation circuit. +5V passes through C35 (capacitor), L4 (30 ohm) bead, C36, C37 (capacitors) to pins 1 and 2 of U5 (DCH010505SN7), through pin 7, through L5 (30 ohm) bead, C38, C39 (capacitors) to generate 5V_N.

[0043] Path 11: Ref_3V3, Ref_1V65 generation circuit. +5V passes through L6 (30 ohm) bead, C42, C43 (capacitors) to pin 5 of U6 (REF2033), through C40, C41 (capacitors) to generate Ref_3V3. Pin 1 of U6 (REF2033) generates Ref_1V65 through C44, C45 (capacitors).

[0044] Path 12_1: Sampled high-voltage signal input loop 1_1. Voltage signal V_A less than (AC peak - 750 - +750V or DC 750V) is introduced from pins 3 and 1 of J3 (connector) and returns to J1 of J3 (connector) through R7, R8, R10, R13 (resistors).

[0045] Path 12_2: Sampled high-voltage signal input loop 1_2. R13 passes through pins 2 and 3 of U7 (AMC1301DWVR) and is connected in parallel with C54 (capacitor) through R17 (resistor) to form the sampled high-voltage signal input loop 1_2.

[0046] Path 13: Power supply loop for the input side of the high-isolation sampling chip. 5V_N passes through C47, through pins 1 and 4 of U7 (AMC1301DWVR) to V_N_Meas.

[0047] Path 14: Power supply loop for the output side of the high-isolation sampling chip. +3.3V passes through C47, through C49, C48 (capacitors), through pins 8 and 5 of U7 (AMC1301DWVR) to GND.

[0048] Path 15: Differential output signal conditioning loop generates AV1 (conditioned signal input to the controller signal). Pins 7 and 8 of U7 (AMC1301DWVR) pass through R11, R15 (resistors), through C51 (capacitor), R12, R16 (resistors), through C53 (capacitor), R18, R9, R14 (resistors), through C46, C52 (capacitors) to generate AV1 (conditioned signal input to the controller signal).

[0049] Path 16: Differential output signal conditioning adds a bias circuit to generate AV1 (conditioned signal into the controller signal). Ref_1V65 passes through C55 (capacitor), through R18, R9, R14 (resistors), through C46, C52 (capacitors), and together with Path 14 generates AV1 (conditioned signal into the controller signal).

[0050] Path 17: AV1 +3.3V clamping protection circuit. AV1 (conditioned signal into the controller signal) passes through V1 (MMBD7000LT1) to Ref_3V3.

[0051] Path 18: AV1 zero potential clamping protection circuit. GND passes through V1 (MMBD7000LT1) to AV1 (conditioned signal into the controller signal).

[0052] Path 19: PWM1A isolation drive control input circuit. Coming from PWM1A (microcontroller PWM output pin), through R23, R20 (resistors), C61 (capacitor), U9 (UCC5390S) pins 2, 3, R24 (resistor), Q1 (2N7002) to DGND.

[0053] Path 20: PWM1A isolation drive control input enable. EN_PWM (from the controller output enable pin) passes through R25 (resistor) to Q1 (2N7002) to DGND.

[0054] Path 21: PWM1A isolation drive control input side power supply circuit. +3.3V_D passes through C58 (capacitor), U9 (UCC5390S) pins 1, 4 to DGND.

[0055] Path 22: PWM1A isolation drive control output side -5V3 power supply circuit. -5V3 passes through C56, C57 (capacitors), through R19 to U9 (UCC5390S) pin 8.

[0056] Path 23: PWM1A isolation drive pulse output to the power transistor. U9 (UCC5390S) pin 7 (output low level), pin 8 (output high level) pass through R21, R22 (resistors) to J4 (terminal) pin 1.

[0057] Path 24: PWM1A isolation drive control output side +20V3 power supply circuit. +20V3 passes through C66, C67 (capacitors) to U9 (UCC5390S) pin 5.

[0058] Path 25: +20V3, -5V3 generation circuit. +12V_D passes through C62, C63 (capacitors) to U10 (R12P22005D) pin 7, through C59, C60 to generate +20V3. U10 (R12P22005D) pin 5 passes through C64, C65 to generate -5V3.

[0059] Path 26: PWM1B isolated drive control input loop. It comes from PWM1B (the PWM output pin of the microcontroller), through R30, R27 (resistors), C72 (capacitor), pins 2 and 3 of U11 (UCC5390S), R31 (resistor), and Q2 (2N7002) to DGND.

[0060] Path 27: PWM1B isolated drive control input loop enable. EN_PWM (from the controller output enable pin) goes through R32 (resistor) to Q2 (2N7002) to DGND.

[0061] Path 28: PWM1B isolated drive control input side power supply loop. +3.3V_D goes through C71 (capacitor), pins 1 and 4 of U11 (UCC5390S) to DGND.

[0062] Path 29: PWM1B isolated drive control output side -5V4 power supply loop. -5V4 goes through C69, C70 (capacitors), through R26 to pin 8 of U11 (UCC5390S).

[0063] Path 30: PWM1B isolated drive control output side +20V4 power supply loop. +20V4 goes through C80, C79 (capacitors) to pin 5 of U11 (UCC5390S).

[0064] Path 31: PWM1B isolated drive pulse output to the power transistor. Pins 7 (output low level) and 8 (output high level) of U11 (UCC5390S) go through R28, R29 (resistors) to pin 1 of J5 (terminal).

[0065] Path 32: +20V4, -5V4 generation circuit. +12V_D goes through C75, C76 (capacitors) to pin 7 of U12 (R12P22005D), and through C75, C77 to generate +20V4. Pin 5 of U12 (R12P22005D) goes through C77, C78 to generate -5V3.

[0066] In the present invention, since the AMC1301DWVR is an isolated precision amplifier with a small-size chip and is packaged in SOIC_8 and uses a resistor to step down the voltage, the PCB board can be made small and light. Since the post-conditioning circuit of the AMC1301DWVR adds a voltage bias of 1V65, the sampling of AC and DC voltages can be achieved. Since a clamping of the V1 GND voltage and the Ref_3V3 voltage is set in the front stage before the analog input pin of the microcontroller, it can effectively prevent the analog input pin of the microcontroller from being damaged due to high-voltage pulse spikes at the analog input port. Since the diode rectification method is not adopted, there will be no dead zone (diode voltage drop), and the use of the AMC1301DWVR, an isolated amplifier with a linearity and accuracy of up to 99.97%, greatly improves the linearity and accuracy. Since the UCC5390S single-channel isolated gate driver is adopted, it has an isolation voltage of up to 5kVRMS. Since the turn-on and turn-off resistances of the output stage of the UCC5390S can be independently configured, it can conveniently solve the problems of the turn-on rising edge and the turn-off falling edge control of the controlled power device, and thus can effectively control the output efficiency of the entire device. Since the UCC5390S connects the gate of the transistor to the internal clamp, it can prevent false connection caused by Miller current. Since the EN_PWM (output PWM enable pin) is set, it can effectively prohibit the output of the PWM wave in a hardware manner during fault protection.

[0067] The above are only the preferred embodiments of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be changed within the scope of the concept described herein through the above teachings or the techniques or knowledge in related fields. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the appended claims of the present invention.

Claims

1. An isolated AC-DC voltage sampling and PWM drive control circuit, characterized in that: It includes an analog sampling circuit, an upper-bridge-arm drive protection circuit of the power module, and a lower-bridge-arm drive protection circuit of the power module; the analog sampling circuit includes a high-voltage AC / DC voltage sampling input terminal module, the high-voltage AC / DC voltage sampling input terminal module is connected to an isolation amplifier module, the isolation amplifier module is connected to an output conditioning and voltage biasing module, the output conditioning and voltage biasing module is connected to a clamping module, and the clamping module is connected to the analog input module of the microcontroller; The sampled and conditioned signal is connected to the analog input terminal of the DSP. The DSP PWM output pin is connected to the input terminal of the isolation drive module, and the upper and lower bridge arms of the power transistor are driven through the isolation drive module. When performing analog sampling, the analog acquisition and processing process is executed. When controlling the upper-bridge-arm power transistor, the upper-bridge-arm processing process of the power transistor is executed. When controlling the lower-bridge-arm power transistor, the lower-bridge-arm processing process of the power transistor is executed.

2. The isolated AC-DC voltage sampling and PWM drive control circuit according to claim 1, characterized in that: The upper-bridge-arm drive protection circuit of the power module includes a first isolated gate driver. The input terminal of the first isolated gate driver is connected to the PWM1A pre-isolation output module and the PWM1A isolation output enable module. The output terminal of the first isolated gate driver is connected to the Q1 isolation output module, and the Q1 isolation output module is connected to the power switch module.

3. The isolated AC-DC voltage sampling and PWM drive control circuit according to claim 1, characterized in that: The lower-bridge-arm drive protection circuit of the power module includes a second isolated gate driver. The input terminal of the second isolated gate driver is connected to the PWM1B pre-isolation output module and the PWM1B isolation output enable module. The output terminal of the second isolated gate driver is connected to the Q2 isolation output module, and the Q2 isolation output module is connected to the power switch module.

4. The isolated AC-DC voltage sampling and PWM drive control circuit according to claim 1, characterized in that: The analog acquisition and processing process includes the following steps: Introduce the sampling point of the AC voltage or DC voltage through the terminal block J3; Step down the input signal by means of resistor voltage division, then perform RC filtering and input it into the isolation amplifier module for differential amplification; Input the differentially amplified signal into the output conditioning and voltage biasing module for conditioning transformation to obtain a voltage signal; Input the conditioned voltage signal into the clamping module, input the sampled and conditioned signal into the analog input port of the DSP controller, subtract the voltage bias and calculate the effective value of the AC voltage or DC voltage using the method of calculating the root mean square within the period.

5. The isolated AC-DC voltage sampling and PWM drive control circuit according to claim 2, characterized in that: The upper-bridge-arm processing process of the power transistor includes the following steps: The DSP controller controls the PWM1A output pin to output a PWM control square wave; The PWM control square wave is input into the first isolated gate driver through a pull-down resistor and a filter capacitor, then the pull-up enable is performed, and the on and off times of the upper-bridge-arm power transistor are controlled through the resistor at the output terminal of the first isolated gate driver and the terminal block J4.

6. The isolated AC-DC voltage sampling and PWM drive control circuit according to claim 3, characterized in that: The lower-bridge-arm processing process of the power transistor includes the following steps: The DSP controller controls the PWM1B output pin to output a PWM control square wave; The PWM control square wave is input into the second isolated gate driver through a pull-down resistor and a filter capacitor, then the pull-up enable is performed, and the on and off times of the lower-bridge-arm power transistor are controlled through the resistor at the output terminal of the second isolated gate driver and the terminal block J5.

7. The isolated AC-DC voltage sampling and PWM drive control circuit according to any one of claims 1-6, characterized in that: It further includes a power supply circuit which provides multiple power sources for powering each circuit.

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