Doherty amplifier

Abstract

The present disclosure provides a Doherty amplifier comprising: a carrier amplification transistor configured to amplify a first input radio frequency (RF) signal; a carrier bias circuit configured to supply a carrier bias voltage to the carrier amplification transistor; a peak amplification transistor configured to amplify a second input RF signal; a peak bias circuit configured to supply a peak bias voltage to the peak amplification transistor; and a first linearization circuit connected between a first terminal to which the second input RF signal is input and a second terminal to which the peak bias voltage is output in the peak bias circuit, and the first linearization circuit is configured to couple a portion of the second input RF signal and to provide the coupled portion to the second terminal.

Description

Technical Field

[0001] The present disclosure relates to a Doherty amplifier. Background Art

[0002] Wireless communication systems apply various digital modulation and demodulation schemes according to the evolution of communication standards. Existing code division multiple access (CDMA) communication systems adopt the quadrature phase shift keying (QPSK) method, and existing wireless LANs compliant with the IEEE communication standard adopt the orthogonal frequency division multiplexing (OFDM) method. In addition, long term evolution (LTE) and LTE-Advanced, which are 3GPP standards, adopt the QPSK scheme, the quadrature amplitude modulation (QAM) scheme, and the OFDM scheme. These wireless communication standards adopt linear modulation methods, which require maintaining the amplitude or phase of the transmission signal during transmission.

[0003] In the latest standards (e.g., 5G and sub-6), as the channel bandwidth becomes wider, the linearity of power amplifiers included in communication systems becomes important. In addition, since these communication systems require high power (referred to as power class 2), the linearity of power amplifiers becomes increasingly important.

[0004] One of the techniques for improving the efficiency of power amplifiers is the Doherty amplifier. These Doherty amplifiers may also require improved linearity. Summary of the Invention

[0005] This Summary of the Invention is provided to introduce a selection of concepts in a simplified form and further describe these concepts in the Detailed Description below. This Summary of the Invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to help determine the scope of the claimed subject matter.

[0006] In one general aspect, a Doherty amplifier includes: a carrier amplification transistor configured to amplify a first input radio frequency (RF) signal; a carrier bias circuit configured to supply a carrier bias voltage to the carrier amplification transistor; a peak amplification transistor configured to amplify a second input RF signal; a peak bias circuit configured to supply a peak bias voltage to the peak amplification transistor; and a first linearization circuit connected between a first terminal to which the second input RF signal is input and a second terminal to which the peak bias voltage is output in the peak bias circuit, and the first linearization circuit is configured to couple a part of the second input RF signal to the second terminal.

[0007] The peak bias circuit may include a transistor configured to supply the peak bias voltage, and the second terminal may be the emitter of the transistor.

[0008] The Doherty amplifier may further include a resistor connected between the emitter of the transistor and the input terminal of the peak amplification transistor.

[0009] The amplitude of the coupled signal coupled by the first linearization circuit may be changed according to the power mode.

[0010] The power mode may include a low power mode and a high power mode, and the amplitude of the coupled signal in the low power mode may be greater than the amplitude of the coupled signal in the high power mode.

[0011] The first linearization circuit may include a resistor and a capacitor connected in series with each other between the first terminal and the second terminal.

[0012] The resistor may be a variable resistor, and the value of the variable resistor may be changed according to the power mode.

[0013] The power mode may include a low power mode and a high power mode, and the value of the variable resistor in the low power mode may be less than the value of the variable resistor in the high power mode.

[0014] The first linearization circuit may include a resistor and a variable capacitor connected in series with each other between the first terminal and the second terminal, and the value of the variable capacitor may be changed according to the power mode.

[0015] The power mode may include a low power mode and a high power mode, and the value of the variable capacitor in the low power mode may be greater than the value of the variable capacitor in the high power mode.

[0016] The Doherty amplifier may further include a second linearization circuit connected between a third terminal to which the first input RF signal is input and a fourth terminal to which the carrier bias voltage in the carrier bias circuit is output, and the second linearization circuit is configured to couple a part of the first input RF signal to the fourth terminal.

[0017] The amplitude of the coupled signal coupled by the first linearization circuit may be greater than the amplitude of the coupled signal coupled by the second linearization circuit.

[0018] The first linearization circuit may include a first resistor and a first capacitor connected in series with each other between the first terminal and the second terminal, and the second linearization circuit may include a second resistor and a second capacitor connected in series with each other between the third terminal and the fourth terminal.

[0019] The value of the first resistor may be less than the value of the second resistor.

[0020] The Doherty amplifier may further include a power divider configured to generate the first input RF signal and the second input RF signal based on an input RF signal.

[0021] The carrier amplification transistor may be biased in class AB by the carrier bias voltage, and the peak amplification transistor may be biased in class C by the peak bias voltage.

[0022] In another general aspect, a Doherty amplifier includes: a carrier amplification transistor configured to amplify a first input radio frequency (RF) signal; a first transistor including a first terminal configured to supply a carrier bias voltage to the carrier amplification transistor; a peak amplification transistor configured to amplify a second input RF signal; a second transistor including a second terminal configured to supply a peak bias voltage to the peak amplification transistor; and a first linearization circuit connected between a terminal to which the second input RF signal is input and the second terminal of the second transistor, and the first linearization circuit is configured to couple a portion of the second input RF signal to the second terminal of the second transistor.

[0023] The Doherty amplifier may further include a second linearization circuit connected between a terminal to which the first input RF signal is input and the first terminal of the first transistor, and the second linearization circuit is configured to couple a portion of the first input RF signal to the first terminal of the first transistor.

[0024] The first linearization circuit may include a first resistor and a first capacitor connected in series with each other between the terminal to which the second input RF signal is input and the second terminal of the second transistor, and the second linearization circuit may include a second resistor and a second capacitor connected in series with each other between the terminal to which the first input RF signal is input and the first terminal of the first transistor.

[0025] The value of the first resistor may be less than the value of the second resistor.

[0026] Other features and aspects will be readily apparent from the following detailed description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a diagram showing a Doherty amplifier according to an embodiment.

[0028] Figure 2A is a diagram showing Figure 1 a circuit diagram of a carrier bias circuit of

[0029] Figure 2B is a circuit diagram showing Figure 1 the peak bias circuit.

[0030] Figure 3A is a diagram showing an example of the linearization circuit 300_2.

[0031] Figure 3B is a diagram showing another example of the linearization circuit 300_2.

[0032] Figure 3C is a diagram showing another example of the linearization circuit 300_2.

[0033] Figure 4 is a diagram showing another example of the linearization circuit 300_2.

[0034] Figure 5 is a diagram showing an example of the variable resistor R3_VAR.

[0035] Figure 6 is a diagram showing another example of the linearization circuit 300_2.

[0036] Figure 7 is a diagram showing a Doherty amplifier according to another embodiment.

[0037] Figure 8 is a diagram showing an example of the linearization circuit 300_1 and an example of the linearization circuit 300_2.

[0038] Throughout the drawings and the detailed description, unless otherwise described, the same reference numerals refer to the same elements. The drawings may not be drawn to scale, and for clarity, illustration, and convenience, the relative dimensions, scales, and depictions of the elements in the drawings may be exaggerated. Detailed Description

[0039] Hereinafter, although examples of the present disclosure will be described in detail with reference to the drawings, it should be noted that the examples are not limited thereto.

[0040] The following detailed description is provided to assist the reader in obtaining a comprehensive understanding of the methods, devices, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, devices, and / or systems described herein will be readily apparent after understanding the present disclosure. For example, the order of operations described herein is merely an example and is not limited to the order set forth herein, but rather changes that will be readily apparent after understanding the present disclosure may be made, except for operations that must occur in a specific order. In addition, descriptions of features known in the art may be omitted for increased clarity and conciseness.

[0041] The features described herein may be implemented in different forms and should not be construed as limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways of implementing the methods, devices, and / or systems described herein that will be readily understood after understanding the present disclosure.

[0042] Throughout the specification, when an element such as a layer, region, or substrate is described as being "on" another element, "connected to" another element, or "coupled to" another element, it can be directly "on" the other element, directly "connected to" the other element, or directly "coupled to" the other element, or there can be one or more other elements intervening therebetween. In contrast, when an element is described as being "directly on" another element, "directly connected to", or "directly coupled to" another element, there are no other elements intervening therebetween.

[0043] As used herein, the term "and / or" includes any one of the associated listed items or any combination of any two or more of them; similarly, "at least one of..." includes any one of the associated listed items or any combination of any two or more of them.

[0044] Although terms such as "first", "second", and "third" may be used herein to describe various components, elements, regions, layers, or sections, these components, elements, regions, layers, or sections will not be limited by these terms. Rather, these terms are only used to distinguish one component, element, region, layer, or section from another. Thus, a first component, first element, first region, first layer, or first section as referred to in the examples described herein may also be referred to as a second component, second element, second region, second layer, or second section without departing from the teachings of the examples.

[0045] For ease of description, spatial relative terms such as "above", "upper", "below", "lower", etc. may be used herein to describe the relationship of one element to another as shown in the figures. Such spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as "above" or "upper" relative to another element will be "below" or "lower" relative to the other element. Thus, the term "above" includes both the orientations of "above" and "below" depending on the spatial orientation of the device. The device may also be positioned in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative terms used herein will be interpreted accordingly.

[0046] The terms used herein are for describing various examples only and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, singular forms are also intended to include plural forms. The terms "comprising," "including," and "having" enumerate the presence of the stated features, quantities, operations, components, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof.

[0047] Due to manufacturing techniques and / or tolerances, the shapes shown in the drawings may change. Accordingly, the examples described herein are not limited to the specific shapes shown in the drawings, but include changes in shape that occur during manufacturing.

[0048] Here, it should be noted that the use of the term "may" with respect to an example (e.g., with respect to what an example may include or implement) means that there is at least one example that includes or implements such a feature, and is not limited to all examples including or implementing such a feature.

[0049] The features of the examples described herein can be combined in various ways that will be readily understood after understanding the present disclosure. Additionally, although the examples described herein have various configurations, other configurations that will be readily understood after understanding the present disclosure are possible.

[0050] Throughout the specification, RF signals may have (but are not limited to) formats according to the following protocols: Wi-Fi (IEEE 802.11 series, etc.), WiMAX (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed Packet Access Plus (HSPA+), High Speed Downlink Packet Access Plus (HSDPA+), High Speed Uplink Packet Access Plus (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Enhanced Digital Cordless Telecommunications (DECT), Bluetooth, Third Generation Partnership Project (3G), Fourth Generation Partnership Project (4G), Fifth Generation Partnership Project (5G), and any other wireless and wired protocols designated later.

[0051] Figure 1 is a diagram showing a Doherty amplifier 1000 according to an embodiment.

[0052] As Figure 1 shown, the Doherty amplifier 1000 according to an embodiment may include a carrier amplification transistor 100_1, a carrier biasing circuit 200_1, a resistor R B1, peak amplification transistor 100_2, peak bias circuit 200_2, resistor R B2 , linearization circuit 300_2, power divider 400, and power combiner 500.

[0053] In Figure 1 , the carrier amplification transistor 100_1, the carrier bias circuit 200_1, and the resistor R B1 can form a carrier amplifier, and the peak amplification transistor 100_2, the peak bias circuit 200_2, and the resistor R B2 can form a peak amplifier. The carrier amplifier can operate independently of the amplitude of the input RF signal RF IN , and the peak amplifier can operate when the amplitude of the input RF signal RF IN is greater than a predetermined threshold RF IN_TH . That is, when the amplitude of the input RF signal RF IN is less than or equal to the predetermined threshold RF IN_TH , the carrier amplifier operates, but the peak amplifier does not. Additionally, when the amplitude of the input RF signal RF IN exceeds the predetermined threshold RF IN_TH , the carrier amplifier and the peak amplifier can operate simultaneously. Thus, the efficiency of the Doherty amplifier 1000 can be improved. Here, the amplitude of the input RF signal RF IN can correspond to the peak voltage of the input RF signal RF IN , or can correspond to the power of the input RF signal RF IN .

[0054] The power divider 400 receives the input RF signal RF IN , and can divide the input RF signal RF IN into a first input RF signal RF IN1 and a second input RF signal RF IN2 . After understanding the present disclosure, the specific configuration and operation of the power divider 400 will be readily understandable; thus, its detailed description can be omitted. Here, the first input RF signal RF IN1 and the second input RF signal RF IN2 can have the same power as each other, or can have different powers. Additionally, when the peak amplifier is not operating, the second input RF signal RF IN2 may not be generated, and the first input RF signal RF IN1 can have the same power as the input RF signal RF IN .

[0055] The carrier amplification transistor 100_1 may include an input terminal IN_100_1 and an output terminal OUT_100_1. The input terminal IN_100_1 may be the base of the carrier amplification transistor 100_1, and the output terminal OUT_100_1 may be the collector of the carrier amplification transistor 100_1. The carrier amplification transistor 100_1 may amplify the power of a first input RF signal RF input to the input terminal IN_100_1 (e.g., the base), and may output the amplified signal through the output terminal OUT_100_1 (e.g., the collector). That is, the RF signal to be amplified is input through the base of the carrier amplification transistor 100_1, and the amplified RF signal may be output through the collector of the carrier amplification transistor 100_1. In addition, in IN1 the base voltage of the carrier amplification transistor 100_1 is represented as "V Figure 1 ". B1 "

[0056] The emitter of the carrier amplification transistor 100_1 may be connected to ground. Although not shown in Figure 1 , a resistor may be additionally connected between the emitter of the carrier amplification transistor 100_1 and ground. In addition, the collector of the carrier amplification transistor 100_1 may be connected to a power supply voltage V CC1 , and the carrier amplification transistor 100_1 may be operated by the power supply voltage V CC1 . In addition, the collector of the carrier amplification transistor 100_1 may be connected to the power supply voltage V Figure 1 through an inductor (not shown in CC1 ) that performs an RF choke function.

[0057] The carrier amplification transistor 100_1 may be implemented as various transistors, such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). In addition, although the carrier amplification transistor 100_1 is shown as an N-type in Figure 1 , it may be replaced with a P-type.

[0058] In addition, although not shown in Figure 1 , a coupling capacitor may be located between the power divider 400 and the input terminal IN_100_1 of the carrier amplification transistor 100_1. The coupling capacitor may perform a function of removing a direct current (DC) component from the RF signal (i.e., blocking the DC component in the RF signal).

[0059] A reference voltage V REF1 and a power supply voltage V BAT1 may be supplied to the carrier bias circuit 200_1 from the outside. Here, the power supply voltage V BAT1 may be a voltage supplied from a battery. In addition, the power supply voltage VBAT1 may be the same voltage as the reference voltage V REF1 The carrier bias circuit 200_1 may generate a carrier bias voltage V REF1 by using the reference voltage V BAT1 and the power supply voltage V BIAS1 . The carrier bias voltage V BIAS1 may be supplied to the input terminal IN_100_1 of the carrier amplification transistor 100_1 through a resistor R B1 , and the bias level (i.e., bias point) of the carrier amplification transistor 100_1 may be set by the carrier bias voltage V BIAS1 .

[0060] The carrier amplification transistor 100_1 may be biased in class AB, and the carrier bias circuit 200_1 may generate a carrier bias voltage V BIAS1 . That is, through the carrier bias voltage V BIAS1 , the carrier amplification transistor 100_1 is biased in class AB. Since the carrier amplification transistor 100_1 is biased in class AB, the carrier amplification transistor 100_1 can perform an amplification operation regardless of the amplitude of the input RF signal RF IN . In the present disclosure, the related description of "biasing a specific transistor in class AB or class C" may mean performing class AB biasing or class C biasing on the specific transistor.

[0061] The resistor R B1 may be connected between the carrier bias circuit 200_1 and the input terminal IN_100_1 of the carrier amplification transistor 100_1. Here, the resistor R B1 may be a ballast resistor that improves the heat dissipation characteristics of the Doherty amplifier 1000. Although Figure 1 the resistor R B1 is shown as a separate component not included in the carrier bias circuit 200_1, the resistor R B1 may be included in the carrier bias circuit 200_1. In addition, due to the voltage drop caused by the resistor R B1 , the base voltage V B1 of the carrier amplification transistor 100_1 may be a voltage lower than the carrier bias voltage V BIAS1 .

[0062] The peak amplification transistor 100_2 may include an input terminal IN_100_2 and an output terminal OUT_100_2. The input terminal IN_100_2 may be the base of the peak amplification transistor 100_2, and the output terminal OUT_100_2 may be the collector of the peak amplification transistor 100_2. The peak amplification transistor 100_2 may amplify the power of the second input RF signal RF input to the input terminal IN_100_2 (e.g., the base), and may output the amplified signal through the output terminal OUT_100_2 (e.g., the collector). That is, the RF signal to be amplified is input through the base of the peak amplification transistor 100_2, and the amplified RF signal may be output through the collector of the peak amplification transistor 100_2. In addition, in IN2 the terminal to which the second input RF signal RF Figure 1 is input is denoted as "IN2", and the base voltage of the peak amplification transistor 100_2 is denoted as "V IN2 ". B2

[0063] The emitter of the peak amplification transistor 100_2 may be connected to ground, and although not shown in Figure 1 , a resistor may be additionally connected between the emitter of the peak amplification transistor 100_2 and ground. In addition, the collector of the peak amplification transistor 100_2 may be connected to the power supply voltage V CC2 , and the peak amplification transistor 100_2 may be operated by the power supply voltage V CC2 . In addition, the collector of the peak amplification transistor 100_2 may be connected to the power supply voltage V Figure 1 through an inductor (not shown in CC2 ) that performs an RF choke function.

[0064] The peak amplification transistor 100_2 may be implemented as various transistors, such as a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and an insulated gate bipolar transistor (IGBT). In addition, although the peak amplification transistor 100_2 is shown as an N-type in Figure 1 , it may be replaced with a P-type.

[0065] In addition, although not shown in Figure 1 , a coupling capacitor may be located between the power divider 400 and the input terminal IN_100_2 of the peak amplification transistor 100_2. For example, the coupling capacitor may be located between the terminal IN2 to which the second input RF signal RF IN2 is input and the input terminal IN_100_2 of the peak amplification transistor 100_2. The coupling capacitor may perform the function of removing the direct current (DC) component from the RF signal (i.e., blocking the direct current (DC) component in the RF signal).

[0066] A reference voltage V and a power supply voltage V can be supplied to the peak bias circuit 200_2 from the outside. REF2 and the power supply voltage V BAT2 . Here, the power supply voltage V BAT2 can be a voltage supplied from a battery. In addition, the power supply voltage V BAT2 can be the same voltage as the reference voltage V REF2 . The peak bias circuit 200_2 can generate a peak bias voltage V REF2 by using the reference voltage V BAT2 and the power supply voltage V BIAS2 . The peak bias voltage V BIAS2 can be supplied to the input terminal IN_100_2 of the peak amplification transistor 100_2 through a resistor R B2 , and the bias level (i.e., the bias point) of the peak amplification transistor 100_2 can be set by the peak bias voltage V BIAS2 .

[0067] The peak amplification transistor 100_2 can be biased in class C, and the peak bias circuit 200_2 can generate a peak bias voltage V BIAS2 . That is, through the peak bias voltage V BIAS2 , the peak amplification transistor 100_2 is biased in class C. Since the peak amplification transistor 100_2 is biased in class C, the peak amplification transistor 100_2 can operate when the amplitude of the input RF signal RF IN is greater than a predetermined threshold RF IN_TH .

[0068] The resistor R B2 can be connected between the peak bias circuit 200_2 and the input terminal IN_100_2 of the peak amplification transistor 100_2. Here, the resistor R B2 can be a ballast resistor that improves the heat dissipation characteristics of the Doherty amplifier 1000. Although Figure 1 the resistor R B2 is shown as a separate component not included in the peak bias circuit 200_2, the resistor R B2 can be included in the peak bias circuit 200_2. In addition, due to the voltage drop caused by the resistor R B2 , the base voltage V B2 of the peak amplification transistor 100_2 can be a voltage lower than the peak bias voltage V BIAS2 .

[0069] The power combiner 500 may receive the output RF signals of the carrier amplification transistor 100_1 and the peak amplification transistor 100_2, and may combine the two signals. In addition, the power combiner 500 may include an impedance inverter (e.g., a load modulation circuit). The impedance inverter may transform the output impedance of the carrier amplification transistor 100_1 according to the operation of the peak amplification transistor 100_2, and perform a 90-degree phase conversion on the output RF signal of the carrier amplification transistor 100_1. For example, when the peak amplification transistor 100_2 is not operating, the output impedance of the carrier amplification transistor 100_1 may have a maximum value through the impedance inverter. That is, the impedance inverter may be designed to provide impedance matching and a 90-degree phase shift. After understanding the disclosure of the present application, the specific configuration and operation of the power combiner 500 will be easily understood, and thus its detailed description may be omitted.

[0070] In addition, the peak bias voltage V BIAS2 may be set to a level lower than the carrier bias voltage V BIAS1 . That is, in order to bias the peak amplification transistor 100_2 to class C and to bias the carrier amplification transistor 100_1 to class AB, the peak bias voltage V BIAS2 may be set lower than the carrier bias voltage V BIAS1 . As an example, the peak bias voltage V BIAS2 may be 0.7V, and the carrier bias voltage V BIAS1 may be 1.2V. Additionally, through the resistor R B1 , the base voltage V B1 of the carrier amplification transistor 100_1 may be reduced, and through the resistor R B2 , the base voltage V B2 of the peak amplification transistor 100_2 may be reduced. After understanding the disclosure of the present application, this phenomenon called base voltage drop will be easily understood, and thus its detailed description may be omitted. Since the peak bias voltage V BIAS2 is lower than the carrier bias voltage V BIAS1 , the base voltage V B2 of the peak amplification transistor 100_2 may be more likely to have problems. Therefore, in the case where the amplitude of the input RF signal RF IN causes the carrier amplifier and the peak amplifier to operate simultaneously, the RF characteristics may be changed, and the linearity of the Doherty amplifier 1000 may be affected. To improve this, the Doherty amplifier 1000 according to an embodiment may further include a linearization circuit 300_2 located in the peak amplifier. The linearization circuit 300_2 may couple a second input RF signal RF IN2 input to the input terminal IN_100_2 of the peak amplification transistor 100_2.Some of the signals in, and output the coupled signals to node N2. Hereinafter, the part of the signals coupled by the linearization circuit 300_2 is referred to as the "coupled input RF signal". The specific configuration and operation of the linearization circuit 300_2 will be described in more detail hereinafter.

[0071] Figure 2A is a circuit diagram showing Figure 1 of the carrier bias circuit 200_1.

[0072] As Figure 2A shown, the carrier bias circuit 200_1 may include a transistor Q1, a transistor Q2, a transistor Q3, a resistor R1, and a capacitor C1.

[0073] The transistors Q1 to Q3 may be implemented as various transistors, such as, heterojunction bipolar transistors (HBTs), bipolar junction transistors (BJTs), and insulated gate bipolar transistors (IGBTs). Additionally, although the transistors Q1 to Q3 are shown as N-type in Figure 2A , they may be replaced with P-type. Furthermore, the bases of the transistors Q1 to Q3 may be used as control terminals and thus may be referred to as "control terminals". The collectors of the transistors Q1 to Q3 are terminals of the transistors, so each of them may be referred to as a "first terminal" or a "second terminal". Additionally, the emitters of the transistors Q1 to Q3 are also terminals of the transistors, so each of them may be referred to as a "second terminal" or a "first terminal".

[0074] The base and the collector of the transistor Q1 may be connected to each other, and the collector of the transistor Q1 may receive a reference voltage V REF1 . Here, the transistor Q1 may have a diode-connected structure.

[0075] The base and the collector of the transistor Q2 may be connected to each other, and the collector of the transistor Q2 may be connected to the emitter of the transistor Q1. The transistor Q2 may have a diode-connected structure, and the emitter of the transistor Q2 may be connected to ground. Additionally, although not shown in Figure 2A , a resistor may be added between the emitter of the transistor Q2 and ground.

[0076] The collector of the transistor Q3 may be connected to a power supply voltage V BAT1 , and the base of the transistor Q3 may be connected to the base of the transistor Q1. In Figure 2A , the base voltage of the transistor Q3 is represented as "V B_Q3 ". Additionally, the emitter of the transistor Q3 may be connected to the input terminal IN_100_1 of the carrier amplification transistor 100_1 through a resistor R B1 . That is, the emitter of the transistor Q3 may be connected to the input terminal IN_100_1 of the carrier amplification transistor 100_1 through a resistor R B1A carrier bias voltage V is supplied to the carrier amplification transistor 100_1 BIAS1 . In addition, the emitter of the transistor Q3 and the resistor R B1 The node N1 connected to each other can be the following Figure 7 Node N1 in

[0077] A capacitor C1 can be connected between the base of the transistor Q3 and the ground. The capacitor C1 can be used to stabilize the base voltage V of the transistor Q3 B_Q3 , and at the same time can be used to reduce the impedance of the transistor Q3.

[0078] The reference voltage V REF1 Can be distributed through the resistor R1, the transistor Q1 and the transistor Q2, whereby the base voltage V of the transistor Q3 can be determined B_Q3 . The carrier bias voltage V can be determined based on the base voltage V of the transistor Q3 B_Q3 BIAS1 . As an example, when the base voltage V of the transistor Q3 B_Q3 Increases, the carrier bias voltage V BIAS1 Can increase.

[0079] Figure 2B Is a circuit diagram showing Figure 1 The peak bias circuit 200_2 of

[0080] As Figure 2B Shown, the peak bias circuit 200_2 can include a transistor Q4, a transistor Q5, a transistor Q6, a resistor R2 and a capacitor C2.

[0081] The transistors Q4 to Q6 can be implemented as various transistors, such as, heterojunction bipolar transistors (HBTs), bipolar junction transistors (BJTs) and insulated gate bipolar transistors (IGBTs). In addition, although the transistors Q4 to Q6 are shown as N-type in Figure 2B , they can be replaced with P-type. In addition, the bases of the transistors Q4 to Q6 can be used as control terminals, so they can be called "control terminals". The collectors of the transistors Q4 to Q6 are the terminals of the transistors, so each of them can be called a "first terminal" or a "second terminal". In addition, the emitters of the transistors Q4 to Q6 are also the terminals of the transistors, so each of them can be called a "second terminal" or a "first terminal".

[0082] The base and the collector of the transistor Q4 can be connected to each other, and the collector of the transistor Q4 can receive the reference voltage V through the resistor R2 REF2 . Here, the transistor Q4 can have a diode-connected structure.

[0083] The base and collector of transistor Q5 can be connected to each other, and the collector of transistor Q5 can be connected to the emitter of transistor Q4. Transistor Q5 can have a diode-connected structure, and the emitter of transistor Q5 can be connected to ground. Additionally, although not shown in Figure 2B a resistor can be added between the emitter of transistor Q5 and ground.

[0084] The collector of transistor Q6 can be connected to the power supply voltage V BAT2 , and the base of transistor Q6 can be connected to the base of transistor Q4. In Figure 2B , the base voltage of transistor Q6 is denoted as "V B_Q6 ". Additionally, the emitter of transistor Q6 can be connected to the input terminal IN_100_2 of the peak amplification transistor 100_2 through resistor R B2 . That is, the emitter of transistor Q6 can supply the peak bias voltage V B2 to the peak amplification transistor 100_2 through resistor R BIAS2 . Moreover, the node where the emitter of transistor Q6 and resistor R B2 are connected to each other is denoted as node N2.

[0085] Capacitor C2 can be connected between the base of transistor Q6 and ground. Capacitor C2 can be used to stabilize the base voltage V B_Q6 of transistor Q6 and can also be used to reduce the impedance of transistor Q6.

[0086] The reference voltage V REF2 can be divided by resistor R2, transistor Q4, and transistor Q5, thereby determining the base voltage V B_Q6 of transistor Q6. The peak bias voltage V B_Q6 can be determined based on the base voltage V BIAS2 of transistor Q6. As an example, when the base voltage V B_Q6 of transistor Q6 increases, the peak bias voltage V BIAS2 can increase.

[0087] As described above, the linearization circuit 300_2 can output the coupled input RF signal to node N2. The coupled input RF signal can be input to the emitter of transistor Q6, so the peak bias voltage V BIAS2 can increase. As the peak bias voltage V BIAS2 increases, the base voltage of the peak amplification transistor 100_2 can increase. That is, through the linearization circuit 300_2, the base voltage of the peak amplification transistor 100_2 can be increased.

[0088] Hereinafter, various examples of the linearization circuit 300_2 will be described in detail with reference to Figures 3A to 3C .

[0089] Figure 3A This is a diagram showing an example of the linearization circuit 300_2.

[0090] As Figure 3A shown, an example of the linearization circuit 300_2 may include a capacitor C3. The capacitor C3 may be connected between the terminal IN2 to which the second input RF signal RF is input and the node N2. The capacitor C2 may couple a part of the signals in the second input RF signal RF and may output the coupled signals to the node N2. IN2 is input to, and the capacitor C2 may couple a part of the signals in the second input RF signal RF IN2 and may output the coupled signals to the node N2.

[0091] Figure 3B This is a diagram showing another example of the linearization circuit 300_2.

[0092] As Figure 3B shown, another example of the linearization circuit 300_2 may include a capacitor C3 and a resistor R3. The first end of the resistor R3 may be connected to the terminal IN2 to which the second input RF signal RF is input, and the capacitor C3 may be connected between the second end of the resistor R3 and the node N2. Additionally, IN2 different from Figure 3B this, the positions of the resistor R3 and the capacitor C3 may be interchanged. That is, the first end of the capacitor C3 may be connected to the terminal IN2 to which the second input RF signal RF is input, and the resistor R3 may be connected between the second end of the capacitor C3 and the node N2. IN2 is input to, and the resistor R3 may be connected between the second end of the capacitor C3 and the node N2.

[0093] In other words, the resistor R3 and the capacitor C3 may be connected in series with each other between the terminal IN2 to which the second input RF signal RF IN2 is input and the node N2. The resistor R3 and the capacitor C3 may couple a part of the signals in the second input RF signal RF IN2 and may output the coupled signals to the node N2.

[0094] Figure 3C This is a diagram showing yet another example of the linearization circuit 300_2.

[0095] As Figure 3C shown, yet another example of the linearization circuit 300_2 may include a capacitor C3 and an inductor L1. The first end of the inductor L1 may be connected to the terminal IN2 to which the second input RF signal RF is input, and the capacitor C3 may be connected between the second end of the inductor L1 and the node N2. Additionally, IN2 different from Figure 3C this, the positions of the inductor L1 and the capacitor C3 may be interchanged. That is, the first end of the capacitor C3 may be connected to the terminal IN2 to which the second input RF signal RF IN2The terminal IN2 to which it is input, and the inductor L1 can be connected between the second end of the capacitor C3 and the node N2.

[0096] In other words, the inductor L1 and the capacitor C3 can be connected in series with each other between the terminal IN2 to which the second input RF signal RF IN2 is input and the node N2. The inductor L1 and the capacitor C3 can couple a part of the signal in the second input RF signal RF IN2 and output the coupled signal to the node N2.

[0097] In addition, according to the amplitude of the coupled input RF signal, the degree of compensation for the base voltage drop of the peak amplification transistor 100_2 can vary. The larger the coupled input RF signal, the more the base voltage drop of the peak amplification transistor 100_2 can be compensated.

[0098] In addition, in Figure 1 in order to improve the efficiency of the peak amplifier, the power supply voltage V CC2 value can be changed according to the power mode. As an example, the power mode can include a high power mode (HPM) and a low power mode (LPM). The value of the power supply voltage V CC2 can be set to be lower in the low power mode (LPM) than in the high power mode (HPM). As the value of the power supply voltage V CC2 decreases, the linearity of the peak amplifier may deteriorate. As an example, the linearity of the peak amplifier may be worse in the low power mode (LPM) than in the high power mode (HPM).

[0099] Therefore, the linearization circuit 300_2 can adjust the coupling amplitude (quantity) with respect to the second input RF signal RF IN2 according to the power mode. That is, the coupled input RF signal output from the linearization circuit 300_2 can have different amplitudes (quantities) according to the power mode. Here, the amplitude of the coupled input RF signal can be the power of the coupled input RF signal.

[0100] As an example, the coupling amplitude (amplitude of the coupled input RF signal) of the linearization circuit 300_2 in the low power mode (LPM) can be greater than the coupling amplitude (amplitude of the coupled input RF signal) of the linearization circuit 300_2 in the high power mode (HPM). That is, depending on the power mode, the amplitude of the coupled input RF signal can have the relationship of Equation 1 below.

[0101] Equation 1:

[0102] In Equation 1, COUPLED_RF IN2_LPM represents the amplitude of the coupled input RF signal in the low power mode, and COUPLED_RF IN2 _HPM represents the amplitude of the coupled input RF signal in the high power mode.

[0103] Accordingly, the linearization circuit 300_2 according to the embodiment can compensate for the degradation of linearity when the power mode is reduced. Reference will be made to Figure 4 Describe in detail how the linearization circuit 300_2 adjusts the coupling amplitude relative to the second input RF signal RF according to the power mode IN2 of the method.

[0104] Figure 4 is a diagram showing another example of the linearization circuit 300_2.

[0105] As Figure 4 shown, another example of the linearization circuit 300_2 may include a variable resistor R3_VAR and a capacitor C3. That is, Figure 4 the linearization circuit of Figure 3B is formed by replacing the resistor R3 in the linearization circuit of

[0106] with a variable resistor R3_VAR. According to the value of the variable resistor R3_VAR, the amplitude of the coupled input RF signal can be changed. When the value of the variable resistor R3_VAR decreases, the amplitude of the coupled input RF signal can increase. That is, since the resistor attenuates the RF signal, the amplitude of the coupled input RF signal can be adjusted by adjusting the value of the variable resistor R3_VAR.

[0107] The value of the variable resistor R3_VAR can be changed according to the power mode. As an example, the value of the variable resistor R3_VAR in the low power mode (LPM) can be less than the value of the variable resistor R3_VAR in the high power mode (HPM). That is, depending on the power mode, the value of the variable resistor R3_VAR can have the relationship of Equation 2 below.

[0108] Equation 2:

[0109] In Equation 2, R3_VAR_LPM represents the value of the variable resistor R3_VAR in the low power mode (LPM), and R3_VAR_HPM represents the value of the variable resistor R3_VAR in the high power mode (HPM).

[0110] In addition, the method of changing the value of the variable resistor R3_VAR according to the power mode can be implemented in various ways. Hereinafter, as an example, a method of changing the value of the variable resistor R3_VAR by a switch will be described.

[0111] Figure 5 This is a diagram showing an example of the variable resistor R3_VAR.

[0112] As Figure 5 shown, the variable resistor R3_VAR may include a resistor R11, a resistor R12, a switch S11, and a switch S12. The terminal P1 may be the first end of the variable resistor R3_VAR, and the terminal P2 may be the second end of the variable resistor R3_VAR.

[0113] The resistor R11 and the resistor R12 may be connected in series with each other between the two terminals P1 and P2. That is, the first end of the resistor R11 may be connected to the terminal P2, and the resistor R12 may be connected between the second end of the resistor R11 and the terminal P1.

[0114] The switch S11 may be connected in parallel across the two ends of the resistor R11, and the switch S12 may be connected in parallel across the two ends of the resistor R12. The switches S11 and S12 may be switched according to the power mode.

[0115] In the low power mode (LPM), one of the switches S11 and S12 may be turned on, and the other of the switches S11 and S12 may be turned off. As an example, the switch S12 may be turned on and the switch S11 may be turned off. Thus, the value of the resistor R11 may become the value of the variable resistor R3_VAR.

[0116] In the high power mode (HPM), all the switches S11 and S12 may be turned off. Therefore, the sum of the value of the resistor R11 and the value of the resistor R12 may become the value of the variable resistor R3_VAR.

[0117] Although Figure 5 a method of changing the value of the variable resistor R3_VAR according to the power mode by using two resistors and two switches is illustrated, a method of changing the value of the variable resistor R3_VAR according to the power mode may also be implemented by using three resistors and three switches. Additionally, a method of changing the value of the variable resistor R3_VAR according to the power mode may be implemented by using four or more resistors and four or more switches. Furthermore, although examples of two power modes are illustrated with reference to Figure 5 this method may also be applied to three power modes (e.g., LPM, medium power mode (MPM), HPM). Such examples will be readily understandable after understanding the disclosure of the present application, and thus their detailed description may be omitted.

[0118] Figure 6 This is a diagram showing another example of the linearization circuit 300_2.

[0119] As Figure 6As shown, another example of the linearization circuit 300_2 may include a resistor R3 and a variable capacitor C3_VAR. That is, Figure 6 the linearization circuit of Figure 3B is formed by replacing the capacitor C3 in the linearization circuit of

[0120] with a variable capacitor C3_VAR. Depending on the value of the variable capacitor C3_VAR, the amplitude of the coupled input RF signal can be changed. When the value of the variable capacitor C3_VAR increases, the amplitude of the coupled input RF signal can increase. That is, the amplitude of the coupled input RF signal can be adjusted by adjusting the value of the variable capacitor C3_VAR.

[0121] The value of the variable capacitor C3_VAR can be changed according to the power mode. As an example, the value of the variable capacitor C3_VAR in the low power mode (LPM) can be greater than the value of the variable capacitor C3_VAR in the high power mode (HPM). That is, depending on the power mode, the value of the variable capacitor C3_VAR can have the relationship of Equation 3 below.

[0122] Equation 3:

[0123] In Equation 3, C3_VAR_LPM represents the value of the variable capacitor C3_VAR in the low power mode (LPM), and C3_VAR_HPM represents the value of the variable capacitor C3_VAR in the high power mode (HPM).

[0124] In addition, the variable capacitor C3_VAR can be implemented by using a varactor diode. Additionally, similar to the method of Figure 5 , the variable capacitor C3_VAR can be implemented by multiple capacitors and multiple switches.

[0125] Figure 7 is a diagram showing a Doherty amplifier 1000' according to another embodiment.

[0126] As Figure 7 shown, the Doherty amplifier 1000' according to another embodiment may include a carrier amplification transistor 100_1, a carrier biasing circuit 200_1, a resistor R B1 , a linearization circuit 300_1, a peak amplification transistor 100_2, a peak biasing circuit 200_2, a resistor R B2 , a linearization circuit 300_2, a power divider 400, and a power combiner 500. Except for adding the linearization circuit 300_1, Figure 7 the Doherty amplifier 1000' of Figure 1 is similar to the Doherty amplifier 1000 ofFigure 7 In this case, the terminal to which the first input RF signal RF is input is denoted as "IN1". IN1 The terminal to which the IN1 is input is denoted as "IN1".

[0127] In addition, although not shown in Figure 7 , a coupling capacitor may be located between the power divider 400 and the input terminal IN_100_1 of the carrier amplification transistor 100_1. For example, the coupling capacitor may be located between the terminal IN1 to which the first input RF signal RF is input and the input terminal IN_100_1 of the carrier amplification transistor 100_1. The coupling capacitor may perform a function of removing a direct current (DC) component from the RF signal (i.e., blocking the direct current (DC) component in the RF signal). Figure 7 In addition, although not shown in Figure 7 , a coupling capacitor may be located between the power divider 400 and the input terminal IN_100_1 of the carrier amplification transistor 100_1. For example, the coupling capacitor may be located between the terminal IN1 to which the first input RF signal RF is input and the input terminal IN_100_1 of the carrier amplification transistor 100_1. The coupling capacitor may perform a function of removing a direct current (DC) component from the RF signal (i.e., blocking the direct current (DC) component in the RF signal). IN1 The terminal to which the IN1 is input is denoted as "IN1". The coupling capacitor may perform a function of removing a direct current (DC) component from the RF signal (i.e., blocking the direct current (DC) component in the RF signal).

[0128] Due to the resistor R B1 , the base voltage V of the carrier amplification transistor 100_1 B1 will decrease. To solve this problem, the Doherty amplifier 1000' may further include a linearization circuit 300_1 located in the carrier amplifier. The linearization circuit 300_1 may couple a part of the first input RF signal RF input to the input terminal IN_100_1 of the carrier amplification transistor 100_1, and output the coupled signal to the node N1. The coupled input RF signal may be input to the emitter of the transistor Q3 of Figure 2A , so that the carrier bias voltage V IN1 can be increased. When the carrier bias voltage V Figure 2A is increased, the base voltage drop of the carrier amplification transistor 100_1 can be compensated. That is, the linearization circuit 300_1 can compensate the base voltage drop of the carrier amplification transistor 100_1. BIAS1 When the carrier bias voltage V BIAS1 is increased, the base voltage drop of the carrier amplification transistor 100_1 can be compensated. That is, the linearization circuit 300_1 can compensate the base voltage drop of the carrier amplification transistor 100_1.

[0129] The specific internal circuit of the linearization circuit 300_1 may correspond to one of Figures 3A to 3C , Figure 4 , and Figure 6 . Figures 3A to 3C , Figure 4 and Figure 6 in .

[0130] As described with reference to Figure 1 , in order to bias the peak amplification transistor 100_2 to class C and bias the carrier amplification transistor 100_1 to class AB, the peak bias voltage V Figure 1 can be set to a voltage lower than the carrier bias voltage V BIAS2 . Since the peak bias voltage V BIAS1 is lower than the carrier bias voltage V BIAS2 , the base voltage V of the peak amplification transistor 100_2 BIAS1 is lower than the carrier bias voltage V B2It may be more prone to problems. When the amplitude of the coupled input RF signal increases, the base voltage may increase. Therefore, the amplitude of the coupled input RF signal output from the linearization circuit 300_2 may be greater than the amplitude of the coupled input RF signal output from the linearization circuit 300_1.

[0131] That is, the amplitude of the coupled input RF signal output from the linearization circuit 300_1 and the amplitude of the coupled input RF signal output from the linearization circuit 300_2 may have the relationship of Equation 4 below.

[0132] Equation 4:

[0133] In Equation 4, COUPLED_RF IN1 represents the amplitude of the coupled input RF signal output from the linearization circuit 300_1, and COUPLED_RF IN2 represents the amplitude of the coupled input RF signal output from the linearization circuit 300_2.

[0134] Figure 8 FIG. is a diagram showing an example of the linearization circuit 300_1 and an example of the linearization circuit 300_2.

[0135] The linearization circuit 300_1 may include a resistor R3_300_1 and a capacitor C3_300_1. The resistor R3_300_1 and the capacitor C3_300_1 may be connected in series with each other between the terminal IN1 to which the first input RF signal RF IN1 is input and the node N1. The resistor R3_300_1 and the capacitor C3_300_1 may couple a part of the signal in the first input RF signal RF IN1 and may output the coupled signal to the node N1.

[0136] The linearization circuit 300_2 may include a resistor R3_300_2 and a capacitor C3_300_2. The resistor R3_300_2 and the capacitor C3_300_2 may be connected in series with each other between the terminal IN2 to which the second input RF signal RF IN2 is input and the node N2. The resistor R3_300_2 and the capacitor C3_300_2 may couple a part of the signal in the second input RF signal RF IN2 and may output the coupled signal to the node N2.

[0137] Furthermore, as an example of satisfying the relationship of Equation 4, the value of the resistor R3_300_1 and the value of the resistor R3_300_2 may have the relationship of Equation 5 below. Here, the value of the capacitor C3_300_1 and the value of the capacitor C3_300_2 may be the same.

[0138] Equation 5:

[0139] Since the resistor attenuates the RF signal, the value of resistor R3_300_2 can be less than the value of resistor R3_300_1.

[0140] As another example satisfying the relationship of Equation 4, the values of capacitor C3_300_1 and capacitor C3_300_2 can have the relationship of Equation 6 below. Here, the values of resistor R3_300_1 and resistor R3_300_2 can be the same.

[0141] Equation 6:

[0142] Since the amplitude of the coupled input RF signal increases as the capacitance value increases, the value of capacitor C3_300_2 can be greater than the value of capacitor C3_300_1.

[0143] The present disclosure aims to provide a Doherty amplifier with improved linearity.

[0144] In one or more embodiments, the linearity of the Doherty amplifier can be improved by applying a linearization circuit.

[0145] Although specific examples have been shown and described above, it will be readily understood that various changes in form and detail can be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be understood only in a descriptive sense and not for purposes of limitation. The description of a feature or aspect in each example will be considered applicable to similar features or aspects in other examples. Suitable results can be obtained if the described techniques are performed in a different order and / or if the components in the described systems, architectures, devices, or circuits are combined in a different manner and / or the components in the described systems, architectures, devices, or circuits are replaced or supplemented by other components or their equivalents. Accordingly, the scope of the present disclosure is not limited by the specific embodiments, but is defined by the claims and their equivalents, and all variations within the scope of the claims and their equivalents will be construed as being included in the present disclosure.

Claims

1. A Doherty amplifier, comprising: a carrier amplifier transistor configured to amplify a first input RF signal; a carrier bias circuit configured to supply a carrier bias voltage to the carrier amplifying transistor; a peak amplifier transistor configured to amplify a second input RF signal; a peak bias circuit configured to supply a peak bias voltage to the peak amplifying transistor; as well as A first linearization circuit is connected between a first terminal to which the second input RF signal is input and a second terminal to which the peak bias voltage is output in the peak bias circuit, and the first linearization circuit is configured to couple a portion of the second input RF signal to the second terminal.

2. The Doherty amplifier according to claim 1, wherein: The peak bias circuit includes a transistor configured to supply the peak bias voltage, and The second terminal is the emitter of the transistor. 3 . The Doherty amplifier of claim 2 , further comprising a resistor connected between the emitter of the transistor and the input terminal of the peak amplification transistor.

4. The Doherty amplifier according to claim 1, wherein: The amplitude of the coupling signal coupled by the first linearization circuit varies according to the power mode.

5. The Doherty amplifier of claim 4, wherein: The power mode includes a low power mode and a high power mode, and The amplitude of the coupled signal in the low power mode is greater than the amplitude of the coupled signal in the high power mode.

6. The Doherty amplifier according to claim 1, wherein: The first linearization circuit includes a resistor and a capacitor connected in series with each other between the first terminal and the second terminal.

7. The Doherty amplifier of claim 6, wherein: The resistor is a variable resistor, and The value of the variable resistor changes according to the power mode.

8. The Doherty amplifier of claim 7, wherein: The power mode includes a low power mode and a high power mode, and A value of the variable resistor in the low power mode is smaller than a value of the variable resistor in the high power mode.

9. The Doherty amplifier according to claim 1, wherein: The first linearization circuit includes a resistor and a variable capacitor connected in series with each other between the first terminal and the second terminal, and The value of the variable capacitor changes according to the power mode.

10. The Doherty amplifier of claim 9, wherein: The power mode includes a low power mode and a high power mode, and The value of the variable capacitor in the low power mode is greater than the value of the variable capacitor in the high power mode.

11. The Doherty amplifier of claim 1 , further comprising a second linearization circuit connected between a third terminal to which the first input RF signal is input and a fourth terminal to which the carrier bias voltage is output in the carrier bias circuit, and configured to couple a portion of the first input RF signal to the fourth terminal.

12. The Doherty amplifier of claim 11, wherein: The amplitude of the coupled signal coupled by the first linearization circuit is greater than the amplitude of the coupled signal coupled by the second linearization circuit.

13. The Doherty amplifier of claim 11, wherein: The first linearization circuit includes a first resistor and a first capacitor connected in series with each other between the first terminal and the second terminal, and The second linearization circuit includes a second resistor and a second capacitor connected in series with each other between the third terminal and the fourth terminal.

14. The Doherty amplifier of claim 13, wherein: The value of the first resistor is smaller than the value of the second resistor. 15 . The Doherty amplifier of claim 1 , further comprising a power divider configured to generate the first input RF signal and the second input RF signal based on an input RF signal.

16. The Doherty amplifier of claim 1, wherein: The carrier amplifier transistor is biased to class AB by the carrier bias voltage, and The peak amplifier transistor is biased into class C by the peak bias voltage.

17. A Doherty amplifier, comprising: a carrier amplifier transistor configured to amplify a first input RF signal; a first transistor including a first terminal configured to supply a carrier bias voltage to the carrier amplifying transistor; a peak amplifier transistor configured to amplify a second input RF signal; a second transistor including a second terminal configured to supply a peak bias voltage to the peak amplifying transistor; as well as A first linearization circuit is connected between a terminal to which the second input RF signal is input and the second terminal of the second transistor, and the first linearization circuit is configured to couple a portion of the second input RF signal to the second terminal of the second transistor.

18. The Doherty amplifier of claim 17 , further comprising a second linearization circuit connected between a terminal to which the first input RF signal is input and the first terminal of the first transistor, and configured to couple a portion of the first input RF signal to the first terminal of the first transistor.

19. The Doherty amplifier of claim 18, wherein: The first linearization circuit includes a first resistor and a first capacitor connected in series with each other between the terminal to which the second input RF signal is input and the second terminal of the second transistor, and The second linearization circuit includes a second resistor and a second capacitor connected in series with each other between the terminal to which the first input RF signal is input and the first terminal of the first transistor.

20. The Doherty amplifier of claim 19, wherein: The value of the first resistor is smaller than the value of the second resistor.

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