AXI interconnection device, system and method, electronic equipment, storage medium and product

Abstract

The embodiment of the invention discloses an AXI interconnection device, system and method, electronic equipment, a storage medium and a product, and belongs to the technical field of computers. The device comprises a first AXI slave device used for receiving first AXI channel information from a first AXI master device; the framing module is used for framing the first AXI channel information into a first frame based on a predetermined frame structure; the control module is used for sending the first frame to the sending module and storing the first frame to the storage module; the sending module is used for sending a first frame to a receiving end, and the first frame is detected at the receiving end and deframed into first AXI channel information based on a frame structure after successful detection; and the control module is also used for obtaining the first frame from the storage module when the receiving end detects that the first frame has an error, and sending the first frame obtained from the storage module to the sending module so as to resend the first frame. Based on a retransmission mechanism, the data accuracy is improved, and the communication accuracy and precision are improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and more specifically, to an Advanced eXtensible Interface (AXI) interconnection device, system, method, electronic device, storage medium, and product. Background Art

[0002] AXI is a high-performance bus protocol that can be used for communication between internal modules of a system on a chip (SoC) and a field-programmable gate array (FPGA), and has the characteristics of high bandwidth and low latency. The AXI protocol divides read and write operations into multiple independent channels, including a read address (AR) channel, a write address (AW) channel, a write data (W) channel, a read data (R) channel, and a write response (B) channel, allowing read and write operations to be performed simultaneously, which can maximize the interface bandwidth.

[0003] In the current AXI protocol, errors may occur during data transmission, and how to improve the data accuracy in AXI interconnection is one of the focuses of the industry. Moreover, the AXI master is directly interconnected with the AXI slave. AXI is a parallel interface bus that includes multiple groups (for example, usually 5 groups) of independent channels. Therefore, there are too many interface signals and too many pins for signal lines between the AXI master and the AXI slave, and the pin area required for chip implementation is large. Summary of the Invention

[0004] The present invention provides an AXI interconnection device, system, method, electronic device, storage medium, and product, which helps to improve data accuracy.

[0005] The technical solutions of the embodiments of the present invention are as follows: An AXI interconnection device is connected between a first AXI master and a receiving end. The AXI interconnection device includes: A first AXI slave, configured to receive first AXI channel information from the first AXI master based on a handshaking mechanism with the first AXI master; A framing module, configured to frame the first AXI channel information into a first frame based on a predetermined frame structure; The device further includes a control module, a sending module, and a storage module, where: The control module is configured to send the first frame to the sending module and store the first frame in the storage module; The sending module is configured to send the first frame to the receiving end, where the first frame is detected at the receiving end and, after successful detection, is deframed into the first AXI channel information based on the frame structure; The control module is further configured to, when the receiving end detects that the first frame is in error, obtain the first frame from the storage module, and send the first frame obtained from the storage module to the sending module, so that the sending module re-sends the first frame obtained from the storage module to the receiving end.

[0006] In one embodiment, the control module is configured to schedule the first frame based on a predetermined scheduling method before sending the first frame to the sending module, where the scheduling method includes at least one of the following: First-come, first-served scheduling method; priority scheduling method; shortest job first scheduling method; round-robin scheduling method; highest response ratio next scheduling method; fair scheduling method; hybrid scheduling method based on priority and time slice.

[0007] In one embodiment, the control module is configured to, when receiving a negative acknowledgment (NACK) signal containing the sequence number of the first frame from the receiving end, determine that the receiving end detects an error in the first frame, and control the first AXI slave device to stop receiving AXI channel information from the first AXI master device.

[0008] In one embodiment, it includes: An alarm module, configured to send an alarm message when the control module does not receive an acknowledgment (ACK) signal or the NACK signal from the receiving end within a predetermined time threshold, or when the retransmission times of the first frame exceed a predetermined number threshold.

[0009] In one embodiment, the control module is configured to, when receiving the NACK signal from the receiving end, send all the frames stored in the storage module starting from the sequence number to the sending module, so that the sending module sends all the frames to the receiving end.

[0010] In one embodiment, the control module is configured to, when the sending module finishes sending all the frames to the receiving end and does not receive a NACK signal containing at least one sequence number of all the frames from the receiving end, control the first AXI slave device to resume receiving AXI channel information from the first AXI master device.

[0011] In one embodiment, the control module is configured to, when receiving the NACK signal from the receiving end, wait for a first predetermined time, and send all the frames stored in the storage module starting from the sequence number to the sending module, where the receiving end closes the data receiving function when sending the NACK signal and opens the data receiving function after a second predetermined time, and the first predetermined time is greater than the second predetermined time.

[0012] In one embodiment, it includes a receiving module and a deframing module, where: The receiving module is configured to receive a second frame from a sending end, where the second frame is generated by the sending end based on the frame structure to frame the second AXI channel information; when detecting that the second frame is in error, it does not send the second frame to the deframing module, generates a NACK signal including the sequence number of the second frame, and sends the NACK signal to the sending end for the sending end to re - send the second frame based on the NACK signal; when detecting that the second frame is correct, it sends the second frame to the deframing module; The deframing module is configured to deframe the second frame into the second AXI channel information based on the frame structure.

[0013] An AXI interconnection system includes a first chip and a second chip; The first chip includes a first AXI master device, a first AXI slave device, a first framing module, a first control module, a first storage module, and a first sending module; The second chip includes a first receiving module, a first deframing module, a second AXI master device, and a second AXI slave device; Wherein the first AXI slave device is configured to receive first AXI channel information from the first AXI master device based on a hand - shaking mechanism with the first AXI master device; the first framing module is configured to frame the first AXI channel information into a first frame based on a predetermined frame structure; the first control module is configured to send the first frame to the first sending module and store the first frame in the first storage module; the first sending module is configured to send the first frame; The first receiving module is configured to receive the first frame, when detecting that the first frame is in error, send a first NACK signal including the sequence number of the first frame to the first control module, and when detecting that the first frame is correct, send the first frame to the first deframing module; the first deframing module is configured to deframe the first frame into the first AXI channel information based on the frame structure and send the first AXI channel information to the second AXI master device; the second AXI master device is configured to send the first AXI channel information to the second AXI slave device based on a hand - shaking mechanism with the second AXI slave device; The first control module is further configured to, when receiving the first NACK signal, obtain the first frame from the first storage module and send the first frame obtained from the first storage module to the first sending module for the first sending module to re - send the first frame obtained from the first storage module.

[0014] In one embodiment, the second chip includes a third AXI master device, a third AXI slave device, a second set of frame modules, a second control module, a second storage module, and a second transmission module; The first chip includes a second receiving module, a second deframing module, a fourth AXI master device, and a fourth AXI slave device; Wherein the third AXI slave device is configured to receive second AXI channel information from the third AXI master device based on a handshaking mechanism with the third AXI master device; the second set of frame modules is configured to frame the second AXI channel information into a second frame based on the frame structure; the second control module is configured to send the second frame to the second transmission module and store the second frame in the second storage module; the second transmission module is configured to transmit the second frame; The second receiving module is configured to receive the second frame, and when it detects that the second frame is in error, send a second NACK signal containing the sequence number of the second frame to the second control module, and when it detects that the second frame is correct, send the second frame to the second deframing module; the second deframing module is configured to deframe the second frame into the second AXI channel information based on the frame structure and send the second AXI channel information to the fourth AXI master device; the fourth AXI master device is configured to send the second AXI channel information to the fourth AXI slave device based on a handshaking mechanism with the fourth AXI slave device; The second control module is further configured to, when receiving the second NACK signal, obtain the second frame from the second storage module and send the second frame obtained from the second storage module to the second transmission module for the second transmission module to re-transmit the second frame obtained from the second storage module.

[0015] An AXI interconnection method includes: Receiving first AXI channel information from the first AXI master device based on a handshaking mechanism with the first AXI master device; Framing the first AXI channel information into a first frame based on a predetermined frame structure; Sending the first frame to a receiving end and storing the first frame in a storage module, where the first frame is detected at the receiving end and, after successful detection, is deframed into the first AXI channel information based on the frame structure; wherein when the receiving end detects that the first frame is in error, obtaining the first frame from the storage module and re-sending the first frame obtained from the storage module to the receiving end.

[0016] In one embodiment, it includes: When receiving a NACK signal containing the sequence number of the first frame from the receiving end, it is determined that the receiving end detects an error in the first frame, and the reception of AXI channel information from the first AXI master is stopped.

[0017] In one embodiment, it includes: When receiving the NACK signal from the receiving end, wait for a first predetermined time, and send all the frames stored in the storage module starting from the sequence number to the receiving end, where the receiving end closes the data reception function when sending the NACK signal and enables the data reception function after a second predetermined time, and the first predetermined time is greater than the second predetermined time.

[0018] An electronic device, including: A memory; A processor; Wherein an application program executable by the processor is stored in the memory, and is used to enable the processor to execute any one of the above AXI interconnection methods.

[0019] A computer-readable storage medium, on which computer-readable instructions are stored, and when the computer-readable instructions are executed by a processor, the processor is enabled to execute any one of the above AXI interconnection methods.

[0020] A program product, including a computer program, which when executed by a processor implements any one of the above AXI interconnection methods.

[0021] As can be seen from the above technical solutions, in the embodiments of the present invention, a first AXI slave device is used to receive first AXI channel information from a first AXI master based on a handshaking mechanism with the first AXI master; a framing module is used to frame the first AXI channel information into a first frame based on a predetermined frame structure; a control module is used to send the first frame to a sending module and store the first frame in a storage module; the sending module is used to send the first frame to a receiving end, where the first frame is detected at the receiving end and after successful detection, it is deframed into first AXI channel information based on the frame structure; the control module is further used to, when the receiving end detects an error in the first frame, obtain the first frame from the storage module and send the first frame obtained from the storage module to the sending module, so that the sending module re-sends the first frame obtained from the storage module to the receiving end. It can be seen that in the embodiments of the present invention, a backup is performed for each data frame sent, and a retransmission is performed for the data frame with an error, implementing a retransmission mechanism in AXI interconnection, which can improve data accuracy, thereby improving the correct rate and accuracy of signal communication.

[0022] In addition, the embodiments of the present invention can precisely control the closing and opening of the data receiving function at the receiving end, the stopping and resuming of the first AXI slave device receiving AXI channel information from the first AXI master device, and the first predetermined time and the second predetermined time, which can ensure that the data received during the retransmission process at the receiving end will not be repeated or omitted, and improve the integrity of the data.

[0023] Moreover, the embodiments of the present invention implement information interaction with the receiving end in the form of framing and deframing, and can adjust (usually reduce) the bit width of the transmission signal line of the first frame as required, which is beneficial to reducing the number of signal lines and can significantly reduce the chip pin area during interconnection. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of an exemplary AXI interconnection in the related art.

[0025] Figure 2 It is a first schematic diagram of an AXI interconnection device according to an embodiment of the present invention.

[0026] Figure 3 It is a schematic diagram of an exemplary frame structure according to an embodiment of the present invention.

[0027] Figure 4 It is a second schematic diagram of an AXI interconnection device according to an embodiment of the present invention.

[0028] Figure 5 It is a schematic diagram of an AXI interconnection system according to an embodiment of the present invention.

[0029] Figure 6 It is a schematic diagram of an AXI interconnection method according to an embodiment of the present invention.

[0030] Figure 7 It is a schematic diagram of an exemplary structure of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] To make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0032] For the sake of brevity and intuitiveness in description, the solutions of the present invention will be elaborated below by describing several representative embodiments. A large number of details in the embodiments are only used to help understand the solutions of the present invention. However, it is obvious that the technical solutions of the present invention can be implemented without being limited to these details. In order to avoid unnecessarily obscuring the solutions of the present invention, some embodiments are not described in detail, but only the framework is given. Hereinafter, "including" means "including but not limited to", and "according to..." means "at least according to..., but not limited to only according to...". Due to the language habits of Chinese, when the quantity of a component is not specifically indicated hereinafter, it means that the component can be one or more, or can be understood as at least one.

[0033] The AXI protocol divides read and write operations into multiple independent channels, including a read address (AR) channel, a write address (AW) channel, a write data (W) channel, a read data (R) channel, and a write response (B) channel, where read and write operations are allowed to occur simultaneously.

[0034] Figure 1 FIG. is a schematic diagram of an exemplary AXI interconnect in the related art. In Figure 1 , the AXI master device and the AXI slave device related to the same read and write operation are directly interconnected. There are multiple independent unidirectional channels between the AXI master device and the AXI slave device, and each channel is composed of specific functions and signals. For example: the write address channel is used for the AXI master device to send the address and related control information of the write operation to the AXI slave device; the write data channel is used for the AXI master device to send write data to the AXI slave device; the write response channel is used for the AXI slave device to send a response to the write operation to the AXI master device, indicating whether the write operation is successful; the read address channel is used for the AXI master device to send the address and related control information of the read operation to the AXI slave device; the read data channel is used for the AXI slave device to send read data to the AXI master device.

[0035] Since each channel contains a large number of signals (for example, the signals in the write address channel can include: the write address (AWADDR) signal; the burst length (AWLEN) signal, indicating the number of data transmitted in a single write operation; the data size (AWSIZE) signal, indicating the size of each data (such as 32 bits, 64 bits); the burst type signal (AWBURST), indicating fixed, incrementing, wrapping, etc.; the valid (AWVALID) signal, indicating that the address and control information are valid; the ready (AWREADY) signal, indicating that the AXI slave device is ready to receive the address information, etc.), there are a large number of signal lines between the directly interconnected AXI master device and AXI slave device, resulting in a large number of pins. In particular: when the AXI master device and the AXI slave device are located on different chips respectively, it is necessary to increase the chip area to arrange a large number of pins, reducing the maintainability of the chip.

[0036] Moreover, in the signal transmission between the AXI master device and the AXI slave device, data errors may occur, and it is difficult to ensure data accuracy based on related technologies.

[0037] In the embodiments of the present invention, a retransmission mechanism in AXI interconnection is implemented. Compared with related technologies, when it is confirmed that data is in error, the erroneous data can be accurately retransmitted, thereby ensuring data accuracy and improving the correct rate and precision of signal communication. In addition, the embodiments of the present invention also ensure that in a scenario where there is a retransmission mechanism, the data frames received by the receiving end will not be repeated or omitted, further improving the integrity of the data.

[0038] Moreover, in the embodiments of the present invention, based on the methods of framing and deframing, the information interaction between the AXI master and slave devices is realized. Compared with related technologies, it helps to reduce pin requirements, especially beneficial for AXI interconnection between chips.

[0039] The above disclosure details the technical defects existing in related technologies, the reasons for these technical defects, and the thinking and analysis process of overcoming these technical defects. In fact, the recognition of the above technical defects is not common knowledge in the art, but a novel discovery by the inventor in the research. In addition, the tracing of the reasons for the technical defects and the thinking and analysis process of overcoming the technical defects are also the step-by-step analysis results of the inventor in the actual research process, and none of them are common knowledge in the art.

[0040] Figure 2 FIG. is a schematic diagram of an AXI interconnection device according to an embodiment of the present invention. The AXI interconnection device is connected between a first AXI master device and a receiving end. The receiving end may include a second AXI master device, a second AXI slave device, a receiving module, and a deframing module.

[0041] The first AXI master device and the second AXI slave device are respectively the participants in the same read operation or the same write operation. For example, in a read operation, the first AXI master device reads data from the second AXI slave device; in a write operation, the first AXI master device writes data to the second AXI slave device.

[0042] The AXI interconnect device includes: a first AXI slave device, configured to receive first AXI channel information from a first AXI master device based on a handshaking mechanism with the first AXI master device. A framing module, configured to frame the first AXI channel information into a first frame based on a predetermined frame structure. The AXI interconnect device further includes a control module, a transmitting module, and a storage module. The control module is configured to send the first frame to the transmitting module and store the first frame in the storage module. The transmitting module is configured to send the first frame to a receiving module in a receiving end, where the first frame is detected by the receiving module in the receiving end. After the receiving module successfully detects the first frame, a deframing module in the receiving end deframes the first frame into first AXI channel information based on the frame structure. The control module is further configured to, when the receiving module in the receiving end detects an error in the first frame, obtain the first frame from the storage module and send the first frame obtained from the storage module to the transmitting module, so that the transmitting module re-sends the first frame obtained from the storage module to the receiving module in the receiving end.

[0043] It can be seen that when the control module sends the first frame to the transmitting module, it stores the first frame in the storage module. A backup of the first frame is implemented in the storage module. When the first frame has an error, the first frame is obtained from the storage module, so that the receiving module re-sends the first frame obtained from the storage module. Therefore, the embodiment of the present invention implements a retransmission mechanism in AXI interconnect, which can reduce data transmission errors, improve data accuracy, and thus improve the correct rate and precision of signal communication.

[0044] In one embodiment, when the framing module frames the first AXI channel information into a first frame, it can store a parity bit determined based on a predetermined parity check method at a predetermined position (such as the frame header, frame tail, or payload part) of the frame structure. For example, the parity check method may include: (1) Parity check: In odd parity, the sum of the data bits and the parity bit is odd. For example, assume there are 4 data bits (1011), and there are 3 ones among these 4 data bits. To make the sum odd, the parity bit should be 0 (because 3 + 0 = 3, and 3 is odd). If the sum of the data received by the receiving end and the parity bit is not odd, it indicates that an error has occurred during data transmission. Even parity is similar to odd parity, requiring that the sum of the data bits and the parity bit must be even. Still taking 4 data bits (1011) as an example, there are 3 ones among these 4 data bits. To make the sum even, the parity bit should be 1 (because 3 + 1 = 4, and 4 is even). If the sum of the data received by the receiving end and the parity bit is not even, it indicates that an error has occurred during data transmission.

[0045] (2) Cyclic Redundancy Check (CRC): CRC is a verification method based on polynomial division. At the sending end, the data is regarded as a polynomial, and the data polynomial is divided by a predefined generating polynomial. The obtained remainder is used as the check code and appended to the data for transmission. At the receiving end, the received data (including the check code) is divided by the same generating polynomial. If the remainder is 0, the data is considered correct.

[0046] (3) Vertical Redundancy Check: In vertical redundancy check, the data is arranged in columns, and a parity check is performed on each column to obtain a check byte. The sending end sends the data and the check byte together. The receiving end performs a parity check on the received data by column and compares the check result with the check byte sent by the sending end to determine whether the data is correct.

[0047] (4) Checksum: In checksum, the data is divided into several bytes (or bits), and a summation operation is performed on these bytes (or bits). The obtained result is used as the checksum and appended to the data for transmission. The receiving end performs the same summation operation on the received data and compares the result with the checksum sent by the sending end to determine whether the data is correct.

[0048] (5) Redundancy Check: Redundancy check improves the reliability of data transmission by adding redundant data. For example, the data can be sent multiple times, and the receiving end determines whether the data is correct by comparing the data sent multiple times.

[0049] (6) Check Code: A check code is a piece of verification data generated by a specific algorithm and appended to the original data for transmission. The receiving end verifies the received data through the same algorithm to determine whether the data is correct. Common check codes include CRC check codes, Hamming check codes, etc.

[0050] (7) Interleaving Check: Interleaving check is a method of performing verification after interleaving the data. For example, the data is interleaved according to certain rules, and then the interleaved data is verified. The receiving end deinterleaves the received data and then performs verification to determine whether the data is correct.

[0051] At the receiving end: After the receiving module in the receiving end receives the first frame, it checks the parity bit. For example, if it is odd parity, the receiving module calculates the sum of the data bits and the parity bit and determines whether it is odd; if it is even parity, the receiving module determines whether the sum is even. If the check result does not conform to the parity check rule (the sum of odd parity is not odd, and the sum of even parity is not even), the receiving module determines that an error has occurred during the transmission of the first frame. Moreover, the deframing module deframes the first frame that has been correctly checked to obtain the first AXI channel information. The first AXI channel information is sent to the second AXI master, where the second AXI master sends the first AXI channel information to the second AXI slave based on the handshaking mechanism with the second AXI slave.

[0052] It can be seen that through the framing process of the framing module, the bit width of the signal line used to transmit the first frame in the sending module can be reduced to any bit, which is beneficial to reducing the number of signal lines and significantly reducing the chip pin area during interconnection.

[0053] In one embodiment, the bit width of the signal line of the sending module is less than the bit width of the signal line between the first AXI slave and the first AXI master. For example, when integrating the first AXI master, the first AXI slave, the framing module, the control module, the alarm module, the storage module, and the sending module into the first chip, the number of pins of the sending module for transmitting the first frame to the second AXI slave outside the chip can be reduced as required (for example, in an extreme case, it can even be reduced to 1 bit), which helps to reduce the pin area of the first chip.

[0054] In one embodiment, the receiving module, the deframing module, the second AXI master, and the second AXI slave can be integrated into a second chip different from the first chip.

[0055] It can be seen that based on Figure 2 the AXI interconnection device shown, the first AXI master sends the first AXI channel information to the second AXI slave. Moreover, in data transmission, the data accuracy is improved based on the retransmission mechanism, and the communication correctness and precision are improved.

[0056] In the AXI protocol, data interaction between the AXI master and the AXI slave is achieved through a handshaking mechanism based on the VALID signal and the READY signal. The handshaking mechanism ensures the reliability and flexibility of data transmission and is applicable to all channels of the AXI protocol (including the read address channel, read data channel, write address channel, write data channel, and write response channel). The core of the handshaking mechanism is to synchronize data transmission through the VALID and READY signals. Among them: The VALID signal is sent by the source end, indicating that the data or control information is ready to be received. The READY signal is sent by the destination end, indicating that the destination end is ready to receive data. Data transmission occurs at the rising edge of the clock when both the VALID and READY signals are high. The handshaking mechanism ensures that data is transmitted only when both the source end and the destination end are ready. The source end can be an AXI master or an AXI slave, and the destination end can also be an AXI master or an AXI slave.

[0057] The handshaking mechanism in each channel is described below.

[0058] (1) Write address channel: Among them: The AXI master raises the AWVALID signal, indicating that the write address and control information are valid; the AXI slave raises the AWREADY signal, indicating that it can receive the address information.

[0059] (2) Write data channel: Among them: The AXI master raises the WVALID signal, indicating that the write data is valid; the AXI slave raises the WREADY signal, indicating that it can receive the data.

[0060] (3) Write response channel: Among them: The AXI slave: raises the BVALID signal, indicating that the write response is valid; the AXI master raises the BREADY signal, indicating that it can receive the response.

[0061] (4) Read address channel: Among them: The AXI master raises the ARVALID signal, indicating that the read address and control information are valid; the AXI slave raises the ARREADY signal, indicating that it can receive the address information.

[0062] (5) Read data channel: Among them: The AXI slave raises the RVALID signal, indicating that the read data is valid; the AXI master: raises the RREADY signal, indicating that it can receive the data.

[0063] In Figure 2 the first AXI slave receives the first AXI channel information from the first AXI master based on the handshaking mechanism in the AXI connection with the first AXI master. For example, the first AXI channel information can be implemented as: write address channel information, write data channel information, and read address channel information.

[0064] For example, the write address channel information may include: the AWID signal, which is used to distinguish write transactions; the write address (AWADDR) signal; the burst length (AWLEN) signal, which represents the number of data transmitted in a single write operation; the data size (AWSIZE) signal, which represents the size of each data (such as 32 bits, 64 bits); the burst type signal (AWBURST); the AWVALID signal, which indicates that the address and control information are valid; the AWREADY signal, which indicates that the AXI slave device is ready to receive the address information, and so on. The write data channel information may include: the WID signal, which is used to identify the write transaction corresponding to the write data; the write data (WDATA); the byte enable (WSTRB) signal, which is used to indicate which specific bytes are valid; the WLAST signal, which is used to indicate that the current data is the last data in the burst transmission; the data valid (WVALID) signal, which is used to indicate that the data is valid; the ready (WREADY) signal, which indicates that the AXI slave device is ready to receive the data. The read address channel information may include: the ARID signal, which is used to distinguish read transactions; the read address (ARADDR); the burst length (ARLEN) signal; the ARSIZE signal, which represents the size of each data; the burst type signal (AWBURST); the ARVALID signal, which indicates that the address and control information are valid; the ARREADY signal, which indicates that the AXI slave device is ready to receive the address information.

[0065] In Figure 2 it, the data sources at the receiving end include two paths, namely the main data path when the data is error-free (the data obtained by the control module from the framing module and sent to the sending module) and the retransmitted data from the storage module when the data is in error. The main data path may contain multiple paths of data (because it includes multiple unidirectional channels). When more than one path of data in the main data path needs to be sent simultaneously, the embodiment of the present invention can automatically start arbitration to perform signal transmission according to a preset scheduling method.

[0066] In one embodiment, the control module is used to schedule the first frame based on a predetermined scheduling method before sending the first frame to the sending module, where the scheduling method includes at least one of the following: first-come-first-served scheduling method; priority scheduling method; shortest job first scheduling method; round-robin scheduling method; highest response ratio first scheduling method; fair scheduling method; hybrid scheduling method based on priority and time slice.

[0067] The above exemplary descriptions of typical instances of the scheduling method and the verification method, those skilled in the art can realize that such descriptions are only exemplary and are not used to limit the protection scope of the embodiments of the present invention.

[0068] After the receiving module in the receiving end receives the first frame, it can generate an ACK signal or a NACK signal based on the detection situation of the first frame, and send the ACK signal or the NACK signal to the control module. Among them: NACK is a negative feedback signal, indicating that the receiving module detects an error in the first frame; the ACK signal indicates that the receiving module detects that the first frame is correct.

[0069] In one embodiment, the control module is configured to determine that the receiving end detects an error in the first frame when receiving a NACK signal including the sequence number of the first frame from the receiving end, and control the first AXI slave device to stop receiving AXI channel information from the first AXI master device. For example, after the receiving module in the receiving end receives the first frame, it checks the check bits of the first frame. If the check result indicates that the first frame is in error, the receiving module in the receiving end sends a NACK signal including the sequence number of the first frame to the control module. When the control module receives the NACK signal, it controls the first AXI slave device to stop receiving AXI channel information from the first AXI master device, so as to ensure that when the data is in error, the first AXI slave device no longer continues to receive new AXI channel information.

[0070] In one embodiment, the AXI device includes an alarm module, which is configured to send an alarm message when the control module does not receive an ACK signal or a NACK signal from the receiving end within a predetermined time threshold, or the number of retransmissions of the first frame exceeds a predetermined number threshold. Therefore, when the control module does not receive an ACK signal or a NACK signal from the receiving end within a predetermined time threshold, or the number of retransmissions of the first frame exceeds a predetermined number threshold, it is determined that a major fault such as a transmission link error occurs, and an alarm message is sent.

[0071] Preferably, the storage module has a predetermined size of capacity to cache multiple data frames, so as to improve the efficiency of the retransmission process. In one embodiment, the control module is configured to, when receiving a NACK signal from the receiving end, send all the frames stored in the storage module starting from the sequence number to the sending module, so that the sending module sends all the frames to the receiving end. For example: Assume that the sequence numbers of the data frames transmitted via the main data path are 1 to 15. Correspondingly, the sequence numbers of the data frames stored in the storage module are 1 to 15. The control module determines that the frame with sequence number 12 is in error based on the NACK signal received from the receiving end. The control module sends the data frames with sequence numbers 12 to 15 to the sending module, so that the sending module sequentially sends the data frames with sequence numbers 12 to 15 to the receiving end.

[0072] In one embodiment, the control module is configured to control the first AXI slave device to resume receiving AXI channel information from the first AXI master device when the sending module completes sending all the frames to the receiving end and does not receive a NACK signal including at least one sequence number of all the frames from the receiving end.

[0073] Example: Assume that the control module determines that the sequence number of the first frame with an error is 12 based on the NACK signal received by the receiving end. The sequence numbers of the data frames stored in the storage module are from 1 to 15. The data frames with sequence numbers from 12 to 15 are sent to the sending module, so that the sending module sequentially sends the data frames with sequence numbers from 12 to 15 to the receiving end. Moreover, during the process of the sending module sending the data frames with sequence numbers from 12 to 15 to the receiving end, the control module does not receive a NACK signal from the receiving end that contains at least one of the sequence numbers from 12 to 15. The control module determines that the retransmission process has been successfully completed and controls the first AXI slave device to resume receiving AXI channel information from the first AXI master device. Therefore, after the retransmission process is completed, the first AXI slave device resumes receiving AXI channel information from the first AXI master device.

[0074] In one embodiment, the control module is configured to, when receiving a NACK signal from the receiving end, wait for a first predetermined time, and send all the frames stored in the storage module starting from the sequence number to the sending module, where the receiving end closes the data receiving function when sending the NACK signal and turns on the data receiving function after a second predetermined time, and the first predetermined time is greater than the second predetermined time.

[0075] Therefore, the receiving end immediately closes the data receiving function when sending a NACK signal, which can prevent duplicate receipt of data. For example, assume that the receiving end detects that the frame with sequence number 12 sent via the main data path is in error, and the receiving end generates a NACK signal containing sequence number 12. However, it takes a certain amount of time for this NACK signal to be transmitted to the control module. If the data receiving function of the receiving end is not closed in time, the receiving end may receive the frame with sequence number 13 sent via the main data path during this period. In the subsequent data retransmission process, all the frames starting from sequence number 12 in the storage module (assuming sequence numbers from 12 to 15) will be retransmitted, and the receiving end may receive the frame with sequence number 13 via the retransmission mechanism, resulting in duplication of the frame with sequence number 13. In the embodiment of the present invention, when the receiving end sends the NACK signal with sequence number 12, it immediately closes the data receiving function, and the data frames with sequence numbers greater than the current sequence number 12 (if any) will be discarded, thus effectively preventing possible retransmission situations during the subsequent data retransmission process.

[0076] Moreover, based on the ingenious design that the first predetermined time is greater than the second predetermined time, it can also ensure that the data packets received by the receiving end during the retransmission period are not missed, improving the integrity of the data.

[0077] For example, assume that the receiving end detects an error in the frame with sequence number 12 sent via the main data path. The receiving end generates a NACK signal containing sequence number 12. When sending the NACK signal, the receiving end turns off the data receiving function and turns on the data receiving function after 5 seconds. If within these 5 seconds, the control module executes the data retransmission process, all frames starting from sequence number 12 in the storage module (assuming sequence numbers 12 to 15) will be retransmitted. Since the data receiving function of the receiving end has not been turned on, some of the frames with sequence numbers 12 to 15 cannot be sent to the receiving end, resulting in data omission. In the embodiment of the present invention, after these 5 seconds, the control module executes the data retransmission process, thereby preventing data omission during data retransmission.

[0078] In one embodiment, based on statistical processing of a time period, the timing of a first predetermined time and a second predetermined time is achieved. For example: when a NACK signal is generated, the receiving end waits for P clock cycles before receiving data (that is, before the end of P clock cycles, the receiving end discards the received data until the end of P clock cycles and then resumes data reception). The control module waits for Q clock cycles before sending data to the receiving end (that is, before the end of Q clock cycles, the control module does not transmit any data in the storage module to the receiving end), and at the same time does not receive data from the main data path until the end of Q clock cycles, and then resumes data transmission, where Q is greater than P. The reasons for the above processing at least include: (1) The NACK signal is a single-bit serial encoded value, and it takes time for the control module to parse the sequence number therein, resulting in the control module not being able to immediately detect an error warning. (2) There is usually a wire delay in the interconnection between chips, and it is necessary to wait for a time to improve the accuracy of data communication before resuming normal data transmission.

[0079] In one embodiment, the AXI interconnection device includes a receiving module and a deframing module, where: the receiving module is used to receive a second frame from the sending end, and the second frame is generated by the sending end based on the frame structure to frame the second AXI channel information; when detecting an error in the second frame, it does not send the second frame to the deframing module, generates a NACK signal containing the sequence number of the second frame, and sends the NACK signal to the sending end for the sending end to retransmit the second frame based on the NACK signal; when detecting that the second frame is correct, it sends the second frame to the deframing module; the deframing module is used to deframe the second frame into the second AXI channel information based on the frame structure. It can be seen that considering that data communication is usually two-way, the embodiment of the present invention also proposes an AXI interconnection device supporting two-way communication.

[0080] Figure 3 A schematic diagram showing an example of the frame structure according to the embodiment of the present invention. As Figure 3As shown, the frame structure includes a frame header field, a frame tail field, N check bits, and N AXI channel information fields (preferably, N is an extensible positive integer). Among them: The frame header field carries the type of AXI channel information. For example, through different information encodings, it can indicate that the current frame structure is a specific channel type among multiple channels of AXI (such as the write address channel, write data channel, write response channel, read address channel, and read data channel). The N AXI channel information fields respectively correspond to N types of AXI channel information for N channels. Each AXI channel information field can carry signals in the corresponding AXI channel information. The N check bits correspond one-to-one with the N AXI channel information fields and are used to save the check results of the corresponding AXI channel information fields (for example, the check results can be implemented as parity check results or CRC check results, etc.). Usually, when at least one check bit fails the detection, it can be determined that the frame is in error. When framing, the AXI channel information is arranged according to a preset frame structure. During the deframing operation, based on this frame structure, the relevant AXI channel information can be successfully parsed.

[0081] The first AXI channel information may include write address channel information, write data channel information, and read address channel information. Therefore, based on Figure 3 the frame structure shown, the first AXI channel information can be carried in the first frame. In fact, Figure 3 the channel types supported by the frame structure shown may also include the write response channel and the read data channel. Therefore, based on this frame structure, the first AXI slave device can return the write response channel information and the read data channel information to the first AXI master device.

[0082] Based on Figure 3 the frame structure shown, the receiving end can calculate the check bits of each AXI channel information field and compare the calculated check bits with the check bits in the frame. When at least one check bit comparison fails, it can be determined that the frame is in error.

[0083] The above exemplary description shows typical examples of the frame structure. Those skilled in the art can realize that this description is only exemplary and is not used to limit the protection scope of the embodiments of the present invention.

[0084] In Figure 2 , an AXI interconnection device for implementing the first AXI master device to send the first AXI channel information to the second AXI slave device is described. Considering that data communication is usually bidirectional, the embodiments of the present invention also propose an AXI interconnection device supporting bidirectional communication.

[0085] Figure 4 FIG. 24 is a second exemplary diagram of an AXI interconnection device according to an embodiment of the present invention. Figure 4The AXI interconnect device shown can enable the first AXI master device connected to the AXI interconnect device to send the first AXI channel information to an AXI slave device outside the AXI interconnect device. Moreover, Figure 4 The AXI interconnect device shown can also enable an AXI master device outside the AXI interconnect device to send the second AXI channel information to the fourth AXI slave device connected to the AXI interconnect device.

[0086] The AXI interconnect device includes a first AXI slave device, a framing module, a control module, an alarm module, a storage module, a sending module, a receiving module, a deframing module, and a fourth AXI master device.

[0087] According to Figure 4 the sending direction shown: The first AXI slave device in the AXI interconnect device receives the first AXI channel information from the first AXI master device based on the handshaking mechanism with the first AXI master device. The framing module frames the first AXI channel information into a first frame based on a predetermined frame structure. The control module sends the first frame to the sending module and stores the first frame in the storage module. The sending module sends the first frame to the receiving end, where the first frame is detected at the receiving end and, after successful detection, is deframed into the first AXI channel information based on the frame structure. When the receiving end detects an error in the first frame, the control module receives a first NACK signal containing the first frame sequence number from the receiving end. The control module retrieves the first frame from the storage module and sends the first frame retrieved from the storage module to the sending module for the sending module to resend the first frame retrieved from the storage module to the receiving end.

[0088] At the receiving end outside the AXI interconnect device, the first frame is received and deframed into the first AXI channel information based on the frame structure. The first AXI channel information obtained by deframing can be sent to a second AXI master device ( Figure 4 not shown in Figure 4 ), where the second AXI master device sends the first AXI channel information to a second AXI slave device (

[0089] not shown in Figure 4 ) based on the handshaking mechanism with the second AXI slave device, thereby completing the communication process from the first AXI master device to the second AXI slave device. Figure 4It is generated based on the second AXI channel information sent (not shown in the figure). The deframing module is used to deframe the second frame into the second AXI channel information based on the frame structure. The fourth AXI master device sends the second AXI channel information to the fourth AXI slave device based on the handshaking mechanism with the fourth AXI slave device, thus completing the communication process from the third AXI master device to the fourth AXI slave device.

[0090] Embodiments of the present invention also propose an AXI interconnect system. This AXI interconnect system is applicable to realizing the two-way communication process between AXI master and slave devices between chips.

[0091] Figure 5 It is a schematic diagram of an AXI interconnect system according to an embodiment of the present invention. As Figure 5 shown, the AXI interconnect system includes a first chip and a second chip. The first chip includes a first AXI master device, a first AXI slave device, a first group of frame modules, a first control module, a first storage module, a first alarm module, and a first sending module. The second chip includes a first receiving module, a first deframing module, a second AXI master device, and a second AXI slave device. The second chip further includes a third AXI master device, a third AXI slave device, a second group of frame modules, a second control module, a second storage module, a second alarm module, and a second sending module. The first chip further includes a second receiving module, a second deframing module, a fourth AXI master device, and a fourth AXI slave device.

[0092] Parity check units are respectively arranged in the first sending module, the second sending module, the first receiving module, and the second receiving module. Odd or even parity check operations can be selected through software configuration to improve the circuit flexibility. When the first sending module and the second sending module send data, they perform parity checks on each data packet in the frame structure based on the parity check unit and fill the check result in the frame tail area of each data packet. The more data packets included in the frame structure, the more accurate the check result. Storing the check result at the end of the packet instead of requiring a separate interconnect signal line can reduce the number of signal lines during interconnection. The AXI signal lines can be arranged to use the idle fields as storage for parity bits, which can further improve the data transmission efficiency. When the first receiving module and the second receiving module receive data, they perform parity checks on each data packet in the frame structure based on the parity check unit and compare the check result with the check result in the frame structure to determine whether the data frame is in error.

[0093] (1): The first AXI master device in the first chip can actively initiate a communication process to the second AXI slave device in the second chip.

[0094] Example: The first AXI slave device receives first AXI channel information from the first AXI master device based on a handshaking mechanism with the first AXI master device. Here, an example is given where the first AXI channel information is specifically write address channel information for illustration.

[0095] The first group of frame modules frame the write address channel information into a first frame based on a predetermined frame structure. The first control module sends the first frame to the first sending module and stores the first frame in the first storage module. The first sending module sends the first frame using signal lines, where the bit width of the signal lines of the first sending module is less than the bit width of the signal lines between the first AXI slave device and the first AXI master device.

[0096] The first receiving module receives the first frame and determines whether the first frame is in error.

[0097] (1) When the first frame is not in error, the first receiving module generates an ACK signal containing the sequence number of the first frame, sends the ACK signal to the first control module; the first deframing module deframes the first frame into write address channel information based on the same frame structure, and sends the write address channel information to the second AXI master device; the second AXI master device sends the write address channel information to the second AXI slave device based on a handshaking mechanism with the second AXI slave device.

[0098] (2) When the first frame is in error, the first receiving module generates a first NACK signal containing the sequence number of the first frame, sends the first NACK signal to the first control module, and closes the data receiving function. When the second predetermined time arrives, the first receiving module resumes the data receiving function.

[0099] When the first control module receives the first NACK signal, it waits for the first predetermined time, and then sends all the frames stored in the first storage module starting from the sequence number of the first frame to the first sending module, so that the first sending module sends all the frames stored in the first storage module starting from the sequence number of the first frame to the receiving end, where the first predetermined time is greater than the second predetermined time.

[0100] When the first control module does not receive any ACK signal, any NACK signal, or the retransmission times of a certain frame exceed the predetermined number threshold within the predetermined time threshold, the first alarm module issues an alarm message.

[0101] Based on a similar framing and deframing method, the first AXI master device can also actively send write data associated with the write address channel information to the second AXI slave device.

[0102] The second AXI slave device sends a response message of the written data to the second AXI master device based on the handshaking mechanism with the second AXI master device. The second AXI master device sends the response message to the second set of frame modules. The second set of frame modules frame the response message into a frame based on the same frame structure. The second control module sends the frame formed by framing the response message to the second transmission module and stores the frame formed by framing the response message in the second storage module.

[0103] The second transmission module sends the frame formed by framing the response message. The second receiving module receives the frame formed by framing the response message and determines whether the frame formed by framing the response message is in error.

[0104] (1) When the frame formed by framing the response message is not in error, the second receiving module generates an ACK signal containing the sequence number of the frame formed by framing the response message, and sends the ACK signal to the second control module; the second deframing module deframes the frame formed by framing the response message into response information based on the same frame structure, and sends the response information to the first AXI slave device; the first AXI slave device sends the response message to the first AXI master device based on the handshaking mechanism with the first AXI master device.

[0105] (2) When the frame formed by framing the response message is in error, the second receiving module generates a second NACK signal containing the sequence number of the frame formed by framing the response message, sends the second NACK signal to the second control module, and closes the data receiving function. When the second predetermined time arrives, the second receiving module turns on the data receiving function again.

[0106] After receiving the second NACK signal, the second control module waits for the first predetermined time, and then sends all the frames stored in the second storage module starting from the sequence number of the frame formed by framing the response message to the second transmission module, so that the second transmission module sends all these frames to the receiving end, where the first predetermined time is greater than the second predetermined time.

[0107] (2): The third AXI master device in the second chip can actively initiate a communication process with the fourth AXI slave device in the first chip.

[0108] Example: The third AXI master device sends second AXI channel information to the third AXI master device based on the handshaking mechanism with the third AXI slave device. Here, the second AXI channel information is specifically taken as the read address channel information for illustration.

[0109] The second set of frame modules frame the read address channel information into a second frame based on a predetermined frame structure. The second control module sends the second frame to the second transmission module and stores the second frame in the second storage module. The second transmission module sends the second frame using a signal line, where the bit width of the signal line of the second transmission module is less than the bit width of the signal line between the third AXI slave device and the third AXI master device.

[0110] The second receiving module receives the second frame and determines whether the second frame is in error.

[0111] (1) When the second frame is not in error, the second receiving module generates an ACK signal containing the sequence number of the second frame, and sends the ACK signal to the second control module; the second deframing module deframes the second frame into read address channel information based on the same frame structure, and sends the read address channel information to the fourth AXI master device; the fourth AXI master device sends the read address channel information to the fourth AXI slave device based on the handshaking mechanism with the fourth AXI slave device.

[0112] (2) When the second frame is in error, the second receiving module generates a second NACK signal containing the sequence number of the second frame, sends the second NACK signal to the second control module, and closes the data receiving function. When the second predetermined time arrives, the second receiving module turns on the data receiving function again.

[0113] After receiving the second NACK signal, the second control module waits for the first predetermined time, and then sends all the frames stored in the second storage module starting from the sequence number of the second frame to the second sending module, so that the second sending module sends all the frames stored in the second storage module starting from the sequence number of the second frame to the second receiving module, where the first predetermined time is greater than the second predetermined time.

[0114] When the second control module does not receive any ACK signal or any NACK signal within a predetermined time threshold, or the retransmission times of a certain frame exceed a predetermined number threshold, the second warning module issues a warning message.

[0115] The fourth AXI slave device sends read data associated with the read address channel information to the fourth AXI master device based on the handshaking mechanism with the fourth AXI master device. The fourth AXI master device sends the read data to the first group of frame modules. The first group of frame modules frame the read data into frames based on the same frame structure. The first control module sends the frames framed from the read data to the first sending module, and stores the frames framed from the read data in the first storage module.

[0116] The first sending module sends the frames framed from the read data. The first receiving module receives the frames framed from the read data and determines whether the frames framed from the read data are in error.

[0117] (1) When the frame formed by framing the read data has no error, the first receiving module generates an ACK signal containing the sequence number of the frame formed by framing the read data, and sends the ACK signal to the first control module; the first deframing module deframes the frame formed by framing the read data into read data based on the same frame structure, and sends the read data to the third AXI slave device; the third AXI slave device sends the read data to the third AXI master device based on the handshaking mechanism with the third AXI master device.

[0118] (2) When the frame formed by framing the read data has an error, the first receiving module generates a first NACK signal containing the sequence number of the frame formed by framing the read data, sends the first NACK signal to the first control module, and closes the data receiving function. When the second predetermined time arrives, the first receiving module turns on the data receiving function again.

[0119] After receiving a NACK signal, the first control module waits for the first predetermined time, and then sends all the frames stored in the first storage module starting from the sequence number of the frame formed by framing the read data to the first sending module, so that the first sending module sends all the frames to the receiving end, where the first predetermined time is greater than the second predetermined time.

[0120] An embodiment of the present invention also proposes an AXI interconnection method. Figure 6 It is a schematic diagram of the AXI interconnection method according to the embodiment of the present invention. Figure 6 The method shown can be executed by a processor. For example, the processor can be implemented as any one of a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), an accelerated processing unit (APU), and a general-purpose graphics processing unit (GPGPU). As Figure 6 shown, the method includes: Step 601: Receive the first AXI channel information from the first AXI master device based on the handshaking mechanism with the first AXI master device.

[0121] Step 602: Frame the first AXI channel information into a first frame based on a predetermined frame structure.

[0122] Step 603: Send the first frame to the receiving end and store the first frame in the storage module. The first frame is detected at the receiving end and, after successful detection, is deframed into the first AXI channel information based on the frame structure. When the receiving end detects an error in the first frame, the first frame is retrieved from the storage module and the first frame retrieved from the storage module is resent to the receiving end.

[0123] In one embodiment, the method includes: when a NACK signal containing the sequence number of the first frame is received from the receiving end, determining that the receiving end detects an error in the first frame and stopping receiving AXI channel information from the first AXI master.

[0124] In one embodiment, the method includes: when a NACK signal is received from the receiving end, waiting for a first predetermined time and sending all the frames stored in the storage module starting from the sequence number to the receiving end. The receiving end turns off the data receiving function when sending the negative acknowledgment signal and turns on the data receiving function after a second predetermined time, where the first predetermined time is greater than the second predetermined time.

[0125] In summary, in the embodiments of the present invention, when data is in error, retransmission is implemented for the erroneous data, realizing the retransmission mechanism in AXI interconnection, which can improve data accuracy, thereby improving the correct rate and precision of signal communication. In addition, the embodiments of the present invention can accurately control the turning off and on of the data receiving function at the receiving end, the stopping and resuming of the first AXI slave receiving AXI channel information from the first AXI master, and the first predetermined time and the second predetermined time, which can ensure that the data frames received at the receiving end are not repeated or omitted, improving the integrity of the data.

[0126] Moreover, in the embodiments of the present invention, the first AXI master and the second AXI slave are not directly interconnected. Instead, based on the AXI interconnection device between the first AXI master and the second AXI slave, information interaction between the first AXI master and the second AXI slave is realized in a frame-forming and deframing manner. The bit width of the signal line for sending the first frame can be adjusted as needed, which is beneficial to reducing the number of signal lines and can significantly reduce the chip pin area during interconnection.

[0127] The embodiments of the present invention also propose an electronic device having a processor-memory architecture. Figure 7 It is a structural diagram of the electronic device according to the embodiments of the present invention. As Figure 7As shown, the electronic device includes a processor 701, a memory 702, and a computer program stored in the memory 702 and executable on the processor 701. When the computer program is executed by the processor 701, it implements any of the above AXI interconnection methods. Among them, the memory 702 can be specifically implemented as various storage media such as electrically erasable programmable read-only memory (EEPROM), flash memory, programmable read-only memory (PROM), etc. The processor 701 can be implemented as including one or more central processing units or one or more field programmable gate arrays, where the field programmable gate array integrates one or more central processing unit cores. Specifically, the central processing unit or central processing unit core can be implemented as a CPU, GPU, GPGPU, MCU, or DSP, and so on.

[0128] It should be noted that not all steps and modules in the above processes and structure diagrams are necessary, and some steps or modules can be ignored according to actual needs. The execution order of each step is not fixed and can be adjusted according to needs. The division of each module is only for the convenience of description and is a functional division. In actual implementation, one module can be implemented by multiple modules, and the functions of multiple modules can also be implemented by the same module. These modules can be located in the same device or in different devices.

[0129] The hardware modules in each implementation manner can be implemented mechanically or electronically. For example, a hardware module can include a specially designed permanent module or logic device (such as a dedicated processor, such as an FPGA or ASIC) for completing specific operations. For example, specific operations can be completed in various types of chips (such as artificial intelligence chips). A hardware module can also include a programmable logic device or module (such as including a general-purpose processor or other programmable processors) temporarily configured by software for performing specific operations. As for whether to specifically implement the hardware module in a mechanical manner, or using a dedicated permanent module, or using a temporarily configured module (such as configured by software), it can be determined according to cost and time considerations.

[0130] The present invention also provides a machine-readable storage medium storing instructions for causing a machine to execute the method as described in this application. Specifically, a system or device equipped with the storage medium can be provided, on which software program codes for implementing the functions of any one of the above-described embodiments are stored, and the computer (or CPU or MPU) of the system or device is caused to read and execute the program codes stored in the storage medium. In addition, based on the instructions of the program codes, an operating system operating on the computer, etc. can be caused to complete part or all of the actual operations. The program codes read from the storage medium can also be written to the memory provided in the expansion board inserted into the computer or to the memory provided in the expansion unit connected to the computer, and then based on the instructions of the program codes, the CPU, etc. installed on the expansion board or the expansion unit can be caused to execute part and all of the actual operations, thereby implementing the functions of any one of the above-described embodiments. Embodiments of the storage medium for providing the program codes include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Optionally, the program codes can be downloaded from a server computer or the cloud via a communication network.

[0131] In this document, "schematic" means "serving as an example, instance, or illustration", and any illustration or embodiment described as "schematic" in this document should not be construed as a more preferred or more advantageous technical solution. To make the drawings concise, only the parts related to the present invention are schematically shown in each drawing, and do not represent the actual structure of the product. Additionally, to make the drawings concise and easy to understand, in some drawings, for components having the same structure or function, only one of them is schematically shown, or only one of them is labeled. In this document, "a" does not mean that the quantity of the relevant part of the present invention is limited to "only one", and "a" does not exclude the case where the quantity of the relevant part of the present invention is "more than one". In this document, "up", "down", "front", "back", "left", "right", "inside", "outside", etc. are only used to represent the relative positional relationship between the relevant parts, rather than to limit the absolute positions of these relevant parts.

[0132] The above are only the preferred embodiments of the present invention, and are not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An AXI interconnect device, characterized in that, Connected between the first AXI master device and the receiving end, the AXI interconnect device includes: A first AXI slave device, configured to receive first AXI channel information from the first AXI master device based on a handshake mechanism with the first AXI master device; A framing module, configured to frame the first AXI channel information into a first frame based on a predetermined frame structure; The device further includes a control module, a sending module, and a storage module, wherein: The control module is configured to send the first frame to the sending module and store the first frame in the storage module; The sending module is configured to send the first frame to the receiving end, wherein the first frame is detected at the receiving end and, after successful detection, is deframed into the first AXI channel information based on the frame structure; The control module is further configured to, when the receiving end detects an error in the first frame, obtain the first frame from the storage module and send the first frame obtained from the storage module to the sending module, so that the sending module re-sends the first frame obtained from the storage module to the receiving end.

2. The device according to claim 1, characterized in that, The control module is configured to schedule the first frame based on a predetermined scheduling method before sending the first frame to the sending module, wherein the scheduling method includes at least one of the following: First-come, first-served scheduling method; Priority scheduling method; Shortest job first scheduling method; Round-robin scheduling method; Highest response ratio next scheduling method; Fair scheduling method; Hybrid scheduling method based on priority and time slice.

3. The device according to claim 2, characterized in that, The control module is configured to, when receiving a negative acknowledgment signal containing the sequence number of the first frame from the receiving end, determine that the receiving end detects an error in the first frame and control the first AXI slave device to stop receiving AXI channel information from the first AXI master device.

4. The device according to claim 3, characterized in that, Including: An alarm module, configured to send an alarm message when the control module does not receive an acknowledgment signal or the negative acknowledgment signal from the receiving end within a predetermined time threshold, or the number of retransmissions of the first frame exceeds a predetermined number threshold.

5. The device according to claim 3, characterized in that, The control module is configured to, when receiving the negative acknowledgment signal from the receiving end, send all the frames stored in the storage module starting from the sequence number to the sending module, so that the sending module sends all the frames to the receiving end.

6. The device according to claim 5, characterized in that, The control module is configured to, when the sending module finishes sending all the frames to the receiving end and does not receive a negative acknowledgment signal containing at least one sequence number of all the frames from the receiving end, control the first AXI slave device to resume receiving AXI channel information from the first AXI master device.

7. The device according to claim 5, characterized in that, The control module is configured to wait for a first predetermined time when receiving the negative acknowledgment signal from the receiving end, and send all frames stored in the storage module starting from the sequence number to the sending module, where the receiving end closes the data receiving function when sending the negative acknowledgment signal and enables the data receiving function after a second predetermined time, and the first predetermined time is greater than the second predetermined time.

8. The device according to any one of claims 1-7, characterized in that, It includes a receiving module and a deframing module, where: The receiving module is configured to receive a second frame from a sending end, where the second frame is generated by the sending end based on the frame structure to frame the second AXI channel information; when detecting that the second frame is in error, not send the second frame to the deframing module, generate a negative acknowledgment signal including the sequence number of the second frame, and send the negative acknowledgment signal to the sending end for the sending end to re-send the second frame based on the negative acknowledgment signal; when detecting that the second frame is correct, send the second frame to the deframing module; The deframing module is configured to deframe the second frame into the second AXI channel information based on the frame structure.

9. An AXI interconnect system, characterized in that, It includes a first chip and a second chip; The first chip includes a first AXI master, a first AXI slave, a first framing module, a first control module, a first storage module, and a first sending module; The second chip includes a first receiving module, a first deframing module, a second AXI master, and a second AXI slave; Wherein the first AXI slave is configured to receive first AXI channel information from the first AXI master based on a handshaking mechanism with the first AXI master; the first framing module is configured to frame the first AXI channel information into a first frame based on a predetermined frame structure; The first control module is configured to send the first frame to the first sending module and store the first frame in the first storage module; The first sending module is configured to send the first frame; The first receiving module is configured to receive the first frame, and when detecting that the first frame is in error, send a first negative acknowledgment signal including the sequence number of the first frame to the first control module, and when detecting that the first frame is correct, send the first frame to the first deframing module; The first deframing module is configured to deframe the first frame into the first AXI channel information based on the frame structure and send the first AXI channel information to the second AXI master; the second AXI master is configured to send the first AXI channel information to the second AXI slave based on a handshaking mechanism with the second AXI slave; The first control module is further configured to, when receiving the first negative acknowledgment signal, obtain the first frame from the first storage module and send the first frame obtained from the first storage module to the first sending module for the first sending module to re-send the first frame obtained from the first storage module.

10. The system according to claim 9, characterized in that, The second chip includes a third AXI master device, a third AXI slave device, a second set of framing modules, a second control module, a second storage module, and a second transmission module; The first chip includes a second receiving module, a second deframing module, a fourth AXI master device, and a fourth AXI slave device; Wherein the third AXI slave device is configured to receive second AXI channel information from the third AXI master device based on a handshaking mechanism with the third AXI master device; the second set of framing modules is configured to frame the second AXI channel information into a second frame based on the frame structure; The second control module is configured to send the second frame to the second transmission module and store the second frame in the second storage module; The second transmission module is configured to transmit the second frame; The second receiving module is configured to receive the second frame. When it detects that the second frame is in error, it sends a second negative acknowledgment signal containing the sequence number of the second frame to the second control module. When it detects that the second frame is correct, it sends the second frame to the second deframing module; the second deframing module is configured to deframe the second frame into the second AXI channel information based on the frame structure and send the second AXI channel information to the fourth AXI master device; the fourth AXI master device is configured to send the second AXI channel information to the fourth AXI slave device based on a handshaking mechanism with the fourth AXI slave device; The second control module is further configured to, when receiving the second negative acknowledgment signal, obtain the second frame from the second storage module and send the second frame obtained from the second storage module to the second transmission module for the second transmission module to retransmit the second frame obtained from the second storage module.

11. A AXI interconnection method, characterized in that, Includes: Receiving first AXI channel information from the first AXI master device based on a handshaking mechanism with the first AXI master device; Framing the first AXI channel information into a first frame based on a predetermined frame structure; Sending the first frame to a receiving end and storing the first frame in a storage module, where the first frame is detected at the receiving end and, after successful detection, is deframed into the first AXI channel information based on the frame structure; wherein when the receiving end detects that the first frame is in error, it obtains the first frame from the storage module and retransmits the first frame obtained from the storage module to the receiving end.

12. The method according to claim 11, characterized in that, Includes: When receiving a negative acknowledgment signal containing the sequence number of the first frame from the receiving end, determining that the receiving end detects that the first frame is in error and stopping receiving AXI channel information from the first AXI master device.

13. The method according to claim 12, characterized in that, Includes: When receiving the negative acknowledgment signal from the receiving end, waiting for a first predetermined time and sending all frames stored in the storage module starting from the sequence number to the receiving end, where the receiving end closes the data receiving function when sending the negative acknowledgment signal and opens the data receiving function after a second predetermined time, and the first predetermined time is greater than the second predetermined time.

14. An electronic device, characterized in that, Includes: A memory; A processor; The memory stores an application program executable by the processor, for causing the processor to execute the AXI interconnect method according to any one of claims 11-13.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-readable instructions, which, when executed by a processor, cause the processor to execute the AXI interconnect method according to any one of claims 11-13.

16. A program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the AXI interconnect method according to any one of claims 11-13.

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