Semiconductor structure and preparation method thereof, storage array and electronic equipment

Abstract

The invention relates to a semiconductor structure and a preparation method thereof, a storage array and electronic equipment. The semiconductor structure comprises a substrate, a plurality of bit lines which are arranged in parallel at intervals, a plurality of word lines which are arranged in parallel at intervals and a plurality of active columns, a plurality of bit lines which are arranged in parallel at intervals are located in the substrate, and each bit line extends along a first direction; the plurality of word lines which are arranged in parallel at intervals are positioned above the bit lines; each word line extends along a second direction, and the second direction is obliquely crossed with the first direction; the plurality of active columns are positioned above the bit lines and are arranged at intervals along the first direction and the second direction; the plurality of active columns which are arranged at intervals along the first direction are positioned on the same bit line; and the plurality of active columns which are arranged at intervals along the second direction are sequentially connected in series by each word line. According to the invention, closer arrangement can be realized, so that the unit area of the structure is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design and manufacturing, and particularly to a semiconductor structure, a preparation method thereof, a memory array and an electronic device. Background Art

[0002] As an important device in the field of integrated circuits, a memory is mainly used in electronic products such as computers and mobile phones to store data. The memory usually adopts a 1T1C structure, that is, a structure in which a select transistor is connected to a storage capacitor. In a memory array, the read and write operations of a single memory cell are performed through bit lines and word lines. The size of the memory cell is mainly determined by the pitch of the bit lines and the pitch of the word lines.

[0003] With the continuous reduction of the memory manufacturing process, the cell area of the memory also decreases accordingly. In the layout of a traditional memory array, the extending directions of the bit lines and the word lines are perpendicular to each other, and the transistor and the storage capacitor are vertically connected, that is, the memory cells in the memory array are arranged in a square shape. However, the square-arranged memory cells are not the most compact arrangement. Therefore, there is still a large room for development in the technical miniaturization of memory cells. Summary of the Invention

[0004] Based on this, the present disclosure provides a semiconductor structure, a preparation method thereof, a memory array and an electronic device, which can achieve a more compact arrangement to reduce the cell area of the structure.

[0005] To solve the above technical problems, according to some embodiments, one aspect of the present disclosure provides a semiconductor structure, which includes a substrate, a plurality of bit lines arranged in parallel at intervals, a plurality of word lines arranged in parallel at intervals, and a plurality of active pillars; the plurality of bit lines arranged in parallel at intervals are located in the substrate, and each bit line extends along a first direction; the plurality of word lines arranged in parallel at intervals are located above the bit lines; each word line extends along a second direction, and the second direction is obliquely intersecting with the first direction; the plurality of active pillars are located above the bit lines and are arranged at intervals along the first direction and the second direction; and the plurality of active pillars arranged at intervals along the first direction are located on the same bit line; each word line serially connects the plurality of active pillars arranged at intervals along the second direction in sequence.

[0006] In some embodiments, the included angle between the first direction and the second direction is 45° to 75°.

[0007] In some embodiments, the active pillar includes a channel region, a first connection end, and a second connection end; the word line surrounds the channel region; the first connection end is located between the channel region and the bit line and is in contact with both the channel region and the bit line; the second connection end is located above the channel region and is in contact with the channel region.

[0008] In some embodiments, multiple active columns are arranged in a multi-row and multi-column array; multiple active columns in the same column are arranged at intervals in a first direction, and their geometric centers are all on a straight line; multiple active columns in the same row are arranged at intervals in a second direction, and their geometric centers are all on a straight line; multiple active columns in the same column are on the same bit line; each word line serially connects multiple active columns in the same row in sequence.

[0009] In some embodiments, multiple active columns are arranged in a multi-row and multi-column staggered arrangement. Multiple active columns in the same column are arranged at intervals in a first direction, and their geometric centers are offset in a second direction. Multiple active columns in the same row are arranged at intervals in a second direction, and their geometric centers are offset in a first direction; multiple active columns in the same column are on the same bit line; each word line serially connects multiple active columns in the same row in sequence.

[0010] In some embodiments, the substrate may include a base and a well layer located on the base. The base is a P-type base, and the well layer is a P-type well layer.

[0011] In some embodiments, the semiconductor structure further includes multiple storage node structures and multiple capacitor structures; the multiple storage node structures are provided in one-to-one correspondence with the active columns and are located on the upper surface of the second connection end; the multiple capacitor structures are provided in one-to-one correspondence with the storage node structures and are located on the upper surface of the storage node structures.

[0012] According to some embodiments, another aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method including:

[0013] Providing a substrate;

[0014] Forming multiple parallel and spaced bit lines in the substrate, and forming multiple active columns and multiple parallel and spaced word lines on the substrate; wherein, the bit lines extend in a first direction; the word lines are located above the bit lines, and each word line extends in a second direction, and the second direction is obliquely intersecting with the first direction; the multiple active columns are located above the bit lines and are arranged at intervals in both the first direction and the second direction; and the multiple active columns arranged at intervals in the first direction are on the same bit line; each word line serially connects multiple active columns arranged at intervals in the second direction in sequence.

[0015] In some embodiments, the included angle between the first direction and the second direction includes 45° to 75°.

[0016] In some embodiments, forming multiple parallel and spaced bit lines in the substrate includes:

[0017] Forming an epitaxial layer on the upper surface of the substrate;

[0018] Etch the epitaxial layer to form a plurality of first trenches, the first trenches extending in a first direction; the plurality of first trenches isolate the epitaxial layer into a plurality of active strips arranged in parallel and spaced apart;

[0019] Form a first protective layer on the sidewalls of the active strips;

[0020] Etch the substrate based on the first protective layer to form bit line trenches in the substrate, the bit line trenches being located directly below the active strips and extending in the first direction;

[0021] Form bit lines in the bit line trenches.

[0022] In some embodiments, before forming a plurality of bit lines arranged in parallel and spaced apart in the substrate, the method further includes:

[0023] Etch the substrate to form sacrificial trenches extending in a second direction in the substrate;

[0024] Form a sacrificial dielectric layer filling the sacrificial trenches.

[0025] In some embodiments, after forming an epitaxial layer on the upper surface of the substrate and before etching the substrate to form sacrificial trenches extending in the second direction, the method further includes:

[0026] Successively form a stacked silicon oxide layer, a silicon nitride layer, and an amorphous carbon layer on the epitaxial layer;

[0027] Successively form a stacked bottom anti-reflection layer and a photoresist layer on the amorphous carbon layer, and a first pattern exposing the silicon oxide layer is formed in the photoresist layer and the bottom anti-reflection layer;

[0028] Etch the amorphous carbon layer based on the first pattern to transfer the first pattern into the amorphous carbon layer;

[0029] Remove the bottom anti-reflection layer and the photoresist layer, and form a first sidewall on the sidewalls of the amorphous carbon layer;

[0030] Remove the amorphous carbon layer.

[0031] In some embodiments, after forming a silicon oxide layer on the epitaxial layer, the method further includes:

[0032] Treat the obtained structure by an ion implantation process to dope the obtained structure with doping impurities and form a heavily doped region;

[0033] Treat the obtained structure by a rapid thermal annealing process to activate the doping impurities.

[0034] In some embodiments, forming an epitaxial layer on the upper surface of the substrate includes: forming a doped N-type epitaxial layer on the upper surface of the substrate.

[0035] In some embodiments, an epitaxial layer is formed on the upper surface of a substrate, including: forming an N-type epitaxial layer on the doped upper surface of the substrate.

[0036] In some embodiments, forming a plurality of active pillars on a substrate includes:

[0037] Forming a first sacrificial layer in a first trench, the first sacrificial layer filling the first trench;

[0038] Etching the first sacrificial layer and the active strip to form a second trench, the second trench extending in a second direction; the second trench and the first trench divide the active strip into a plurality of active pillars; the active pillars include a first connection end, a channel region, and a second connection end that are integrally connected in sequence from bottom to top, and the first connection end is in contact with the bit line.

[0039] In some embodiments, forming a plurality of word lines arranged in parallel and spaced apart on a substrate includes:

[0040] Forming a bottom dielectric layer at the bottom of the second trench;

[0041] Forming an isolation dielectric layer and a second sacrificial layer in the second trench; both the isolation dielectric layer and the second sacrificial layer are located on the upper surface of the bottom dielectric layer, and the second sacrificial layer is located between the isolation dielectric layer and the channel region;

[0042] Forming a first covering dielectric layer in the second trench;

[0043] Removing the second sacrificial layer to form a word line gap, the word line gap exposing the channel region, the word line gap extending in the second direction;

[0044] Forming a word line in the word line gap, the word line covering the channel region.

[0045] In some embodiments, after forming a plurality of word lines arranged in parallel and spaced apart on a substrate, the method further includes:

[0046] Forming a second covering dielectric layer in the second trench, the second covering dielectric layer filling the second trench;

[0047] Forming a storage node structure on the upper surface of the second connection end, the storage node structures being arranged in one-to-one correspondence with the active pillars;

[0048] Forming a capacitor structure on the upper surface of each storage node structure, the capacitor structures being arranged in one-to-one correspondence with the storage node structures.

[0049] According to some embodiments, another aspect of the present disclosure provides a memory array, including the above semiconductor structure, and a plurality of differential amplifiers arranged at intervals; the plurality of differential amplifiers are all located between adjacent semiconductor structures, and each differential amplifier is shared by adjacent bit lines in the adjacent semiconductor structures.

[0050] According to some embodiments, another aspect of the present disclosure provides an electronic device including the above-described storage array.

[0051] The embodiments of the present disclosure have the following advantages:

[0052] In the embodiments of the present disclosure, each bit line extends along a first direction, and each word line extends along a second direction. The second direction is obliquely intersecting with the first direction, that is, the extending direction of the bit line is obliquely intersecting with the extending direction of the word line. Moreover, a plurality of active pillars are located above the bit lines and are arranged at intervals along both the first direction and the second direction; and the plurality of active pillars arranged at intervals along the first direction are located on the same bit line; each word line serially connects the plurality of active pillars arranged at intervals along the second direction in sequence. Thus, on the basis that the distance between adjacent active pillars remains unchanged, the pitch between adjacent bit lines can be reduced, and correspondingly, the pitch between adjacent word lines can also be reduced. That is to say, in the semiconductor structure of the embodiments of the present disclosure, the unit area surrounded by four adjacent active pillars can be reduced, which is beneficial to further miniaturization of the structure, thereby realizing a more closely arranged semiconductor structure.

[0053] Moreover, a plurality of differential amplifiers are all located between adjacent semiconductor structures, and each differential amplifier is shared by adjacent bit lines in adjacent semiconductor structures. By realizing a more closely arranged semiconductor structure, the noise between differential amplifiers can be reduced, thereby improving the performance and reliability of the storage array. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0055] Figure 1 A top view schematic diagram of a semiconductor structure in the related art;

[0056] Figure 2a A top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0057] Figure 2b A three-dimensional structure schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0058] Figure 3 A flowchart schematic diagram of a preparation method of a semiconductor structure provided in an embodiment of the present disclosure;

[0059] Figure 4Schematic three-dimensional structure diagram of the structure obtained in step S111 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0060] Figure 5 Schematic three-dimensional structure diagram of the structure obtained in step S112 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0061] Figure 6 Schematic three-dimensional structure diagram of the structure obtained in step S113 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0062] Figure 7 Schematic three-dimensional structure diagram of the structure obtained in step S114 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0063] Figure 8 Schematic three-dimensional structure diagram of the structure obtained in step S115 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0064] Figure 9 Schematic three-dimensional structure diagram of the structure obtained in step S116 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0065] Figure 10 Schematic three-dimensional structure diagram of the structure obtained in step S117 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0066] Figure 11 Schematic three-dimensional structure diagram of the structure obtained in step S118 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0067] Figure 12 Schematic three-dimensional structure diagram of the structure obtained in step S119 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0068] Figure 13 Schematic three-dimensional structure diagram of the structures obtained in steps S131 and S132 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0069] Figure 14 Schematic three-dimensional structure diagram of the structures obtained in steps S133 and S134 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0070] Figure 15 Schematic three-dimensional structure diagram of the structure obtained in step S135 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0071] Figure 16 Schematic three-dimensional structure diagram of the structure obtained by forming a hard mask stack in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0072] Figure 17 Schematic three-dimensional structure diagram of the structure obtained by patterning a hard mask stack in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0073] Figure 18 Schematic three-dimensional structure diagram of the structure obtained in step S212 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0074] Figure 19 Schematic three-dimensional structure diagram of the structure obtained in step S215 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0075] Figure 20 Schematic three-dimensional structure diagram of the structure obtained in steps S22 and S23 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0076] Figure 21 Schematic three-dimensional structure diagram of the structure obtained in steps S31 to S33 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0077] Figure 22 Schematic top view diagram of a memory array provided in an embodiment of the present disclosure.

[0078] Description of reference numerals:

[0079] 10. Substrate; 101. Substrate base; 102. Well layer; 11. Epitaxial layer; 12. Silicon oxide layer; 13. Silicon nitride layer; 14. Amorphous carbon layer; 15. Bottom anti-reflection layer; 16. Photoresist layer; 161. First pattern; 17. First sidewall; 18. Second sidewall; 181. Sidewall material layer; 19. Hard mask stack; 191. First hard mask layer; 192. Second hard mask layer; 20. Bit line; 21. First trench; 201. Second pattern; 30. Word line; 40. Active pillar; 41. Channel region; 411. First gate dielectric layer; 412. Second gate dielectric layer; 42. First connection end; 43. Second connection end; 401. Active strip; 402. Sacrificial trench; 403. Third sidewall; 51. Memory node structure; 52. Capacitor structure; 61. First isolation layer; 62. Second isolation layer; 63. Third isolation layer; 64. Sacrificial dielectric layer; 70. Differential amplifier. Detailed implementation manners

[0080] To facilitate the understanding of this application, the following will provide a more comprehensive description of this application with reference to the relevant accompanying drawings. The preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of this application more thorough and comprehensive.

[0081] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0082] The term "and / or" used herein includes any and all combinations of one or more of the related listed items. When using "including", "having", and "comprising" described herein, unless a clear limiting term is used, such as "only", "consisting of", etc., another component can also be added. Unless otherwise mentioned, the singular form of a term can include the plural form and should not be understood as having a quantity of one.

[0083] It should be understood that although terms such as "first" and "second" can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element.

[0084] In the description of this disclosure, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific situations.

[0085] Please refer to Figures 2a to 22 , it should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of this disclosure. Although only the components related to this disclosure are shown in the illustrations and are not drawn according to the number, shape, and size of the components in actual implementation, the types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0086] In the field of integrated circuit design and manufacturing technology, the common methods to increase device integration include reducing the feature size of semiconductor devices and improving the semiconductor cell structure. As the feature size of semiconductor devices decreases, tiny-sized transistors suffer from severe short-channel effects. Therefore, by improving the semiconductor cell topology, reducing the area occupied by semiconductor cells under the same feature size condition is another effective way to increase the integration of semiconductor devices.

[0087] As the memory manufacturing process continues to shrink, the cell area of the memory decreases from 8F 2 to 6F 2 and then to 4F 2 , where F (feature) represents the minimum feature unit. As Figure 1 described, taking 4F 2 as an example, the distance between bit lines is 2F, the distance between word lines is also 2F, the layout of the memory array is that the bit lines and word lines are perpendicular, the transistor and the storage capacitor are vertically connected, and the storage unit U is arranged in a square, that is, the area of the entire storage unit U is 4F 2 . However, the square-arranged storage unit is not the most compact layout, and there is still great room for the technological miniaturization of storage units.

[0088] The present disclosure aims to provide a semiconductor structure, a method for preparing the same, a memory array, and an electronic device, which can achieve a more compact arrangement to reduce the cell area of the structure.

[0089] According to some embodiments, a semiconductor structure is provided.

[0090] Exemplarily, the above semiconductor structure can be used to form a semiconductor device (such as a memory). The memory may include a transistor structure and a capacitor connected to the transistor structure. The capacitor is used to store data, and the transistor structure is used to read the data in the capacitor or write data into the capacitor. It can be understood that the semiconductor structure provided by the embodiments of the present application can be directly used as a memory structure or as a component of a memory structure. For example, it can be a memory array in a 1T1C structure, but not limited thereto. The semiconductor structure provided by the embodiments of the present application can also be used as other structures.

[0091] Please refer to Figure 2a, the semiconductor structure includes a substrate 10, a plurality of bit lines 20 arranged in parallel and spaced apart, a plurality of word lines 30 arranged in parallel and spaced apart, and a plurality of active pillars 40; the plurality of bit lines 20 arranged in parallel and spaced apart are located within the substrate 10, and each bit line 20 extends along a first direction; the plurality of word lines 30 arranged in parallel and spaced apart are located above the bit lines 20; each word line 30 extends along a second direction, and the second direction is obliquely intersecting with the first direction; the plurality of active pillars 20 are located above the bit lines and are arranged at intervals along both the first direction and the second direction; and the plurality of active pillars 20 arranged at intervals along the first direction are located on the same bit line 20; each word line 30 serially connects the plurality of active pillars 20 arranged at intervals along the second direction in sequence.

[0092] In the semiconductor structure of the above embodiment, each bit line 20 extends along the first direction, each word line 30 extends along the second direction, and the second direction is obliquely intersecting with the first direction, that is, the extending direction of the bit line 20 is obliquely intersecting with the extending direction of the word line 30. Moreover, the plurality of active pillars 20 are located above the bit lines and are arranged at intervals along both the first direction and the second direction; and the plurality of active pillars 20 arranged at intervals along the first direction are located on the same bit line 20; each word line 30 serially connects the plurality of active pillars 20 arranged at intervals along the second direction in sequence. Thus, on the basis that the distance between adjacent active pillars 40 remains unchanged, the pitch between adjacent bit lines 20 can be reduced, and correspondingly, the pitch between adjacent word lines 30 can also be reduced. That is to say, in the semiconductor structure of the embodiment of the present disclosure, the unit area surrounded by adjacent four active pillars 40 can be reduced, which is beneficial to the further miniaturization of the structure, thereby realizing a more closely arranged semiconductor structure. It should be noted that the first direction is Figure 2a the x direction shown, and the second direction is Figure 2a the y direction shown. The second direction being obliquely intersecting with the first direction can be understood as the second direction not being perpendicular to the first direction. Exemplarily, there is an included angle a between the second direction and the first direction, and the included angle a can be an acute angle.

[0093] Exemplarily, the distance between adjacent active pillars 40 can be 2F. On the premise that there is an included angle a between the second direction and the first direction, the pitch L between adjacent word lines 30 is 2F * sina, where F is the minimum feature size of the chip manufacturing process, that is, the area of the unit U surrounded by adjacent four active pillars 40 is 4F 2 * sina. Since the included angle a is an acute angle, that is, sina is less than 1, therefore, compared with the unit area 4F in the related art 2 , the area of the unit U in the embodiment of the present disclosure is 4F 2 * sina, which is obviously less than 4F 2 , thereby realizing the further miniaturization of the semiconductor structure and enabling the semiconductor structure to achieve a more compact arrangement.

[0094] In some embodiments, the included angle α between the first direction and the second direction includes 45° to 75°. For example, the included angle α can be 45°, 50°, 55°, 60°, 65°, 70°, or 75°, etc. Exemplarily, in an embodiment where the included angle α is 60°, the pitch L between adjacent word lines 30 is 2F * sinα = F, that is, the area of the unit U surrounded by four adjacent active pillars 40 is 4F 2 *sinα = 2F 2 , compared with the unit area 4F in the related art 2 , the area of the unit U in this embodiment is 2F 2 which is less than 4F 2 , thereby realizing further miniaturization of the semiconductor structure and enabling a more compact arrangement of the semiconductor structure.

[0095] In some embodiments, a plurality of active pillars 40 are arranged in a multi-row and multi-column array; the plurality of active pillars 40 in the same column are spaced along the first direction, and their geometric centers are all on a straight line; the plurality of active pillars 40 in the same row are spaced along the second direction, and their geometric centers are all on a straight line; the plurality of active pillars 40 in the same column are located on the same bit line 20; each word line 30 serially connects the plurality of active pillars 40 in the same row in sequence.

[0096] In some embodiments, a plurality of active pillars 40 are arranged in a multi-row and multi-column staggered arrangement. The plurality of active pillars 40 in the same column are spaced along the first direction, and their geometric centers are offset in the second direction. The plurality of active pillars 40 in the same row are spaced along the second direction, and their geometric centers are offset in the first direction; the plurality of active pillars 40 in the same column are located on the same bit line 20; each word line 30 serially connects the plurality of active pillars 40 in the same row in sequence. Please refer to Figure 2b , in some embodiments, the active pillar 40 includes a channel region 41, a first connection end 42, and a second connection end 43; the word line 30 surrounds the channel region 41; the first connection end 42 is located between the channel region 41 and the bit line 20 and is in contact with both the channel region 41 and the bit line 20; the second connection end 43 is located above the channel region 41 and is in contact with the channel region 41.

[0097] Exemplarily, the first connection end 42 can be a source electrode, and the second connection end 43 can be a drain electrode, or the first connection end 42 can be a drain electrode, and the second connection end 43 can be a source electrode.

[0098] Exemplarily, a part of the word line 30 surrounding the channel region 41 can be used as a gate, and the gate and the active column 40 can be used to jointly form a transistor. For example, it can be used as a select transistor in a memory. It can be understood that the word line 30 surrounding the channel region 41 can form a gate-all-around (GAA) structure, thereby increasing the contact area between the gate and the active column 40 to improve the gate control ability. Moreover, the GAA structure is also beneficial to saving the structural size to further increase the distribution density of the semiconductor structure, thereby further increasing the storage density of the device.

[0099] In some embodiments, the substrate 10 may include a substrate 101 and a well layer 102 located on the substrate 101; exemplarily, the substrate 101 is a P-type substrate 101, and the well layer 102 is a P-type well layer 102.

[0100] In some embodiments, the semiconductor structure further includes a plurality of storage node structures 51 and a plurality of capacitor structures 52; the plurality of storage node structures 51 are arranged in one-to-one correspondence with the active columns 40 and are located on the upper surface of the second connection end 43; the plurality of capacitor structures 52 are arranged in one-to-one correspondence with the storage node structures 51 and are located on the upper surface of the storage node structures 51.

[0101] It can be understood that since the storage node structures 51 are arranged in one-to-one correspondence with the active columns 40, and the capacitor structures 52 are arranged in one-to-one correspondence with the storage node structures 51, on the basis that the unit area surrounded by four adjacent active columns 40 is reduced, the arrangement of the capacitor structures 52 and the storage nodes is also closer, which is beneficial to further miniaturization of the structure.

[0102] This application also provides a method for manufacturing a semiconductor structure according to some embodiments, which is used to manufacture the semiconductor structure provided in the above embodiments. Therefore, the beneficial effects possessed by the above semiconductor structure are also possessed by this manufacturing method.

[0103] Please refer to Figure 3 , in some embodiments, the method for manufacturing a semiconductor structure may include the following steps:

[0104] Step S10: Provide a substrate;

[0105] Step S20: Form a plurality of bit lines arranged in parallel and spaced apart in the substrate, and form a plurality of active columns and a plurality of word lines arranged in parallel and spaced apart on the substrate; wherein, the bit lines extend along a first direction; the word lines are located above the bit lines, and each word line extends along a second direction, and the second direction is obliquely intersecting with the first direction; the plurality of active columns are located above the bit lines and are arranged at intervals along the first direction and the second direction; and the plurality of active columns arranged at intervals along the first direction are located on the same bit line; each word line sequentially connects the plurality of active columns arranged at intervals along the second direction.

[0106] In some embodiments, the included angle α between the first direction and the second direction includes 45° to 75°, so as to achieve further miniaturization of the semiconductor structure, enabling the semiconductor structure to achieve a more compact arrangement.

[0107] In some embodiments, step S20 includes:

[0108] Step S21: Form a plurality of bit lines arranged in parallel and spaced apart in the substrate, and the bit lines extend along the first direction;

[0109] Step S22: Form a plurality of active pillars on the substrate, and the plurality of active pillars are arranged in multiple rows and columns; the active pillars are located above the bit lines; and a plurality of active pillars in the same column are located on the same bit line;

[0110] Step S23: Form a plurality of word lines arranged in parallel and spaced apart on the substrate, the word lines are located above the bit lines, each word line extends along the second direction, and the second direction is obliquely intersecting with the first direction; each word line sequentially connects a plurality of active pillars in the same row.

[0111] In some embodiments, step S21, forming a plurality of bit lines arranged in parallel and spaced apart in the substrate, includes:

[0112] Step S211: Form an epitaxial layer on the upper surface of the substrate;

[0113] Step S212: Etch the epitaxial layer to form a plurality of first trenches, and the first trenches extend along the first direction; the plurality of first trenches isolate the epitaxial layer into a plurality of active strips arranged in parallel and spaced apart;

[0114] Step S213: Form a first protective layer on the side walls of the active strips;

[0115] Step S214: Etch the substrate based on the first protective layer to form bit line trenches in the substrate, and the bit line trenches are located directly below the active strips and extend along the first direction;

[0116] Step S215: Form bit lines in the bit line trenches.

[0117] In some embodiments, step S211, forming an epitaxial layer on the upper surface of the substrate, includes:

[0118] Step S2111: Form a doped N-type epitaxial layer on the upper surface of the substrate.

[0119] In some embodiments, step S211, forming an epitaxial layer on the upper surface of the substrate, includes:

[0120] Step S2112: Dope the upper surface of the substrate to form an N-type epitaxial layer.

[0121] In some embodiments, step S22, forming a plurality of active pillars on the substrate, includes:

[0122] Step S221: Form a first sacrificial layer in the first trench, and the first sacrificial layer fills the first trench.

[0123] Step S222: Etch the first sacrificial layer and the active strip to form a second trench, and the second trench extends along a second direction; the second trench and the first trench divide the active strip into multiple active columns; the active column includes a first connection end, a channel region, and a second connection end that are integrally connected in sequence from bottom to top, and the first connection end is in contact with the bit line.

[0124] In some embodiments, in step S23, forming a plurality of word lines arranged in parallel and spaced apart on the substrate includes:

[0125] Step S231: Form a bottom dielectric layer at the bottom of the second trench.

[0126] Step S232: Form an isolation dielectric layer and a second sacrificial layer in the second trench; both the isolation dielectric layer and the second sacrificial layer are located on the upper surface of the bottom dielectric layer, and the second sacrificial layer is located between the isolation dielectric layer and the channel region.

[0127] Step S233: Form a first capping dielectric layer in the second trench.

[0128] Step S234: Remove the second sacrificial layer to form a word line gap, and the word line gap exposes the channel region, and the word line gap extends along the second direction.

[0129] Step S235: Form a word line in the word line gap, and the word line covers the channel region.

[0130] In some embodiments, after forming a plurality of word lines arranged in parallel and spaced apart on the substrate, that is, after step S20, the method further includes:

[0131] Step S31: Form a second capping dielectric layer in the second trench, and the second capping dielectric layer fills the second trench.

[0132] Step S32: Form a storage node structure on the upper surface of the second connection end, and the storage node structures are arranged in one-to-one correspondence with the active columns.

[0133] Step S33: Form a capacitor structure on the upper surface of each storage node structure, and the capacitor structures are arranged in one-to-one correspondence with the storage node structures.

[0134] It should be understood that although Figure 3 each step in the flowchart is shown in sequence according to the indication of the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, Figure 3At least a part of the steps may include multiple steps or multiple stages, which do not necessarily need to be executed and completed at the same moment, but can be executed at different moments, and the execution order of these steps or stages does not necessarily need to be sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0135] To more clearly illustrate the method for preparing a storage unit provided in some of the above embodiments, please refer to the following in combination with Figures 4 to 21 to understand some embodiments of the present application.

[0136] The embodiments of the present application do not specifically limit the constituent material of the substrate 10. As an example, the substrate 10 can be composed of a semiconductor material, an insulating material, a conductor material, or any combination of their material types. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate 10, a silicon germanium (SiGe) substrate 10, a silicon germanium carbon (SiGeC) substrate 10, a silicon carbide (SiC) substrate 10, a gallium arsenide (GaAs) substrate 10, an indium arsenide (InAs) substrate 10, an indium phosphide (InP) substrate 10, or other III / V semiconductor substrates 10 or II / VI semiconductor substrates 10. Or, for another example, the substrate 10 can be a layered substrate 10 including a stack such as Si and SiGe, a stack of Si and SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0137] Please refer to Figures 4 to 15 , in step S10, the following steps can be included.

[0138] Step S11: As Figures 4 to 6 shown, provide the substrate 10 and form an epitaxial layer 11 on the substrate 10;

[0139] Step S12: As Figures 7 to 12 shown, etch the substrate 10 to form a sacrificial trench 402 extending in the second direction in the substrate 10;

[0140] Step S13: As Figures 13 to 15 shown, form a sacrificial dielectric layer 64 filled in the sacrificial trench 402.

[0141] Exemplarily, after forming the epitaxial layer 11 on the substrate 10 in step S11, a patterned mask stack structure can also be patterned on the epitaxial layer 11, and in step S12, a sacrificial trench 402 extending in the second direction can be formed in the substrate 10 based on the patterned mask stack structure. For example, a sacrificial trench 402 extending in the second direction can be formed in the substrate 10 based on the patterned mask stack structure by using a self-aligned dual imaging process, which can include the following steps:

[0142] Step S111: As shown in Figure 4 , provide a substrate 10, form an epitaxial layer 11 on the substrate 10, and then sequentially form a stacked silicon oxide layer 12, a silicon nitride layer 13, and an amorphous carbon layer 14 on the epitaxial layer 11;

[0143] Exemplarily, in step S111, the substrate 10 may include a substrate 101 and a well layer 102 located on the substrate 101. Among them, the substrate 101 may be a P-type substrate 101. Correspondingly, the well layer 102 located on the substrate 101 is a P-type well layer 102.

[0144] Exemplarily, in step S111, the silicon oxide layer 12 may be an oxide layer; after forming the epitaxial layer 11, a thermal oxidation process may be used to grow the oxide layer, and the thickness of the oxide layer is 4 nm - 6 nm. For example, the thickness of the oxide layer is 4 nm, 4.5 nm, 5 nm, 5.5 nm, or 6 nm, etc.

[0145] Furthermore, after forming the silicon oxide layer 12, an ion implantation process may also be used to process the obtained structure to dope impurities therein to form a heavily doped region, and then a rapid annealing process is used to process the obtained structure to activate the doped impurities. Exemplarily, the impurity element may be a P-type ion. For example, the P-type ion may include but is not limited to any one or more of boron ions, gallium ions, boron fluoride ions, and indium ions, etc.

[0146] Exemplarily, in step S111, the silicon nitride layer 13 may be a trisilicon tetranitride layer.

[0147] Step S112: As shown in Figure 5 , sequentially form a stacked bottom antireflection layer 15 and a photoresist layer 16 on the amorphous carbon layer 14, and perform exposure and development on the photoresist layer 16 to form a first pattern 161 exposing the silicon oxide layer 12 in the photoresist layer 16 and the bottom antireflection layer 15;

[0148] Exemplarily, in step S112, the bottom antireflection layer 15 is an organic antireflection layer or an inorganic antireflection layer. The bottom antireflection layer 15 is located between the photoresist layer 16 and the substrate 10, which can increase the lithography process window and improve the lithography line width control ability.

[0149] Step S113: As shown in Figure 6 , etch the amorphous carbon layer 14 based on the first pattern 161 in the bottom antireflection layer 15 and the photoresist layer 16 to transfer the first pattern 161 into the amorphous carbon layer 14;

[0150] It can be understood that in step S113, the amorphous carbon layer 14 can be used to form a mandrel in the SADP process to facilitate the subsequent execution of the SADP process.

[0151] Step S114: As Figure 7 shown, remove the bottom antireflection layer 15 and the photoresist layer 16; form a first sidewall 17 on the sidewalls of the amorphous carbon layer 14;

[0152] Here, since the first sidewall 17 is formed on the sidewalls of the amorphous carbon layer 14, that is, the density of the first sidewall 17 is twice that of the amorphous carbon layer 14, the first doubling of the density is achieved.

[0153] Exemplarily, in step S114, the first sidewall 17 can be formed on the sidewalls of the amorphous carbon layer 14 by chemical vapor deposition. The chemical vapor deposition process can include one or several of atmospheric-pressure chemical vapor deposition (APCVD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0154] For example, the first sidewall 17 can be formed on the sidewalls of the amorphous carbon layer 14 by atomic layer deposition (ALD). Since the atomic layer deposition process has excellent conformality and uniformity when depositing on three-dimensional complex surfaces, the thickness of the first sidewall 17 is relatively uniform.

[0155] Exemplarily, the material of the first sidewall 17 includes silicon carbonitride.

[0156] Exemplarily, in step S114, an ashing process can be adopted to remove the bottom antireflection layer 15 and the photoresist layer 16.

[0157] Further, after removing the bottom antireflection layer 15 and the photoresist layer 16 and before forming the first sidewall 17 on the sidewalls of the amorphous carbon layer 14, it can further include a step of cleaning the obtained structure. Cleaning the obtained structure can remove impurities on the surface of the obtained structure, avoid affecting subsequent processes, and thus ensure the performance of the device. Specifically, the obtained structure can be cleaned multiple times with a cleaning solution, and the obtained structure can be placed in a cleaning tank containing the cleaning solution for cleaning.

[0158] For example, during multiple cleanings of the obtained structure, the cleaning solution for the first cleaning may include a Piranha etch cleaning solution, which can be used to remove a large amount of organic residues on the surface of the obtained structure and can effectively remove photoresist and other difficult-to-remove organic materials. Exemplarily, the Piranha etch cleaning solution includes sulfuric acid and 30% concentration hydrogen peroxide, and the mixing ratio of the two can be 3:1, 4:1, or 7:1, etc. Since the mixture of sulfuric acid and 30% concentration hydrogen peroxide is a strong oxidant, it can not only remove most organic substances but also hydroxylate most surfaces, making them hydrophilic.

[0159] For example, during multiple cleanings of the obtained structure, the cleaning solution for the first cleaning can be an SC-1 cleaning solution, which is composed of ammonium hydroxide, hydrogen peroxide, and water. It can be understood that due to the action of hydrogen peroxide, a hydrophilic natural oxide film is formed on the surface of the obtained structure, enabling the cleaning solution to penetrate between the surface of the obtained structure and impurity particles. And because the natural oxide layer on the surface of the obtained structure and the impurity particles on the surface of the obtained structure are corroded by ammonium hydroxide, the particles attached to the surface of the obtained structure fall into the cleaning solution, thereby achieving the purpose of removing impurity particles.

[0160] It should be noted that the cleaning solution and cleaning process specifically used for cleaning the obtained structure are known to those skilled in the art and will not be elaborated here. It should be noted that after cleaning the obtained structure, a drying step for the obtained structure is also required, and the method for drying the obtained structure is well-known to those skilled in the art and will not be elaborated here.

[0161] Step S115: As Figure 8 shown, etch back the structure obtained in step S114 to remove the amorphous carbon layer 14.

[0162] Exemplarily, in step S115, isotropic selective etching can be used to remove the amorphous carbon layer 14. It can be understood that due to the geometric effect of the sidewalls of the amorphous carbon layer 14, the first sidewalls 17 deposited on both sides of it will remain and form the first sidewalls 17 (spacers) in the SADP process.

[0163] Exemplarily, after step S115, it may also include a step of cleaning the obtained structure with an SC-1 cleaning solution, which will not be elaborated here.

[0164] Step S116: As Figure 9 shown, form a conformal covering sidewall material layer 181 on the surface of the first sidewall 17;

[0165] Exemplarily, in step S116, a conformal sidewall material layer 181 can also be grown on the surface of the first sidewall 17 isotropically by a chemical vapor deposition process. For example, in step S116, an atomic layer deposition technique can also be used to form the sidewall material layer 181 to form a sidewall material layer 181 with a relatively uniform thickness.

[0166] Step S117: As Figure 10 shown, the structure obtained in step S116 is etched back to remove a part of the sidewall material layer 181, thereby forming a second sidewall 18, and the top surface of the second sidewall 18 is lower than the top surface of the first sidewall 17.

[0167] Here, since the second sidewall 18 is formed on the sidewall of the first sidewall 17, that is, the density of the second sidewall 18 is twice that of the first sidewall 17, thus realizing the second doubling of the density.

[0168] Exemplarily, this step can be carried out by anisotropic etching. Anisotropic etching can selectively etch materials in a preset crystal orientation or crystal plane direction, while leaving very little or almost no etching traces in other directions. Using anisotropic etching for etching back in this step can make the morphology of the obtained structure more precise and controllable.

[0169] Exemplarily, the material of the second sidewall 18 includes silicon oxide.

[0170] Exemplarily, after step S117, it can also include the step of cleaning the obtained structure with an SC-1 cleaning solution, which will not be elaborated here.

[0171] Step S118: As Figure 11 shown, the first sidewall 17 is removed, the silicon nitride layer 13 is etched based on the second sidewall 18, and the silicon oxide layer 12 is exposed;

[0172] Step S119: As Figure 12 shown, based on the silicon nitride layer 13, the silicon oxide layer 12, the epitaxial layer 11 and the well layer 102 are etched in sequence to form a sacrificial trench 402 extending in the second direction, and the second sidewall 18 is removed;

[0173] Exemplarily, after step S119, an anisotropic etching process can be used to etch the silicon oxide layer 12, the epitaxial layer 11 and the well layer 102 in sequence; among them, etching the silicon oxide layer 12, the epitaxial layer 11 and the well layer 102 can be based on a one-time etching process or a step-by-step etching process.

[0174] Exemplarily, after step S119, it can also include the step of cleaning the obtained structure with a Piranha etching cleaning solution, a diluted hydrofluoric acid solution, an SC-1 cleaning solution or an SC-2 cleaning solution, which will not be elaborated here.

[0175] It should be noted that the SC-2 cleaning solution can be composed of hydrogen chloride, hydrogen peroxide, and water, and can be used for cleaning metal contamination on the surface of silicon wafers.

[0176] As Figures 13 to 15 shown, in some embodiments, step S13 of forming the sacrificial dielectric layer 64 filled in the sacrificial trench 402 may include the following steps.

[0177] Step S131: As Figure 13 shown, form a first isolation layer 61 on the sidewall of the sacrificial trench 402; deposit and form a second isolation layer 62 and a third isolation layer 63 on the surface of the first isolation layer 61 away from the substrate, the third isolation layer 63 is located between the second isolation layer 62 and the first isolation layer 61, and the top surfaces of both the second isolation layer 62 and the third isolation layer 63 are flush with the top surface of the well layer 102;

[0178] In some embodiments, in combination with Figure 12 and 13 for understanding, in step S131, it may include the following steps.

[0179] Step S1311: Use atomic layer deposition technology to form a conformal coverage first isolation material layer (not shown) on the sidewall of the sacrificial trench 402 and the top surface of the silicon nitride layer 13;

[0180] Exemplarily, the material of the first isolation material layer includes ethyl silicate doped with impurities. For example, the first isolation material layer can be one or more of P-type ion-doped ethyl silicate, silicon oxynitride, and silicon oxide, where the P-type ions can include but are not limited to any one or more of boron ions, gallium ions, boron fluoride ions, and indium ions, etc.

[0181] Step S1312: Use atomic layer deposition technology to form a third isolation material layer (not shown) on the surface of the first isolation material layer away from the substrate 10;

[0182] Exemplarily, the third isolation material layer can be a single-layer structure or a multi-layer structure. For example, the multi-layer third isolation material layer can include a stacked structure of a silicon oxynitride layer, a silicon oxide layer, and a silicon oxynitride layer.

[0183] Step S1313: Use chemical deposition technology to form a second isolation material layer (not shown) in the sacrificial trench 402, the second isolation material layer fills the sacrificial trench 402, and the second isolation material layer covers the top surface of the second isolation material layer;

[0184] Exemplarily, the second isolation material layer includes an ethyl silicate layer. For example, the second isolation material layer is an undoped ethyl silicate layer.

[0185] Step S1314: Recess the structure obtained in step S1313 using a planarization process until the top surface of the silicon nitride layer 13 is exposed, remove the silicon nitride layer 13 using hot phosphoric acid cleaning, and clean the obtained structure using SC-1 cleaning solution;

[0186] Step S1315: Recess the structure obtained in step S1314 to remove the silicon oxide layer 12 and part of the first isolation material layer and the third isolation material layer until the top surface of the epitaxial layer 11 is exposed; the remaining first isolation material layer forms the first isolation layer 61;

[0187] Step S1315: Remove part of the second isolation material layer and the third isolation material layer until the top surfaces of the remaining second isolation material layer and the remaining third isolation material layer are flush with the top surface of the well layer 102. The remaining second isolation material layer forms the second isolation layer 62, and the remaining third isolation material layer forms the third isolation layer 63;

[0188] Exemplarily, a selective etching process with a high selectivity ratio can be used to remove part of the second isolation material layer and the third isolation material layer.

[0189] Step S132: Process the structure obtained in step S131 using a high-temperature rapid annealing process, so that the impurity ions in the first isolation layer 61 diffuse into the well layer 102 to increase the doping concentration, enhance the isolation effect, and avoid leakage.

[0190] Step S133: As Figure 14 shown, form a first gate dielectric layer 411, which covers the surface exposed by the sacrificial trench 402 and is located on the exposed outer surface of the first isolation layer 61 and the top surface of the epitaxial layer 11;

[0191] Exemplarily, in step S133, the first gate dielectric layer 411 can be a silicon oxide layer, and the first gate dielectric layer 411 can be grown using a thermal oxidation process;

[0192] Exemplarily, the thickness of the first gate dielectric layer 411 can be 2nm - 4nm, for example, the thickness of the oxide layer can be 2nm, 2.5nm, 3nm, 3.5nm, or 4nm, etc.

[0193] Step S134: As Figure 14 shown, use an ion implantation process to implant impurity ions into the structure obtained in step S133. The implantation angle has a preset included angle with the second direction, and then use a rapid annealing process to activate the impurity ions.

[0194] Exemplarily, in step S134, the impurity ions can be N-type impurity ions. For example, the N-type impurity ions can include, but are not limited to, any one or more of phosphorus ions, arsenic ions, and antimony ions, etc.

[0195] Exemplarily, the range of the preset included angle is 5° - 10°. For example, the preset included angle can be 5°, 6°, 7°, 8°, 9° or 10°, etc.

[0196] Step S135: As Figure 15 shown, a sacrificial dielectric layer 64 is formed in the sacrificial trench 402, and the top surface of the sacrificial dielectric layer 64 is higher than the top surface of the first gate dielectric layer 411;

[0197] Exemplarily, the material of the sacrificial dielectric layer 64 is amorphous silicon.

[0198] As Figures 15 to 19 , in some embodiments, in step S21, a plurality of bit lines 20 arranged in parallel and spaced apart are formed in the substrate 10, including:

[0199] Step S211: An epitaxial layer 11 is formed on the upper surface of the substrate 10;

[0200] It should be noted that in the embodiment of performing step S111, the epitaxial layer 11 formed on the upper surface of the substrate 10 in step S211 can be understood as the same epitaxial layer 11 formed in step S111, and those skilled in the art can select the formation step of the epitaxial layer 11 according to the actual application situation.

[0201] In some embodiments, in step S211, an epitaxial layer 11 is formed on the upper surface of the substrate 10, including:

[0202] Step S2111: A doped N-type epitaxial layer 11 is formed on the upper surface of the substrate 10.

[0203] In some embodiments, in step S211, an epitaxial layer 11 is formed on the upper surface of the substrate 10, including:

[0204] Step S2112: The upper surface of the substrate 10 is doped to form an N-type epitaxial layer 11.

[0205] In some embodiments, as Figure 15 shown, after step S211, a hard mask stack 19 can also be formed on the top surface of the sacrificial dielectric layer 64; Exemplarily, the hard mask stack 19 can include a stacked first hard mask layer 191 and a second hard mask layer 192;

[0206] Exemplarily, the material of the first hard mask layer 191 is silicon carbonitride, and the material of the second hard mask layer 192 is amorphous carbon;

[0207] Exemplarily, as Figures 15 to 17 shown, after forming the hard mask stack 19 on the top surface of the sacrificial dielectric layer 64, it further includes patterning the hard mask stack 19 to form a second pattern 201, and forming a third sidewall 403, and removing the second hard mask layer 192;

[0208] Exemplarily, the material of the third sidewall 403 is silicon nitride.

[0209] Step S212: As Figure 18 shown, etch the epitaxial layer 11 to form a plurality of first trenches 21, and the first trenches 21 extend along a first direction; the plurality of first trenches 21 isolate the epitaxial layer 11 into a plurality of active strips 401 arranged in parallel at intervals;

[0210] Exemplarily, in step S212, while etching the epitaxial layer 11, the sacrificial dielectric layer 64 and the first gate dielectric layer 411 are also etched synchronously, that is, the active strip 401 includes a part of the epitaxial layer 11, a part of the sacrificial dielectric layer 64, and a part of the first gate dielectric layer 411.

[0211] Exemplarily, in step S212, it may further include the steps of implanting impurity ions into the bottom of the active strip 401 by an ion implantation process and then activating the impurity ions by a rapid annealing process to facilitate subsequent ohmic contact. Exemplarily, the impurity ions may be N-type impurity ions. For example, the N-type impurity ions may include, but are not limited to, any one or more of phosphorus ions, arsenic ions, and antimony ions, etc.

[0212] Step S213: Form a first protective layer (not shown) on the sidewall of the active strip 401;

[0213] Step S214: Etch the substrate 10 based on the first protective layer to form a bit line 20 trench (not shown) in the substrate 10. The bit line 20 trench is located directly below the active strip 401 and extends along the first direction;

[0214] Step S215: As Figure 19 shown, form a bit line 20 in the bit line 20 trench.

[0215] Exemplarily, in step S215, the constituent material of the bit line 20 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); the metal silicide includes tungsten silicide (WSi).

[0216] In some embodiments, step S22 of forming a plurality of active posts 40 on the substrate 10 includes:

[0217] Step S221: Form a first sacrificial layer (not shown) in the first trench 21, and the first sacrificial layer fills the first trench 21;

[0218] Step S222: Etch the first sacrificial layer and the active strip 401 to form a second trench (not shown), the second trench extending along the second direction; the second trench and the first trench 21 divide the active strip 401 into a plurality of active columns 40; the active column 40 includes a first connection end 42, a channel region 41, and a second connection end 43 that are integrally connected in sequence from bottom to top, and the first connection end 42 is in contact with the bit line 20.

[0219] Exemplarily, in step S222, the active strip 401 is etched, that is, the sacrificial dielectric layer 64 is removed.

[0220] In some embodiments, as Figure 20 shown, before step S23, there is also a step of forming a second gate dielectric layer 412 on the opposite sidewalls of the active column 40 along the second direction;

[0221] Exemplarily, the second gate dielectric layer 412 can be formed by an In Situ Stream Generation (ISSG) process. As a rapid thermal annealing process, ISSG can heat and cool the obtained structure in a relatively short time, with less required thermal budget and better temperature uniformity. In the ISSG process, usually a small amount of hydrogen is introduced into an oxygen atmosphere as a catalyst, and a combustion-like chemical reaction occurs on the surface of the obtained structure at high temperature. This reaction generates a large number of gas-phase active free radicals, mainly atomic oxygen, and these free radicals participate in the oxidation process of the obtained structure. Due to the strong oxidation of atomic oxygen, the finally obtained oxide film has fewer defects in the body, thereby improving the quality of the second gate dielectric layer 412. Additionally, the second gate dielectric layer 412 can also be formed by atomic layer deposition.

[0222] Exemplarily, the material of the second gate dielectric layer may include, but is not limited to, silicon oxides (such as silicon dioxide), silicon nitrides (silicon oxynitrides), nitrides (such as silicon nitride), metal oxides (such as Al2O3), metal oxynitrides (such as AlON), metal silicides, high-k dielectric materials (dielectric constant greater than 3.9), low-k dielectric materials (dielectric constant greater than or equal to 2.5 and less than 3.9), ultra-low-k dielectric materials (dielectric constant less than 2.5), ferroelectric materials, antiferroelectric materials, carbides (silicon carbide), or combinations thereof. Exemplarily, high-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3).

[0223] In some embodiments, as Figure 20As shown, before step S23, after forming the second gate dielectric layer 412, it may further include a step of forming a work function layer, which is located on the surface of the second gate dielectric layer 412 and can be used to adjust the work function, thereby improving the performance of the device.

[0224] Exemplarily, the work function layer may be a titanium nitride layer, and the work function layer can be formed by an atomic layer deposition process.

[0225] In some embodiments, as Figure 20 shown, step S23 of forming a plurality of word lines 30 arranged in parallel and spaced apart on the substrate 10 includes:

[0226] Step S231: Form a bottom dielectric layer (not shown) at the bottom of the second trench;

[0227] Step S232: Form an isolation dielectric layer and a second sacrificial layer (not shown) in the second trench; both the isolation dielectric layer and the second sacrificial layer are located on the upper surface of the bottom dielectric layer, and the second sacrificial layer is located between the isolation dielectric layer and the channel region 41;

[0228] Step S233: Form a first capping dielectric layer (not shown) in the second trench;

[0229] Step S234: Remove the second sacrificial layer to form a word line 30 gap (not shown), the word line 30 gap exposes the channel region 41, and the word line 30 gap extends along the second direction;

[0230] Step S235: Form a word line 30 in the word line 30 gap, and the word line 30 covers the channel region 41.

[0231] Exemplarily, in step S235, the constituent material of the word line 30 includes but is not limited to one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal can be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); the metal silicide includes tungsten silicide (WSi).

[0232] In some embodiments, as Figure 21 shown, after forming a plurality of word lines 30 arranged in parallel and spaced apart on the substrate 10, that is, after step S20, the method further includes:

[0233] Step S31: Form a second capping dielectric layer (not shown) in the second trench, and the second capping dielectric layer fills the second trench;

[0234] Step S32: A storage node structure 51 is formed on the upper surface of the second connection end 43, and the storage node structures 51 are arranged in one-to-one correspondence with the active columns 40;

[0235] Exemplarily, the material of the storage node structure 51 can be highly doped polysilicon, so as to reduce the contact resistance of the storage node structure 51.

[0236] Step S33: A capacitor structure 52 is formed on the upper surface of each storage node structure 51, and the capacitor structures 52 are arranged in one-to-one correspondence with the storage node structures 51.

[0237] Please refer to Figure 22 , in some embodiments, a storage array is provided, including the above semiconductor structure, including the above semiconductor structure, and a plurality of differential amplifiers 70 arranged at intervals; the plurality of differential amplifiers 70 are all located between adjacent semiconductor structures, and each differential amplifier 70 is shared by adjacent bit lines 20 in adjacent semiconductor structures.

[0238] In the storage array of the above embodiment, the plurality of differential amplifiers 70 are all located between adjacent semiconductor structures, and each differential amplifier 70 is shared by adjacent bit lines 20 in adjacent semiconductor structures. By implementing more closely arranged semiconductor structures, the noise between the differential amplifiers 70 can be reduced, thereby improving the performance and reliability of the storage array.

[0239] In some embodiments, an electronic device is provided, including the above storage array. Since a storage array with better performance and reliability is adopted, therefore, the electronic device of this embodiment has more beneficial performance and higher reliability.

[0240] Please note that the above embodiments are for illustrative purposes only and do not imply a limitation on the present disclosure.

[0241] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0242] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0243] The above embodiments merely represent several implementation manners of the present disclosure. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the disclosed patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all fall within the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; Multiple bit lines arranged in parallel at intervals, located within the substrate, and each of the bit lines extends along a first direction; Multiple word lines arranged in parallel at intervals, located above the bit lines; each of the word lines extends along a second direction, and the second direction intersects obliquely with the first direction; Multiple active pillars, the active pillars are located above the bit lines, and are arranged at intervals along both the first direction and the second direction; and multiple active pillars arranged at intervals along the first direction are located on the same bit line; each word line sequentially connects multiple active pillars arranged at intervals along the second direction.

2. The semiconductor structure according to claim 1, characterized in that, The included angle between the first direction and the second direction is 45° to 75°.

3. The semiconductor structure according to claim 1, characterized in that, The active pillar comprises: A channel region, and the word line surrounds the channel region; A first connection end, located between the channel region and the bit line, and in contact with both the channel region and the bit line; A second connection end, located above the channel region, and in contact with the channel region.

4. The semiconductor structure according to claim 1, characterized in that, Multiple active pillars are arranged in a multi-row and multi-column array; multiple active pillars in the same column are arranged at intervals along the first direction, and their geometric centers are all on a straight line; multiple active pillars in the same row are arranged at intervals along the second direction, and their geometric centers are all on a straight line; Multiple active pillars in the same column are located on the same bit line; each word line sequentially connects multiple active pillars in the same row.

5. The semiconductor structure according to claim 1, characterized in that, The multiple active pillars are arranged in a multi-row and multi-column staggered arrangement, multiple active pillars in the same column are arranged at intervals along the first direction, and their geometric centers are offset in the second direction, multiple active pillars in the same row are arranged at intervals along the second direction, and their geometric centers are offset in the first direction; Multiple active pillars in the same column are located on the same bit line; each word line sequentially connects multiple active pillars in the same row.

6. The semiconductor structure according to claim 1, characterized in that, The substrate may include a substrate base and a well layer located on the substrate base, the substrate base is a P-type substrate, and the well layer is a P-type well layer.

7. The semiconductor structure according to any one of claims 1 to 3, characterized in that, Further comprising: Multiple storage node structures, arranged in one-to-one correspondence with the active pillars, and located on the upper surface of the second connection end; Multiple capacitor structures, arranged in one-to-one correspondence with the storage node structures, and located on the upper surface of the storage node structures.

8. A method for manufacturing a semiconductor structure, characterized in that, The method comprises: Providing a substrate; Forming multiple bit lines arranged in parallel at intervals within the substrate, and forming multiple active pillars and multiple word lines arranged in parallel at intervals on the substrate; wherein, the bit lines extend along a first direction; the word lines are located above the bit lines, each of the word lines extends along a second direction, and the second direction intersects obliquely with the first direction; multiple active pillars are located above the bit lines, and are arranged at intervals along both the first direction and the second direction; and multiple active pillars arranged at intervals along the first direction are located on the same bit line; each word line sequentially connects multiple active pillars arranged at intervals along the second direction.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, The included angle between the first direction and the second direction is 45° to 75°.

10. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, Forming multiple bit lines arranged in parallel at intervals within the substrate, comprising: Form an epitaxial layer on the upper surface of the substrate; Etch the epitaxial layer to form a plurality of first trenches, the first trenches extending along the first direction; the plurality of first trenches isolate the epitaxial layer into a plurality of active strips arranged in parallel at intervals; Form a first protective layer on the sidewalls of the active strips; Etch the substrate based on the first protective layer to form bit line trenches in the substrate, the bit line trenches being located directly below the active strips and extending along the first direction; Form the bit lines in the bit line trenches.

11. The method for preparing a semiconductor structure according to claim 10, wherein, Before forming a plurality of bit lines arranged in parallel at intervals in the substrate, further include: Etch the substrate to form sacrificial trenches extending along the second direction in the substrate; Form a sacrificial dielectric layer filled in the sacrificial trenches.

12. The method for preparing a semiconductor structure according to claim 11, wherein, After forming an epitaxial layer on the upper surface of the substrate and before etching the substrate to form sacrificial trenches extending along the second direction in the substrate, further include: Form a stacked silicon oxide layer, silicon nitride layer, and amorphous carbon layer on the epitaxial layer in sequence; Form a stacked bottom anti-reflection layer and photoresist layer on the amorphous carbon layer, a first pattern exposing the silicon oxide layer being formed in the photoresist layer and the bottom anti-reflection layer; Etch the amorphous carbon layer based on the first pattern to transfer the first pattern into the amorphous carbon layer; Remove the bottom anti-reflection layer and the photoresist layer, and form a first sidewall on the sidewalls of the amorphous carbon layer; Remove the amorphous carbon layer.

13. The method for preparing a semiconductor structure according to claim 12, wherein, After forming the silicon oxide layer on the epitaxial layer, further include: Treat the obtained structure by an ion implantation process so that the obtained structure is doped with doping impurities and a heavily doped region is formed; Treat the obtained structure by a rapid annealing process to activate the doping impurities.

14. The method for preparing a semiconductor structure according to claim 10, wherein, Forming an epitaxial layer on the upper surface of the substrate includes: Form a doped N-type epitaxial layer on the upper surface of the substrate.

15. The method for preparing a semiconductor structure according to claim 10, wherein, Forming an epitaxial layer on the upper surface of the substrate includes: Dope the upper surface of the substrate to form an N-type epitaxial layer.

16. The method for preparing a semiconductor structure according to claim 10, wherein, Forming a plurality of active pillars on the substrate includes: Form a first sacrificial layer in the first trenches, the first sacrificial layer filling the first trenches; Etch the first sacrificial layer and the active strips to form second trenches, the second trenches extending along the second direction; the second trenches and the first trenches divide the active strips into a plurality of the active pillars; the active pillars include a first connection end, a channel region, and a second connection end integrally connected in sequence from bottom to top, and the first connection end is in contact with the bit line.

17. The method for preparing a semiconductor structure according to claim 16, wherein, Forming a plurality of word lines arranged in parallel at intervals on the substrate includes: Form a bottom dielectric layer at the bottom of the second trenches; Form an isolation dielectric layer and a second sacrificial layer in the second trenches; both the isolation dielectric layer and the second sacrificial layer are located on the upper surface of the bottom dielectric layer, and the second sacrificial layer is located between the isolation dielectric layer and the channel region; Form a first covering dielectric layer in the second trenches; Remove the second sacrificial layer to form a word line gap, the word line gap exposing the channel region, the word line gap extending along the second direction; A word line is formed within the word line gap, and the word line covers the channel region.

18. The method for preparing a semiconductor structure according to claim 17, wherein, After forming a plurality of word lines arranged in parallel and spaced apart on the substrate, the method further includes: Forming a second covering dielectric layer in the second trench, and the second covering dielectric layer fills the second trench; Forming a storage node structure on the upper surface of the second connection end, and the storage node structures are arranged in one-to-one correspondence with the active columns; Forming a capacitor structure on the upper surface of each of the storage node structures, and the capacitor structures are arranged in one-to-one correspondence with the storage node structures.

19. A storage array, characterized in that, Comprising at least two semiconductor structures according to any one of claims 1-7, and a plurality of differential amplifiers arranged at intervals; A plurality of the differential amplifiers are all located between adjacent semiconductor structures, and each of the differential amplifiers is shared by adjacent bit lines in the adjacent semiconductor structures.

20. An electronic device, characterized in that, Comprising a memory array according to claim 19.

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