Semiconductor device

Abstract

A semiconductor device may include a substrate and an interconnect layer on the substrate. The interconnect layer may include an insulating layer, a conductive line, and a conductive contact, and the insulating layer may include an upper insulating layer on a lower insulating layer. The conductive contact may extend into a lower portion of the upper insulating layer and into the lower insulating layer, and the conductive line may be on the lower insulating layer and intersect the upper insulating layer. The upper insulating layer may include a low-k dielectric material.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0187396, filed with the Korean Intellectual Property Office on December 20, 2023, the entire contents of which are incorporated herein by reference. Technical field

[0003] The present disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including metal wires and a method of manufacturing the same. Background art

[0004] Due to the small size, multi - functionality, and / or low - cost characteristics of semiconductor devices, semiconductor devices are considered important components in the electronics industry. Semiconductor devices are classified into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices including both memory and logic elements.

[0005] Due to the recent increasing demand for electronic devices with fast and / or low power consumption, semiconductor devices may need to operate at a faster speed and / or a lower operating voltage. To meet this demand, it is necessary to increase the integration density of semiconductor devices. However, an increase in the integration density of semiconductor devices may lead to a deterioration in the reliability of semiconductor devices. In addition, with the highly developed electronics industry, the demand for highly reliable semiconductor devices has increased. Therefore, many studies are being conducted to achieve highly integrated and highly reliable semiconductor devices. Summary of the invention

[0006] Embodiments of the inventive concept provide a semiconductor device having improved electrical characteristics and a method of manufacturing the same.

[0007] According to some embodiments of the inventive concept, a semiconductor device may include a substrate and an interconnection layer on the substrate. The interconnection layer may include an insulating layer, a wire, and a conductive contact. The insulating layer may include an upper insulating layer on a lower insulating layer. The conductive contact may extend into a lower portion of the upper insulating layer and into the lower insulating layer, and the wire may be on the lower insulating layer and cross the upper insulating layer. The upper insulating layer may include a low - k dielectric material.

[0008] According to some embodiments of the inventive concept, a semiconductor device may include a substrate, a cell structure on the substrate, and an interconnection layer on the cell structure. The interconnection layer may include an insulating layer, a wire, and a conductive contact, and the insulating layer may include an upper insulating layer on a lower insulating layer. The conductive contact may include a first portion and a second portion on the first portion. The first portion may extend into the lower insulating layer, and the second portion may extend into a lower portion of the upper insulating layer. The first portion may have a first width in a first direction parallel to a top surface of the substrate, and the second portion may have a second width in the first direction. The first width may decrease as a distance to the top surface of the substrate decreases in a second direction perpendicular to the top surface of the substrate. The second width may be substantially constant in the second direction.

[0009] According to some embodiments of the inventive concept, a semiconductor device may include: a semiconductor substrate including a cell region and a peripheral region adjacent to the cell region, and including a cell active pattern on the cell region; a word line on the semiconductor substrate crossing the cell active pattern; a bit line on the semiconductor substrate crossing the word line; a storage node contact on an end of each cell active pattern; a landing pad on the storage node contact; a capacitor on the landing pad; and an interconnection layer on the capacitor. The interconnection layer may include an insulating layer, a plurality of conductive contacts, and a plurality of wires spaced apart from each other in a first direction parallel to a top surface of the semiconductor substrate. The insulating layer may include an upper insulating layer on a lower insulating layer. Each conductive contact extends into a lower portion of the upper insulating layer and extends into the lower insulating layer. A first wire of the plurality of wires extends into an upper portion of a first conductive contact of the plurality of conductive contacts. The upper insulating layer may include a first dielectric material, and the lower insulating layer may include a second dielectric material. A first dielectric constant of the first dielectric material may be less than a second dielectric constant of the second dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a plan view showing a cell structure of a semiconductor device according to some embodiments of the inventive concept.

[0011] Figure 2 is a cross-sectional view showing a semiconductor device according to some embodiments of the inventive concept.

[0012] Figure 3 is a view showing Figure 2 an enlarged cross-sectional view of a portion “CU1” of

[0013] Figure 4 is an enlarged cross-sectional view of a semiconductor device showing a portion “CU1” corresponding to a comparative example and Figure 2 of

[0014] Figure 5 , Figure 6A ,Figure 7A , Figure 8A and Figure 9A are cross-sectional views showing a process of manufacturing a semiconductor device according to some embodiments of the inventive concept.

[0015] Figure 6B , Figure 7B , Figure 8B and Figure 9B are views showing Figure 6A a partial “CU2” of Figure 7A a partial “CU3” of Figure 8A a partial “CU4” of Figure 9A and a partial “CU5” of DETAILED DESCRIPTION

[0016] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0017] Figure 1 is a plan view showing a cell structure of a semiconductor device according to some embodiments of the inventive concept. Figure 2 is a cross-sectional view showing a semiconductor device according to some embodiments of the inventive concept, specifically showing a cell region portion and a peripheral region taken along line A-A' of Figure 1 .

[0018] Referring to Figure 1 and Figure 2 , a substrate 100 including a cell region CR and a peripheral region PR may be provided. The substrate 100 may be a semiconductor substrate (e.g., a silicon substrate, a germanium substrate, or a silicon germanium substrate). A cell structure CS may be disposed on the cell region CR of the substrate 100, and a peripheral circuit may be disposed on the peripheral region PR of the substrate 100.

[0019] The cell structure CS may include a cell device isolation pattern 150C disposed in the cell region CR of the substrate 100. The cell device isolation pattern 150C may define a cell active pattern CACT. The cell active pattern CACT may be a portion of the substrate 100 protruding in a first direction D1.

[0020] In the present specification, the first direction D1 may be defined as a direction perpendicular to the top surface 100U of the substrate 100. The second direction D2 may be defined as a direction parallel to the top surface of the substrate. The third direction D3 may be defined as a direction parallel to the top surface of the substrate. The fourth direction D4 may be defined as a direction parallel to the top surface 100U of the substrate 100 and perpendicular to the third direction D3. The second direction D2 may be defined as a direction parallel to the top surface 100U of the substrate 100 and not parallel to the third direction D3 and the fourth direction D4.

[0021] Each of the unit active patterns CACT may be a strip pattern elongated in the second direction D2. The unit device isolation pattern 150C may be inserted between the unit active patterns CACT and may be formed of or include at least one of an oxide, a nitride, and / or a oxynitride.

[0022] The unit structure CS may include word lines WL provided on the unit region CR of the substrate 100. The word lines WL may be provided to cross the unit active patterns CACT and the unit device isolation pattern 150C. The word lines WL may extend in a third direction D3 and may be spaced apart from each other in a fourth direction D4. Each word line WL may include a unit gate electrode GE buried in the substrate 100, a unit gate dielectric pattern GI inserted between the unit gate electrode GE and the unit active pattern CACT and between the unit gate electrode GE and the unit device isolation pattern 150C, and a unit gate capping pattern CAP provided on the top surface of the unit gate electrode GE. The unit gate electrode GE may include a conductive material. In some embodiments, the conductive material may be one of a doped semiconductor material (e.g., doped silicon or doped germanium), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), a metal material (e.g., tungsten, titanium, or tantalum), and / or a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide). The unit gate dielectric pattern GI may include, for example, a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer. The unit gate capping pattern CAP may include, for example, a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer.

[0023] The unit structure CS may include a first impurity region SD1 and a second impurity region SD2 provided in each unit active pattern CACT. The second impurity regions SD2 may be spaced apart from each other with the first impurity region SD1 inserted therebetween. The first impurity region SD1 may be provided between a pair of word lines WL provided to cross the unit active pattern CACT. The second impurity regions SD2 may be spaced apart from each other with a pair of word lines WL inserted therebetween. The first impurity region SD1 may be doped to have the same conductivity type as the second impurity region SD2.

[0024] The cell structure CS may include an insulating layer 305 on a cell region CR of a substrate 100, a bit line BL on the insulating layer 305, and a bit line capping pattern 337 on the bit line BL. The insulating layer 305 may cover a word line and a cell active pattern CACT, overlap with the word line and the cell active pattern CACT, or be located on the word line WL and the cell active pattern CACT. The bit line BL may be disposed on the substrate 100 to cross or intersect with the word line WL. The bit line BL may be arranged to cross the word line WL. The bit line BL may extend in a fourth direction D4 and may be spaced apart from each other in a third direction D3. Each bit line BL may include a polysilicon pattern 330, an ohmic pattern 331, and a metal-containing pattern 332 sequentially stacked along a first direction D1. The bit line capping patterns 337 may be respectively disposed on the bit lines BL. The bit line capping pattern 337 may be formed of or include at least one of insulating materials (e.g., silicon nitride).

[0025] The cell structure CS may include a bit line contact DC disposed under each bit line BL. The bit line contact DC may be disposed under each bit line BL and may be spaced apart from each other in the fourth direction D4. Each of the bit line contacts DC may be electrically connected to a first impurity region SD1. The bit line contact DC may be formed of or include at least one of a doped semiconductor material (e.g., doped silicon and / or doped germanium), a conductive metal nitride (e.g., titanium nitride and / or tantalum nitride), a metal material (e.g., tungsten, titanium, and / or tantalum), or a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, and / or titanium silicide). The cell structure CS may include a lower insulating gap fill layer 341 disposed on side surfaces of each bit line contact DC.

[0026] The cell structure CS may include: a storage node contact BC disposed between a pair of adjacent bit lines BL; and a bit line spacer SP inserted between each bit line BL and the storage node contact BC. The storage node contact BC may be disposed on opposite ends of each cell active pattern CACT and may be spaced apart from each other in the fourth direction D4. The storage node contact BC may be formed of or include doped or undoped polysilicon. The bit line spacer SP may include a first sub-spacer 321 and a second sub-spacer 325 which are spaced apart from each other by an air gap AG. The first sub-spacer 321 may cover a side surface of each bit line BL and a side surface of each bit line capping pattern 337, overlap with the side surface of each bit line BL and the side surface of each bit line capping pattern 337, or be located on the side surface of each bit line BL and the side surface of each bit line capping pattern 337. The second sub-spacer 325 may be adjacent to the storage node contact BC. The first sub-spacer 321 and the second sub-spacer 325 may be formed of or include the same material (e.g., silicon nitride).

[0027] The cell structure CS may include a storage node ohmic layer 309 disposed on each storage node contact BC, a diffusion barrier pattern 311 disposed on the storage node ohmic layer 309, and a landing pad LP disposed on the diffusion barrier pattern 311. The storage node ohmic layer 309 may be formed of or include a metal silicide. The diffusion barrier pattern 311 may conformally cover the storage node ohmic layer 309, the first sub-spacer 321 and the second sub-spacer 325, and the bit line capping pattern 337, overlap with the storage node ohmic layer 309, the first sub-spacer 321 and the second sub-spacer 325, and the bit line capping pattern 337, or be located on the storage node ohmic layer 309, the first sub-spacer 321 and the second sub-spacer 325, and the bit line capping pattern 337. The diffusion barrier pattern 311 may be formed of or include at least one of metal nitrides (e.g., titanium nitride or tantalum nitride). The landing pad LP may be formed of or include a metal-containing material (e.g., tungsten). An upper portion of the landing pad LP may have a width greater than a width of the storage node contact BC. The upper portion of the landing pad LP may be offset from the storage node contact BC in a direction parallel to the top surface 100U of the substrate 100.

[0028] The cell structure CS may include a first capping pattern 358 and a second capping pattern 360 inserted between adjacent landing pads LP. Each of the first capping pattern 358 and the second capping pattern 360 may be formed of or include at least one of silicon nitride, silicon oxide, silicon oxynitride, and a porous material. The air gap AG between the first sub-spacer 321 and the second sub-spacer 325 may extend into the region between the landing pads LP. The first capping pattern 358, the bit line capping pattern 337, and the landing pads LP may be partially exposed through the air gap AG.

[0029] The cell structure CS may include a capacitor CA disposed on a cell region CR of a substrate 100. The capacitor CA may include a bottom electrode BE, a top electrode TE, and a dielectric layer DL inserted between each bottom electrode BE and the top electrode TE, respectively, where the top electrode TE covers, overlaps, or is on the bottom electrode BE. The bottom electrode BE may be formed of or include at least one of doped polysilicon, a metal nitride material (e.g., titanium nitride), or a metal material (e.g., tungsten, aluminum, and / or copper). Each bottom electrode BE may be shaped similar to a cylinder, a hollow cylinder, or a cup shape.

[0030] The cell structure CS may include an upper support pattern SS1 and a lower support pattern SS2 provided to support the bottom electrode BE. The upper support pattern SS1 may be provided to support an upper side surface of the bottom electrode BE, and the lower support pattern SS2 may be provided to support a lower side surface of the bottom electrode BE. The upper support pattern SS1 and the lower support pattern SS2 may be formed of or include at least one of insulating materials (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride). The cell structure CS may include an etch stop layer 370 disposed between the bottom electrodes BE to cover, overlap, or be on the first capping pattern 358 and the second capping pattern 360. The etch stop layer 370 may be formed of or include at least one of insulating materials (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride).

[0031] The dielectric layer DL may be provided to cover the surface of the bottom electrode BE and the surfaces of the upper support pattern SS1 and the lower support pattern SS2, overlap with the surface of the bottom electrode BE and the surfaces of the upper support pattern SS1 and the lower support pattern SS2, or be on the surface of the bottom electrode BE and the surfaces of the upper support pattern SS1 and the lower support pattern SS2. The top electrode TE may be disposed on the dielectric layer DL to fill the space between the bottom electrodes BE. The top electrode TE may be formed of or include at least one of doped polysilicon, doped silicon germanium, a metal nitride material (e.g., titanium nitride), or a metal material (e.g., tungsten, aluminum, and / or copper).

[0032] The first interconnect layer INC1, the second interconnect layer INC2, and the third interconnect layer INC3 may be sequentially stacked along the first direction D1 on the substrate 100 and the cell structure CS. The first interconnect layer INC1 may be the lowermost one of the interconnect layers INC1, INC2, and INC3, and the third interconnect layer INC3 may be the uppermost one of the interconnect layers INC1, INC2, and INC3. Figure 2 An example of providing three interconnect layers INC1, INC2, and INC3 is shown, but the inventive concept is not limited to this example. Additional interconnect layers may be provided between the lowermost interconnect layer (i.e., INC1) and the uppermost interconnect layer (i.e., INC3).

[0033] The first interconnect layer INC1 may include a first interconnect insulating layer IS1, a first conductive contact CT1, and a first wire CL1.

[0034] The first interconnect insulating layer IS1 may include a first lower insulating layer 400 and a first upper insulating layer 415, which are sequentially stacked along the first direction D1 on the cell region CR and the peripheral region PR.

[0035] Specifically, the first lower insulating layer 400 may be disposed on the cell region CR and the peripheral region PR of the substrate 100. The first lower insulating layer 400 may cover the cell structure CS of the cell region CR, overlap with the cell structure CS of the cell region CR, or be on the cell structure CS of the cell region CR, and may cover the peripheral region PR of the substrate (e.g., peripheral circuits), overlap with the peripheral region PR of the substrate, or be on the peripheral region PR of the substrate. The first lower insulating layer 400 may include a first dielectric material. The first dielectric material may be formed of or include silicon oxide (e.g., tetraethyl orthosilicate (TEOS; Si(OC2H5)4)).

[0036] The first upper insulating layer 415 may be disposed on the first lower insulating layer 400. The first upper insulating layer 415 may include a second dielectric material. The second dielectric material may include a low-k dielectric material having a higher etching rate and a lower dielectric constant than the first dielectric material in the first lower insulating layer 400. The second dielectric material in the first upper insulating layer 415 may have a dielectric constant of 3.5 or less. In some embodiments, the second dielectric material may be formed of or include at least one of SiCOH, SiOF, and polyimide.

[0037] Here, the first upper insulating layer 415 may include a first low-k dielectric layer 410 and a second low-k dielectric layer 420 sequentially stacked on the first lower insulating layer 400. The first low-k dielectric layer 410 may correspond to the lower portion of the first upper insulating layer 415. The second low-k dielectric layer 420 may correspond to the upper portion of the first upper insulating layer 415. The bottom surface of the first low-k dielectric layer 410 may contact the top surface of the first lower insulating layer 400. Different from the illustrated example, there may be no observable boundary between the first low-k dielectric layer 410 and the second low-k dielectric layer 420.

[0038] The first conductive contact CT1 may be disposed on the cell region CR and the peripheral region PR of the substrate 100. In some embodiments, a plurality of first conductive contacts CT1 may be arranged along the fourth direction D4. Specifically, at least one of the first conductive contacts CT1 may be provided to penetrate or extend into the first lower insulating layer 400 and the lower portion of the first upper insulating layer 415, and may be connected to the top electrode TE of the capacitor CA. Other first conductive contacts CT1 may be provided to penetrate or extend into the first lower insulating layer 400 and the lower portion of the first upper insulating layer 415, and may be electrically connected to the substrate 100 (e.g., peripheral circuit) on the peripheral region PR. Here, a part of the top surface of the first conductive contact CT1 may contact the bottom surface of the second low-k dielectric layer 420. Relative to the substrate, the level of the top surface of the first lower insulating layer 400 may be lower than the level of the top surface of the first conductive contact CT1. The first conductive contact CT1 may be formed of or include at least one of a metal material (e.g., copper, tungsten, and / or aluminum) and a conductive metal nitride material.

[0039] The first conductive line CL1 may be disposed on the first lower insulating layer 400. In some embodiments, a plurality of first conductive lines CL1 may be arranged in a fourth direction D4 to cross or intersect the first upper insulating layer 415. That is, the first upper insulating layer 415 may cover, overlap with, or be located on the side surface of each of the first conductive lines CL1. Specifically, at least one of the first conductive lines CL1 may be provided to penetrate or extend into the upper portion of the first upper insulating layer 415 and the first conductive contact CT1, and may be disposed on the first lower insulating layer 400. Other first conductive lines CL1 may be provided to penetrate or extend into the first upper insulating layer 415 and contact the top surface of the first lower insulating layer 400. The first conductive line CL1 may be formed of or include at least one of a metal material (e.g., copper, tungsten, and / or aluminum) and a conductive metal nitride material.

[0040] The second interconnect layer INC2 may be disposed on the first interconnect layer INC1. The second interconnect layer INC2 may include a second interconnect insulating layer IS2, a second conductive contact CT2, and a second conductive line CL2.

[0041] The second interconnect insulating layer IS2 may include a second lower insulating layer 430 and a second upper insulating layer 445, which are sequentially stacked on the cell region CR and the peripheral region PR in a first direction D1.

[0042] Specifically, the second lower insulating layer 430 may be disposed on the first upper insulating layer 415. The second lower insulating layer 430 may be formed of or include the same dielectric material as the first lower insulating layer 400 (e.g., the first dielectric material). In some embodiments, the first dielectric material may be formed of or include silicon oxide (e.g., tetraethyl orthosilicate (TEOS; Si(OC2H5)4)).

[0043] The second upper insulating layer 445 may be disposed on the second lower insulating layer 430. The second upper insulating layer 445 may include the same second dielectric material as the first upper insulating layer 415. The second dielectric material may include a low-k dielectric material having a higher etching rate and a lower dielectric constant than the first dielectric material in the second lower insulating layer 430. The second dielectric material in the second upper insulating layer 445 may have a dielectric constant of 3.5 or less. In some embodiments, the second dielectric material may be formed of or include at least one of SiCOH, SiOF, and polyimide.

[0044] Here, the second upper insulating layer 445 may include a third low-k dielectric layer 440 and a fourth low-k dielectric layer 450 that are sequentially stacked on the second lower insulating layer 430. The third low-k dielectric layer 440 may correspond to the lower portion of the second upper insulating layer 445. The fourth low-k dielectric layer 450 may correspond to the upper portion of the second upper insulating layer 445. The bottom surface of the third low-k dielectric layer 440 may contact the top surface of the second lower insulating layer 430.

[0045] The second conductive contact CT2 may be disposed on the first interconnect layer INC1. In some embodiments, a plurality of second conductive contacts CT2 may be arranged along the fourth direction D4. The second conductive contact CT2 may be provided to penetrate or extend into the second lower insulating layer 430 and the lower portion of the second upper insulating layer 445, and may be connected to a corresponding one of the first wires CL1. The second conductive contact CT2 may be formed of at least one of a metal material (e.g., copper, tungsten, and / or aluminum) and a conductive metal nitride material or include at least one of a metal material and a conductive metal nitride material.

[0046] The second wire CL2 may be disposed on the second lower insulating layer 430. In some embodiments, a plurality of second wires CL2 may be arranged along the fourth direction D4. Specifically, the second wire CL2 may be provided to penetrate or extend into the upper portion of the second upper insulating layer 445 and the second conductive contact CT2, and may be disposed on the second lower insulating layer 430. The second wire CL2 may be formed of at least one of a metal material (e.g., copper, tungsten, and / or aluminum) and a conductive metal nitride material or include at least one of a metal material and a conductive metal nitride material.

[0047] The third interconnect layer INC3 may be disposed on the second interconnect layer INC2. The third interconnect layer INC3 may include a third interconnect insulating layer IS3, a third conductive contact CT3, and a third wire CL3.

[0048] The third interconnect insulating layer IS3 may include a third lower insulating layer 470, a passivation layer 480, and a protective layer 490, which are disposed on the cell region CR and the peripheral region PR and sequentially stacked along the first direction D1.

[0049] Specifically, the third lower insulating layer 470 may be disposed on the second upper insulating layer 445. The third lower insulating layer 470 may be formed of silicon oxide or include silicon oxide. In some embodiments, the third lower insulating layer 470 may be formed of tetraethyl orthosilicate (TEOS; Si(OC2H5)4) or include the tetraethyl orthosilicate.

[0050] The passivation layer 480 may be disposed on the third lower insulating layer 470. The passivation layer 480 may be formed of or include a hydrogen-containing insulating material. The protective layer 490 may be disposed on the passivation layer 480. The protective layer 490 may be formed of or include, for example, silicon nitride.

[0051] The third conductive contact CT3 may be disposed on the second interconnecting layer INC2. In some embodiments, a plurality of third conductive contacts CT3 may be arranged along the fourth direction D4. The third conductive contact CT3 may be provided to penetrate or extend into the third lower insulating layer 470 and may be connected to a corresponding one of the second conductive lines CL2. The third conductive contact CT3 may be formed of or include at least one of a metal material (e.g., copper, tungsten, and / or aluminum) and a conductive metal nitride material.

[0052] The third conductive line CL3 may be disposed on the third lower insulating layer 470. The third conductive line CL3 may be arranged along the fourth direction D4 and may be disposed on the corresponding third conductive contact CT3. Here, the passivation layer 480 may cover, overlap with, or be located on the third conductive line CL3.

[0053] Each of the third conductive lines CL3 may include a metal compound pattern 481, a metal pattern 482, and a capping pattern 483 sequentially stacked along the first direction D1. The metal compound pattern 481 and the metal pattern 482 may be formed of or include the same metal material. The metal compound pattern 481 may be in contact with the bottom surface of the metal pattern 482. The capping pattern 483 may be in contact with the top surface of the metal pattern 482. The metal compound pattern 481 may be inserted between the capping pattern 483 and the metal pattern 482. In some embodiments, the metal compound pattern 481 and the metal pattern 482 may be formed of or include at least one of a metal material (e.g., copper, tungsten, and / or aluminum) and a conductive metal nitride material, and the capping pattern 483 may be formed of or include at least one of Ta, TaN, Ti, and TiN.

[0054] Figure 3 is a magnified cross-sectional view showing Figure 2 a portion “CU1” of

[0055] Referring to Figure 3, the first conductive contact CT1 may include a first portion P1 and a second portion P2 on the first portion P1. The first portion P1 may be the lower part of the first conductive contact CT1, which is provided to penetrate or extend into the first lower insulating layer 400. The second portion P2 may be the upper part of the first conductive contact CT1, which is provided to penetrate or extend into the lower part of the first upper insulating layer 415. That is to say, the second portion P2 may be the portion of the first conductive contact CT1 that penetrates the first low-k dielectric layer 410. The second portion P2 may be disposed on the first lower insulating layer 400.

[0056] The first portion P1 may have a first width W1 in the fourth direction D4. Here, referring to Figure 2 , the first portion P1 may have a tapered shape. For example, the first width W1 may decrease as the distance to the top surface 100U of the substrate 100 in the first direction D1 decreases. The second portion P2 may have a second width W2 in the fourth direction D4. The second width W2 may be constant and independent of the position in the first direction D1. In other words, the width of the first conductive contact CT1 in the fourth direction D4 may be substantially constant from the level of the bottom surface of the first wire CL1 to the level of the top surface of the first conductive contact CT1.

[0057] The first barrier metal BP1 may be disposed on the side surface and the bottom surface of the first conductive contact CT1. The first barrier metal BP1 may be disposed between the first conductive contact CT1 and the first lower insulating layer 400 and between the first conductive contact CT1 and the first upper insulating layer 415. The first barrier metal BP1 may be formed of at least one of titanium (Ti), titanium nitride (TiN), and tungsten (W) or include at least one of titanium (Ti), titanium nitride (TiN), and tungsten (W). The first barrier metal BP1 may prevent the metal material included in the first conductive contact CT1 from diffusing into the first lower insulating layer 400 and the first upper insulating layer 415.

[0058] The first wire CL1 may be provided to penetrate or extend into the first upper insulating layer 415. At least one of the first wires CL1 may be provided to penetrate or extend into a part of the second portion P2 of the first conductive contact CT1 and may be electrically connected to the first conductive contact CT1.

[0059] The first wire CL1 may have a third width W3 in the fourth direction D4. The third width W3 may be substantially constant from the bottom surface to the top surface of the first wire CL1. The first wire CL1 may have a first height H1 in the first direction D1. Here, the first low-k dielectric layer 410 may have a first thickness T1 in the first direction D1, and the first thickness T1 may be 10% to 20% of the first height H1.

[0060] The second barrier metal BP2 may be disposed on a side surface and a bottom surface of the first wire CL1. That is to say, the second barrier metal BP2 may be disposed between the first wire CL1 and the first upper insulating layer 415. The second barrier metal BP2 may be formed of at least one of titanium (Ti), titanium nitride (TiN), and tungsten (W) or may include at least one of titanium (Ti), titanium nitride (TiN), and tungsten (W). The second barrier metal BP2 may prevent the metal material included in the first wire CL1 from diffusing into the first upper insulating layer 415.

[0061] The first conductive contact CT1 may be spaced apart from the first wire CL1 that does not penetrate or extend into the first conductive contact CT1 by a first distance L1 in a fourth direction D4. In the present specification, the first distance L1 may be the shortest distance in the fourth direction D4 between the first conductive contact CT1 and the first wire CL1 that does not penetrate or extend into the first conductive contact CT1. The first distance L1 may be greater than or equal to 20% of the third width W3. In some embodiments, the first distance L1 may be 20% to 40% of the third width W3.

[0062] Although not shown in a similar Figure 3 magnified view, the second conductive contact CT2 and the second wire CL2 in the second interconnect layer INC2 may be provided to have shapes and relative positions that are substantially the same as the shapes and relative positions of the first conductive contact CT1 and the first wire CL1 described with reference to Figure 3 the description.

[0063] Figure 4 is a magnified cross-sectional view of a semiconductor device showing a portion “CU1” according to a comparative example and corresponding to Figure 2 . The elements previously described with reference to Figure 3 may be identified with the same reference numerals without repeating their overlapping descriptions.

[0064] With reference to Figure 4 , the first conductive contact CT1 may be provided to penetrate or extend into the first lower insulating layer 400. That is to say, the first conductive contact CT1 according to the comparative example may not penetrate or extend into the first upper insulating layer 415. Here, the first conductive contact CT1 may have a fourth width W4 in the fourth direction D4. Different from the first conductive contact CT1 described with reference to Figure 3 , both the upper and lower portions of the first conductive contact CT1 may have a tapered shape, and thus, the fourth width W4 may decrease as the distance to the top surface 100U of the substrate 100 in the first direction D1 decreases.

[0065] The first wire CL1 may include a third portion P3 and a fourth portion P4 on the third portion P3. The third portion P3 may be the lower part of the first wire CL1, which penetrates or extends into the first lower insulating layer 400. The fourth portion P4 may be the upper part of the first wire CL1 that penetrates the first upper insulating layer 415.

[0066] The third portion P3 may have a fifth width W5 in a fourth direction D4. The third portion P3 may have a tapered shape, and thus, the fifth width W5 may decrease as the distance along the first direction D1 to the top surface 100U of the substrate 100 decreases. The fourth portion P4 may have a sixth width W6 in the fourth direction D4. The sixth width W6 may be greater than the fifth width W5 and may be constant in the first direction D1.

[0067] The first conductive contact CT1 may be spaced apart from the first wire CL1 that does not penetrate or extend into the first conductive contact CT1 by a second distance L2 in the fourth direction D4. Since the overall shape of the first conductive contact CT1 is tapered, the second distance L2 may be shorter than the first distance L1 described with reference to Figure 3 The second distance L2 may be less than or equal to 10% of the sixth width W6.

[0068] Specifically, Figure 3 the upper part of the first conductive contact CT1 in the embodiment of

[0069] may have a shape with a constant width in the fourth direction D4 instead of a tapered shape. In contrast, the upper part of the first conductive contact CT1 in the comparative example may be arranged such that the width in the fourth direction D4 increases as the distance from the top surface 100U of the substrate 100 increases. Thus, compared with the embodiment of the inventive concept, the distance between the first conductive contact CT1 and the adjacent first wire CL1 may increase.

[0070] Conversely, in a semiconductor device according to some embodiments of the inventive concept, an upper portion of a conductive contact of an interconnection layer may have a constant width. Accordingly, compared to a semiconductor device according to a comparative example, the conductive contact may be spaced apart from a wire that does not penetrate or extend into the conductive contact by a large distance. Here, the upper portion of the conductive contact may penetrate or extend into an insulating layer having a low dielectric constant. Accordingly, an electrical short circuit problem between the conductive contact and the wire may be prevented or suppressed. In addition, since the distance between the conductive contact and the wire is increased, the number of conductive contacts may be increased and the integration density of the semiconductor device may be increased.

[0071] In addition, a lower width of a wire according to some embodiments of the inventive concept may be greater than a lower width of a wire according to a comparative example. This may enable an increase in a contact area between the wire and the conductive contact and a reduction in a resistance between the wire and the conductive contact.

[0072] Figure 5 , Figure 6A , Figure 7A , Figure 8A and Figure 9A are cross-sectional views illustrating a process of manufacturing a semiconductor device according to some embodiments of the inventive concept. Figure 6B , Figure 7B , Figure 8B and Figure 9B are Figure 6A partial “CU2” of Figure 7A partial “CU3” of Figure 8A partial “CU4” of Figure 9A and partial “CU5” of

[0073] Referring to Figure 5 , a substrate 100 may be prepared. Preparation of the substrate 100 may include: providing a substrate 100 including a cell region CR and a peripheral region PR, and forming a cell structure CS on the cell region CR of the substrate 100. As described above, the cell structure CS may include a bit line BL, a word line WL, and a capacitor CA.

[0074] Next, a first lower insulating layer 400 and a first initial low-k dielectric layer 410P may be formed on the substrate 100, and the first initial low-k dielectric layer 410P covers the first lower insulating layer 400, overlaps with the first lower insulating layer 400, or is located on the first lower insulating layer 400.

[0075] Referring to Figure 6A and Figure 6B, the first initial conductive contact CT1P may be formed to penetrate or extend into the first lower insulating layer 400 and the first initial low-k dielectric layer 410P. The first initial conductive contact CT1P may include: a vertical portion CT1a provided to penetrate or extend into the first lower insulating layer 400 and the first initial low-k dielectric layer 410P in a first direction D1; and a horizontal portion CT1b provided on the first initial low-k dielectric layer 410P and extending in a fourth direction D4.

[0076] Specifically, the formation of the first initial conductive contact CT1P may include: etching the first lower insulating layer 400 and the first initial low-k dielectric layer 410P to form a plurality of contact holes. The contact holes in the cell region may be formed to expose the top surface of the top electrode TE of the capacitor CA, and the contact holes in the peripheral region may be formed to expose the top surface 100U of the substrate 100. The formation of the first initial conductive contact CT1P may further include: forming a first barrier metal BP1 to cover the side surfaces and bottom surfaces of each contact hole and the top surface of the first initial low-k dielectric layer 410P, overlapping with the side surfaces and bottom surfaces of each contact hole and the top surface of the first initial low-k dielectric layer 410P, or located on the side surfaces and bottom surfaces of each contact hole and the top surface of the first initial low-k dielectric layer 410P; and depositing a metal material on the first barrier metal BP1 to partially or completely fill the unfilled space of the contact holes and cover the first initial low-k dielectric layer 410P, overlap with the first initial low-k dielectric layer 410P, or be located on the first initial low-k dielectric layer 410P.

[0077] Here, as described above with reference to Figure 2 the first initial low-k dielectric layer 410P has a higher etching rate than the first lower insulating layer 400, so the shape of the vertical portion CT1a in the first lower insulating layer 400 may be different from the shape of the vertical portion CT1a in the first initial low-k dielectric layer 410P. Specifically, the width of the vertical portion CT1a penetrating the first lower insulating layer 400 in the fourth direction D4 may decrease as the distance from the top surface 100U of the substrate 100 in the first direction D1 decreases. The width of the vertical portion CT1a penetrating the first initial low-k dielectric layer 410P in the fourth direction D4 may be substantially constant regardless of the position in the first direction D1.

[0078] Referring to Figure 7A and Figure 7B, a grinding process including a chemical mechanical polishing (CMP) process or a dry etching process can be performed on the first initial conductive contact CT1P and the first initial low-k dielectric layer 410P. As a result of the grinding process on the first initial conductive contact CT1P, the horizontal portion CT1b can be removed, leaving only a part of the vertical portion CT1a. In some embodiments, the grinding process can be performed to reduce the thickness of the first initial low-k dielectric layer 410P in the first direction D1. The remaining part of the vertical portion CT1a can form the first conductive contact CT1. The first initial low-k dielectric layer 410P thinned by the grinding process can form the first low-k dielectric layer 410.

[0079] Referring to Figure 8A and Figure 8B , the second low-k dielectric layer 420 can be formed on the first low-k dielectric layer 410 and the first conductive contact CT1. The second low-k dielectric layer 420 can cover the top surface of the first conductive contact CT1, overlap with the top surface of the first conductive contact CT1, or be located on the top surface of the first conductive contact CT1. The second low-k dielectric layer 420 can constitute the first upper insulating layer 415 or be included in the first upper insulating layer 415, and the first upper insulating layer 415 is formed on the first lower insulating layer 400.

[0080] Referring to Figure 9A and Figure 9B , the first wire CL1 can be formed to penetrate or extend into the first upper insulating layer 415.

[0081] Specifically, the formation of the first wire CL1 can include: etching a part of the upper portions of the second low-k dielectric layer 420, the first low-k dielectric layer 410, and the first conductive contact CT1 to form a plurality of vias; forming a second barrier metal BP2 to cover, overlap with, or be on the side surfaces and bottom surfaces of each via; and filling the vias covered or overlapped with the second barrier metal BP2 with a metal material.

[0082] Except for the step of etching a part of the upper portion of the first conductive contact CT1, the first wire CL1 that does not penetrate or extend into the first conductive contact CT1 can be formed by the same process as the first wire CL1 that penetrates or extends into the first conductive contact CT1.

[0083] Here, since as described with reference to Figure 2 , the first upper insulating layer 415 includes a material with a high etching rate, the width of the first wire CL1 in the fourth direction D4 can be substantially constant regardless of the position in the first direction D1.

[0084] Next, although not shown, a process similar to that described with reference to Figure 5 ,Figure 6A , Figure 7A , Figure 8A and Figure 9A a process similar to the described process to form a second interconnect layer INC2 and a third interconnect layer INC3 on the first upper insulating layer 415, and thus, a semiconductor device having a Figure 2 structure can be manufactured.

[0085] According to some embodiments of the inventive concept, in an interconnect layer of a semiconductor device, an upper portion of a conductive contact may penetrate or extend into an insulating layer including a low-k dielectric material having a high etching rate. The upper portion of the conductive contact may have a shape with a substantially constant width instead of a tapered shape. In this case, the distance between the conductive contact and the wire may be increased, and thus, an electrical short circuit problem between the conductive contact and the wire may be suppressed. In addition, the number of conductive contacts may be increased, where the conductive contacts may be placed at the increased distances, and the integration density of the semiconductor device may be increased.

[0086] As used herein, the terms "comprising," "including," "having," and any other variations thereof specify the presence of the stated features, steps, operations, elements, components, and / or groups, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or their groups. Further, it will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. Rather, these terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Although example embodiments of the inventive concept have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: substrate; as well as an interconnect layer on the substrate, Wherein, the interconnection layer includes an insulating layer, a conductive wire and a conductive contact. Wherein, the insulating layer comprises an upper insulating layer located on the lower insulating layer, wherein the conductive contact extends to the lower portion of the upper insulating layer and extends into the lower insulating layer, wherein the conductive wire is located on the lower insulating layer and intersects with the upper insulating layer, and Wherein, the upper insulating layer comprises a low-k dielectric material.

2. The semiconductor device according to claim 1, wherein The dielectric constant of the low-k dielectric material in the upper insulating layer is equal to or less than 3.

5.

3. The semiconductor device according to claim 1, wherein The low-k dielectric material in the upper insulating layer includes at least one of SiCOH, SiOF and polyimide, and Wherein, the lower insulating layer comprises silicon oxide.

4. The semiconductor device according to claim 1, wherein A width of a lower portion of the conductive line in a first direction parallel to a top surface of the substrate is substantially constant in a second direction perpendicular to the top surface of the substrate.

5. The semiconductor device according to claim 4, wherein: Relative to the substrate, a top surface of the lower insulating layer is lower than a top surface of the conductive contact.

6. The semiconductor device according to claim 4, wherein: A distance between the conductive contact and the conductive line is in a range of 20% to 40% of a width of the conductive line.

7. The semiconductor device according to claim 6, further comprising: a cell structure located between the substrate and the interconnect layer, Wherein, the unit structure includes a capacitor, Wherein, the capacitor comprises: a plurality of bottom electrodes spaced apart from each other in the first direction; A top electrode on the bottom electrode; and a dielectric layer extending between each of the bottom electrodes and the top electrode, and Wherein, the conductive contact is located on the top electrode.

8. A semiconductor device comprising: substrate; a unit structure on the substrate; as well as The interconnect layer on the cell structure, Wherein, the interconnection layer includes an insulating layer, a conductive wire and a conductive contact. Wherein, the insulating layer comprises an upper insulating layer located on the lower insulating layer, The conductive contact comprises a first portion and a second portion on the first portion, wherein the first portion extends into the lower insulating layer, wherein the second portion extends to the lower portion of the upper insulating layer, wherein the first portion has a first width in a first direction parallel to the top surface of the substrate, wherein the second portion has a second width in the first direction, wherein the first width decreases as the distance from the top surface of the substrate in a second direction perpendicular to the top surface of the substrate decreases, and The second width is substantially constant in the second direction.

9. The semiconductor device according to claim 8, wherein: The upper insulating layer includes at least one of SiCOH, SiOF and polyimide.

10. The semiconductor device according to claim 8, wherein The conductive line extends into the upper insulating layer and into the second portion of the conductive contact.

11. The semiconductor device according to claim 8, further comprising: a first barrier metal disposed between the conductive contact and the lower insulating layer and between the conductive contact and the upper insulating layer; as well as A second barrier metal is located between the conductive line and the upper insulating layer.

12. The semiconductor device according to claim 8, wherein The upper insulating layer is on the side surface of the conductive line.

13. The semiconductor device according to claim 8, wherein The thickness of the lower insulating layer is in the range of 10% to 20% of the height of the conductive line.

14. The semiconductor device according to claim 8, wherein: The width of the lower portion of the conductive line in the first direction is substantially constant in the second direction.

15. The semiconductor device according to claim 8, wherein A second portion of the conductive contact is on the lower insulating layer.

16. A semiconductor device comprising: a semiconductor substrate including a cell region and a peripheral region adjacent to the cell region, and including a cell active pattern on the cell region; A word line on the semiconductor substrate, which crosses the cell active pattern; A bit line on the semiconductor substrate, which crosses the word line; a storage node contact located on an end of each of the cell active patterns; a landing pad on the storage node contact; a capacitor on the landing pad; as well as an interconnect layer, which is on the capacitor, The interconnect layer includes an insulating layer, a plurality of conductive contacts, and a plurality of conductive lines, wherein the plurality of conductive lines are spaced apart in a first direction parallel to a top surface of the semiconductor substrate, Wherein, the insulating layer comprises an upper insulating layer located on the lower insulating layer, wherein each of the conductive contacts extends into a lower portion of the upper insulating layer and into the lower insulating layer, wherein a first conductive wire among the plurality of conductive wires extends into an upper portion of a first conductive contact among the plurality of conductive contacts, Wherein, the upper insulating layer comprises a first dielectric material, Wherein, the lower insulating layer comprises a second dielectric material, and The first dielectric constant of the first dielectric material is smaller than the second dielectric constant of the second dielectric material.

17. The semiconductor device according to claim 16, wherein: The shortest distance in the first direction between the first conductive contact and the first conductive line that does not extend to the first conductive contact is greater than or equal to 20% of a width of the first conductive line in the first direction.

18. The semiconductor device according to claim 16, wherein: Relative to the semiconductor substrate, a top surface of the lower insulating layer is lower than a top surface of the first conductive contact.

19. The semiconductor device according to claim 16, wherein: A width of the first conductive contact in the first direction is substantially constant from a bottom surface of the first conductive line to a top surface of the first conductive contact.

20. The semiconductor device according to claim 16, wherein The first dielectric material includes at least one of SiCOH, SiOF and polyimide, and Wherein, the second dielectric material includes silicon oxide.

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