Apparatus including memory word line structures

Abstract

The invention relates to an apparatus including a memory word line structure. The apparatus includes: a word line array including a plurality of word lines each extending through a memory pad in a first horizontal direction, the plurality of word lines including a first word line and a second word line arranged adjacent to each other in a second horizontal direction; and a word line contact of the first word line, the word line contact being separated from the second word line by a gap. The first word line and the second word line each have a first oxide film at a central region of the word line array in the memory pad. The first word line and the second word line each have a second oxide film at an edge region of the word line array outside the memory pad, the second oxide film having a thickness greater than a thickness of the first oxide film.

Description

Technical Field

[0001] The present disclosure relates to an apparatus including a memory word line structure. Background Art

[0002] High data reliability, high-speed memory access, low power consumption, and reduced chip size are some of the characteristics required for semiconductor memory devices such as dynamic random access memories (DRAMs). A memory device includes a plurality of memory cells for storing information. The memory cells may be organized at intersections of word lines and bit lines. The word lines may be arranged in a row array and the bit lines may be arranged in a column array, thereby forming a line matrix in a horizontal plane or a planar view. During an access operation, a word line may be activated, and data may be read from the memory cells along the bit lines to a sense amplifier that may detect the information stored in the memory cells.

[0003] Each word line may have a word line contact coupled thereto and in electrical contact therewith for, for example, electrically connecting the word line to other circuit components or elements. In a vertical plane or in a cross-sectional view, a bottom portion of the word line contact may be coupled to a top portion of the word line. In a word line array, a word line contact of a word line (or a first word line) in one row may be separated from a word line (or a second word line) in an adjacent row that is adjacent to the first word line by a gap to prevent a short circuit between the word line contact and the second word line. As design rules require further shrinking of the memory device, the gap between the word line contact of the first word line and the second word line (which may be referred to as having a short-circuit margin or simply a short margin) may become smaller. Accordingly, it is necessary to provide such a gap or margin large enough to prevent a short circuit. Summary of the Invention

[0004] In one aspect, the present disclosure relates to an apparatus including: a word line array including a plurality of word lines each extending through a memory pad in a first horizontal direction, the plurality of word lines including a first word line and a second word line arranged adjacent to each other in a second horizontal direction; and a word line contact of the first word line, the word line contact being separated from the second word line by a gap, wherein the first word line and the second word line each have a first oxide film at a central region of the word line array in the memory pad, and the first word line and the second word line each have a second oxide film at an edge region of the word line array outside the memory pad, the thickness of the second oxide film being greater than the thickness of the first oxide film.

[0005] In another aspect, the present disclosure relates to a device including: a word line array including a plurality of word lines extending in a first horizontal direction, the plurality of word lines including a first word line and a second word line arranged adjacent to each other in a second horizontal direction; and a word line contact of the first word line, the word line contact being separated from the second word line by a gap, wherein each of the first word line and the second word line has a first oxide film at a central region of the word line array and a second oxide film at an edge region of the word line array, the thickness of the second oxide film being greater than the thickness of the first oxide film, each of the first word line and the second word line has a first cross-sectional width at the edge region of the word line array, the first cross-sectional width being equal to a second cross-sectional width at the central region of the word line array, and each of the first word line and the second word line is located in a corresponding trench in a semiconductor substrate, and each of the corresponding trenches has a third cross-sectional width at the edge region of the word line array, the third cross-sectional width being greater than a fourth cross-sectional width at the central region of the word line array.

[0006] In another aspect, the present disclosure relates to a device including: a first word line located in a first trench in a semiconductor substrate; a first oxide film located between the first word line and the first trench; a first word line contact of the first word line; a second word line located in a second trench in the semiconductor substrate, the second word line and the second trench being arranged adjacent to the first word line and the first trench, respectively; and a second oxide film located between the second word line and the second trench, wherein the first word line contact of the first word line is separated from the second word line by a gap, the first word line has a central portion in a memory pad and an edge portion outside the memory pad, and the first oxide film at the edge portion of the first word line includes a first sub-oxide film and a second sub-oxide film stacked on each other and has a thickness greater than the thickness of the first oxide film at the central portion of the first word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A block diagram of an example semiconductor system according to an embodiment of the present disclosure.

[0008] Figure 2 A schematic configuration of an example word line array in a plan view according to an embodiment of the present disclosure is depicted.

[0009] Figure 3 A schematic configuration of an example word line structure in a cross-sectional view according to an embodiment of the present disclosure is depicted.

[0010] Figure 4A A schematic configuration of an example central region word line structure in a cross-sectional view according to an embodiment of the present disclosure is depicted.

[0011] Figure 4B A schematic configuration of an example edge region word line structure in a cross-sectional view according to an embodiment of the present disclosure is depicted.

[0012] Figures 5A to 5G Depicts an example process for forming a word line structure in a semiconductor substrate in a top view according to an embodiment of the present disclosure.

[0013] Figure 6 Depicts a schematic configuration of an example semiconductor system according to an embodiment of the present disclosure. Detailed Description

[0014] Various example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The following detailed description refers to the drawings that illustrate specific aspects of embodiments in which the present disclosure may be practiced. The embodiments are described in sufficient detail to enable those skilled in the art to practice the present disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some of the disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0015] In the description, common or related elements and substantially identical elements are denoted by the same reference signs, and their description may be reduced or omitted. In the drawings, for ease of illustration, some of the same reference signs of the same or substantially identical elements may be omitted. In the drawings, the size and size ratio of each unit do not necessarily match the actual size and size ratio in the embodiments.

[0016] Figure 1 Is a block diagram of an example semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a dynamic random access memory (DRAM) device. In some embodiments of the present disclosure, the semiconductor device 100 may be included in a semiconductor memory device. The DRAM device may include an interface die and a plurality of core dies stacked on the interface die. In Figure 1 the example, certain components are shown to be located on the interface (IF) die 130, while other components are shown as part of each of the core dies 140. For clarity, only a single core die 140 and its components are shown; however, there may be multiple core dies (e.g., 2, 4, 6, 8, 16, or more) each having components similar to one another. Figure 1 The example semiconductor device 100 of shows a specific arrangement of components between the IF die 130 and the core die 140; however, other arrangements may be used in other embodiments. For example, in some embodiments, the refresh control circuit 116 may be located on the IF die 130. For illustration purposes, the core die 140 is drawn as a rectangular box smaller than the IF 130; however, the core die 140 and the IF die 130 may have any size relationship with each other. For example, the core die 140 and the IF die 130 may be approximately the same size.

[0017] The semiconductor device 100 includes a memory array 118 on each of the core dies 140. The memory array 118 is shown as including a plurality of memory banks. In Figure 1 an embodiment, the memory array 118 is shown as including eight memory banks BANK0 - BANK7. The memory arrays 118 of other embodiments may include more or fewer banks. Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC disposed at intersections of the plurality of word lines WL and the plurality of bit lines BL. Selection of the word lines WL is performed by the row decoder 108, and selection of the bit lines BL is performed by the column decoder 110, each of which may also be located on each of the core dies 140. In Figure 1 an embodiment, the row decoder 108 includes a respective row decoder for each memory bank, and the column decoder 110 includes a respective column decoder for each memory bank. The bit lines BL are coupled to respective sense amplifiers (SAMP) of the memory array 118. Read data from the bit lines BL is amplified by the sense amplifiers SAMP and transmitted to the RWAMP 120 via complementary local data lines (LIOT / B), a transfer gate (TG), and complementary main data lines (MIOT / B) coupled to the read / write amplifier (RWAMP) 120. Conversely, write data output from the RWAMP 120 is transmitted to the sense amplifiers SAMP via the complementary main data lines MIOT / B, the transfer gate TG, and the complementary local data lines LIOT / B, and written into the memory cells MC coupled to the bit lines BL.

[0018] The semiconductor device 100 may employ a plurality of external terminals located on the IF die 130, the plurality of external terminals including: command and address (CA) terminals coupled to command and address buses to receive commands, addresses, and chip select (CS) signals; clock terminals for receiving clocks CK and / CK; data terminals DQ for providing data; and power terminals for receiving power potentials VDD, VSS, and VDDQ.

[0019] An external clock CK and / CK that are supplied to the input circuit 112 are provided to the clock terminals on the IF die 130. The external clocks CK and / CK can be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 106 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clocks can be used for the timing operations of various internal circuits. The internal clock LCLK is provided to the input and output (IO) circuit 122 to time the operations of the circuits included in the IO circuit 122. For example, it is provided to the data receiver to time the reception of write data.

[0020] The internal clock LCLK can include a read clock (RCLK) for controlling the timing of read operations and a write clock (WCLK) for controlling the timing of write operations. The internal clock can be passed to the IO circuit 122. In some cases, the internal clock can also be passed to internal components of the core die 140, such as the RWAMP 120.

[0021] Memory addresses can be supplied to the CA terminals of the IF die 130. The memory addresses supplied to the CA terminals are transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108, and supplies the decoded column address YADD to the column decoder 110. The address decoder 104 can also supply a decoded bank address BADD, which can indicate the bank of the memory array 118 that contains the decoded row address XADD and column address YADD. Commands can be supplied to the CA terminals. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing the memory (such as a read command for performing a read operation and a write command for performing a write operation), and other commands and operations. The access commands can be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD that indicate one or more memory cells to be accessed.

[0022] Commands can be provided to the command decoder 106 as internal command signals via the command / address input circuit 102 of the IF die 130. The command decoder 106 includes circuitry for decoding the internal command signals to generate various internal signals and commands for performing operations. For example, the command decoder 106 can provide a row command signal for selecting a word line and a column command signal for selecting a bit line.

[0023] The semiconductor device 100 can receive an access command as a read command. When a read command is received and a bank address, a row address, and a column address are supplied in a timely manner along with an activate command and the read command, read data is read from the memory cells corresponding to the row address and the column address in the memory array 118. The read command is received by a command decoder 106, which provides an internal command to cause the read data from the memory cells in the memory array 118 to be provided to the RWAMP 120. The read data is output from the data terminal DQ to the outside of the semiconductor device 100 via the IO circuit 122.

[0024] The semiconductor device 100 can receive an access command as a write command. When a write command is received and a bank address, a row address, and a column address are supplied in a timely manner along with an activate command and the write command, write data is supplied to the RWAMP 120 via the DQ terminal. The write data supplied to the data terminal DQ is written to the memory cells corresponding to the row address and the column address in the memory array 118. The write command is received by a command decoder 106, which provides an internal command to cause the write data to be received by a data receiver in the IO circuit 122. A write clock may also be provided to an external clock terminal to time the reception of the write data by the data receiver of the IO circuit 122. The write data is supplied to the RWAMP 120 via the IO circuit 122.

[0025] The semiconductor device 100 can also receive a command that causes it to perform one or more refresh operations as part of a self-refresh mode. In some embodiments, the self-refresh mode command may be sent from the outside to the semiconductor device 100. In some embodiments, the self-refresh mode command may be periodically generated by components of the device. In some embodiments, a refresh signal AREF may also be activated when an external signal indicates a self-refresh entry command.

[0026] A power supply potential VDD and VSS are supplied to the power supply terminals of the IF die 130. The power supply potential VDD and VSS are supplied to an internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials, such as VPP, VOD, VARY, VPERI, etc., based on the power supply potential VDD and VSS.

[0027] A power supply potential VDDQ is also supplied to the power supply terminals of the IF die 130. The power supply potential VDDQ is supplied to the IO circuit 122. In one embodiment of the present disclosure, the power supply potential VDDQ may be the same potential as the power supply potential VDD. In another embodiment of the present disclosure, the power supply potential VDDQ may be a potential different from the power supply potential VDD. The power supply potential VDDQ is used for the IO circuit 122 so that power supply noise generated by the IO circuit 122 does not propagate to other circuit blocks.

[0028] In some embodiments of the present disclosure, a plurality of memory cells MC form a memory cell array in each memory bank of the memory array 118. The memory cell array may include a plurality of memory pads MAT (not separately depicted in the Figure 1 schematic). The memory cell array may be divided into a plurality of memory pads MAT. Each memory pad MAT is assigned a set of word lines and bit lines. In the assigned group, the word line array extends in a first horizontal direction, and the bit line array extends in a second horizontal direction perpendicular (or substantially perpendicular within reasonable tolerances of manufacturing, measurement, etc.) to the first horizontal direction. Each line extends through the memory pad MAT to an external region of the memory pad MAT. In the external region of the memory pad MAT, a word line driver may be coupled to the word lines and a sense amplifier may be coupled to the bit lines. The memory pad may also be referred to as a memory array pad.

[0029] Figure 2 FIG. depicts a schematic configuration of an example word line array in a plan view according to an embodiment of the present disclosure. The word line array includes a plurality of word lines WL1-WLn (which may also be collectively referred to as WL) that extend in one horizontal direction (e.g., a first horizontal direction along the X-axis in the figure) and are arranged parallel to each other in another horizontal direction (e.g., a second horizontal direction along the Y-axis in the figure). Each word line WL extends through the memory pad (or memory array pad) MAT in the first horizontal direction and extends to its exterior.

[0030] In a plan view, the region of the word line array inside the memory pad MAT may be referred to as the central region. The region of the word line array outside the memory pad MAT may be referred to as the edge region. The central region and the edge region may include a central portion and an edge portion of each word line WL, respectively. The edge region includes at least two edge regions on one side and the other side outside the memory pad MAT in the first horizontal direction. The central region may be an intermediate region between the two edge regions.

[0031] At the edge region outside the memory pad MAT, word line contacts WLC are provided to each word line WL. The word line contacts WLC may be in electrical contact with at least the word lines WL. In the illustrated example, word line contacts WLC are provided to every two word lines (e.g., every odd-numbered word line) WL on one side of the memory pad MAT and different every two word lines (e.g., every even-numbered word line) WL on the other side of the memory pad MAT. For example, in Figure 2 the figure, on the left side of the memory pad MAT, word line contacts WLC1 and WLC3 are provided to the first word line WL1 and the third word line WL3 of the first and third row arrays, respectively, and on the right side of the memory pad MAT, word line contacts WLC2 and WLC4 are provided to the second word line WL2 and the fourth word line WL3 of the second and fourth row arrays, respectively.

[0032] In addition, there is a gap GP between a word line contact WLC of a word line WL (e.g., the first word line WL1) in one row and another word line WL (e.g., the second word line WL2) in an adjacent row that is disposed adjacent to the first word line WL1. Thus, the word line contact WLC1 of the first word line WL1 is separated from the second word line WL2 by the gap GP to prevent a short circuit therebetween. The gap GP electrically isolates the word line contact WLC1 from the second word line WL2. Thus, the gap GP has a short-circuit tolerance between adjacent word line contacts and word lines, such as WLC1 in the first row and WL2 in the second row, or WLC2 in the second row and WL3 in the third row in the illustrated configuration.

[0033] Figure 3 FIG. depicts a schematic configuration of an example word line structure in a cross-sectional view according to an embodiment of the present disclosure. In the illustrated configuration, word lines WL1 and WL2 are buried in respective trenches 301 formed in a semiconductor substrate 300, with an oxide film 302 between the word lines and the trenches. A word line contact WLC1 is provided to the first word line WL1. There is also a polysilicon layer 303 formed on each of the word lines WL1 and WL2. The polysilicon layer 303 can improve device refresh characteristics. The word line contact WLC1 passes through the polysilicon layer 303 of the first word line WL1, and at least a portion (e.g., the bottom portion) thereof lands on or touches at least a portion (e.g., the top portion) of the first word line WL1. Although at least a portion of the word line contact WLC1 is in electrical contact with the first word line WL1, the word line contact WLC1 is electrically isolated from the second word line WL2 by the gap GP therebetween. The gap GP can have a dimension D to prevent a short circuit between the word line contact WLC1 of the first word line WL1 and the adjacent second word line WL2. Since design rules require further shrinking of the memory device, the gap GP can become smaller.

[0034] Figure 4A FIG. depicts a schematic configuration of an example center region word line structure in a cross-sectional view according to an embodiment of the present disclosure. Figure 4B FIG. depicts a schematic configuration of an example edge region word line structure in a cross-sectional view according to an embodiment of the present disclosure. Figure 4A and Figure 4B each have elements identical to the elements of the word line structure of Figure 3 wherein the elements include trenches 401, oxide films 402, and polysilicon layers 403 corresponding to trenches 301, oxide films 302, and polysilicon layers 303, respectively. In the present embodiment, in order to provide a sufficiently large gap GP to prevent a short circuit between the word line contact WLC1 of the first word line WL1 and the second word line WL2, the cross-sectional width (or the critical dimension CD in the Y-axis direction in the drawing) A of the edge region of each of the word lines WL1 and WL2EA The cross-sectional width A of the central region equal to each of the word lines WL1 and WL2 CA . A EA May be the same as or substantially the same as A within reasonable tolerances of manufacturing, measurement, etc. In this text, WL1 and WL2 may be collectively referred to as WL. CA

[0035] In this embodiment, based on the memory device specifications, design rules, etc., the cross-sectional width C of the trench 401 formed in the semiconductor substrate 400 at the edge region EA Is set to be greater than the cross-sectional width C of the trench 401 at the central region CA . In the trench size relationship C EA > C CA In the case of, the cross-sectional width or thickness B of the oxide film 402 deposited on the surface of the trench 401 at the edge region EA Is greater than the cross-sectional width or thickness B of the oxide film 402 at the central region CA (B EA > B CA ), while the A of the edge region of the word line WL EA Is equal to the A of the central region of the word line WL CA (A EA = A CA ), as illustrated in the figure. As an example, the oxide film 402 at the edge region may include a stacked oxide film, which includes a plurality of oxide films stacked on top of each other, increasing the total thickness of the oxide film 402 such that it is thicker than the oxide film 402 at the central region. Figure 4B The dashed lines in the oxide film 402 in the figure indicate the presence of a plurality of oxide films stacked or layered on top of each other. The stacked oxide film (such as the oxide films 502 and 504) is further described below. The oxide film 402 at the central region may include a single oxide film. In C EA > C CA In the trench having A EA = A CA And B EA > B CA In the case of the above configuration, a gap GP with a sufficient size D can be obtained to prevent a short circuit between the word line contact WLC1 of the first word line WL1 and the adjacent second word line WL2.

[0036] Figures 5A to 5G Depicts an example process for forming a word line structure in a semiconductor substrate in a plan view according to an embodiment of the present disclosure. The word line may be Figure 1 The word line WL in. The word line may be Figures 2 to 4B The word lines WL1, WL2,...WLn in.​

[0037] As shown in Figure 5A , trenches 501 are formed in semiconductor substrate 500 by, for example, etching. The trenches 501 extend in a first horizontal direction (e.g., the X-axis direction in the figure) and are arranged parallel to each other in a second horizontal direction (e.g., the Y-axis direction in the figure). Each trench 501 extends through memory pad MAT in the first horizontal direction and extends outside memory pad MAT. Based on memory device specifications, design rules, etc., the trenches 501 in the central region within memory pad MAT and the trenches 501 in the edge region outside memory pad MAT have a width dimension relationship C EA >C CA .

[0038] As shown in Figure 5B , an oxide film 502 is provided to the surface of trenches 501 by, for example, oxide deposition. The oxide film 502 can be an oxide layer. The thickness of the oxide film 502 at the central region and the thickness at the edge region can be the same as each other (or substantially the same within reasonable tolerances of manufacturing, measurement, etc.).

[0039] As shown in Figure 5C , a photoresist film 503 is provided as a hard mask to the region of memory pad MAT to cover the memory pad region in a top view. Any conventional technique for providing a hard mask of photoresist material can be used as appropriate.

[0040] As shown in Figure 5D , an additional oxide film 504 is provided on the oxide film 502 in trenches 501 by, for example, another oxide deposition. This provides a stack of the first oxide film 502 and the second oxide film 504 and increases the total oxide film thickness in each trench 501. The additional oxide deposition can include radical deposition of, for example, oxygen radicals. Example conditions for the additional oxide deposition include, but are not limited to, a temperature range of 60 - 100 °C and a pressure range of 300 - 500 Pa. The process conditions can be used and adjusted as appropriate to achieve the desired dimensions of the oxide film 504. Optionally, the total oxide film thickness as the thickness of the stacked oxide films 502 and 504 in trenches 501 can be controlled. The materials of the oxide film 502 and 504 can be the same or different. The oxide film 502 and 504 can also be referred to as the first sub-oxide film 502 and the second sub-oxide film 504, respectively. Together, the two sub-oxide films 502 and 504 can form a stacked oxide film on the surface of trenches 501, which is only thicker than the oxide film 502.

[0041] Subsequently, as shown in Figure 5E , the oxide film 504 in the region of memory pad MAT is removed by, for example, etch-back to expose the underlying photoresist film 503, and asFigure 5F As shown in, the photoresist film 503 is removed by, for example, wet stripping. Any conventional etch-back technique and stripping technique may be used as appropriate. As illustrated, while the trench 501 in the central region of the memory pad MAT has a single oxide film formed by the oxide film 502, the trench 501 in the edge region outside the memory pad MAT has a stacked oxide film formed by the oxide films 502 and 504. In addition, the stacked oxide film is thicker than the single oxide film by B EA >B CA , such that the remaining space of the trench 501 has a uniform cross-sectional width (in the Y-axis direction in the figure) in the edge region and the central region.

[0042] Next, as Figure 5G shown in, word lines WL (e.g., WL1 and WL2) are provided by, for example, depositing and etching a conductive material to fill the remaining space of the trench 501. The conductive material may be a metal material. Any conventional deposition and etch-back techniques may be used as appropriate. In addition, although not depicted separately, a polysilicon layer such as the polysilicon layers 303 / 403 is formed on the top portion of each of the word lines WL by, for example, depositing and etching a polysilicon material.

[0043] With the above process according to an embodiment of the present invention, a word line configuration having a specific relationship between the central region and the edge region with respect to the memory pad MAT, such as a word line width A EA = A CA , an oxide film width B EA >B CA (the stacked sub-oxide films 502 and 504 at the edge region are thicker than the single oxide film 502 at the central region) and a trench width C EA >C CA provide a configuration with higher flexibility. In addition, in the case of the above configuration, referring back to Figure 4B , when a word line contact WLC1 made of a conductive material is formed in electrical contact with the first word line WL1 by a subsequent process and is electrically isolated from an adjacent second word line WL2 through a gap GP, the gap GP may have a short-circuit tolerance with a sufficient size D between the word line contact WLC1 of the first word line WL1 and the adjacent second word line WL2 to prevent a short circuit therebetween. Therefore, it is possible to further flexibly and reliably adjust the size D of the gap or the short-circuit tolerance.

[0044] Figure 6 depicts a schematic configuration of an example semiconductor system 600 according to an embodiment of the present disclosure. In an embodiment of the present disclosure, the semiconductor system 600 includes a semiconductor memory device 601. In some embodiments of the present disclosure, the semiconductor memory device 601 may include Figure 1semiconductor device 100. The semiconductor system 600 may further include a central processing unit (CPU) and a memory controller 604, which may be a controller chip on an interposer 605 on a package substrate 608. The interposer 605 may include one or more power lines 610 that can supply a power voltage from the package substrate 608. The interposer 605 may include a plurality of channels 611 that can interconnect the CPU and the memory controller 604 with the semiconductor memory device 601. The semiconductor memory device 601 may be a DRAM. The memory controller 604 may provide a clock signal, a command signal, and may further transmit and receive data signals. The plurality of channels 611 may transmit data signals between the memory controller and the memory device 601.

[0045] The semiconductor memory device 601 may include a plurality of dies (or chips) 602, and the dies 602 include at least one interface (IF) die (or chip) 603 and a plurality of memory core dies (or chips) 606 that are stacked on each other. In some embodiments, each of the plurality of memory core dies 606 may include a core die 140, and the IF die 603 may include the IF die 130 of the semiconductor device 100.

[0046] The number of memory core dies 606 is not limited to four as in the illustrated example, and may be more or less as the case may be. Each of the memory core dies 606 may include a plurality of memory cells and circuitry for accessing the memory cells. For example, the memory cells may be DRAM cells. The memory cells may be arranged in an array. The semiconductor memory device 601 may include conductive vias 607 that couple the IF die 603 and the memory core dies 606 by penetrating the IF die 603 and the memory core dies 606. The IF die 603 may be coupled to the interposer 605 via interconnects 609. For example, the interconnects 609 may be micro-bumps with a bump pitch less than or less than about one hundred microns and exposed on the outside of the IF die 603. A portion of each of the interconnects 609 may be coupled to one or more power lines 610. Another portion of each of the interconnects 609 may be coupled to one or more of the channels 611.

[0047] DRAM is only one example, and the embodiments and descriptions herein are not intended to be limited to DRAM. Memory devices other than DRAM, such as static random access memory (SRAM), flash memory, erasable programmable read only memory (EPROM), magnetoresistive random access memory (MRAM), and phase change memory, may also be applied as the semiconductor memory device 901. In addition, devices other than memory (including logic ICs such as microprocessors and application specific integrated circuits (ASICs)) may also be applied as the semiconductor device according to the embodiments of the present invention.

[0048] Although various embodiments of the present disclosure have been described in detail, those skilled in the art should understand that the embodiments of the present disclosure can extend beyond the specifically disclosed embodiments to other alternative embodiments and / or their uses, as well as modifications and equivalents. Additionally, based on the described embodiments, other modifications within the scope of the present disclosure will be readily apparent to those skilled in the art. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments can be made and still fall within the scope of the present disclosure. It should be understood that the various features and aspects of the embodiments can be combined with each other or substituted for each other to form different modes of the embodiments. Therefore, it is intended that the scope of the present disclosure should not be limited by the specific embodiments described above.

Claims

1. A device comprising: a word line array including a plurality of word lines each extending through the memory pad in a first horizontal direction, the plurality of word lines including a first word line and a second word line arranged adjacent to each other in a second horizontal direction; and a word line contact of the first word line, the word line contact being separated from the second word line by a gap, wherein the first word line and the second word line each have a first oxide film at a central region of the word line array in the memory pad, and The first word line and the second word line each have a second oxide film at an edge region of the word line array outside the memory pad, the second oxide film having a thickness greater than a thickness of the first oxide film. 2 . The apparatus of claim 1 , wherein the gap has a size to prevent a short circuit between the word line contact of the first word line and the second word line. The apparatus of claim 2 , wherein the gap is short circuit tolerant. 4 . The apparatus of claim 1 , wherein the word line contact contacts the first word line in the edge region of the word line array.

5. The apparatus according to claim 1, wherein the first word line and the second word line are each located in a corresponding trench in a semiconductor substrate, and the second oxide film includes a first sub-oxide film on a surface of the corresponding trench and a second sub-oxide film on a surface of the first sub-oxide film.

6. The apparatus of claim 1, wherein the first word line and the second word line each have a first cross-sectional width at the edge region of the word line array, the first cross-sectional width being equal to a second cross-sectional width at the center region of the word line array.

7. The device of claim 6 , wherein the first word line and the second word line are each located in a corresponding trench in a semiconductor substrate, and each of the corresponding trenches has a third cross-sectional width at the edge region of the word line array, the third cross-sectional width being greater than a fourth cross-sectional width at the center region of the word line array.

8. The device according to claim 1, wherein The first word line and the second word line each have a first cross-sectional width at the edge region of the word line array, the first cross-sectional width being equal to a second cross-sectional width at the center region of the word line array, The first word line and the second word line are each located in a corresponding trench in the semiconductor substrate, and each of the corresponding trenches has a third cross-sectional width at the edge region of the word line array, the third cross-sectional width being greater than a fourth cross-sectional width at the center region of the word line array, and The gap has a size to prevent a short circuit between the word line contact of the first word line and the second word line. 9 . The apparatus according to claim 1 , wherein the first oxide film is a single oxide film, and the second oxide film is a stacked oxide film including a plurality of oxide films stacked on each other.

10. A device comprising: a word line array including a plurality of word lines extending in a first horizontal direction, the plurality of word lines including a first word line and a second word line arranged adjacent to each other in a second horizontal direction; and a word line contact of the first word line, the word line contact being separated from the second word line by a gap, wherein the first word line and the second word line each have a first oxide film at a central region of the word line array and a second oxide film at an edge region of the word line array, the thickness of the second oxide film being greater than the thickness of the first oxide film, The first word line and the second word line each have a first cross-sectional width at the edge region of the word line array, the first cross-sectional width being equal to a second cross-sectional width at the center region of the word line array, and The first word line and the second word line are respectively located in corresponding grooves in the semiconductor substrate, and each of the corresponding grooves has a third cross-sectional width at the edge area of ​​the word line array, and the third cross-sectional width is greater than a fourth cross-sectional width at the center area of ​​the word line array.

11. The device according to claim 10, wherein The plurality of word lines each extend through the memory pad in the first horizontal direction, The central region of the word line array is located in the memory pad, and The edge region of the word line array is located outside the memory pad.

12. The apparatus of claim 10, wherein the gap has a short circuit tolerance having a size to prevent a short circuit between the word line contact of the first word line and the second word line.

13. The apparatus of claim 10, wherein the word line contact contacts the first word line in the edge region of the word line array outside a memory pad. 14 . The apparatus according to claim 10 , wherein the second oxide film includes a first sub oxide film on a surface of the trench and a second sub oxide film on a surface of the first sub oxide film.

15. An apparatus comprising: a first word line disposed in a first trench in the semiconductor substrate; a first oxide film located between the first word line and the first trench; a first word line contact of the first word line; a second word line located in a second trench in the semiconductor substrate, the second word line and the second trench being arranged adjacent to the first word line and the first trench, respectively; and a second oxide film located between the second word line and the second trench, wherein The first word line contact of the first word line is separated from the second word line by a gap, The first word line has a center portion in the memory pad and an edge portion outside the memory pad, and The first oxide film at the edge portion of the first word line includes a first sub oxide film and a second sub oxide film stacked on each other, and has a thickness greater than that of the first oxide film at the center portion of the first word line.

16. The apparatus of claim 15, wherein the gap has a size to prevent a short circuit between the first word line contact of the first word line and the second word line. 17 . The apparatus of claim 15 , wherein the first oxide film at the center portion of the first word line includes a single oxide film, and a total thickness of the stacked first and second sub-oxide films is greater than a thickness of the single oxide film. 18 . The apparatus of claim 17 , wherein a cross-sectional width of the edge portion of the first word line is equal to a cross-sectional width of the center portion of the first word line. 19 . The apparatus of claim 18 , wherein a cross-sectional width of the first trench at the edge portion of the first word line is greater than a cross-sectional width of the first trench at the center portion of the first word line.

20. The apparatus of claim 15, wherein the first word line and the second word line extend through the memory pad in a first horizontal direction and are arranged adjacent to each other in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction.

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