Semiconductor device

Abstract

A semiconductor device may include: a bit line extending in a first direction; a bit line dielectric layer on a sidewall of the bit line; a channel layer in contact with the bit line; a word line extending in a second direction crossing the first direction; a gate capping layer in contact with a first sidewall of the word line; a gate dielectric layer in contact with the channel layer and a second sidewall of the word line; and a first dielectric structure extending in the first direction. The first dielectric structure may include a dielectric material different from a dielectric material of the gate capping layer. The word line, the gate dielectric layer, and the gate capping layer may be in contact with an inner sidewall of the first dielectric structure.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly, to semiconductor devices including dielectric structures. Background Art

[0002] The reduction of design rules of semiconductor devices can lead to the development of manufacturing technologies to improve the integration, operating speed, and / or manufacturing yield of semiconductor devices. Accordingly, transistors having vertical channels have been proposed to increase their integration, current driving ability, etc. Summary of the Invention

[0003] Some embodiments of the inventive concept provide semiconductor devices having improved electrical characteristics and increased integration.

[0004] According to some embodiments of the inventive concept, a semiconductor device may include: a bit line extending in a first direction; a bit line dielectric layer on sidewalls of the bit line; a channel layer in contact with the bit line; a word line extending in a second direction crossing the first direction; a gate capping layer in contact with a first sidewall of the word line; a gate dielectric layer in contact with the channel layer and a second sidewall of the word line, the second sidewall of the word line being opposite to the first sidewall; and a first dielectric structure extending in the first direction. The first dielectric structure may include a dielectric material different from a dielectric material of the gate capping layer. The word line, the gate dielectric layer, and the gate capping layer may be in contact with an inner sidewall of the first dielectric structure.

[0005] According to some embodiments of the inventive concept, a semiconductor device may include: a bit line extending in a first direction; a bit line dielectric layer on sidewalls of the bit line; a channel layer in contact with the bit line; a word line extending in a second direction crossing the first direction; a gate capping layer in contact with a first sidewall of the word line; a gate dielectric layer in contact with the channel layer and a second sidewall of the word line, the second sidewall of the word line being opposite to the first sidewall; and a dielectric structure in contact with a third sidewall of the word line. The gate dielectric layer and the dielectric structure may each include an oxide. The bit line dielectric layer may include: a first top surface in contact with the gate dielectric layer; and a second top surface in contact with a bottom surface of the dielectric structure.

[0006] According to some embodiments of the inventive concept, a semiconductor device may include: bit lines extending in a first direction; a bit line dielectric layer on sidewalls of the bit lines; a channel layer in contact with the bit lines; word lines extending in a second direction crossing the first direction; a gate capping layer in contact with a first sidewall of the word lines; a gate dielectric layer in contact with the channel layer and a second sidewall of the word lines, the second sidewall of the word lines being opposite to the first sidewall; a dielectric structure in contact with a third sidewall of the word lines; a first dielectric pattern in contact with the gate capping layer; a second dielectric pattern spaced apart from the first dielectric pattern with the dielectric structure therebetween; an upper capping layer in contact with the gate capping layer, the first dielectric pattern, and the second dielectric pattern; an upper dielectric layer on the upper capping layer; a landing pad extending at least into the upper dielectric layer and in contact with the channel layer; and a data storage pattern connected to the landing pad. A bottom surface of the upper capping layer may be in contact with a top surface of the dielectric structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A FIG. shows a block diagram illustrating a semiconductor device according to some embodiments.

[0008] Figure 1B and Figure 1C FIG. shows a simplified perspective view illustrating a semiconductor device according to some embodiments.

[0009] Figure 2 FIG. shows a plan view illustrating a semiconductor device according to some embodiments.

[0010] Figure 3 FIG. shows a cross-sectional view taken along line A-A' of Figure 2 .

[0011] Figure 4A FIG. shows a cross-sectional view taken along line B-B' of Figure 2 .

[0012] Figure 4B FIG. shows a cross-sectional view taken along line C-C' of Figure 2 .

[0013] Figure 4C FIG. shows a cross-sectional view taken along line D-D' of Figure 2 .

[0014] Figure 5A 、 Figure 5B and Figure 5C FIGS. show cross-sectional views illustrating a semiconductor device according to some embodiments.

[0015] Figure 6A 、 Figure 6B and Figure 6C FIGS. show cross-sectional views illustrating a semiconductor device according to some embodiments.

[0016] Figure 7 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 12 、 Figure 13A 、 Figure 13B and Figure 13C Figures showing a method of manufacturing a semiconductor device according to some embodiments.

[0017] Figure 14 Figure showing a plan view of a semiconductor device according to some embodiments.

[0018] Figure 15 Figures showing a cross-sectional view taken along line A-A' of Figure 14 .

[0019] Figure 16A Figures showing a cross-sectional view taken along line B-B' of Figure 14 .

[0020] Figure 16B Figures showing a cross-sectional view taken along line C-C' of Figure 14 .

[0021] Figure 16C Figures showing a cross-sectional view taken along line D-D' of Figure 14 . DETAILED DESCRIPTION

[0022] Hereinafter, a semiconductor package and a method of manufacturing the semiconductor package according to some embodiments of the present inventive concept will be discussed with reference to the accompanying drawings.

[0023] Figure 1A Figure showing a block diagram of a semiconductor device according to some embodiments.

[0024] Referring to Figure 1A , the semiconductor device may include a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and a control logic 5.

[0025] The memory cell array 1 may include a plurality of memory cells MC arranged in a two-dimensional or three-dimensional manner. Each memory cell MC may be connected between word lines WL and bit lines BL that cross each other and connected to the word lines WL and the bit lines BL.

[0026] Each memory cell MC may include a selection element TR and a data storage element DS. The selection element TR and the data storage element DS may be electrically connected to each other. The selection element TR may be connected to both the word line WL and the bit line BL. For example, the selection element TR may be provided at the intersection of the word line WL and the bit line BL.

[0027] The selection element TR may include a field effect transistor. The data storage element DS may include a capacitor, a magnetic tunnel junction pattern, or a variable resistor. For example, the gate terminal of the transistor as the selection element TR may be connected to the word line WL, the first source / drain terminal of the transistor may be connected to the bit line BL, and the second source / drain terminal of the transistor may be connected to the data storage element DS.

[0028] The row decoder 2 may decode an address input from an external source (not shown) and may select one of the word lines WL in the memory cell array 1. The address decoded in the row decoder 2 may be provided to a row driver (not shown), and in response to a control operation of the control circuit, the row driver may supply a first specific voltage to the selected word line WL and a second specific voltage to each unselected word line WL.

[0029] The column decoder 4 may provide a data transfer path between the sense amplifier 3 and an external device (e.g., a memory controller). The column decoder 4 may decode an address input from an external source and may select one of the bit lines BL. In response to the address decoded by the column decoder 4, the sense amplifier 3 may detect and amplify the voltage difference between the selected bit line BL and a reference bit line, and then may output the amplified voltage difference.

[0030] The control logic 5 may generate a control signal that controls an operation of writing data to and / or reading data from the memory cell array 1.

[0031] Figure 1B and Figure 1C shows a simplified perspective view of a semiconductor device according to some embodiments.

[0032] Referring to Figure 1B and Figure 1C a semiconductor device may include a peripheral circuit structure PS and a cell array structure CS connected to the peripheral circuit structure PS.

[0033] The peripheral circuit structure PS may include a core / peripheral circuit formed on a substrate SUB. The core / peripheral circuit may include the row decoder 2 and the column decoder 4, the sense amplifier 3, and the control logic 5 discussed with reference to Figure 1A The unit array structure CS may include a memory cell array (see

[0034] Figure 1A ​1), the memory cell array includes memory cells arranged in a two-dimensional or three-dimensional manner (see Figure 1A MC). As described above, each memory cell (see Figure 1A MC) may include a selection element TR and a data storage element DS.

[0035] In some embodiments, a vertical channel transistor (VCT) may be included as the selection element TR of each memory cell (see Figure 1A MC). The vertical channel transistor may include a channel whose longitudinal direction is perpendicular to the top surface of the substrate SUB. The data storage element DS of each memory cell (see Figure 1A MC) may include a capacitor.

[0036] In Figure 1B example, a peripheral circuit structure PS may be provided on the substrate SUB, and a cell array structure CS may be provided on the peripheral circuit structure PS.

[0037] In Figure 1C example, a peripheral circuit structure PS may be provided on a first substrate SUB1, and a cell array structure CS may be provided on a second substrate SUB2. The first substrate SUB1 and the second substrate SUB2 may face each other.

[0038] The peripheral circuit structure PS may be provided with a first metal pad LMP at its uppermost part. The first metal pad LMP may be electrically connected to the core / peripheral circuit (see Figure 1A 2, 3, 4, and 5).

[0039] The cell array structure CS may be provided with a second metal pad UMP at its lowermost part. The second metal pad UMP may be electrically connected to the memory cell array (see Figure 1A 1). The second metal pad UMP may be in direct contact with or bonded to the first metal pad LMP of the peripheral circuit structure PS.

[0040] Figure 2 The figure shows a plan view of a semiconductor device according to some embodiments. Figure 3 The figure shows Figure 2 a cross-sectional view taken along line A-A' of Figure 4A The figure shows Figure 2 a cross-sectional view taken along line B-B' of Figure 4B The figure shows Figure 2 a cross-sectional view taken along line C-C' of Figure 4C The figure shows Figure 2 a cross-sectional view taken along line D-D' of

[0041] Referring to Figures 2 to 4C, the lower dielectric layer LIL can be provided on the substrate SUB. The substrate SUB can have a plate shape elongated along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 can intersect with each other. For example, the first direction D1 and the second direction D2 can be horizontal directions orthogonal to each other. The lower dielectric layer LIL can include a dielectric material. For example, the lower dielectric layer LIL can include an oxide.

[0042] In some embodiments, the peripheral circuit structure PS discussed with reference to Figure 1B can be provided between the substrate SUB and the lower dielectric layer LIL. In some embodiments, an integrated circuit (such as a logic device) can be provided between the substrate SUB and the lower dielectric layer LIL.

[0043] The bit line dielectric layer BIL can be provided on the lower dielectric layer LIL. The bit line dielectric layer BIL can include a dielectric material. A plurality of bit lines BL can be provided in the bit line dielectric layer BIL. The bit line dielectric layer BIL can be in the space between the sidewalls of the bit lines BL (for example, can fill the space). The bit lines BL can extend in the first direction D1. The bit lines BL can be arranged along the second direction D2. The bit lines BL can be spaced apart from each other in the second direction D2.

[0044] The bit lines BL can include a conductive material. The bit lines BL can include, for example, at least one material selected from doped polysilicon, metals (such as Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, or Co), conductive metal nitrides (such as TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, or RuTiN), conductive metal silicides, and conductive metal oxides (such as PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), or LSCO), but the inventive concept is not limited thereto. The bit lines BL can include a single layer or multiple layers of the above materials. In some embodiments, the bit lines BL can include two-dimensional semiconductor materials, such as graphene, carbon nanotubes, or any combination thereof.

[0045] The channel layers ACP can be provided on the bit lines BL. A plurality of channel layers ACP can be in contact with one bit line BL. The channel layers ACP provided on one bit line BL can be arranged along the first direction D1.

[0046] The channel layer ACP may include a semiconductor material. The channel layer ACP may include an oxide semiconductor, which may include at least one selected from InGaZnO, InGaSiO, InSnZnO, InZnO, ZnO, ZnSnO, ZnON, ZrZnSnO, SnO, HfInZnO, GaZnSnO, AlZnSnO, YbGaZnO, and InGaO, but the inventive concept is not limited thereto. For example, the channel layer ACP may include indium gallium zinc oxide (IGZO). The channel layer ACP may include a single layer or multiple layers of the oxide semiconductor. The channel layer ACP may include an amorphous, crystalline, or polycrystalline oxide semiconductor. In some embodiments, the channel layer ACP may have a bandgap energy greater than that of silicon. For example, the channel layer ACP may have a bandgap energy of about 1.5 eV to about 5.6 eV. For example, when the bandgap energy of the channel layer ACP is in the range from about 2.0 eV to about 4.0 eV, the channel layer ACP may exhibit optimal channel performance. For example, the channel layer ACP may be polycrystalline or amorphous, but the inventive concept is not limited thereto. In some embodiments, the channel layer ACP may include a two-dimensional semiconductor material, such as graphene, carbon nanotubes, or any combination thereof.

[0047] The first word line WL1 and the second word line WL2 may be provided. The first word line WL1 and the second word line WL2 may be provided on the gate dielectric layer GI to be discussed below. The first word line WL1 and the second word line WL2 may be in contact with the gate dielectric layer GI to be discussed below. The first word line WL1 and the second word line WL2 may be spaced apart from each other in the first direction D1. The first word line WL1 and the second word line WL2 may extend in the second direction D2.

[0048] The first word line WL1 and the second word line WL2 may include a conductive material. The first word line WL1 and the second word line WL2 may include at least one material selected from, for example, doped polysilicon, metals (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, or Co), conductive metal nitrides (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, or RuTiN), conductive metal silicides, and conductive metal oxides, but the inventive concept is not limited thereto. The first word line WL1 and the second word line WL2 may include a single layer or multiple layers of the above materials. In some embodiments, the first word line WL1 and the second word line WL2 may include a two-dimensional semiconductor material, such as graphene, carbon nanotubes, or any combination thereof.

[0049] The first word line WL1 may have a first sidewall WL1_S1, a second sidewall WL1_S2, and a third sidewall WL1_S3. The second word line WL2 may have a first sidewall WL2_S1, a second sidewall WL2_S2, and a third sidewall WL2_S3. The first sidewall WL1_S1 of the first word line WL1 may face the first sidewall WL2_S1 of the second word line WL2. The adjacent sidewalls of the first word line WL1 and the second word line WL2 may be the first sidewall WL1_S1 of the first word line WL1 and the first sidewall WL2_S1 of the second word line WL2. The second sidewall WL1_S2 of the first word line WL1 may be opposite to the first sidewall WL1_S1 of the first word line WL1. The second sidewall WL2_S2 of the second word line WL2 may be opposite to the first sidewall WL2_S1 of the second word line WL2. The first sidewall WL1_S1 and the second sidewall WL1_S2 of the first word line WL1 may extend in a second direction D2. Similarly, the first sidewall WL2_S1 and the second sidewall WL2_S2 of the second word line WL2 may extend in the second direction D2. The third sidewall WL1_S3 of the first word line WL1 may connect the first sidewall WL1_S1 and the second sidewall WL1_S2 of the first word line WL1 to each other. The third sidewall WL2_S3 of the second word line WL2 may connect the first sidewall WL2_S1 and the second sidewall WL2_S2 of the second word line WL2 to each other. The third sidewall WL1_S3 of the first word line WL1 and the third sidewall WL2_S3 of the second word line WL2 may contact a dielectric structure IST to be discussed below.

[0050] A gate dielectric layer GI may be provided on the channel layer ACP. The gate dielectric layer GI may contact the channel layer ACP, the second sidewall WL1_S2 of the first word line WL1, the second sidewall WL2_S2 of the second word line WL2, and a gate capping layer GP to be discussed in more detail below. The gate dielectric layer GI may extend in the second direction D2. The gate dielectric layer GI may include a dielectric material. For example, the gate dielectric layer GI may include an oxide.

[0051] A gate capping layer GP may be provided. The gate capping layer GP may be provided on the first word line WL1 and the second word line WL2 and on the gate dielectric layer GI. The gate capping layer GP may contact the first sidewall WL1_S1 of the first word line WL1 and the first sidewall WL2_S1 of the second word line WL2. The gate capping layer GP may include a dielectric material. For example, the gate capping layer GP may include a nitride.

[0052] The lower molding layer DML can be provided on the bit line BL. The lower molding layer DML can be provided between the channel layers ACP adjacent to each other along the first direction D1. The lower molding layer DML can be provided on the bit lines BL arranged along the second direction D2. The lower molding layer DML can be in contact with the channel layers ACP adjacent to each other and with the bit lines BL arranged along the second direction D2. The lower molding layer DML can connect the channel layer ACP to the dielectric structure IST that will be discussed in more detail below. The lower molding layer DML can include a dielectric material.

[0053] The upper molding layer UML can be provided. The upper molding layer UML can be provided on the lower molding layer DML. The upper molding layer UML can be provided between the channel layers ACP adjacent to each other. The upper molding layer UML can be in contact with the top surface of the lower molding layer DML and the channel layers ACP adjacent to each other. The upper molding layer UML can include a dielectric material.

[0054] The dielectric structure IST can be provided. The dielectric structure IST can extend in the first direction D1. The dielectric structure IST can be spaced apart from the bit line BL in the second direction D2. The dielectric structure IST can be in contact with the bit line dielectric layer BIL, the first word line WL1, the second word line WL2, the gate dielectric layer GI, and the gate capping layer GP. The dielectric structure IST can include a dielectric material.

[0055] The first dielectric pattern IP1 can be provided on the gate capping layer GP. The first dielectric pattern IP1 can cover the gate capping layer GP. The first dielectric pattern IP1 can be in contact with the gate capping layer GP and the dielectric structure IST.

[0056] The second dielectric pattern IP2 can be provided. The second dielectric pattern IP2 can be spaced apart from the first dielectric pattern IP1 with the dielectric structure IST in between. The second dielectric pattern IP2 can be in contact with the dielectric structure IST.

[0057] The first dielectric pattern IP1 and the second dielectric pattern IP2 can include a dielectric material. For example, the first dielectric pattern IP1 and the second dielectric pattern IP2 can include an oxide.

[0058] As in Figures 4A - 4CBest seen in, dummy dielectric layer DI and dummy capping layer DC can be provided between bit line dielectric layer BIL and second dielectric pattern IP2. Dummy dielectric layer DI can be provided on bit line dielectric layer BIL. Dummy capping layer DC can be on dummy dielectric layer DI. Dummy dielectric layer DI can be in contact with bit line dielectric layer BIL, dummy capping layer DC, and dielectric structure IST. Dummy capping layer DC can be in contact with second dielectric pattern IP2, dummy dielectric layer DI, and dielectric structure IST. Dummy dielectric layer DI can be spaced apart from gate dielectric layer GI across dielectric structure IST. Dummy capping layer DC can be spaced apart from gate capping layer GP across dielectric structure IST. Dummy dielectric layer DI and dummy capping layer DC can include dielectric materials. For example, dummy dielectric layer DI can include an oxide and dummy capping layer DC can include a nitride.

[0059] Upper capping layer UC can be provided. Upper capping layer UC can be on gate capping layer GP, first dielectric pattern IP1, second dielectric pattern IP2, and dielectric structure IST. Upper capping layer UC can be in contact with the top surface of gate capping layer GP, the top surface of first dielectric pattern IP1, the top surface of second dielectric pattern IP2, and the top surface of dielectric structure IST. Upper capping layer UC can include a dielectric material. Upper capping layer UC can include a nitride.

[0060] Landing pads LP can be provided on channel layer ACP. Landing pads LP can vertically overlap channel layer ACP. Landing pads LP can be spaced apart from each other in a first direction D1 and a second direction D2 and can be arranged in a matrix pattern, a zigzag pattern, a honeycomb pattern, or any other suitable pattern. When viewed in a plan view, each of landing pads LP can have a circular, oval, rectangular, square, diamond, hexagonal, or any other suitable shape.

[0061] Landing pads LP can include a conductive material. Landing pads LP can be formed of, for example, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or any combination thereof, but the inventive concept is not limited thereto.

[0062] Upper dielectric layer UIL can be provided between landing pads LP. Upper dielectric layer UIL can be provided on upper capping layer UC. Upper dielectric layer UIL can be in contact with the top surface of upper capping layer UC. Upper dielectric layer UIL can separate landing pads LP from each other. Upper dielectric layer UIL can include a dielectric material. For example, upper dielectric layer UIL can include a nitride.

[0063] A data storage pattern DSP can be provided on the landing pad LP accordingly. The data storage pattern DSP can be electrically connected to the channel layer ACP through the landing pad LP.

[0064] In some embodiments, the data storage pattern DSP can be a capacitor that includes a bottom electrode, a top electrode, and a capacitor dielectric layer between the bottom electrode and the top electrode. In this case, the bottom electrode can be in contact with the landing pad LP and can have a circular, oval, rectangular, square, diamond, hexagonal, or any other suitable shape when viewed in a plan view. The shape of the bottom electrode of the capacitor or the data storage pattern DSP can correspond to the shape of the landing pad LP.

[0065] In some embodiments, the data storage pattern DSP can be a variable resistance pattern whose two resistance states are switched due to an electrical pulse. For example, the data storage pattern DSP can include a phase change material (whose crystalline state changes based on the amount of current), a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material.

[0066] The dielectric structure IST can have an inner sidewall IST_IS, an outer sidewall IST_OS, a top surface, and a bottom surface. The inner sidewall IST_IS of the dielectric structure IST can be in contact with the bit line dielectric layer BIL, the lower molding layer DML, the upper molding layer UML, the gate dielectric layer GI, the gate capping layer GP, the third sidewall WL1_S3 of the first word line WL1, the third sidewall WL2_S3 of the second word line WL2, and the first dielectric pattern IP1. The outer sidewall IST_OS of the dielectric structure IST can be in contact with the bit line dielectric layer BIL, the dummy dielectric layer DI, the dummy capping layer DC, and the second dielectric pattern IP2. The top surface of the dielectric structure IST can be in contact with the bottom surface of the upper capping layer UC. The top surface of the dielectric structure IST can be coplanar with the top surface of the gate capping layer GP, the top surface of the first dielectric pattern IP1, and the top surface of the second dielectric pattern IP2. The bottom surface of the dielectric structure IST can be in contact with the bit line dielectric layer BIL. The dielectric structure IST can extend into the bit line dielectric layer BIL.

[0067] The bit line dielectric layer BIL may have a first top surface BIL_U1, a second top surface BIL_U2, a third top surface BIL_U3, a first connection surface BIL_C1, and a second connection surface BIL_C2. The first top surface BIL_U1 of the bit line dielectric layer BIL may be in contact with the lower molding layer DML and the gate dielectric layer GI. The second top surface BIL_U2 of the bit line dielectric layer BIL may be in contact with the bottom surface of the dielectric structure IST. The third top surface BIL_U3 of the bit line dielectric layer BIL may be in contact with the dummy dielectric layer DI. The second top surface BIL_U2 of the bit line dielectric layer BIL may be at a level lower than the levels of the first top surface BIL_U1 of the bit line dielectric layer BIL and the third top surface BIL_U3 of the bit line dielectric layer BIL. The first connection surface BIL_C1 of the bit line dielectric layer BIL may connect the first top surface BIL_U1 and the second top surface BIL_U2 of the bit line dielectric layer BIL to each other. The first connection surface BIL_C1 of the bit line dielectric layer BIL may be in contact with the inner sidewall IST_IS of the dielectric structure IST. The second connection surface BIL_C2 of the bit line dielectric layer BIL may connect the second top surface BIL_U2 and the third top surface BIL_U3 of the bit line dielectric layer BIL to each other. The second connection surface BIL_C2 of the bit line dielectric layer BIL may be in contact with the outer sidewall IST_OS of the dielectric structure IST.

[0068] The dielectric structure IST, the gate capping layer GP, the first dielectric pattern IP1, and the second dielectric pattern IP2 may have their top surfaces coplanar with each other.

[0069] The dielectric structure IST may include a dielectric material different from the dielectric materials of the bit line dielectric layer BIL and the upper molding layer UML. The dielectric structure IST may include a dielectric material the same as the dielectric material of the lower molding layer DML. For example, the dielectric structure IST and the lower molding layer DML may include an oxide, and the bit line dielectric layer BIL and the upper molding layer UML may include a nitride.

[0070] A semiconductor device according to some embodiments may include a dielectric structure IST through which oxygen molecules are supplied to the channel layer ACP through the lower molding layer DML when an annealing process is performed. Thus, the vacancies in the channel layer ACP may be filled with oxygen molecules to reduce the resistance of the channel layer ACP and improve the electrical characteristics of the semiconductor device.

[0071] Figure 5A , Figure 5B and Figure 5C FIG. shows a cross-sectional view showing a semiconductor device according to some embodiments. Figure 5A FIG. shows corresponding to Figure 4ACross-sectional view. Figure 5B shows a cross-section corresponding to Figure 4B Cross-sectional view. Figure 5C shows a cross-section corresponding to Figure 4C Cross-sectional view. Except as described below, Figure 5A , Figure 5B and Figure 5C The semiconductor devices of Figures 2 to 4C can be similar to the semiconductor devices of

[0072] Referring to Figure 5A , Figure 5B and Figure 5C , the dielectric structure IST can extend through the bit line dielectric layer BIL. The bit line dielectric layer BIL can have sidewalls BIL_S. The sidewalls BIL_S of the bit line dielectric layer BIL can contact the inner sidewall IST_IS and the outer sidewall IST_OS of the dielectric structure IST. The bottom surface of the dielectric structure IST can contact the lower dielectric layer LIL. The bottom surface of the dielectric structure IST can be at a level lower than the level of the bottom surface of the bit line dielectric layer BIL and the level of the bottom surface of the bit line BL.

[0073] Figure 6A , Figure 6B and Figure 6C show cross-sectional views of semiconductor devices according to some embodiments. Figure 6A shows a cross-section corresponding to Figure 4A Cross-sectional view. Figure 6B shows a cross-section corresponding to Figure 4B Cross-sectional view. Figure 6C shows a cross-section corresponding to Figure 4C Cross-sectional view. Except as described below, Figure 6A , Figure 6B and Figure 6C The semiconductor devices of Figures 2 to 4C can be similar to the semiconductor devices of

[0074] Referring to Figure 6A , Figure 6B and Figure 6C , the bottom surface of the dielectric structure IST can contact the top surface BIL_U of the bit line dielectric layer BIL. The top surface BIL_U of the bit line dielectric layer BIL can be coplanar with the top surface of the bit line BL. The bottom surface of the dielectric structure IST can be coplanar with the bottom surface of the lower molding layer DML, the bottom surface of the gate dielectric layer GI, and the bottom surface of the dummy dielectric layer DI.

[0075] Figure 7 , Figure 8A , Figure 8B , Figure 8C , Figure 9A , Figure 9B , Figure 9C ,Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 12 , Figure 13A , Figure 13B and Figure 13C FIGs. showing a method of manufacturing a semiconductor device according to some embodiments. Figure 7 and Figure 12 may correspond to Figure 3 . Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 13A may correspond to Figure 4A . Figure 8B , Figure 9B , Figure 10B , Figure 11B and Figure 13B may correspond to Figure 4B . Figure 8C , Figure 9C , Figure 10C , Figure 11C and Figure 13C may correspond to Figure 4C .

[0076] Referring to Figure 7 , Figure 8A , Figure 8B and Figure 8C , a lower dielectric layer LIL may be formed on a substrate SUB. A bit line dielectric layer BIL may be formed on the lower dielectric layer LIL. A bit line BL may be formed in the bit line dielectric layer BIL.

[0077] A lower molding layer DML and an upper molding layer UML may be formed on the bit line dielectric layer BIL. The upper molding layer UML may be formed on the lower molding layer DML. A channel layer ACP may be formed between the lower molding layers DML adjacent to each other in a first direction D1 and between the upper molding layers UML adjacent to each other in the first direction D1. An initial gate dielectric layer pGI may be formed on the lower molding layer DML, the upper molding layer UML, the channel layer ACP, and the bit line dielectric layer BIL. The initial gate dielectric layer pGI may cover the lower molding layer DML, the upper molding layer UML, the channel layer ACP, and the bit line dielectric layer BIL and be conformal with them. A first word line WL1 and a second word line WL2 may be formed on the initial gate dielectric layer pGI. An initial gate capping layer pGP may be formed on the initial gate dielectric layer pGI, the first word line WL1, and the second word line WL2. The initial gate capping layer pGP may cover the initial gate dielectric layer pGI, the first word line WL1, and the second word line WL2 and be conformal with them.

[0078] The initial gate dielectric layer pGI and the initial gate capping layer pGP may include dielectric materials. For example, the initial gate dielectric layer pGI may include an oxide, and the initial gate capping layer pGP may include a nitride.

[0079] An initial dielectric pattern pIP may be formed on the initial gate capping layer pGP. The formation of the initial dielectric pattern pIP may include forming the initial dielectric pattern pIP covering the initial gate capping layer pGP and removing an upper portion of the initial dielectric pattern pIP to expose a top surface of the initial gate capping layer pGP.

[0080] In some embodiments, the upper portion of the initial dielectric pattern pIP may be removed by a chemical mechanical polishing (CMP) process. Thus, the initial dielectric pattern pIP and the initial gate capping layer pGP may have their top surfaces coplanar with each other.

[0081] Refer to Figure 9A 、 Figure 9B and Figure 9C , an opening op may be formed. The formation of the opening op may include: forming a photoresist pattern on the initial dielectric pattern pIP and the initial gate capping layer pGP; performing a lithography process to form a hole in the photoresist pattern; and using the photoresist pattern as an etch mask to remove a portion of each of the initial dielectric pattern pIP, the initial gate capping layer pGP, the initial gate dielectric layer pGI, the first word line WL1, the second word line WL2, and the bit line dielectric layer BIL.

[0082] A portion of the initial dielectric pattern pIP may be removed to form a first dielectric pattern IP1 and a second dielectric pattern IP2. The initial dielectric pattern pIP whose portion is removed may be defined as the first dielectric pattern IP1 and the second dielectric pattern IP2. A portion of the initial gate capping layer pGP may be removed to form a gate capping layer GP and a dummy capping layer DC. The initial gate capping layer pGP whose portion is removed may be defined as the gate capping layer GP and the dummy capping layer DC. A portion of the initial gate dielectric layer pGI may be removed to form a gate dielectric layer GI and a dummy dielectric layer DI. The initial gate dielectric layer pGI whose portion is removed may be defined as the gate dielectric layer GI and the dummy dielectric layer DI.

[0083] The opening op can be defined as an empty space indicating the formation by removing a portion of each of the initial dielectric pattern pIP, the initial gate overlay pGP, the initial gate dielectric layer pGI, the first word line WL1, the second word line WL2, and the bit line dielectric layer BIL through the holes in the photoresist pattern. In some embodiments, a dry etching process may be employed to remove a portion of each of the initial dielectric pattern pIP, the initial gate overlay pGP, the initial gate dielectric layer pGI, the first word line WL1, the second word line WL2, and the bit line dielectric layer BIL.

[0084] After forming the opening op, the photoresist pattern can be removed. In some embodiments, the photoresist pattern can be removed by an ashing process or a lift-off process.

[0085] Referring to Figure 10A 、 Figure 10B and Figure 10C ,an initial dielectric layer p1 can be formed. The initial dielectric layer p1 can be in the opening op and can fill the opening op. The initial dielectric layer p1 can cover the top surface of each of the gate overlay GP, the first dielectric pattern IP1, and the second dielectric pattern IP2. The initial dielectric layer p1 can include a dielectric material. For example, the initial dielectric layer p1 can include an oxide. After forming the initial dielectric layer p1, a heat treatment process can be performed. In some embodiments, the heat treatment process can be performed by an annealing process.

[0086] Referring to Figure 11A 、 Figure 11B and Figure 11C ,the upper portion of the initial dielectric layer p1 can be removed to form a dielectric structure IST. The initial dielectric layer p1 with its upper portion removed can be defined as the dielectric structure IST. The upper portion of the initial dielectric layer p1 can be removed to expose the top surface of each of the gate overlay GP, the first dielectric pattern IP1, and the second dielectric pattern IP2.

[0087] In some embodiments, the upper portion of the initial dielectric layer p1 can be removed by a chemical mechanical polishing process or a back etching process. Thus, the gate overlay GP, the first dielectric pattern IP1, the second dielectric pattern IP2, and the dielectric structure IST can have their top surfaces coplanar with each other.

[0088] Referring to Figure 12 、 Figure 13A 、 Figure 13B and Figure 13C ,an upper overlay UC can be formed. The upper overlay UC can cover the exposed top surfaces of each of the gate overlay GP, the first dielectric pattern IP1, and the second dielectric pattern IP2 and be conformal with them.

[0089] Return reference Figure 3 , Figure 4A , Figure 4B and Figure 4C , an upper dielectric layer UIL can be formed on the upper cover layer UC. A process can be performed to remove a part of the upper cover layer UC and a part of the upper dielectric layer UIL. A landing pad LP can be formed. The landing pad LP can fill the empty space formed by removing the part of the upper cover layer UC and the part of the upper dielectric layer UIL. In some embodiments, a part of each of the channel layer ACP, the gate dielectric layer GI, the gate cover layer GP, the first dielectric pattern IP1, and the upper molding layer UML can be removed together with the part of the upper cover layer UC and the part of the upper dielectric layer UIL. The landing pad LP can fill the empty space formed by removing the parts of the channel layer ACP, the gate dielectric layer GI, the gate cover layer GP, the first dielectric pattern IP1, and the upper molding layer UML. The data storage pattern DSP can be formed to connect to the corresponding landing pad in the landing pad LP.

[0090] In a method of manufacturing a semiconductor device according to some embodiments, since an initial dielectric layer p1 containing an oxide is included, an annealing process can be performed to move oxygen molecules in the initial dielectric layer p1 through the lower molding layer DML to the channel layer ACP. Therefore, the vacancies in the channel layer ACP can be filled with oxygen molecules to reduce the resistance of the channel layer ACP and improve the electrical characteristics of the semiconductor device.

[0091] Figure 14 Shows a plan view of a semiconductor device according to some embodiments. Figure 15 Shows a cross-sectional view taken along line Figure 14 A-A' Figure 16A Shows a cross-sectional view taken along line Figure 14 B-B' Figure 16B Shows a cross-sectional view taken along line Figure 14 C-C' Figure 16C Shows a cross-sectional view taken along line Figure 14 D-D' Figures 14 to 16C The semiconductor device can be similar to the semiconductor device of Figures 2 to 4C except for the following description.

[0092] Refer to Figure 14 , Figure 15 , Figure 16A , Figure 16B and Figure 16C, the dielectric structure ISTa may include a first dielectric structure ISTa1 and a second dielectric structure ISTa2. The first dielectric structure ISTa1 and the second dielectric structure ISTa2 may be spaced apart from each other in the second direction D2 across the bit line BL. The first dielectric structure ISTa1 and the second dielectric structure ISTa2 may include a dielectric material. For example, the first dielectric structure ISTa1 and the second dielectric structure ISTa2 may include an oxide.

[0093] The bit line BLa may include a first bit line BLa1, a second bit line BLa2, and a third bit line BLa3 that are spaced apart from each other in the second direction D2. The second dielectric structure ISTa2 may be between the first bit line BLa1 and the second bit line BLa2. The first bit line BLa1 and the second bit line BLa2 may be adjacent to the second dielectric structure ISTa2. The third bit line BLa3 may be adjacent to the first dielectric structure ISTa1. The second bit line BLa2 and the third bit line BLa3 may be between the first dielectric structure ISTa1 and the second dielectric structure ISTa2.

[0094] The channel layer ACPa may include a first channel layer ACPa1, a second channel layer ACPa2, and a third channel layer ACPa3 that are spaced apart from each other in the second direction D2. The first channel layer ACPa1 may be provided on the first bit line BLa1. The second channel layer ACPa2 may be provided on the second bit line BLa2. The third channel layer ACPa3 may be provided on the third bit line BLa3. The second dielectric structure ISTa2 may be between the first channel layer ACPa1 and the second channel layer ACPa2. The first channel layer ACPa1 and the second channel layer ACPa2 may be adjacent to the second dielectric structure ISTa2. The third channel layer ACPa3 may be adjacent to the first dielectric structure ISTa1. The second channel layer ACPa2 and the third channel layer ACPa3 may be between the first dielectric structure ISTa1 and the second dielectric structure ISTa2.

[0095] The first dielectric structure ISTa1 may be similar to Figures 2 to 4C the dielectric structure IST discussed in

[0096] The second dielectric structure ISTa2 can be spaced apart from the dummy dielectric layer DIa, the dummy capping layer DCa, and the second dielectric pattern IPa2. The second dielectric structure ISTa2 can separate the first word lines WLa1 from each other in the second direction D2. The second dielectric structure ISTa2 can separate the second word lines WLa2 from each other in the second direction D2. The second dielectric structure ISTa2 can separate the gate dielectric layers GIa from each other in the second direction D2. The second dielectric structure ISTa2 can separate the gate capping layers GPa from each other in the second direction D2. The second dielectric structure ISTa2 can separate the first dielectric patterns IPa1 from each other in the second direction D2. The second dielectric structure ISTa2 can separate the lower molding layers DMLa from each other in the second direction D2. The second dielectric structure ISTa2 can separate the upper molding layers UMLa from each other in the second direction D2.

[0097] The bit line dielectric layer BILa can include a first top surface BILa_U1, a second top surface BILa_U2, a third top surface BILa_U3, a first connection surface BILa_C1, and a second connection surface BILa_C2, and can further include a fourth top surface BILa_U4 and a third connection surface BILa_C3. The fourth top surface BILa_U4 and the third connection surface BILa_C3 of the bit line dielectric layer BILa can be in contact with the second dielectric structure ISTa2. The fourth top surface BILa_U4 of the bit line dielectric layer BILa can be located at a level lower than the levels of the first top surface BILa_U1 of the bit line dielectric layer BILa and the third top surface BILa_U3 of the bit line dielectric layer BILa. The third connection surface BILa_C3 of the bit line dielectric layer BILa can connect the first top surface BILa_U1 and the fourth top surface BILa_U4 of the bit line dielectric layer BILa to each other.

[0098] The second dielectric structure ISTa2 can have sidewalls ISTa2_S, a bottom surface, and a top surface. Each sidewall ISTa2_S of the second dielectric structure ISTa2 can be in contact with the third connection surface BILa_C3 of the bit line dielectric layer BILa, the first word line WL1a, the second word line WLa2, the gate dielectric layer GIa, the gate capping layer GPa, the first dielectric pattern IPa1, the lower molding layer DMLa, and the upper molding layer UMLa. The bottom surface of the second dielectric structure ISTa2 can be in contact with the fourth top surface BILa_U4 of the bit line dielectric layer BILa. The top surface of the second dielectric structure ISTa2 can be in contact with the upper capping layer UCa.

[0099] A semiconductor device according to some embodiments of the inventive concept may include a dielectric structure that supplies oxygen molecules to a channel layer when an annealing process is performed. Accordingly, vacancies in the channel layer may be filled with oxygen molecules to reduce the resistance of the channel layer and improve the electrical characteristics of the semiconductor device.

[0100] In a method of manufacturing a semiconductor device according to some embodiments of the inventive concept, oxygen molecules in an initial dielectric layer may move through a lower molding layer into the channel layer, and thus vacancies in the channel layer may be filled with oxygen molecules to reduce the resistance of the channel layer and improve the electrical characteristics of the semiconductor device.

[0101] Although the inventive concept has been described in connection with some examples of embodiments of the inventive concept shown in the drawings, those skilled in the art will understand that various changes and modifications can be made without departing from the technical spirit and essential features of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications, and changes can be made without departing from the scope of the inventive concept.

[0102] This application claims the priority of Korean Patent Application No. 10-2023-0187258, filed on Dec. 20, 2023, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: A bit line extending in a first direction; a bit line dielectric layer on the sidewalls of the bit line; a channel layer in contact with the bit line; a word line extending in a second direction intersecting the first direction; a gate capping layer in contact with a first sidewall of the word line; a gate dielectric layer in contact with the channel layer and a second sidewall of the word line, the second sidewall of the word line being opposite to the first sidewall; as well as a first dielectric structure extending in the first direction, wherein the first dielectric structure comprises a dielectric material different from a dielectric material of the gate cap layer, and The word line, the gate dielectric layer and the gate cap layer are in contact with the inner sidewall of the first dielectric structure.

2. The semiconductor device according to claim 1, further comprising: a first dielectric pattern, contacting the gate capping layer; a second dielectric pattern, spaced apart from the first dielectric pattern via the first dielectric structure; as well as a dummy dielectric layer and a dummy capping layer between the bit line dielectric layer and the second dielectric pattern, The first dielectric structure includes an outer sidewall in contact with the dummy dielectric layer, the dummy cover layer and the second dielectric pattern.

3. The semiconductor device according to claim 2, further comprising an upper cover layer in contact with a top surface of the first dielectric pattern, wherein the gate cover layer has a top surface in contact with the upper cover layer, and The top surface of the gate capping layer, the top surface of the first dielectric pattern, and the top surface of the first dielectric structure are coplanar with each other.

4. The semiconductor device according to claim 1 , further comprising a lower molding layer in contact with the bit line and the channel layer, The lower molding layer is in contact with the inner sidewall of the first dielectric structure. 5 . The semiconductor device of claim 4 , wherein the lower molding layer and the first dielectric structure comprise oxide. 6 . The semiconductor device of claim 4 , wherein a bottom surface of the lower molding layer and a bottom surface of the first dielectric structure are coplanar with each other.

7. The semiconductor device according to claim 1, further comprising a second dielectric structure, the second dielectric structure being spaced apart from the first dielectric structure via the channel layer in the second direction, The second dielectric structure includes a dielectric material that is the same as the dielectric material of the first dielectric structure and is in contact with the bit line dielectric layer.

8. The semiconductor device according to claim 7, wherein the bit line comprises a first bit line, a second bit line, and a third bit line spaced apart from each other in the second direction, wherein the second bit line and the third bit line are between the first dielectric structure and the second dielectric structure, and The second dielectric structure is between the first bit line and the second bit line.

9. The semiconductor device according to claim 8, wherein the channel layer comprises: a first channel layer on the first bit line; a second channel layer on the second bit line; as well as a third channel layer on the third bit line, The second dielectric structure is between the first channel layer and the second channel layer. 10 . The semiconductor device according to claim 1 , further comprising an upper capping layer contacting a top surface of the first dielectric structure and a top surface of the gate capping layer.

11. The semiconductor device according to claim 1 , further comprising a lower dielectric layer on a bottom surface of the bit line, The bottom surface of the first dielectric structure contacts the lower dielectric layer. 12 . The semiconductor device according to claim 11 , wherein a level of the bottom surface of the first dielectric structure is lower than a level of the bottom surface of the bit line. 13 . The semiconductor device of claim 1 , wherein the dielectric material of the first dielectric structure is different from a dielectric material of the bit line dielectric layer.

14. A semiconductor device comprising: A bit line extending in a first direction; a bit line dielectric layer on the sidewalls of the bit line; a channel layer in contact with the bit line; a word line extending in a second direction intersecting the first direction; a gate capping layer in contact with a first sidewall of the word line; a gate dielectric layer in contact with the channel layer and a second sidewall of the word line, the second sidewall of the word line being opposite to the first sidewall; as well as a dielectric structure contacting a third sidewall of the word line, wherein each of the gate dielectric layer and the dielectric structure comprises an oxide, and The bit line dielectric layer comprises: a first top surface in contact with the gate dielectric layer; and A second top surface is in contact with the bottom surface of the dielectric structure.

15. The semiconductor device according to claim 14, wherein the bit line dielectric layer further has a connection surface connecting the first top surface to the second top surface, and The connection surface of the bit line dielectric layer contacts the inner sidewall of the dielectric structure.

16. The semiconductor device according to claim 14, wherein the channel layer includes a first channel layer and a second channel layer spaced apart from each other in the second direction, The dielectric structure is between the first channel layer and the second channel layer.

17. The semiconductor device according to claim 14, further comprising a lower molding layer contacting the bit line and the channel layer, The lower molding layer connects the channel layer to the dielectric structure.

18. The semiconductor device according to claim 17, further comprising an upper molding layer between the lower molding layer and the gate dielectric layer, The upper molding layer includes a dielectric material different from a dielectric material of the dielectric structure and contacts an inner sidewall of the dielectric structure.

19. A semiconductor device comprising: A bit line extending in a first direction; a bit line dielectric layer on the sidewalls of the bit line; a channel layer in contact with the bit line; a word line extending in a second direction intersecting the first direction; a gate capping layer in contact with a first sidewall of the word line; a gate dielectric layer in contact with the channel layer and a second sidewall of the word line, the second sidewall of the word line being opposite to the first sidewall; a dielectric structure in contact with a third sidewall of the word line; a first dielectric pattern, contacting the gate capping layer; a second dielectric pattern, spaced apart from the first dielectric pattern via the dielectric structure; an upper cover layer, contacting the gate cover layer, the first dielectric pattern and the second dielectric pattern; an upper dielectric layer on the upper cover layer; a landing pad extending at least into the upper dielectric layer and contacting the channel layer; as well as Data storage pattern, connected to the landing pad, The bottom surface of the upper cover layer contacts the top surface of the dielectric structure.

20. The semiconductor device according to claim 19, wherein the word line comprises a first word line and a second word line spaced apart from each other in the first direction, The first word line and the second word line are in contact with an inner sidewall of the dielectric structure.

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