Semiconductor device

Abstract

A semiconductor device may include a substrate, bottom electrodes disposed on the substrate, a support pattern disposed between the bottom electrodes when viewed in a plan view, an upper electrode covering the bottom electrodes and the support pattern, and a dielectric layer disposed between the bottom electrodes and the upper electrode and between the support pattern and the upper electrode, and a first conductive contact connected to the upper electrode. The upper electrode includes a metal layer, a first hydrogen diffusion barrier layer, and a first semiconductor layer sequentially stacked on the dielectric layer. The first conductive contact is spaced apart from the first hydrogen diffusion barrier layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device including a hydrogen diffusion barrier layer. Background Art

[0002] Semiconductor devices include various categories, including semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices including both memory elements and logic elements.

[0003] With the recent trend of high speed and low power consumption in electronic devices, there is also a need for semiconductor devices in the electronic devices to meet the requirements of increasing the operation speed and / or reducing the operation voltage, which requires a higher integration density of the semiconductor devices. However, as the integration density of the semiconductor devices increases, the electrical characteristics of the semiconductor devices may deteriorate. Accordingly, many studies are being conducted to improve the electrical characteristics of the semiconductor devices. Summary of the Invention

[0004] Embodiments of the inventive concept provide a semiconductor device having improved electrical characteristics.

[0005] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate, a bottom electrode disposed on the substrate, a support pattern disposed between the bottom electrodes when observed in a plan view, a top electrode covering the bottom electrode and the support pattern, a dielectric layer disposed between the bottom electrode and the top electrode and between the support pattern and the top electrode, and a first conductive contact connected to the top electrode. The top electrode includes a metal layer, a first hydrogen diffusion barrier layer, and a first semiconductor layer sequentially stacked on the dielectric layer. The first conductive contact is spaced apart from the first hydrogen diffusion barrier layer.

[0006] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate, a bottom electrode on the substrate, a support pattern disposed between the bottom electrodes when observed in a plan view, a top electrode covering the bottom electrode and the support pattern, and a dielectric layer disposed between the bottom electrode and the top electrode and between the support pattern and the top electrode. The top electrode includes a metal layer, a first semiconductor layer, a first hydrogen diffusion barrier layer, and a second semiconductor layer sequentially stacked on the dielectric layer. Each of the first semiconductor layer and the second semiconductor layer includes silicon germanium.

[0007] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate including a cell array region and a peripheral region, a word line disposed on the cell array region of the substrate, a first impurity region in a portion of the substrate disposed on one side of the word line, a second impurity region in a portion of the substrate disposed on the opposite side of the word line, a bit line disposed on the cell array region of the substrate, crossing the word line, and connected to the first impurity region, a bottom electrode disposed on the cell array region of the substrate and connected to the second impurity region, a support pattern disposed between the bottom electrodes when viewed in a plan view, an upper electrode covering the bottom electrode and the support pattern, a dielectric layer disposed between the bottom electrode and the upper electrode and between the support pattern and the upper electrode, and a first conductive contact coupled to the upper electrode. The upper electrode includes a metal layer, a first hydrogen diffusion barrier layer, and a first semiconductor layer sequentially stacked on the dielectric layer. The first conductive contact is spaced apart from the first hydrogen diffusion barrier layer and contacts the first semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a plan view showing a semiconductor device according to an embodiment of the inventive concept.

[0009] Figure 2A is a cross-sectional view taken along line A-A' and B-B' of Figure 1

[0010] Figure 2B and 2C is a cross-sectional view showing a modified example of the semiconductor device of Figure 2A and corresponding to line A-A' and B-B' of Figure 1

[0011] Figure 3A is a cross-sectional view taken along line A-A' and B-B' of Figure 1 to show a semiconductor device according to an embodiment of the inventive concept.

[0012] Figure 3B and Figure 3C is a cross-sectional view showing a modified example of the semiconductor device of Figure 3A and corresponding to line A-A' and B-B' of Figure 1

[0013] Figure 4 is a cross-sectional view showing the semiconductor device taken along line C-C' of Figure 1 Figure 2A

[0014] Figure 5A is a cross-sectional view showing an enlarged view of the "P1" portion of Figure 4

[0015] Figure 5B is a cross-sectional view showing Figure 4 ​​​​​​An enlarged cross-sectional view of the "P2" portion.

[0016] Figure 6 shows a cross-section taken along Figure 1 line C-C' of Figure 3A a semiconductor device.

[0017] Figure 7A shows Figure 6 an enlarged cross-sectional view of portion P3.

[0018] Figure 7B shows Figure 6 an enlarged cross-sectional view of portion P4.

[0019] Figure 8 , 9 , 10, 11, 12, and 13 are cross-sectional views sequentially showing the process of manufacturing Figure 4 a semiconductor device.

[0020] Figure 14 and Figure 15 are cross-sectional views showing the process of manufacturing Figure 6 a semiconductor device. Detailed Description

[0021] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0022] Figure 1 is a plan view of a semiconductor device according to an embodiment of the inventive concept. Figure 2A is a cross-sectional view taken along Figure 1 lines A-A' and B-B' of

[0023] Referring to Figure 1 and FIG. 2, a substrate 301 including a cell array region CAR and a peripheral region PER may be provided. The peripheral region PER may be disposed adjacent to the cell array region CAR. Word lines WL and bit lines BL may be disposed on the cell array region CAR, and peripheral circuits for driving the word lines WL and the bit lines BL may be disposed on the peripheral region PER. The peripheral region PER may be referred to as a core region or a peripheral circuit region. The substrate 301 may be, for example, a silicon substrate, a germanium substrate, or a silicon germanium substrate.

[0024] The device isolation layer 302 may be disposed in the substrate 301 to define an active portion ACT including a cell active portion ACTC and a peripheral active portion ACTP. The device isolation layer 302 may be disposed in a trench TCH. Each cell active portion ACTC may have an isolated shape. When observed in a plan view, each cell active portion ACTC may be a bar pattern extending along a first direction D1. The device isolation layer 302 may include an oxide liner, a nitride liner, and an insulating gap fill layer. The cell active portions ACTC may be arranged parallel to each other along the first direction D1, and each cell active portion ACTC may have an end adjacent to the center of another adjacent cell active portion ACTC.

[0025] The WL word line may cross the cell active portion ACTC. The word line WL may be disposed in a groove GR1 formed in the device isolation layer 302 and the cell active portion ACTC. For example, the groove GR1 may be disposed around the word line WL. The word line WL may be disposed parallel to a second direction D2 that is not parallel to the first direction D1. The word line WL may be recessed in the substrate 301.

[0026] The word line WL may include a conductive material. A gate insulating layer 307 may be disposed between the word line WL and the inner surface of each groove GR1. For example, the gate insulating layer 307 may surround the word line WL and be in direct contact therewith. The groove GR1 may have a relatively large depth in the device isolation layer 302 and a relatively small depth in the active portion ACT. The gate insulating layer 307 may be formed of or include at least one of thermal oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. Each word line WL may have an uneven bottom surface. For example, the word line WL may have a circular bottom surface.

[0027] A first impurity region 3d may be disposed in each cell active portion ACTC arranged between each pair of word lines WL, and a pair of second impurity regions 3b may be disposed in opposite edge regions of each cell active portion ACTC. In an embodiment of the inventive concept, the first impurity region 3d and the second impurity region 3b may be doped with an n-type impurity. The first impurity region 3d may correspond to a common drain region, and the second impurity region 3b may correspond to a source region.

[0028] Each word line WL and its adjacent first and second impurity regions 3d and 3b may constitute a transistor. Since the word line WL is disposed in the groove GR1, in a given planar area, the channel region under the word line WL may have an increased channel length. Therefore, short-channel effects and the like can be suppressed.

[0029] The top surface of the word line WL may be set at a level lower than the top surface of the cell active portion ACTC. The word line covering pattern 310 may be disposed on each word line WL. The word line covering pattern 310 may be a linear pattern that extends along the length direction of the word line WL, and this length direction is a horizontal direction. The word line covering pattern 310 may cover the entire top surface of the word line WL thereunder. The word line covering pattern 310 may fill the groove GR1 on the word line WL. The word line covering pattern 310 may be formed of, for example, silicon nitride or include, for example, silicon nitride.

[0030] The interlayer insulating pattern 305 may be disposed on the substrate 301. The interlayer insulating pattern 305 may be formed of or include at least one of silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layer or multi-layer structure. When observed in a plan view, the interlayer insulating pattern 305 may be an island-shaped pattern spaced apart from each other along the horizontal direction. The interlayer insulating pattern 305 may cover two ends of two adjacent active portions ACT.

[0031] The upper portions of the substrate 301, the device isolation layer 302, and the word line covering pattern 310 may be partially recessed to form a first recessed region R1. A part of the side surface of the first recessed region R1 may be aligned with the side surface of the interlayer insulating pattern 305.

[0032] The bit line BL may be disposed on the interlayer insulating pattern 305. The bit line BL may at least partially cover the word line covering pattern 310 and the word line WL. The bit line BL may be disposed parallel to the third direction D3, and the third direction D3 is not parallel to the first direction D1 and the second direction D2. The bit line BL may include a bit line polysilicon pattern 330, a bit line diffusion prevention pattern 331, and a bit line metal-containing pattern 332 stacked on top of each other in sequence. The bit line polysilicon pattern 330 may be formed of doped polysilicon or include doped polysilicon. The bit line diffusion prevention pattern 331 may be formed of or include at least one of metal nitride materials (e.g., titanium nitride). The bit line metal-containing pattern 332 may be formed of or include at least one of metal materials (e.g., tungsten, titanium, and tantalum) or conductive metal nitride materials (e.g., titanium nitride, tantalum nitride, and tungsten nitride). The bit line covering pattern 337 may be disposed on each bit line BL. The bit line covering pattern 337 may be formed of an insulating material (e.g., silicon nitride) or include an insulating material (e.g., silicon nitride).

[0033] The bit line contact DC can be disposed in the first recessed region R1. And the bit line contact DC can perpendicularly cross the bit line BL. The bit line contact DC can be formed of doped or undoped polysilicon or include doped or undoped polysilicon. The side surface of the bit line contact DC can contact the side surface of the interlayer insulating pattern 305. Refer to Figure 1 , the side surface of the bit line contact DC contacting the interlayer insulating pattern 305 can be concave. The bit line contact DC can electrically connect the first impurity region 3d to the bit line BL.

[0034] The lower gap-fill insulating pattern 341 can be formed in the portion of the first recessed region R1 where the bit line contact DC is not filled. For example, the lower gap-fill insulating pattern 341 can be disposed adjacent to the side surface of the bit line contact DC. The lower gap-fill insulating pattern 341 can be formed of at least one of silicon oxide, silicon nitride, or silicon oxynitride or include at least one of silicon oxide, silicon nitride, or silicon oxynitride, and can have a single-layer or multi-layer structure.

[0035] The storage node contact BC can be disposed between a pair of adjacent bit lines BL. The storage node contacts BC can be spaced apart from each other. The storage node contact BC can include doped polysilicon. The storage node contact BC can have a concave top surface. An insulating pattern can be provided between the bit lines BL and between the storage node contacts BC.

[0036] The bit line spacer BS can be inserted between the bit line BL and the storage node contact BC. The bit line spacer BS can include a first sub-spacer 321 and a second sub-spacer 325, which are separated from each other by a gap region GP. The gap region GP can be referred to as an air gap region. The first sub-spacer 321 can cover the side surface of the bit line BL and the side surface of the bit line covering pattern 337. The second sub-spacer 325 can be disposed adjacent to the storage node contact BC. For example, the second sub-spacer 325 can cover the side surface of the storage node contact BC. The first and second sub-spacers 321 and 325 can include the same material. For example, the first and second sub-spacers 321 and 325 can be formed of silicon nitride or include silicon nitride.

[0037] The height of the upper end of the second sub-spacer 325 can be set at a level lower than the height of the upper end of the first sub-spacer 321. The first sub-spacer 321 can cover the side surface of the bit line contact DC and the side surface and bottom surface of the first recessed region R1. For example, the first sub-spacer 321 can be inserted between the bit line contact DC and the lower gap-fill insulating pattern 341, between the word line covering pattern 310 and the lower gap-fill insulating pattern 341, between the substrate 301 and the lower gap-fill insulating pattern 341, and between the device isolation layer 302 and the lower gap-fill insulating pattern 341.

[0038] The ohmic layer 309 of the storage node may be disposed on the storage node contact BC. The ohmic layer 309 of the storage node may include a metal silicide. The ohmic layer 309 of the storage node may be formed of or include, for example, cobalt silicide. The diffusion prevention pattern 311a may conformally cover the ohmic layer 309 of the storage node, the first and second spacers 321 and 325, and the bit line covering pattern 337. The diffusion prevention pattern 311a may include at least one of metal nitride materials (e.g., titanium nitride and tantalum nitride). The landing pad LP may be disposed on the diffusion prevention pattern 311a. The landing pad LP may be formed of or include at least one metal-containing material (e.g., tungsten). The upper portion of the landing pad LP may cover at least a part of the top surface of the bit line covering pattern 337 and may have a greater width than the storage node contact BC. The center of the landing pad LP may be offset from the center of the storage node contact BC along the second direction D2. A part of the bit line BL may vertically overlap the landing pad LP. The upper side surface of the bit line covering pattern 337 may overlap the landing pad LP and may be at least partially covered by the third spacer 327. Another upper side surface of the bit line covering pattern 337 may define a second recessed region R2.

[0039] The sum of the widths of the first spacer 321 and the third spacer 327 measured at the upper horizontal level of the bit line spacer BS may be less than the sum of the widths of the first spacer 321, the gap region GP, and the second spacer 325 measured at the lower horizontal level of the bit line spacer BS. The difference in the width sums increases the process margin in subsequent processes for forming the landing pad LP. Therefore, disconnection or open circuit between the landing pad LP and the storage node contact BC can be prevented.

[0040] The landing pad separation pattern LS may be disposed on the second recessed region R2. The upper end of the gap region GP may be defined by the landing pad separation pattern LS. For example, the landing pad separation pattern LS may at least partially cover the upper end of the gap region GP. The landing pad separation pattern may include at least one of a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, a silicon carbonitride layer, or a porous layer. The top surface of the landing pad separation pattern LS may be coplanar with the top surface of the landing pad LP. Between the bottom electrodes BE, the landing pad separation pattern LS may be covered with an etch stop layer EL. The etch stop layer EL may be formed of or include at least one of insulating materials (e.g., silicon nitride, silicon oxide, and silicon oxynitride).

[0041] The bottom electrode BE can be respectively disposed on the landing pad LP. The bottom electrode BE can be formed of or include at least one of doped polysilicon, a metal nitride material (e.g., titanium nitride), or a metal material (e.g., tungsten, aluminum, and copper). The bottom electrode BE can have a cylindrical shape, a hollow cylindrical shape, or a cup shape.

[0042] The upper side surfaces of the bottom electrodes BE disposed adjacent to each other can be connected to each other through the support pattern SP. The support pattern SP can include a first support pattern SP1 and a second support pattern SP2. The second support pattern SP2 can be located at a higher level than the first support pattern SP1 and can be spaced apart from each other in the vertical direction. The second support pattern SP2 can be in contact with the upper side surface of the bottom electrode BE. The first support pattern SP1 can be in contact with the middle side surface of the bottom electrode BE. The first and second support patterns SP1 and SP2 can be formed of or include an insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, or carbon silicon nitride). The first and second support patterns SP1 and SP2 can prevent the bottom electrode BE from falling or collapsing during the process of manufacturing a semiconductor device. In the present specification, the support pattern is shown as having a bilayer structure including the first and second support patterns SP1 and SP2, but the inventive concept is not limited to this example. For example, a semiconductor device can include one support pattern or include first to third support patterns located at different levels. However, for the sake of brevity, the following description will relate to a semiconductor device including the first and second support patterns SP1 and SP2.

[0043] The dielectric layer DE can be provided on the first support pattern SP1, the second support pattern SP2, and the bottom electrode BE. The dielectric layer DE can conformally cover the first support pattern SP1, the second support pattern SP2, and the bottom electrode BE. For example, the dielectric layer DE can be interposed between the bottom electrode BE and the upper electrode UE and between the second support pattern SP2 and the upper electrode UE. The dielectric layer DE can have the same crystal structure as the bottom electrode BE. For example, the dielectric layer DE can have a tetragonal structure. In an embodiment, the dielectric layer DE can be formed of or include at least one of a metal oxide material (e.g., HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2) or a perovskite dielectric material (e.g., SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, and PLZT), and can have a single-layer or multi-layer structure.

[0044] The upper electrode UE may be provided on the dielectric layer DE and cover the first support pattern SP1, the second support pattern SP2, and the bottom electrode BE. The bottom electrode BE, the dielectric layer DE, and the upper electrode UE may form a capacitor CAP. As an example, according to an embodiment of the inventive concept, the capacitor CAP may be used as a data storage element in a semiconductor device.

[0045] The upper electrode UE may include a metal layer ML, a first hydrogen diffusion barrier layer HBP1, and a first semiconductor layer SL1 that are sequentially stacked on the dielectric layer DE. The metal layer ML may conformally cover the dielectric layer DE. The metal layer ML may be formed of titanium nitride (TiN) or include titanium nitride (TiN).

[0046] The first hydrogen diffusion barrier layer HBP1 may be disposed on the metal layer ML. The first hydrogen diffusion barrier layer HBP1 may contact a part of the top surface of the metal layer. For example, a part of the bottom surface of the first hydrogen diffusion barrier layer HBP1 may contact the top surface of the metal layer ML. However, a part of the first hydrogen diffusion barrier layer HBP1 may not contact the metal layer ML. For example, a part of the bottom surface of the first hydrogen diffusion barrier layer HBP1 may be spaced apart from the metal layer ML and expose a part of the top surface of the metal layer ML. Here, a gap portion GAP may be formed between the metal layer ML and the first hydrogen diffusion barrier layer HBP1. The gap portion GAP may be a portion that is not filled with a conductive material or a dielectric material. In an embodiment, the first hydrogen diffusion barrier layer HBP1 may be formed of or include at least one of titanium (Ti), tungsten (W), titanium nitride (TiN), tungsten nitride (WN), titanium silicon nitride (TSN), or tungsten silicon nitride (WSN). In addition, as will be described with reference to Figures 4 to 7B the first hydrogen diffusion barrier layer HBP1 may prevent hydrogen atoms from diffusing from the conductive contact and the first interlayer insulating layer into the metal layer ML and the dielectric layer DE.

[0047] The first semiconductor layer SL1 may be disposed on the first hydrogen diffusion barrier layer HBP1. The first semiconductor layer SL1 may conformally cover the first hydrogen diffusion barrier layer HBP1. In an embodiment of the inventive concept, the first semiconductor layer SL1 may be formed of or include silicon germanium (SiGe). The conductive contact may be connected to the first semiconductor layer SL1.

[0048] The thickness of the first hydrogen diffusion barrier layer HBP1 may be less than the thickness of the first semiconductor layer SL1. In an embodiment of the inventive concept, the first hydrogen diffusion barrier layer HBP1 may have a thickness ranging from about to and the first semiconductor layer SL1 may have a thickness ranging from about to a thickness range, but the inventive concept is not limited to this example. The thickness of the first hydrogen diffusion barrier layer HBP1 may be variably changed as long as the first hydrogen diffusion barrier layer HBP1 can effectively prevent hydrogen atoms from diffusing into the metal layer ML and the dielectric layer DE.

[0049] Figure 2B and Figure 2C To illustrate Figure 2A a modified example of a semiconductor device and corresponding to Figure 1 cross-sectional views taken along lines A-A' and B-B'. To the extent that elements are not described in detail, it may be assumed that the element is at least similar to the corresponding element already described in the previous figures.

[0050] Referring to Figure 2B , in addition to the metal layer ML, the first hydrogen diffusion barrier layer HBP1, and the first semiconductor layer SL1, the upper electrode UE may further include a second hydrogen diffusion barrier layer HBP2 disposed on the first semiconductor layer SL1 and a second semiconductor layer SL2 disposed on the second hydrogen diffusion barrier layer HBP2.

[0051] The second hydrogen diffusion barrier layer HBP2 may conformally cover the first semiconductor layer SL1. The second hydrogen diffusion barrier layer HBP2 may include the same or a similar material as the first hydrogen diffusion barrier layer HBP1. For example, the second hydrogen diffusion barrier layer HBP2 may be formed of or include at least one of titanium (Ti), tungsten (W), titanium nitride (TiN), tungsten nitride (WN), titanium silicon nitride (TSN), or tungsten silicon nitride (WSN). The second hydrogen diffusion barrier layer HBP2 together with the first hydrogen diffusion barrier layer HBP1 may prevent hydrogen atoms from diffusing from the conductive contact and the first interlayer insulating layer into the metal layer ML and the dielectric layer DE.

[0052] The second semiconductor layer SL2 may be disposed on the second hydrogen diffusion barrier layer HBP2 and may conformally cover the second hydrogen diffusion barrier layer HBP2. The conductive contact may be connected to the second semiconductor layer SL2. For example, a first conductive contact (e.g., Figure 4 CT1 of

[0053] Reference Figure 2C, in addition to the metal layer ML, the first hydrogen diffusion barrier layer HBP1, and the first semiconductor layer SL1, the upper electrode UE may further include a plurality of hydrogen diffusion barrier layers and a plurality of semiconductor layers stacked on the first semiconductor layer SL1.

[0054] A plurality of hydrogen diffusion barrier layers and a plurality of semiconductor layers may be alternately stacked. For example, the second hydrogen diffusion barrier layer HBP2 may be stacked on the first semiconductor layer SL1, and the second semiconductor layer SL2 may be stacked on the second hydrogen diffusion barrier layer HBP2. In addition, the remaining hydrogen diffusion barrier layers and the remaining semiconductor layers may be alternately stacked to form the upper electrode UE.

[0055] The uppermost layer of the upper electrode UE may be the semiconductor layer SLT. For example, the semiconductor layer SLT, which is the uppermost layer among the semiconductor layers, may be disposed at a higher level than the hydrogen diffusion barrier layer HBPT, which is the uppermost layer among the hydrogen diffusion barrier layers. For example, one of the semiconductor layers SLT may be located at the uppermost level of the upper electrode UE. The uppermost semiconductor layer SLT may be stacked on the uppermost hydrogen diffusion barrier layer HBPT. A conductive contact may be connected to the uppermost semiconductor layer SLT. For example, Figure 4 the first conductive contact CT1 may be connected to the uppermost semiconductor layer SLT and may be spaced apart from the uppermost hydrogen diffusion barrier layer HBPT.

[0056] Each hydrogen diffusion barrier layer may include the same or similar material as the first hydrogen diffusion barrier layer HBP1. For example, each hydrogen diffusion barrier layer may be formed of or include at least one of titanium (Ti), tungsten (W), titanium nitride (TiN), tungsten nitride (WN), titanium silicon nitride (TSN), or tungsten silicon nitride (WSN). Together with the first hydrogen diffusion barrier layer HBP1, the hydrogen diffusion barrier layers may prevent hydrogen atoms from diffusing from the conductive contact and the first interlayer insulating layer into the metal layer ML and the dielectric layer DE.

[0057] Each semiconductor layer may include the same or similar material as the first semiconductor layer SL1. In an embodiment of the inventive concept, each semiconductor layer may be formed of or include silicon germanium.

[0058] Figure 3A is a cross-sectional view taken along lines A-A' and B-B' of Figure 1 to illustrate a semiconductor device according to an embodiment of the inventive concept. To the extent that an element is not described in detail, it may be assumed that the element is at least similar to the corresponding element already described in the previous figures.

[0059] Reference Figure 3A, the upper electrode UE may include a metal layer ML, a first semiconductor layer SL1, a first hydrogen barrier layer HBP1, and a second semiconductor layer SL2, which are sequentially stacked on the dielectric layer DE. For example, the second semiconductor layer SL2 may be stacked on the first hydrogen barrier layer HBP1 (which is stacked on the first semiconductor layer SL1). The upper electrode UE may fill the space between the bottom electrodes BE, the space between the first support pattern SP1 and the second support pattern SP2, and the space between the first support pattern SP1 and the etch stop layer EL. For example, the metal layer ML may conformally cover the dielectric layer DE, and the first semiconductor layer SL1 may cover at least a part of the top surface of the metal layer ML. The first semiconductor layer SL1 may fill the empty spaces located between the bottom electrodes BE, between the first and second support patterns SP1 and SP2, and between the first support pattern SP1 and the etch stop layer EL, and may not be filled with the metal layer ML. In an embodiment of the inventive concept, the first semiconductor layer SL1 may be formed of or include silicon germanium (SiGe).

[0060] The first hydrogen barrier layer HBP1 may conformally cover the first semiconductor layer SL1. In an embodiment of the inventive concept, the first hydrogen barrier layer HBP1 may be formed of or include at least one of titanium (Ti), tungsten (W), titanium nitride (TiN), tungsten nitride (WN), titanium silicon nitride (TSN), or tungsten silicon nitride (WSN).

[0061] The second semiconductor layer SL2 may conformally cover the first hydrogen barrier layer HBP1. The second semiconductor layer SL2 may include the same or similar material as the first semiconductor layer SL1, and may be formed of or include, for example, silicon germanium (SiGe). A conductive contact may be connected to the second semiconductor layer SL2.

[0062] Figure 3B and 3C To illustrate Figure 3A a modified example of the semiconductor device and corresponding to Figure 1 a cross-sectional view taken along lines A-A' and B-B'. To the extent that an element is not described in detail, it may be assumed that the element is at least similar to the corresponding element already described in the previous figures.

[0063] Referring to Figure 3B , in addition to the metal layer ML, the first semiconductor layer SL1, the first hydrogen barrier layer HBP1, and the second semiconductor layer SL2, the upper electrode UE may further include a second hydrogen barrier layer HBP2 disposed on the second semiconductor layer SL2 and a third semiconductor layer SL3 disposed on the second hydrogen barrier layer HBP2.

[0064] The second hydrogen diffusion barrier layer HBP2 can conformally cover the second semiconductor layer SL2. The second hydrogen diffusion barrier layer HBP2 can include the same or similar materials as the first hydrogen diffusion barrier layer HBP1. For example, the second hydrogen diffusion barrier layer HBP2 can be formed of or include at least one of titanium (Ti), tungsten (W), titanium nitride (TiN), tungsten nitride (WN), titanium silicon nitride (TSN), or tungsten silicon nitride (WSN). Together with the first hydrogen diffusion barrier layer HBP1, the second hydrogen diffusion barrier layer HBP2 can prevent hydrogen atoms from diffusing from the conductive contact and the first interlayer insulating layer into the metal layer ML and the dielectric layer DE.

[0065] The third semiconductor layer SL3 can be disposed on the second hydrogen diffusion barrier layer HBP2 and conformally cover the second hydrogen diffusion barrier layer HBP2. The conductive contact can be connected to the third semiconductor layer SL3. For example, the first conductive contact (e.g., Figure 6 CT1) can be connected to the third semiconductor layer SL3 and can be spaced apart from the second hydrogen diffusion barrier layer HBP2. The third semiconductor layer SL3 can include the same or similar materials as the first and second semiconductor layers SL1 and SL2. As an example, the third semiconductor layer SL3 can be formed of or include silicon germanium (SiGe). For example, each of the first to third semiconductor layers SL1, SL2, and SL3 can be formed of or include silicon germanium.

[0066] Referring to Figure 3C , in addition to the metal layer ML, the first hydrogen diffusion barrier layer HBP1, and the first semiconductor layer SL1, the upper electrode UE can further include a plurality of hydrogen diffusion barrier layers and a plurality of semiconductor layers stacked on the first semiconductor layer SL1.

[0067] A plurality of hydrogen diffusion barrier layers and a plurality of semiconductor layers can be alternately stacked. For example, the second hydrogen diffusion barrier layer HBP2 can be stacked on the second semiconductor layer SL2, and the third semiconductor layer SL3 can be stacked on the second hydrogen diffusion barrier layer HBP2. In addition, the remaining hydrogen diffusion barrier layers and the remaining semiconductor layers can be alternately stacked to form the upper electrode UE.

[0068] The uppermost layer in the upper electrode UE can be a semiconductor layer. For example, the semiconductor layer SLT, which is the uppermost one among the semiconductor layers, can be disposed at a higher level than the hydrogen diffusion barrier layer HBPT, which is the uppermost one among the hydrogen diffusion barrier layers. For example, one of the semiconductor layers SLT can be located at the top level of the upper electrode UE. The uppermost semiconductor layer SLT can be stacked on the uppermost hydrogen diffusion barrier layer HBPT. The conductive contact can be connected to the uppermost semiconductor layer SLT. For example, Figure 6 the first conductive contact CT1 can be connected to the uppermost semiconductor layer SLT and can be spaced apart from the uppermost hydrogen diffusion barrier layer HBPT.

[0069] Each hydrogen diffusion barrier layer may include a material that is the same as or similar to the first hydrogen diffusion barrier layer HBP1. For example, each hydrogen diffusion barrier layer may be formed of or include at least one of titanium (Ti), tungsten (W), titanium nitride (TiN), tungsten nitride (WN), titanium silicon nitride (TSN), or tungsten silicon nitride (WSN). Together with the first hydrogen diffusion barrier layer HBP1, the hydrogen diffusion barrier layer can prevent hydrogen atoms from diffusing from the conductive contact and the first interlayer insulating layer into the metal layer ML and the dielectric layer DE.

[0070] Each semiconductor layer may include a material that is the same as or similar to the first semiconductor layer SL1. For example, each semiconductor layer may be formed of or include silicon germanium.

[0071] Figure 4 To show a cross-sectional view of a semiconductor device taken along the C-C' line of Figure 1 of Figure 2A the semiconductor device. Figure 5A is a magnified cross-sectional view showing the Figure 4 "P1" portion of Figure 5B is a magnified cross-sectional view showing the Figure 4 "P2" portion of

[0072] Referring to Figure 1 and Figure 4 , the peripheral transistor PTR may be disposed on the peripheral region PER. The peripheral transistor PTR may include a peripheral gate insulating layer Gox, a peripheral gate electrode GE, a peripheral capping pattern GCP, and a peripheral spacer GS covering its side surfaces. The peripheral transistor PTR may further include a peripheral source / drain region 3p, which is formed in the substrate 301 and adjacent to both sides of the peripheral gate insulating layer Gox. The peripheral region PER may be at least partially covered by the first lower insulating layer 340. In an embodiment, the first lower insulating layer 340 may be formed of or include silicon oxide. The top surface of the first lower insulating layer 340 may be coplanar with the top surface of the peripheral capping pattern GCP. The second lower insulating layer 350 may be disposed on the first lower insulating layer 340. The second lower insulating layer 350 and the peripheral capping pattern GCP may include the same material as the bit line capping pattern 337. For example, the second lower insulating layer 350 and the peripheral capping pattern GCP may be formed of or include silicon nitride. The sum of the thickness of the second lower insulating layer 350 and the thickness of the peripheral capping pattern GCP may be substantially equal to the thickness of the bit line capping pattern 337.

[0073] The first peripheral contact plug PCT can penetrate through the first and second lower insulating layers 340 and 350 and can contact the peripheral source / drain region 3p. The first peripheral contact plug PCT may include a protruding portion extending to a level higher than that of the second lower insulating layer 350. The third lower insulating layer 360 may be disposed on the second lower insulating layer 350. The third lower insulating layer 360 may include the same material as the landing pad isolation pattern LS. A part of the third lower insulating layer 360 may extend into the second lower insulating layer 350. For example, the bottom surface of the third lower insulating layer 360 may be disposed at a level lower than the top end of the second lower insulating layer 350. The landing pad LP, the landing pad isolation pattern LS, the third lower insulating layer 360, and the first peripheral contact plug PCT may have top surfaces that are substantially coplanar with each other.

[0074] The first interlayer insulating layer IL1 may be disposed on the peripheral region PER and cover the third lower insulating layer 360. The first interlayer insulating layer IL1 may be formed of a hydrogen-containing insulating material. In an embodiment of the inventive concept, the first interlayer insulating layer IL1 may be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a porous insulating material (e.g., SiOCH), and may have a single-layer or multi-layer structure. The first interlayer insulating layer IL1 may at least partially cover the side surface UE_S of the upper electrode UE. The top surface of the first interlayer insulating layer IL1 may be coplanar with the top surface UE_U of the upper electrode UE.

[0075] The second interlayer insulating layer IL2 may be disposed on the upper electrode UE and the first interlayer insulating layer IL1. The second interlayer insulating layer IL2 may be formed of a hydrogen-containing insulating material. In an embodiment of the inventive concept, the second interlayer insulating layer IL2 may be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a porous insulating material (e.g., SiOCH), and may have a single-layer or multi-layer structure.

[0076] The third interlayer insulating layer IL3 may be disposed on the second interlayer insulating layer IL2. The third interlayer insulating layer IL3 may be formed of a hydrogen-containing insulating material. In an embodiment of the inventive concept, the third interlayer insulating layer IL3 may be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a porous insulating material (e.g., SiOCH), and may have a single-layer or multi-layer structure. An additional interlayer insulating layer or an additional passivation layer may be formed on the third interlayer insulating layer IL3. The additional interlayer insulating layer and the additional passivation layer may be formed of or include a hydrogen-containing insulating material.

[0077] In the cell array region CAR, the first conductive contact CT1 may penetrate the second interlayer insulating layer IL2 and may contact the upper electrode UE. The second conductive contact CT2 may penetrate the third interlayer insulating layer IL3 and may contact the first conductive contact CT1. Each of the first and second conductive contacts CT1 and CT2 may be formed of or include at least one of titanium nitride, tantalum nitride, tungsten nitride, tungsten, aluminum, or copper.

[0078] In the peripheral region PER, the first peripheral conductive contact PCT1 may penetrate the first and second interlayer insulating layers IL1 and IL2 and may contact each first peripheral contact plug PCT. The second peripheral conductive contact PCT2 may penetrate the third interlayer insulating layer IL3 and may contact the first peripheral conductive contact PCT1. Each of the first and second peripheral conductive contacts PCT1 and PCT2 may be formed of or include at least one of titanium nitride, tantalum nitride, tungsten nitride, tungsten, aluminum, or copper.

[0079] To reduce failures caused by silicon dangling bonds in the substrate 301, a heat treatment process may be performed after the formation of the passivation layer. As a result of the heat treatment process, hydrogen atoms in the passivation layer may diffuse into the substrate 301 through the conductive pattern and may be coupled to silicon atoms in the substrate 301. Accordingly, failures caused by silicon dangling bonds may be suppressed. The hydrogen atoms in the passivation layer may diffuse into the first and second conductive contacts CT1 and CT2 through the wires on the first and second conductive contacts CT1 and CT2. In addition, the hydrogen atoms in the passivation layer may diffuse into the first semiconductor layer SL1 via the first and second conductive contacts CT1 and CT2. In the case where the hydrogen atoms diffusing into the first semiconductor layer SL1 diffuse into the dielectric layer DE through the upper electrode UE, the mechanical / electrical characteristics of the semiconductor device may deteriorate. However, according to an embodiment of the present inventive concept, the first hydrogen diffusion barrier layer HBP1 may be provided in the upper electrode UE to contact and surround the metal layer ML, and thus, hydrogen atoms may be prevented from diffusing into the dielectric layer DE. In addition, although the first hydrogen diffusion barrier layer HBP1 is provided in the upper electrode UE, by reducing the thickness of the first semiconductor layer SL1, the total thickness of the upper electrode UE may be reduced. Accordingly, the lateral thickness of the upper electrode UE surrounding the bottom electrode BE may be reduced, and an additional bottom electrode may be provided on the cell array region CAR. Accordingly, the integration density of the semiconductor device may be increased.

[0080] Referring to Figure 4 and Figure 5A, a first hydrogen diffusion barrier layer HBP1, a first semiconductor layer SL1, and a second interlayer insulating layer IL2 may be sequentially disposed. For example, the second interlayer insulating layer IL2 may be disposed on the semiconductor layer SL1, and the semiconductor layer SL1 may be disposed on the first hydrogen diffusion barrier layer HBP1. A first conductive contact CT1 may be formed on the first semiconductor layer SL1 and pass through the second interlayer insulating layer IL2, and may be connected to the first semiconductor layer SL1. The first conductive contact CT1 may include a first barrier pattern BP1 and a first metal pattern MP1. The first barrier pattern BP1 may be in contact with the second interlayer insulating layer IL2 and the first semiconductor layer SL1, and the first metal pattern MP1 may be formed in the first barrier pattern BP1. For example, the second interlayer insulating layer IL2 may at least partially surround the first barrier pattern BP1. The first barrier pattern BP1 may be formed of or include at least one of metal nitride materials (e.g., titanium nitride, tantalum nitride, and tungsten nitride), and the first metal pattern MP1 may be formed of or include at least one of metal materials (e.g., tungsten, aluminum, and copper).

[0081] As described above, hydrogen atoms in the passivation layer may diffuse into the first conductive contact CT1, and hydrogen atoms in the second interlayer insulating layer IL2 may also diffuse into the first conductive contact CT1. The hydrogen atoms diffused into the first conductive contact CT1 may diffuse into the first semiconductor layer SL1.

[0082] The first conductive contact CT1 may be connected to the upper electrode UE and may be spaced apart from the first hydrogen diffusion barrier layer HBP1. For example, the first hydrogen diffusion barrier layer HBP1 may be disposed below the first conductive contact CT1 and the first semiconductor layer SL1. For example, the bottom surface CT1_L of the first conductive contact CT1 may be located at a level higher than the top surface of the first hydrogen diffusion barrier layer HBP1. Here, the bottom surface CT1_L of the first conductive contact CT1 may refer to the bottom surface of the first barrier pattern BP1. The first hydrogen diffusion barrier layer HBP1 may be located at a level lower than the first conductive contact CT1 and may prevent hydrogen atoms diffused into the first conductive contact CT1 from diffusing into the metal layer ML and the dielectric layer DE below the first hydrogen diffusion barrier layer HBP1. Therefore, deterioration of the electrical characteristics of the semiconductor device can be prevented.

[0083] Refer to Figure 4 and Figure 5B, the first hydrogen diffusion barrier layer HBP1, the first semiconductor layer SL1, and the first interlayer insulating layer IL1 may be arranged side by side. The first interlayer insulating layer IL1 may be in contact with the upper side surface UE_S of the upper electrode UE, and hydrogen atoms in the first interlayer insulating layer IL1 may diffuse into the first semiconductor layer SL1. The first hydrogen diffusion barrier layer HBP1 may be interposed between the first interlayer insulating layer IL1 and the metal layer ML and prevent hydrogen atoms in the first interlayer insulating layer IL1 from diffusing into the metal layer ML and the dielectric layer DE.

[0084] Figure 6 To show a cross-sectional view of a semiconductor device taken along Figure 1 the center line C-C'. Figure 3A of the semiconductor device. Figure 7A FIG. is a magnified cross-sectional view showing a part of P3 of Figure 6 the semiconductor device. Figure 7B FIG. is a magnified cross-sectional view showing a part of P4 of Figure 6 the semiconductor device. To some extent, elements are not described in detail, and it can be assumed that the element is at least similar to the corresponding element already described in the previous drawings.

[0085] Referring to Figure 6 and Figure 7A , the first semiconductor layer SL1, the first hydrogen diffusion barrier layer HBP1, the second semiconductor layer SL2, and the second interlayer insulating layer IL2 may be arranged in sequence. For example, the second interlayer insulating layer IL2 may be disposed on the second semiconductor layer SL2, the second semiconductor layer SL2 is disposed on the first hydrogen diffusion barrier layer HBP1, and the first hydrogen diffusion barrier layer HBP1 is disposed on the first semiconductor layer SL1. The first conductive contact CT1 may be formed on the second semiconductor layer SL2 and pass through the second interlayer insulating layer IL2 and may be connected to the second semiconductor layer SL2. The first conductive contact CT1 may include a first barrier pattern BP1 and a first metal pattern MP1. The first barrier pattern BP1 may be in contact with the second interlayer insulating layer IL2 and the second semiconductor layer SL2, and the first metal pattern MP1 may be formed in the first barrier pattern BP1.

[0086] The first conductive contact CT1 may be connected to the upper electrode UE and be spaced apart from the first hydrogen diffusion barrier layer HBP1. For example, the first hydrogen diffusion barrier layer HBP1 may be disposed below the first conductive contact CT1 and the second semiconductor layer SL2. For example, the bottom surface CT1_L of the first conductive contact CT1 may be at a level higher than the top surface of the first hydrogen diffusion barrier layer HBP1. Therefore, hydrogen atoms diffused through the first conductive contact CT1 can be prevented from diffusing into the first semiconductor layer, the metal layer ML, and the dielectric layer DE located below the first hydrogen diffusion barrier layer HBP1. Therefore, deterioration of the electrical characteristics of the semiconductor device can be prevented.

[0087] Referring toFigure 6 and 7B , the first semiconductor layer SL1, the first hydrogen barrier layer HBP1, the second semiconductor layer SL2, and the first interlayer insulating layer IL1 may be arranged side by side. The first interlayer insulating layer IL1 may be in contact with the upper side surface UE_S of the upper electrode UE, and hydrogen atoms in the first interlayer insulating layer IL1 may diffuse into the second semiconductor layer SL2. The first hydrogen barrier layer HBP1 may be interposed between the second semiconductor layer SL2 and the first semiconductor layer SL1, and may prevent hydrogen atoms diffused from the first interlayer insulating layer IL1 into the second semiconductor layer SL2 from being diffused into the first semiconductor layer SL1, the metal layer ML, and the dielectric layer DE.

[0088] Figures 8 to 13 For sequential illustration Figure 4 of a cross-sectional view of a manufacturing process of a semiconductor device.

[0089] Reference Figure 8 , a substrate 301 having a cell array region CAR and a peripheral region PER may be provided. Figure 4 The word line WL, the bit line BL, the peripheral transistor PTR, the bottom electrode BE, and the first and second support patterns SP1 and SP2 may be formed on the substrate 301.

[0090] A via hole PH may be formed between adjacent bottom electrodes BE. As an example, each via hole PH may have a circular shape, and may be provided between three adjacent bottom electrodes BE and expose a part of the side surface of each of the three bottom electrodes BE. However, the inventive concept is not limited to this example, and via holes PH may be provided in various shapes between a plurality of bottom electrodes BE.

[0091] Reference Figure 9 , the dielectric layer DE and the metal layer ML may be sequentially formed on the substrate 301. For example, the dielectric layer DE may be disposed closer to the substrate and under the metal layer ML. The formation of the dielectric layer DE and the metal layer ML may be performed using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process. The dielectric layer DE and the metal layer ML may conformally cover the first support pattern SP1, the second support pattern SP2, and the bottom electrode BE. The dielectric layer DE and the metal layer ML may fill a part of the via hole PH between the bottom electrodes BE, and a remaining portion of the via hole PH that may not be filled with the dielectric layer DE and the metal layer ML may form a gap portion GAP. The gap portion GAP may be an empty region not filled with the dielectric layer DE and the metal layer ML.

[0092] Referring to Figure 10, a first hydrogen diffusion barrier layer HBP1 can be formed on the metal layer ML. The formation of the first hydrogen diffusion barrier layer HBP1 can be performed using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process. The first hydrogen diffusion barrier layer HBP1 can only fill a part of the vias PH. The first hydrogen diffusion barrier layer HBP1 may not fill the entire gap portion GAP between the metal layers ML. Therefore, the gap portion GAP can remain in the vias PH even after the formation of the first hydrogen diffusion barrier layer HBP1. For example, a part of the bottom surface of the first hydrogen diffusion barrier layer HBP1 may not contact the top surface of the metal layer ML. Thus, the top surface of the metal layer ML may include an exposed portion not covered by the first hydrogen diffusion barrier layer HBP1.

[0093] Referring to Figure 11 , a first semiconductor layer SL1 can be formed on the first hydrogen diffusion barrier layer HBP1. The formation of the first semiconductor layer SL1 can be performed using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process.

[0094] Reference Figure 12 , a mask pattern MK can be formed on the first semiconductor layer SL1. The mask pattern MK can at least partially cover the top surface and the side surface of the first semiconductor layer SL1. The mask pattern MK can be a photoresist pattern or a spin-on hard mask (SOH) pattern. The mask pattern MK can be formed to cover the cell array region CAR and expose the peripheral region PER. The dielectric layer DE, the metal layer ML, and the first semiconductor layer SL1 can be removed from the peripheral region PER using the mask pattern MK as an etching mask to form the upper electrode UE and expose the third lower insulating layer 360. Then, the mask pattern MK can be removed by an additional process.

[0095] Referring to Figure 13 , a first interlayer insulating layer IL1 can be formed on the substrate 301. The first interlayer insulating layer IL1 can be formed to at least partially cover the top surface and the side surface of the upper electrode UE and the peripheral region PER. Then, a polishing process (e.g., a chemical mechanical polishing (CMP) process) can be performed on the top surface of the first interlayer insulating layer IL1. As a result of the polishing process, the top surface of the upper electrode UE can be exposed to the outside and can have a flat or planarized shape. Here, the top surface of the upper electrode UE can have a substantially flat shape, and the side surface of the upper electrode UE can have a non-flat shape. A second interlayer insulating layer IL2 can be formed on the first interlayer insulating layer IL1. Then, the first and second conductive contacts CT1 and CT2 and the first peripheral conductive contact PCT1 can be formed.

[0096] Figure 14 andFigure 15 Cross-sectional views of a manufacturing process of a semiconductor device shown successively Figure 6 are presented.

[0097] Referring to Figure 9 and Figure 14 , a first semiconductor layer SL1 may be formed on a metal layer ML. The formation of the first semiconductor layer SL1 may be performed using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process. The first semiconductor layer SL1 may fill an unfilled portion of a via hole PH. For example, the first semiconductor layer SL1 may fill an entire gap portion GAP between the metal layers ML. In addition, the first semiconductor layer SL1 may fill a remaining space between the first and second support patterns SP1 and SP2 and a remaining space between the first support pattern SP1 and an etch stop layer EL.

[0098] Referring to Figure 15 , a first hydrogen diffusion barrier layer HBP1 and a second semiconductor layer SL2 may be sequentially formed on the first semiconductor layer SL1. Each of the first hydrogen diffusion barrier layer HBP1 and the second semiconductor layer SL2 may be formed by an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process. Thereafter, a mask pattern may be formed as described previously with reference to Figures 12 to 14 . Then, the first semiconductor layer SL1, the first hydrogen diffusion barrier layer HBP1, and the second semiconductor layer SL2 on a peripheral region PER may be removed using the mask pattern to form an upper electrode. In addition, first and second interlayer insulating layers may be sequentially formed on the upper electrode.

[0099] According to an embodiment of the inventive concept, a hydrogen diffusion barrier layer may be disposed in the upper electrode and prevent hydrogen atoms in the interlayer insulating layer and the conductive contact from diffusing into the lower electrode and the dielectric layer. Accordingly, deterioration of electrical characteristics of the semiconductor device may be prevented.

[0100] In addition, although the hydrogen diffusion barrier layer is disposed on the bottom electrode, the total thickness of the upper electrode may be reduced by reducing the thickness of the semiconductor layer. This makes it possible to improve the electrical characteristics of the semiconductor device.

[0101] Although example embodiments of the inventive concept have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and details may be made thereto without departing from the spirit and scope of the appended claims.

[0102] Cross-reference to related applications

[0103] This patent application claims priority to Korean Patent Application No. 10-2023-0187425, filed with the Korean Intellectual Property Office on December 20, 2023, the disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device comprising: substrate; A bottom electrode, disposed on the substrate; a support pattern, when viewed in a plan view, disposed between the bottom electrodes; an upper electrode, covering the bottom electrode and the support pattern; a dielectric layer disposed between the bottom electrode and the upper electrode and between the support pattern and the upper electrode; and a first conductive contact connected to said upper electrode, The upper electrode comprises a metal layer, a first hydrogen diffusion barrier layer and a first semiconductor layer sequentially stacked on the dielectric layer, and The first conductive contact is spaced apart from the first hydrogen diffusion barrier layer. 2 . The semiconductor device according to claim 1 , wherein the first hydrogen diffusion barrier layer comprises at least one of titanium, tungsten, titanium nitride, tungsten nitride, titanium silicon nitride, and tungsten silicon nitride. 3 . The semiconductor device according to claim 1 , wherein the first semiconductor layer comprises silicon germanium (SiGe). 4 . The semiconductor device according to claim 1 , wherein the upper electrode further comprises a second hydrogen diffusion barrier layer disposed on the first semiconductor layer and a second semiconductor layer disposed on the second hydrogen diffusion barrier layer. 5 . The semiconductor device according to claim 4 , wherein each of the first semiconductor layer and the second semiconductor layer comprises silicon germanium.

6. The semiconductor device according to claim 1, wherein the upper electrode further comprises a plurality of hydrogen diffusion barrier layers and a plurality of semiconductor layers alternately stacked on the first semiconductor layer, and Wherein the first conductive contact is connected to the uppermost one of the semiconductor layers. 7 . The semiconductor device according to claim 6 , wherein each of the semiconductor layers comprises silicon germanium (SiGe). 8 . The semiconductor device according to claim 1 , wherein a thickness of the first hydrogen diffusion barrier layer is smaller than a thickness of the first semiconductor layer. 9 . The semiconductor device according to claim 1 , wherein a bottom surface of the first conductive contact is disposed at a higher level than a top surface of the first hydrogen diffusion barrier layer.

10. The semiconductor device according to claim 1, further comprising: a first interlayer insulating layer covering side surfaces of the upper electrode; and a second interlayer insulating layer disposed on a top surface of the upper electrode and a top surface of the first interlayer insulating layer, The first conductive contact penetrates the second interlayer insulating layer and contacts the first semiconductor layer. 11 . The semiconductor device according to claim 10 , wherein the first interlayer insulating layer and the second interlayer insulating layer include a hydrogen-containing insulating material.

12. A semiconductor device comprising: substrate; a bottom electrode on the substrate; a support pattern, when viewed in a plan view, disposed between the bottom electrodes; an upper electrode, covering the bottom electrode and the support pattern; and a dielectric layer provided between the bottom electrode and the upper electrode and between the support pattern and the upper electrode, The upper electrode comprises a metal layer, a first semiconductor layer, a first hydrogen diffusion barrier layer and a second semiconductor layer sequentially stacked on the dielectric layer, and Wherein, each of the first semiconductor layer and the second semiconductor layer includes silicon germanium. 13 . The semiconductor device according to claim 12 , wherein the first hydrogen diffusion barrier layer comprises at least one of titanium, tungsten, titanium nitride, tungsten nitride, titanium silicon nitride, and tungsten silicon nitride.

14. The semiconductor device according to claim 12, wherein the upper electrode further comprises a second hydrogen diffusion barrier layer disposed on the second semiconductor layer and a third semiconductor layer disposed on the second hydrogen diffusion barrier layer, and The third semiconductor layer includes silicon germanium (SiGe).

15. The semiconductor device according to claim 12, wherein the upper electrode further comprises a plurality of hydrogen diffusion barrier layers and a plurality of semiconductor layers alternately stacked on the second semiconductor layer, wherein an uppermost one of the semiconductor layers is located at a higher level than an uppermost one of the hydrogen diffusion barrier layers, and Each of the semiconductor layers includes silicon germanium (SiGe).

16. The semiconductor device according to claim 12, further comprising: a first interlayer insulating layer covering the side surface of the upper electrode; A second interlayer insulating layer disposed on the upper electrode and the first interlayer insulating layer; and a first conductive contact penetrating the second interlayer insulating layer and connected to the second semiconductor layer, Wherein a bottom surface of the first conductive contact is disposed at a higher level than a top surface of the first hydrogen diffusion barrier layer. 17 . The semiconductor device according to claim 16 , wherein each of the first interlayer insulating layer and the second interlayer insulating layer includes a hydrogen-containing insulating material.

18. A semiconductor device comprising: A substrate including a cell array region and a peripheral region; A word line, disposed on the cell array region of the substrate; a first impurity region disposed in a portion of the substrate on one side of the word line; a second impurity region disposed in a portion of the substrate on an opposite side of the word line; A bit line, disposed on the cell array region of the substrate, intersecting the word line and connected to the first impurity region; a bottom electrode disposed on the cell array region of the substrate and connected to the second impurity region; a support pattern, when viewed in a plan view, disposed between the bottom electrodes; an upper electrode, covering the bottom electrode and the support pattern; a dielectric layer disposed between the bottom electrode and the upper electrode and between the support pattern and the upper electrode; and a first conductive contact coupled to the upper electrode, The upper electrode comprises a metal layer, a first hydrogen diffusion barrier layer and a first semiconductor layer sequentially stacked on the dielectric layer, and The first conductive contact is spaced apart from the first hydrogen diffusion barrier layer and is in contact with the first semiconductor layer. 19 . The semiconductor device according to claim 18 , wherein the first hydrogen diffusion barrier layer comprises at least one of titanium, tungsten, titanium nitride, tungsten nitride, titanium silicon nitride, and tungsten silicon nitride.

20. The semiconductor device according to claim 18, further comprising: a first interlayer insulating layer covering side surfaces of the upper electrode; and a second interlayer insulating layer on the upper electrode and the first interlayer insulating layer, Wherein a bottom surface of the first conductive contact is located at a higher level than a top surface of the first hydrogen diffusion barrier layer.

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