Read-only memory array, integrated circuit device and manufacturing method thereof

Abstract

A read-only memory (ROM) array includes first to fourth metal lines aligned with first to fourth active regions in a first direction and located in a first front side metal layer of a semiconductor substrate in first to fourth rows of four ROM bits positioned on a front side of the semiconductor substrate along respective first to fourth active regions, and fifth to eighth metal lines which align the first to fourth active regions in the first direction and are located on the first backside metal layer of the semiconductor substrate. The first to fourth metal lines include one of a bit line or a source line of the ROM array, and the fifth to eighth metal lines include the other of the bit line or the source line of the read-only memory array. The embodiment of the invention also discloses an integrated circuit device and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to a read-only memory array, an integrated circuit device, and a method of manufacturing the same. Background Art

[0002] The continuous trend of miniaturization of integrated circuits (ICs) has led to devices that are gradually smaller, consume less power, but provide more functions at higher speeds than earlier technologies. This miniaturization is achieved through design and manufacturing innovations associated with increasingly stringent specifications. Various electronic design automation (EDA) tools are used to generate, modify, and verify the design of semiconductor devices while ensuring compliance with IC structure design and manufacturing specifications. Summary of the Invention

[0003] According to one aspect of an embodiment of the present application, a read-only memory (ROM) array is provided, including: a first row to a fourth row of four ROM bits, positioned along respective first to fourth active regions on a front side of a semiconductor substrate; first to fourth metal lines, aligned with the first to fourth active regions in a first direction and located in a first front-side metal layer of the semiconductor substrate; and fifth to eighth metal lines, aligned with the first to fourth active regions in the first direction and located in a first back-side metal layer of the semiconductor substrate, wherein the first to fourth metal lines include one of a bit line or a source line of the ROM array, and the fifth to eighth metal lines include the other of the bit line or the source line of the ROM array.

[0004] According to another aspect of an embodiment of the present application, an integrated circuit (IC) device is provided, including: first to fourth active regions, extending in a semiconductor substrate between a first pseudo-gate structure and a second pseudo-gate structure, wherein each of the first to fourth active regions includes five source / drain (S / D) structures; a plurality of gate electrodes, extending through the first to fourth active regions, wherein the plurality of gate electrodes are offset from each of the first pseudo-gate structure and the second pseudo-gate structure by a gate pitch, and a distance between the first pseudo-gate structure and the second pseudo-gate structure corresponds to five times the gate pitch; first to fourth metal lines, aligned with the first to fourth active regions in a first direction and located in a first front-side metal layer of the semiconductor substrate; fifth to eighth metal lines, aligned with the first to fourth active regions in the first direction and located in a first back-side metal layer of the semiconductor substrate; a front-side via structure, located between a first S / D structure of the five S / D structures of each of the first to fourth active regions and one of the first to fourth metal lines; and a back-side via structure, located between a second S / D structure of the five S / D structures of each of the first to fourth active regions and one of the fifth to eighth metal lines.

[0005] According to another aspect of embodiments of the present application, a method of manufacturing an integrated circuit (IC) device is provided. The method includes: forming a first active region to a fourth active region on a front side of a semiconductor substrate; forming a first metal-like definition (MD) section to a fifth MD section on each of the first active region to the fourth active region; constructing a plurality of gate structures, wherein constructing the plurality of gate structures includes: constructing a first dummy gate structure and a second dummy gate structure above an end point of each of the first active region to the fourth active region; and constructing a plurality of gate electrodes extending across the first active region to the fourth active region, wherein the plurality of gate structures include a gate pitch, and the first dummy gate structure and the second dummy gate structure are spaced apart by a distance corresponding to five times the gate pitch; forming a front-side via structure on the MD section among the five MD sections on each of the first active region to the fourth active region; forming a first metal wire to a fourth metal wire in a first front-side metal layer of the semiconductor substrate and covering the first active region to the fourth active region, and one of the first metal wire to the fourth metal wire is formed on the front-side via structure; forming a back-side via structure, the back-side via structure straddling the MD section among the five MD sections on each of the first active region to the fourth active region on one of the first active region to the fourth active region; and forming a fifth metal wire to an eighth metal wire in a first back-side metal layer of the semiconductor substrate and below the first active region to the fourth active region, and one of the fifth metal wire to the eighth metal wire is formed on the back-side via structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for the sake of clear discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1A and Figure 1B are a front view plan view and a layout view of the front and back sides of an IC device according to some embodiments.

[0008] Figure 2A and Figure 2B are a front view plan view and a layout view of the front and back sides of an IC device according to some embodiments.

[0009] Figure 3A and Figure 3B are a front view plan view and a layout view of the front and back sides of an IC device according to some embodiments.

[0010] Figure 4A and Figure 4B are a front view plan view and a layout view of the front and back sides of an IC device according to some embodiments.

[0011] Figure 5is a side view of an IC device and a layout diagram according to some embodiments.

[0012] Figure 6 is a schematic diagram and a layout diagram of an IC device according to some embodiments.

[0013] Figure 7A and Figure 7B are a front view and a back view plan of an IC device and a layout diagram according to some embodiments.

[0014] Figure 8A and Figure 8B are a front view and a back view plan of an IC device and a layout diagram according to some embodiments.

[0015] Figure 9A and Figure 9B are a front view and a back view plan of an IC device and a layout diagram according to some embodiments.

[0016] Figure 10A and Figure 10B are a front view and a back view plan of an IC device and a layout diagram according to some embodiments.

[0017] Figure 11 is a schematic diagram and a layout diagram of an IC device according to some embodiments.

[0018] Figure 12A and Figure 12B are a front view and a back view plan of an IC device and a layout diagram according to some embodiments.

[0019] Figure 13A and Figure 13B are a front view and a back view plan of an IC device and a layout diagram according to some embodiments.

[0020] Figure 14 is a flowchart of a method for manufacturing an IC according to some embodiments.

[0021] Figure 15 is a flowchart of a method for generating an IC layout diagram according to some embodiments.

[0022] Figure 16 is a block diagram of an IC layout diagram generation system according to some embodiments.

[0023] Figure 17 is a block diagram of an IC manufacturing system and its related IC manufacturing process according to some embodiments. DETAILED DESCRIPTION

[0024] The following disclosure provides many different embodiments or examples for implementing the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0025] In addition, for ease of description, spatial relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spatial relationship terms are intended to include different orientations of the device during use or operation. The device may be positioned otherwise (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used herein may be interpreted accordingly.

[0026] In various embodiments, an integrated circuit (IC) device and corresponding layout and manufacturing method include four rows of four read-only memory (ROM) bits of a ROM array located on four active regions, a first metal line above the active regions in a first front-side metal layer, and a second metal line below the active regions in a first back-side metal layer. The first metal line includes one of the bit lines or source lines of the ROM array, and the second metal line includes the other of the bit lines or source lines of the ROM array.

[0027] Compared with other methods, for example, methods where both the bit lines and source lines are located in the front-side metal layer, the IC device can thus have a smaller total area and a larger width of the bit lines and source lines, thereby reducing resistance.

[0028] As described below, according to various embodiments, Figure 1A / Figure 1B 、 Figure 2A / Figure 2B 、 Figure 3A / Figure 3B and Figure 4A / Figure 4B depict front and back plan views of NOR-type ROM IC device / layout 100 - 400, Figure 5 is a side view of the IC device / wiring diagram, Figure 6 is a schematic diagram 600 of the IC, Figure 7A / Figure 7B 、Figure 8A / Figure 8B 、 Figure 9A / Figure 9B and Figure 10A / Figure 10B FIGS. 700 - 1000 are plan views of the front and back sides of a NOR - type ROM integrated circuit device / layout corresponding to the programming states of schematic diagram 600, Figure 11 FIG. 1100 is a schematic diagram of an IC device, Figure 12A / Figure 12B and Figure 13A / Figure 13B FIGS. 1200 and 1300 are plan views of the front and back sides of a NOR - type ROM IC device / layout corresponding to schematic diagram 1100, Figure 14 FIG. 1400 is a flow chart of a method for fabricating a NOR - type ROM integrated circuit based on one or more of the corresponding ones of IC layout diagrams 100 - 400, 700 - 1000, 1200, or 1300, using, for example, a system 1600 discussed below with reference to Figure 16 and / or an IC manufacturing process associated with an IC manufacturing system 1700 discussed below with reference to Figure 17 For ease of illustration, each figure herein, such as

[0029] is simplified. These figures are views of IC structures, devices, and layout diagrams, including and excluding various features to facilitate the discussion below. In various embodiments, in addition to the features shown in Figures 1A - 5 、 Figures 7A - 10B 、 Figures 12A to 13B an IC structure, device, and / or layout diagram also includes one or more components corresponding to a power distribution structure, metal interconnects, contacts, vias, gate structures, source / drain (S / D) structures, body connections, or other transistor elements, isolation structures, etc. Figures 1A - 5 、 Figures 7A - 10B 、 Figures 12A to 13B In each of the IC device / layouts

[0030] 、 Figures 1A - 5 、 Figures 7A - 10B 、 Figures 12A to 13B reference numerals denote IC device components and IC layout features for at least partially defining the corresponding IC device components during the manufacturing process, such as the method 1400 discussed below with reference to Figure 14 and / or the method discussed below with reference to Figure 17The IC manufacturing processes discussed in relation to the IC manufacturing system 1700. Accordingly, each of the IC device / layouts 100-400, 700-1000, 1200, and 1300 represents a view of the IC layouts 100-400, 700-1000, 1200, 1300 and the corresponding IC devices 100-400, 700-1000, 1200, 1300.

[0031] Figure 1A and Figure 1B depict the corresponding front and back plane views of the IC device / layout 100 in the X and Y directions according to some embodiments, and keys corresponding to the features discussed below. Figure 2A and Figure 2B depict the corresponding front and back plane views of the IC device / layout 200 in the X and Y directions according to some embodiments. The IC device / layouts 100 and 200 (also referred to as ROM arrays 100 and 200 in some embodiments) include most of the common features except for bit lines BL0-BL3 and source line VSS, as described below.

[0032] Each of the IC device / layouts 100 and 200 includes active regions / areas A0-A3 extending in the X direction. In some embodiments, based on the IC device / wiring diagram 100 or 200, there are no additional active regions / areas between the active regions / areas A0-A3, which are referred to as adjacent active regions / areas.

[0033] Each active region / area A0-A3 extends from a pseudo-gate region / structure D1 to a pseudo-gate region or structure D2. Each pseudo-gate region / structure D2 extends in the Y direction, and gate regions and gate structures G0-G5 extend in the Y direction between the pseudo-gate regions / structures D1 and D2. Each of the gate regions / structures G0 and G1 intersects / overlaps with each of the active regions / areas A0-A3, each of the gate regions / structures G2 and G3 crosses / overlaps with each of the active regions / areas A0 and A1, and each of the gate regions / structures G4 and G5 crosses / overlaps with each of the active regions / areas A2 and A3.

[0034] The gate region / structure G0 is offset by a pitch CPP in the positive X direction from the dummy gate region / structure D1, which is also referred to as the contact poly pitch CPP in some embodiments. The gate region / structure G1 is offset by a pitch CPP in the positive X direction from the gate region / structure G0. Each of the gate regions / structures G2 and G4 is offset by a pitch CPP in the positive X-axis direction from the gate region / structure G1. The gate region / structure G3 is offset by a pitch CPP in the positive X direction from the gate region / structure G2. The gate region / structure G5 is offset by a pitch CPP in the positive X direction from the gate region / structure G4. The dummy gate region / structure D2 is offset by a pitch CPP in the positive X direction from each of the gate regions and structures G3 and G5.

[0035] Each of the IC layout diagrams 100 and 200 includes a boundary PR, which is also referred to as the layout routing boundary PR or the pr boundary (prBoundary) PR in some embodiments, corresponding to a closed region in the IC layout diagram that can be used for routing signal and power connections, such as as part of an automated placement and routing (APR) algorithm. The dummy gate regions D1 and D2 extend along the vertical portion of the boundary PR.

[0036] Each of the IC layout diagrams 100 and 200 also includes a cut gate region CG that extends in the X direction (a single instance is marked in Figure 1A and Figure 2A for clarity). The location where the cut gate region CG intersects the gate region in the IC layout diagram 100 corresponds to the isolation structure ISO in the corresponding IC device 100 (a single instance is marked in Figure 1A and Figure 2A for clarity).

[0037] Each of the gate regions / structures G0 and G1 has two endpoints at an instance of the cut gate region CG, which extend along the horizontal portion of the boundary PR and correspond to two instances of the isolation structure ISO. The gate regions / structures G2 and G4 have a single endpoint at the same instance of the cut gate region CG that corresponds to a single instance of the isolation structure ISO. The gate regions / structures G3 and G5 have a single endpoint at the same instance of the cut gate region CG that corresponds to a single instance of the isolation structure ISO.

[0038] Near each location where the gate regions / structures G0 - G5 intersect / overlap with the active region / areas A0 - A3, the corresponding active region / areas A0 - A3 include two instances of source / drain (S / D) region / structure SD and an overlying metal-like defining (MD) region / section MD (a single instance in Figure 1A and Figure 2A is collectively referred to as SD / MD for clarity). As used herein, the term S / D region / structure can refer to the source or the drain individually or collectively, depending on the context.

[0039] Each of the IC device / layout diagrams 100 and 200 includes front-side metal lines extending in the X direction in the first front-side metal layer and intersecting / overlapping with the corresponding active regions / zones A0 - A3, also referred to as back-side metal regions / sections in some embodiments, and back-side metal lines extending in the X direction in the first back-side metal layer and intersecting / lying beneath the corresponding active regions / zones A0 - A3. Based on at least a portion of the front-side or back-side metal lines being aligned with at least one portion of a given active region in the Z direction ( Figures 1A - 2B not shown in the figure) perpendicular to each of the X and Y directions, the front-side or back-side metal lines are considered to be above / below the given active regions A0 - A3.

[0040] As Figures 1A - 2B shown, the IC device / layout diagram 100 includes front-side metal lines including bit lines BL0 - BL3 and back-side metal lines including four instances of the source line VSS, and the IC device / layout diagram 200 includes front-side metal lines including four instances of the source line VSS and back-side metal lines including bit lines BL0 - BL3.

[0041] A source line, such as the source line VSS, is a metal line electrically connected to a power reference node (not shown) of an IC circuit (such as a ROM circuit including the ROM array 100 or 200), and is thus configured to receive a power reference voltage, such as VSS or ground.

[0042] A bit line, such as the bit lines BL0 - BL3, is a metal line electrically connected to a signal source and / or selection circuit (not shown) of an IC circuit (such as a ROM circuit including the ROM array 100 or 200), and is thus configured to receive one or more bias signals, such as a bias voltage, as part of the read operation of the ROM array.

[0043] In some embodiments, one or both of the IC device / layout diagrams 100 or 200 include one or more additional metal lines or regions / sections (not shown), such as signal lines or power pole lines, which extend in the X direction in the first front-side and / or back-side metal layer between the corresponding instances of the bit lines BL0 - BL3 and / or the source line VSS.

[0044] Via regions / structures VG (for clarity, Figure 1A and Figure 2AThe metal region / segment WL0 intersects / overlaps with the gate region / structure G0 and the corresponding via region / structure VG, the metal region / segment WL1 intersects / overlaps with the gate region / structure G1 and the corresponding via region / structure VG, the metal region / segment WL2 intersects / overlaps with the gate region / structure G4 and the corresponding via region / structure VG, and the metal region / segment WL3 intersects / overlaps with the gate region / structure G3 and the corresponding via region / structure VG.

[0045] Each of the metal regions / segments WL0, WL1, WL2, and WL3 and the corresponding via region / structure VG is part of a corresponding word line (collectively referred to as word lines WL) electrically connected to the corresponding gate region / structure G0, G1, G3, or G4. In some embodiments, metal regions / segments WL0-WL3 are referred to as word lines WL0-WL3.

[0046] A word line, such as word lines WL0-WL3, is a metal line electrically connected to a signal source and / or selection circuit (not shown) of an IC circuit (e.g., a ROM circuit including ROM array 100 or 200), and is thereby configured to receive one or more activation signals, such as an activation voltage, as part of a read operation of the ROM array.

[0047] In some embodiments, for example, the following Figures 11 - 13B In the IC device / layout 1200 or 1300 discussed, the gate region / structure G2 extends beyond the IC device / layout 100 or 200 in the positive Y direction ( Figures 1A - 2B ), an instance of metal region / segment WL2 intersects / overlaps with an extension of gate region / structure G2 and a corresponding via region / structure VG, and / or gate region / structure G5 is in the negative Y direction ( Figures 1A - 2B 1 and 200 ), an instance of metal region / segment WL3 intersects / overlaps an extended portion of gate region / structure G5 and its corresponding via region / via.

[0048] The active region / area, such as active regions / areas A0 - A3, is a region in an IC layout included in a manufacturing process, also known as oxide diffusion or definition (OD), as part of defining an active region directly in a semiconductor substrate or in an n-well or p-well region / area (not shown for clarity), where one or more IC device components, such as S / D structures, are formed. In some embodiments, the active region is the n-type or p-type active region of a planar transistor, a FinFET, or a GAA transistor. In various embodiments, the active region (structure) includes semiconductor materials (such as silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), etc.), dopant materials (such as boron (B), phosphorus (P), arsenic (As), gallium (Ga), or one or more of another suitable material).

[0049] In some embodiments, the active region is a region in an IC layout included in a manufacturing process, as part of defining a nanosheet structure, e.g., a continuous volume of one or more layers of semiconductor material with n-type or p-type doping. In various embodiments, a single nanosheet layer includes a single layer or multiple layers of a given semiconductor material.

[0050] In the embodiments discussed herein, each instance of the active region / area A0 - A3 is the same in the n-type or p-type active region / area, e.g., a p-type active region / area corresponding to an n-type ROM bit, as described below.

[0051] The S / D region / structure, such as S / D region or structure SD, is a region in an IC layout as part of defining the S / D structure, also known as a semiconductor structure in some embodiments, configured to have a doping type opposite to that of the corresponding active region. In some embodiments, the S / D region / structure is configured to have a lower resistivity than an adjacent channel component, e.g., a part of the corresponding active region / area of a planar FET, a fin structure of a FinFET, or a gate structure of a GAA transistor. In some embodiments, the S / D region / structure includes one or more portions with a doping concentration greater than one or more doping concentrations present in the corresponding channel feature. In some embodiments, the S / D region / structure includes an epitaxial region of semiconductor material, such as Si, SiGe, and / or silicon carbide SiC.

[0052] The MD region / section, such as MD region / section MD, is a conductive region in the IC layout included in the manufacturing process, and is part of the MD section in and / or on the semiconductor substrate, also referred to as a conductive section or MD wire or trace. In some embodiments, the MD section includes a portion of at least one metal layer (such as a contact layer) that overlies and contacts the substrate and has a thickness small enough to form an insulating layer between the MD section and the overlying metal layer (such as the first metal layer). In various embodiments, the MD section includes one or more of copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al) or another metal or material suitable for providing a low-resistance electrical connection between IC structural elements, i.e., a resistance level below a predetermined threshold that corresponds to one or more tolerance levels for resistance-based circuit performance effects.

[0053] In various embodiments, the MD section includes a portion of the semiconductor substrate and / or epitaxial layer, and its doping level, for example based on an implantation process, is sufficient to give the section a low-resistance level. In various embodiments, the doped MD section includes one or more dopant materials with a doping concentration of about 1*10 16 / cubic centimeter (cm -3 ) or higher.

[0054] In some embodiments, the manufacturing process includes two MD layers, and the MD region / section, such as MD region / section MD, refers to the two MDs in the manufacturing process.

[0055] The gate region / structure, such as gate regions / structures G0 - G5, is a region in the IC layout included in the manufacturing process as part of the defined gate structure. The gate structure is a volume that includes one or more conductive sections (such as gate electrodes) that include one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru) or one or more other metals or other suitable materials, and is substantially surrounded by one or more insulating materials, and one or more conductive sections are configured to control the voltage supplied to an adjacent gate dielectric layer.

[0056] The gate dielectric layer, such as the gate dielectric layer of gate structures G0 - G5, includes one or more insulating materials, such as silicon dioxide, silicon nitride (Si3N4) and / or one or more other suitable materials, such as a low-k material with a k value less than 3.8 or a high-k material with a k value greater than 3.8 or 7.0, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5) or titanium oxide (TiO2), suitable for providing a high resistance between IC structural elements, i.e., a resistance level above a predetermined threshold that corresponds to one or more tolerance levels for resistance-based circuit performance.

[0057] The cut gate region, e.g., cut gate region CG, which is also referred to as the cut poly (CPO) region CG in some embodiments, is a region included in an IC layout in a manufacturing process as part of defining a gate electrode (which is removed and replaced with one or more dielectric materials in an operation after the gate electrode is formed to electrically isolate adjacent portions of the gate electrode from each other).

[0058] The isolation component / structure, e.g., isolation component / structure ISO, is a feature of one or more regions included in an IC layout in a manufacturing process as part of defining an isolation structure and is configured to electrically isolate adjacent components (e.g., adjacent gate electrode portions) from each other based on the cut gate region of the IC layout. In some embodiments, the isolation component / structure, e.g., isolation component / structure ISO, includes a dielectric region / volume located between adjacent components (e.g., gate regions / structures G2 and G4 or G3 and G5). The dielectric region is a region included in the IC layout during a manufacturing process as part of defining a volume that includes one or more insulating materials.

[0059] In some embodiments, the isolation component / structure includes a dielectric region corresponding to a dummy (e.g., electrically isolated) gate region / structure (e.g., dummy gate region / structure D1 or D2). In some embodiments, the dummy gate region / structure includes a gate region / structure that is electrically connected (e.g., bonded) to one or more components (e.g., adjacent instances of the S / D region / structure SD) to turn off a corresponding transistor. In some embodiments, a dummy gate region / structure that overlaps / covers an edge of an active region / area (e.g., dummy gate region / structure D1 or D2) is referred to as a continuous poly on oxide definition edge (CPODE) region / structure.

[0060] A metal line or region, e.g., a power supply line VSS or a bit line BL, is a region included in an IC layout in a manufacturing process as part of defining a metal line structure or section that includes one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials, in a given metal layer of the manufacturing process.

[0061] In some embodiments, the metal region / section corresponds to the first front-side metal layer of the manufacturing process (which is also referred to as the metal zero layer M0 or the front-side metal zero layer M0 in some implementations), or a second or higher-level front-side metal layer, such as the metal layer M1 discussed below.

[0062] In some embodiments, the metal region / section corresponds to the first backside metal layer of the manufacturing process (also referred to as backside metal layer zero BM0 in some implementations), or a second or higher-level backside metal layer, such as backside metal layer BM1 discussed below.

[0063] The via region / structure, such as the via regions or structures VG or VD, VIA0, VB, or BVIA0 discussed below, is an area in the IC layout that, as part of defining the via structure, includes one or more conductive materials configured to provide an electrical connection between a first (e.g., overlying) conductive structure (e.g., metal segments WL0 - WL3 or metal line VSS or BL) and a second (e.g., underlying) conductive structure (e.g., the gate electrodes of gate structures G0 - G5) or MD section (e.g., an instance of MD section MD) or S / D structure (e.g., an instance of S / D structure SD) aligned in the positive or negative Z direction.

[0064] In some embodiments, the via region / structure, such as the via region or structure VB discussed below, corresponds to the electrical connection between a first conductive structure and a second conductive structure, where the first conductive structure is a backside conductive structure, such as a backside metal region / section in backside metal layer BM0.

[0065] Figure 3A and Figure 3B Depicts the corresponding front and backside plan views and key of the IC device / layout in the X and Y directions 300 according to some embodiments. Figure 4A and Figure 4B Depicts the IC device / wiring diagram 400 in the X and Y directions and key. The IC device / layout diagrams 300 and 400 (also referred to as ROM arrays 300 and 400 in some embodiments) include most of the features common to the respective IC device / wiring diagrams 100 and 200 described above, except for the arrangement of the gate regions / structures G0 - G7 and word lines WL0 - WL3 as described below.

[0066] Each of the IC device / layout diagrams 300 and 400 includes active regions / areas A0 - A3 and instances of S / D regions / structures and MD regions / sections arranged as described above with respect to Figures 1A - 2B The IC device / layout diagram 300 includes front and backside metal layers / sections, including the corresponding bit lines BL0 - BL3 and source line VSS as described above with respect to the IC device / wiring diagrams 100 and Figure 1A and Figure 1B The IC device / layout diagram 400 includes front and backside metal layers / sections, including the corresponding source line VSS and bit lines BL0 - BL3 as described above with respect to the IC device / layout diagrams 200 and Figure 2A and Figure 2B The corresponding source line VSS and bit lines BL0 - BL3 as described above.

[0067] Compared with the IC device / layout diagrams 100 and 200, each of the IC device / wiring diagrams 300 and 400 includes three instances of a cut gate region CG extending between the dummy gate regions D1 and D2, such that each of the gate regions / structures G0 and G1 intersects / overlaps each of the active regions / areas A0 and A1, rather than intersecting / overlapping the active regions A0 - A3. Each of the gate regions / structures G6 and G7 intersects / overlaps each of the active regions / areas A2 and A3.

[0068] Thus, each of the gate regions / structures G0 - G3 has a first end point at an instance of the cut gate region CG, the instance of the cut gate region CG extends along the top horizontal portion of the boundary PR and corresponds to four instances of the isolation structure ISO, and each of the gate regions / structures G4 - G7 has a first end point at an instance of the cut gate region CG, the instance of the cut gate region CG extends along the bottom horizontal portion of the boundary PR and corresponds to three instances of the isolation structure ISO.

[0069] In Figures 3A - 4B the illustrated embodiment, each of the gate regions / structures G0 - G7 has a second end point at a third instance of the cut gate region CG, the third instance extends between the active regions / areas A1 and A2 and corresponds to four instances of the isolation structure ISO. In some embodiments, the IC layout diagrams 300 and / or 400 do not include the third instance of the cut gate region CG corresponding to four instances of the isolation structure ISO, and the gate regions / structures G0 - G3 are continuous with the corresponding gate regions / structures G4 - G7 such that the corresponding gate electrodes overlap each of the active regions A0 - A3.

[0070] As Figures 3A - 4B shown, the IC device / layout diagrams 300 and 400 include instances of a metal region / section WL0 that intersects / overlaps each of the gate regions / structures G0 and G6 and the corresponding via regions / structures VG, instances of a metal region / section WL1 that intersects or covers the gate regions / structures G1 and G7 and the corresponding via regions / structures VG, instances of a metal region or section WL2 that intersects / overlaps the gate regions / structures G2 and G4 and the corresponding via regions / structures VG, and instances of a metal region / section WL3 that intersects / overlaps the gate regions / structures G3 and G5 and the corresponding via regions / structures VGA.

[0071] Figure 5 A portion of the IC device / layout diagrams 100 - 400 and the elements in the X and Z directions are shown according to some embodiments. Figure 5 The elements shown are not necessarily included in the same X - Z plane or aligned along the shown X direction, and the shown arrangement is only for illustrating the relative positions of the elements of the IC device / layout diagrams 100 - 400 along the Z direction.

[0072] As Figure 5 shown, the active region / zone OD represents one of the active regions / zones A0 - A3. The gate region / structure PO located on the active region / zone OD represents one of the gate regions / structures G0 - G7. The front - side via region / structure VG is located on the gate electrode of the gate region / structure PO, and the first front - side metal region / section M0 located in the first front - side metal layer and on the front - side via region / structure VG represents one of the metal regions / sections WL0 - WL3. The first front - side via region / structure VIA0 located on the first front - side metal region / section M0 and the first side metal region / section M1 located in the second front - side metal layer and on the first front - side via region / structure VIA0 represent another electrical connection of a word line corresponding to one of the metal regions / sections WL0 - WL3.

[0073] The MD region / section MD is located on the active region / zone OD, the front - side via region / structure VD is located on the MD region / section MD, and the second front - side metal region / section M0 located in the first front - side metal layer and on the front - side via region / structure VD represents one of the bit lines BL0 - BL3 or the source line VSS. The second front - side via region / structure VIA0 located on the second front - side metal region / section M0 and the second front - side metal region / section M1 located in the second front - side metal layer and on the second front - side via region / section VIA0 represent another electrical connection of one of the bit lines BL0 - BL3 or the source line VSS.

[0074] The back - side via region / structure VB is located on the active region / zone OD, and the back - side metal region / section BM0 located in the first back - side metal layer and on the back - side via region / structure VG represents one of the bit lines BL0 - BL3 or the source line VSS. The back - side via region / structure BVIA0 located on the back - side metal region / section BM0 and the back - side metal region / section BM1 located in the second back - side metal layer and on the back - side via structure BVIA represent another electrical connection of one of the bit lines BL0 - BL3 or the source line VSS.

[0075] With the above configuration, each of the IC devices / layouts 100 - 400 includes a four - row R0 - R3 array of ROM bits B(0,0) - B(3,3), and each row includes a total of four ROM bits (one row is highlighted and labeled for clarity). Figures 1A - 4A Each ROM bit B(0,0) - B(3,3) (corresponding to B(word - line number, row number)) includes the intersection / overlap of the gate regions / structures G0 - G5 (electrically connected to the corresponding word line WL, e.g., including the metal regions / sections WL0 - WL3) and the active regions / zones A0 - A3, as well as adjacent active sections, including two adjacent S / D regions / structures SD and the overlying MD region / section MD.

[0076] By further including electrical connections between two adjacent active regions / region portions and each of the corresponding front-side or back-side bit lines BL0-BL3 and front-side or back-side source lines VSS, e.g., through the corresponding S / D regions / structures SD, MD regions / sections MD, and via regions / structures VD to the front-side metal lines, or through the corresponding back-side via regions or structures VB to the back-side metal lines, a given ROM bit is considered to have a first logic state corresponding to a functional transistor, e.g., logic 1, as discussed below with respect to Figures 6 - 10B discussed. By further including a single or no electrical connection between two adjacent active regions / region portions and the corresponding bit lines BL0-BL3 or source lines VSS, or including an electrical connection between each adjacent active region / region portion and a single one of the bit lines BL0-BL3 or source lines VSS, a given ROM bit is considered to have a second logic state corresponding to a non-functional transistor, e.g., logic 0.

[0077] In Figures 1A - 4B the illustrated embodiments, each of the IC devices / layouts 100-400 does not include an instance of the front-side via region / structure VD or the back-side via region / structure VB, and thus each ROM bit B(0,0)-B(3,3) has a second logic state corresponding to no electrical connection to the corresponding bit lines BL0-BL3 or source lines VSS. In some embodiments, e.g., the non-limiting examples of the IC devices / layouts 700-1000 discussed below with respect to Figures 6 - 10B the IC devices / wiring diagrams 100-400 include one or more of the ROM bits B(0,0)-B(3,3) that have a first logic state corresponding to an electrical connection (including via regions / structures VD and VB to each corresponding bit line BL0-BL3 and source line VSS).

[0078] As Figures 1A - 4B each of the four ROM bits B(0,0)-B(3,0) in row R0 includes a total of five S / D regions / structures SD, corresponding to three S / D regions / structures SD shared between adjacent ROM bits corresponding to the four ROM bits B(0,0)-B(3,0). The configurations of the ROM bits B(0,1)-B(3,1) in row R1, B(0,2)-B(3,2) in row R2, and B(0,3)-B(3,3) (not labeled) in row R3 are similar.

[0079] Accordingly, each of the IC devices / layouts 100 - 400 is configured to include an array of ROM bits B(0,0) - B(3,3), each row among rows R0 - R3 including a total of four ROM bits, the ROM bits being located in four active regions A0 - A3, a first metal wire including one of bit lines BL0 - BL3 or source line VSS above the active regions in the first front - side metal layer, and a second metal wire including the other of bit lines BL0 - BL3 or source line VSS below the active regions in the first back - side metal layer. Compared with other methods, for example, those methods where both the bit lines and the source line are located in the front - side metal layer, the IC device / layout diagrams 100 - 400 are thus capable of having a smaller total area and increased bit line and source line widths, thereby reducing resistance.

[0080] Figure 6 is a schematic diagram 600 of an IC according to some embodiments, Figures 7A - 10B is the corresponding front - side and back - side plan views of IC device / layout diagrams 700 - 1000 corresponding to the schematic diagram 600.

[0081] IC device / layout diagrams 700 - 1000 are non - limiting examples of respective IC device / wiring diagrams 100 - 400 including ROM bits, each of the ROM bits having a first logic state corresponding to logic 1 (logic 1 ROM bit) and a second logic state corresponding to logic 0 (logic 0 ROM bit). In addition to Figures 1A - 4B the features shown in Figures 7A - 10A also include an example of a front - side via region / structure VD (labeled as a single for clarity), Figures 7B - 10B including an example of a back - side via region or structure VB (labeled as a single for clarity), as described below.

[0082] As Figure 6 shown, the four rows of ROM bits (corresponding to rows R0 - R3) in the schematic diagram 600 represent non - limiting examples of bytes including logic 0 and logic 1 ROM bits to have values 0100, 0101, 0110, and 0111. IC schematic diagrams 600 including other byte values (e.g., ranging from 0000 to 1111) are within the scope of the present disclosure.

[0083] As Figures 7A - 10B shown, the IC device / layout diagrams 700 - 1000 can be used as the corresponding diagrams among the IC device / wiring diagrams 100 - 400 discussed above Figures 1A - 5 and adding examples of via regions / structures VD and VB, as described below.

[0084] In Figure 7A 、 Figure 7B 、 Figure 9A and Figure 9BIn the illustrated embodiments, the corresponding IC device / layout 700 or 900 includes each logic 1 ROM bit location, including a front via region / structure VD located between an adjacent MD region / section MD (and underlying S / D region / structure SD and active region / section A0 - A3 portions) and one of the corresponding overlying bit lines BL1 - BL3, and a back via region / structure VB located between another adjacent active region / section A0 - A3 and the corresponding underlying source line VSS. Each logic 0 ROM bit includes zero via regions / structures VD or VB, a single front via region / structure VD corresponding to the active region / section A0 - A3 portion shared with an adjacent logic 1 ROM bit, a single back via region and structure VB corresponding to the active region / section A0 - A3 portion shared with an adjacent logic 1 ROM bit, or, in the case of position B (WL2, BL1), a back via region / structure VB located between each adjacent active region / section A1 portion and the corresponding back source line VSS.

[0085] In Figure 8A , Figure 8B , Figure 10A and Figure 10B the illustrated embodiments, the corresponding IC device / layout 800 or 1000 includes each logic 1 ROM bit location, including a front via region / structure VD located between an adjacent MD region / section MD (and underlying S / D region / structure SD and active region / section A0 - A3 portions) and the corresponding overlying source line VSS, and a back via region / structure VB located between another adjacent active region / section A0 - A3 portion and the corresponding underlying bit lines BL0 - BL3. Each logic 0 ROM bit includes zero via regions / structures VD or VB, a single front via region / structure VD corresponding to the active region / section A0 - A3 portion shared with an adjacent logic 1 ROM bit, a single back via region / structure VB corresponding to the active region / section A0 - A3 portion shared with an adjacent logic 1 ROM bit, or, in the case of position B (WL2, BL1), a back via region / structure VB located between each adjacent active region / section A1 portion and the bit line BL1.

[0086] Figures 6 - 10B FIG. depicts a non - limiting example of an IC device / layout 100 - 400 configured to include logic 1 and logic 0 ROM bits such that byte values from 0000 - 1111 can be programmed. Other configurations of the IC device / layout 100 including logic 1 and logic 0 ROM bits are also within the scope of the present disclosure, where byte values from 0000 - 1111 can be programmed.

[0087] In some embodiments, multiple instances of the IC device / layout diagrams 100 - 400, e.g., including the logic 1 and logic 0 ROM bits as described above, are positioned adjacent to each other along the X and / or Y directions, e.g., in one or more columns and one or more rows of the IC device / wiring diagrams 100 - 400.

[0088] In such embodiments, each instance of the IC device / layout diagrams 100 - 400 includes electrical connections to each of the word lines WL0 - WL3. In some embodiments, the electrical connections are from each instance of a respective one of the word lines WL0 - WL3 to a shared component, such as an input / output (I / O) pad.

[0089] In some embodiments, instances of the IC device / layout diagrams 100 or 200 that are adjacent to each other along the Y direction include adjacent, and thus shared, gate regions / structures as described above Figures 1A - 2B e.g., including gate regions G2 and G4 in the instance word line WL2 or including gate regions G3 and G5 in the instance of the word line WL3. Thus, the respective instances of the gate regions / structures G2 / G4 and G3 / G5 included in the word lines WL2 and WL3 have a length in the Y direction equal to the length of the instances of the gate regions / structures G0 and G1 included in the word lines WL0 and WL1.

[0090] Thus, the instances of the gate regions / structures G2 / G4 and G3 / G5 included in the word lines WL2 and WL3 also have a staggered position relative to the instances of the gate regions / structures G0 and G1 included in the word lines WL0 and WL1, where the instances of the metal regions / sections WL1 and WL3 are aligned with each other in the X direction, and the instances of the metal regions / sections WL0 and WL2 are aligned with each other in the X direction.

[0091] Such embodiments are thus configured to include multiple instances of the IC device / layout diagrams 100 or 200, including corresponding gate regions / structures of equal length electrically connected to a single word line, thereby having more uniform parasitic capacitance, resistance, and leakage characteristics than other methods (e.g., where the corresponding gate regions / sections electrically connected to a single word line have significantly varying lengths).

[0092] Figure 11 is a schematic diagram 1100 of an IC according to some embodiments, Figures 12A - 13B is a corresponding front - side and back - side plan view of the IC device / layout diagrams 1200 - 1300 corresponding to the schematic diagram 1100.

[0093] The IC device / layout diagrams 1200 and 1300 (also referred to as ROM arrays 1200 and 1300 in some embodiments) include the above - mentioned Figures 1A - 8BThe corresponding IC device / wiring diagrams 100 and 200 and the X and Y directions are discussed, where, for clarity, Figures 1A - 2B the various features marked in

[0094] each of the IC device / layout diagrams 1200 and 1300 also includes a pseudo-array DA1 adjacent to the IC device / wiring diagram 100 or 200 in the positive Y direction and a pseudo-array DA2 adjacent to it in the negative Y direction. Each of the pseudo-arrays DA1 and DA2 includes two active region / area instances corresponding to the active regions / areas A0 - A3 (not marked for clarity), two instances of a metal region / section pseudo-BL corresponding to the bit lines BL0 - BL3, and two examples of the source line VSS, extending in the X direction between instances of the pseudo-gate region / structure D1 and D2 (not marked for clarity purposes), as described above with respect to Figures 1A - 10B stated.

[0095] As Figure 12A and Figure 12B shown, the IC device / layout diagram 1200 includes a front-side metal region / section containing an instance of the pseudo-BL and a back-side region / section containing an instance of the source line VSS. As Figure 13A and Figure 13B shown, the IC device / layout diagram 1300 includes a front-side metal region / section containing an instance of the source line VSS and a back-side region / section containing an instance of the pseudo-BL.

[0096] The pseudo-array DA1 also includes an instance of the gate region / structure G0 (not marked for clarity) and extensions of the corresponding metal region / section WL0, the pseudo-gate region / structure D3, the gate region / structure G2, and the corresponding metal region / section WL2, as well as an extension of the gate region / structure G3. As Figure 12A and Figure 12B shown, the pseudo-array DA1 of the IC device / layout diagram 1200 includes electrical connections corresponding to those of the schematic diagram 1100 between each active region / area portion adjacent to each of the gate regions / structures G1, G4, and G5 and the corresponding upper source line VSS (through instances of the back-side via region / structure VB and the front-side via region / structure VD, with only a single one marked for clarity). As Figure 13A and Figure 13B shown, the pseudo-array DA1 of the IC device / layout diagram 1300 includes electrical connections corresponding to those of the schematic diagram 1100 between each active region / area portion adjacent to each of the gate regions / structures G1, G4, and G5 and the corresponding upper source line VSS (through instances of the front-side via region / structure VD, with only a single one marked for clarity).

[0097] The dummy array DA2 also includes instances of dummy gate regions / structures D4, gate regions / structures G1 (not labeled for clarity), and corresponding metal regions / sections WL1, extensions of gate regions / structures G4, and extensions of gate regions / structures G5 and corresponding metal regions / sections WL3. As Figure 12A and Figure 12B shown, the dummy array DA2 includes electrical connections corresponding to schematic diagram 1100 (through instances of front-side via regions / structures VD, labeled as a single instance for clarity) between each active region / section adjacent to each gate region / structure G1, G4, and G5 and the corresponding overlying source line VSS. As Figure 13A and Figure 13B shown, the dummy array DA2 includes electrical connections corresponding to schematic diagram 1100 (through instances of front-side via regions / structures VD, labeled as a single instance for clarity) between each active region / section adjacent to each gate region / structure G1, G4, and G5 and the corresponding overlying source line VSS.

[0098] In Figures 12A - 13B the embodiment shown, for illustrative purposes, each of IC device / layout diagrams 1200 and 1300 includes a corresponding IC device / wiring diagram 100 or 200 (including all logic 0 ROM bits) and a single instance of each of dummy arrays DA1 and DA2. In some embodiments, IC device / layout diagrams 1200 and / or 1300 include one or more corresponding IC device / wiring diagrams 100 or 200 and / or multiple instances of dummy arrays DA1 and / or DA2. In some embodiments, IC device / layout diagram 1200 or 1300 includes one or more instances of the corresponding IC device / wiring diagram 100 or 200, and in addition to or instead of logic 0 ROM bits, includes one or more logic 1 ROM bits, e.g., as discussed above with respect to Figures 6 - 10B as discussed.

[0099] By including one or more instances of dummy arrays DA1 and / or DA2, each of IC device / layout diagrams 1200 and 1300 includes gate regions / structures corresponding to a single word line electrical connection having equal length and termination based on source line connections, thereby achieving the above-described uniform parasitic capacitance, resistance, and leakage characteristics.

[0100] Figure 14 is a flowchart of a method 1400 of manufacturing an IC device according to some embodiments. Method 1400 is operable to form some or all of one or more of IC devices 100 - 400, 700 - 1000, 1200, or 1300 discussed above with respect to Figures 1A - 13B discussed.

[0101] In some embodiments, some or all of the operations of method 1400 are performed by performing a plurality of fabrication operations (e.g., lithography, diffusion, deposition, etching, planarization, or one or more of other operations suitable for building a plurality of IC devices in a semiconductor wafer) to build a portion of a plurality of integrated circuit devices (e.g., transistors, logic gates, memory cells, interconnect structures, and / or other suitable devices).

[0102] In some embodiments, the operations of method 1400 are performed in Figure 14 the order shown in. In some embodiments, the operations of method 1400 are performed in an order different from the order shown in Figure 14 . In some embodiments, one or more additional operations are performed before, during, and / or after the operations of method 1400. In some embodiments, performing some or all of the operations of method 1400 includes performing one or more of the operations discussed below with respect to IC fabrication system 1700 and Figure 17 .

[0103] At operation 1402, first through fourth active regions are formed in a semiconductor substrate. In some embodiments, forming the first through fourth active regions includes forming active regions A0 - A3 as discussed above with respect to Figures 1A - 13B .

[0104] Forming the first through fourth active regions includes forming the first through fourth active regions having a length in a first direction equal to five times the gate pitch, e.g., a distance in the X direction equal to five times the gate pitch CPP as discussed above with respect to Figures 1A - 13B .

[0105] In some embodiments, forming the first through fourth active regions includes performing one or more deposition and / or implantation processes in regions of the semiconductor substrate corresponding to one or more instances of ICs 100 - 400, 700 - 1000, 1200, or 1300. In some embodiments, forming the first through fourth active regions includes forming S / D structures and / or MD segments, e.g., S / D structures SD and / or MD segments as discussed above with respect to Figures 1A - 13B .

[0106] In some embodiments, forming the first through fourth active regions includes forming active regions other than the first through fourth active regions, e.g., fifth through eighth active regions aligned with the first through fourth active regions in the X or Y direction as described above, or fifth through eighth active regions configured according to pseudo arrays DA1 and / or DA2 as described above with respect to Figures 11 - 13B .

[0107] In operation 1404, a plurality of gate structures are constructed over the first through fourth active regions. Constructing the plurality of gate structures includes constructing first and second dummy gate structures that are separated by a five-fold gate pitch and are located over the endpoints of the first through fourth active regions, and constructing a plurality of gate electrodes between the first and second dummy gate structures and over the first through fourth active regions. In some embodiments, constructing the plurality of gate structures includes constructing the dummy gate structures D1 and D2 discussed above with respect to Figures 1A - 13B as discussed.

[0108] In some embodiments, constructing the first and second dummy gate structures includes constructing one or more dummy gate structures in addition to the first and second dummy gate structures, e.g., as discussed above with respect to Figures 11 - 13B as described.

[0109] In some embodiments, constructing the plurality of gate electrodes includes constructing the gate electrodes as part of gate structures G0-G5 or G0-G7 located over active regions A0-A3, as discussed above with respect to Figures 1A - 13B as described. In some embodiments, constructing the plurality of gate electrodes includes forming isolation structures adjacent to each gate electrode, e.g., an example of the isolation structure ISO discussed above with respect to Figures 1A - 13B as discussed.

[0110] In some embodiments, constructing the plurality of gate structures includes constructing one or more gate structures in addition to the gate structures located over the first through fourth active regions, e.g., as discussed above with respect to Figures 11 - 13B as described.

[0111] In some embodiments, constructing the plurality of gate structures includes performing one or more of a plurality of fabrication operations, such as lithography, diffusion, deposition, etching, planarization, or other operations suitable for constructing the plurality of gate structures, as discussed above with respect to Figures 1A - 13B as described.

[0112] In operation 1406, an electrical connection is formed from a portion of the first active region adjacent to one of the gate electrodes to one of the front-side bit lines or source lines of the ROM circuit. In some embodiments, forming the electrical connection from the portion of the first active region adjacent to the gate electrode to one of the front-side bit lines or source lines includes forming a front-side via structure VD over examples of the MD structure MD and the S / D structure SD, and forming a portion of the active regions A0-A3 to one or more overlying front-side bit lines BL0-BL3 or source line VSS, as discussed above with respect to Figures 1A - 13B as described.

[0113] In some embodiments, forming the electrical connection from the portion of the first active region includes forming the electrical connection based on a ROM bit programming pattern.

[0114] In some embodiments, forming an electrical connection, e.g., by performing one or more of operations 1406-1410, includes forming one or more via structures and / or metal segments by performing a plurality of fabrication operations, the plurality of fabrication steps including depositing and patterning one or more photoresist layers, performing one or more etching processes, and performing one or more deposition processes, whereby one or more conductive materials are configured to form a continuous low-resistance structure.

[0115] In operation 1408, in some embodiments, an electrical connection is formed from the plurality of gate electrodes to the first through fourth word lines of the ROM circuit. In some embodiments, forming the electrical connection includes forming the metal segments WL0-WL3 of the word lines WL0-WL3 discussed above with respect to Figures 1A - 13B the word lines WL0-WL3.

[0116] In some embodiments, forming an electrical connection from the plurality of gate electrodes to the first through fourth word lines of the ROM circuit includes forming an electrical connection from one or more front-side bit lines in the ROM circuit (e.g., the bit lines BL0-BL3 discussed above with respect to Figures 1A - 13B the bit lines BL0-BL3) to one or more signal sources and / or select circuits, or forming an electrical connection from one or more front-side source lines (e.g., the source line VSS discussed above with respect to Figures 1A - 13B the source line VSS) to one or more power reference voltage nodes.

[0117] At operation 1410, an electrical connection is formed from a second active region portion adjacent to one of the gate electrodes to one of the back-side bit lines or source lines of the ROM circuit. In some embodiments, forming an electrical connection from a second active region portion adjacent to a gate electrode to one of the back-side bit lines or source lines includes forming a back-side via structure VB over a portion of the active regions A0-A3 to reach one or more of the underlying back-side bit lines BL0-BL3 or source line VSS, as discussed above with respect to Figures 1A - 13B the same.

[0118] In some embodiments, forming an electrical connection from a second active region portion adjacent to one of the gate electrodes to one of the back-side bit lines or source lines of the ROM circuit includes forming an electrical connection from one or more back-side bit lines in the ROM circuit (e.g., the bit lines BL0-BL3 discussed above with respect to Figures 1A - 13B the bit lines BL0-BL3) to one or more power reference voltage nodes.

[0119] In some embodiments, forming an electrical connection from the second active region includes forming the electrical connection based on a ROM bit programming pattern.

[0120] By performing some or all of the operations of method 1400, an IC device is fabricated, wherein the ROM bit array includes each of four rows, each row including a total of four ROM bits, a first metal line including one of a bit line or a source line above the active region in a first front-side metal layer, and a second metal line including the other of the bit line or a power line below the active region in a first back-side metal layer, thereby enabling the benefits described above with respect to IC devices 100-400, 700-100, 1200, and 1300.

[0121] Figure 15 is a flowchart of a method 1500 for generating an IC layout, e.g., one or more of the IC layouts 100-400, 700-1000, 1200, or 1300 discussed above with respect to Figures 1A - 13B discussed IC layout 100-400, 700-1000, 1200, or 1300.

[0122] In some embodiments, generating the IC layout includes generating an IC layout corresponding to the IC device fabricated based on the generated IC layout, e.g., the IC devices 100-400, 700-1000, 1200, or 1300 discussed above as Figures 1A - 13B discussed.

[0123] In some embodiments, some or all of method 1500 is performed by a processor of a computer, e.g., the processor 1602 of the IC layout generation system 1600 discussed below with reference to Figure 16 discussed.

[0124] Some or all of the operations of method 1500 can be performed as part of a design process executed in a design house (e.g., the design house 1720 discussed below with reference to Figure 17 discussed).

[0125] In some embodiments, the operations of method 1500 are performed in the Figure 15 order shown. In some embodiments, the operations of method 1500 are performed simultaneously and / or in an order different from the Figure 15 order shown. In some embodiments, one or more operations are performed before, between, during, and / or after one or more of the operations of method 1500.

[0126] In operation 1502, in the IC layout of the ROM circuit, the first through fourth active regions are arranged between the dummy gate regions, the dummy gate regions being spaced five times the gate pitch. In some embodiments, as described above with respect to Figures 1A - 13B arranging the first through fourth active regions between the dummy gate regions includes arranging active regions A0-A3 between dummy gate regions D1 and D2 separated by a five-pitch CPP.

[0127] In some embodiments, arranging the first through fourth adjacent active regions includes arranging active regions other than the first through fourth adjacent active regions. For example, as described above with respect to Figures 1A - 13B as discussed.

[0128] In operation 1504, the first through fourth gate regions are arranged between the dummy gate regions and intersect the first through fourth active regions. In some embodiments, arranging the first through fourth gate regions includes arranging gate regions G0 - G5 or G0 - G7 between the dummy gate regions D1 and D2 and intersecting the active regions A0 - A3, as described above with respect to Figures 1A - 13B as discussed.

[0129] In some embodiments, arranging the first through fourth gate regions includes intersecting the first through fourth gate regions with a cut gate region, such as the cut gate region CG discussed above with respect to Figures 1A - 13B the cut gate region CG discussed above.

[0130] In some embodiments, arranging the first through fourth gate regions includes arranging gate regions other than the first through fourth gate regions. For example, as described above with respect to Figures 1A - 13B as discussed.

[0131] In operation 1506, in some embodiments, electrical connections from the four gate regions to the first through fourth word lines of the ROM circuit are configured in the IC layout. In some embodiments, configuring the electrical connections from the four gate regions to the first through fourth word lines includes configuring instances of metal regions WL0 - WL4 and via regions VG, as described above with respect to Figures 1A - 13B as discussed.

[0132] In some embodiments, configuring the electrical connections from the four gate regions to the first through fourth word lines includes configuring electrical connections from one or more gate regions and from the four gate regions to the first through fourth word lines. For example, as described above with respect to Figures 1A - 13B as discussed.

[0133] In operation 1508, electrical connections from the first and second active region areas adjacent to one or more gate regions to the front - side and back - side bit lines and the source line of the ROM circuit are configured in the IC layout. In some embodiments, configuring the electrical connections from the first and second active region / areas adjacent to one or more gate regions to the front - side and back - side bit lines and the source line of the ROM circuit includes configuring one or more instances of front - side via regions VD, MD regions MD, S / D regions S / D, and / or regions of the active regions A0 - A3 into one or more instances of the front - side bit lines BL0 - BL3 or the source line VSS, and configuring the back - side via region VB and / or regions of the active regions A0 - A4 into one or more of the back - side source line VSS or the front - side bit lines BL0 - BL3, as discussed above with respect to Figures 1A - 13B as discussed.

[0134] In some embodiments, configuring the electrical connections from the first and second active regions adjacent to one or more gate regions to the front-side and back-side bit lines and source lines of the ROM circuit includes configuring the electrical connections from one or more active regions (other than the first and second active regions) to the front-side and back-side bit lines and source lines of the ROM circuit. For example, as described above with respect to Figures 1A - 13B described.

[0135] In some embodiments, configuring the electrical connections from the first and second active regions / areas adjacent to one or more gate regions to the front-side and back-side bit lines and source lines of the ROM circuit includes performing a ROM programming operation.

[0136] In operation 1510, in some embodiments, an IC layout diagram including first to fourth adjacent active regions and first to fourth gate regions is stored in a memory device. In some embodiments, storing the IC layout diagram in the memory device includes storing one or more of the IC layout diagrams 100-400, 700-1000, 1200, or 1300 discussed above with respect to Figures 1A - 13B in the memory device.

[0137] In various embodiments, storing the IC layout diagram in the memory device includes storing the IC layout diagram in a non-volatile, computer-readable memory or cell library (such as a database), and / or includes storing the IC layout diagram through a network. In some embodiments, storing the integrated circuit layout diagram in the memory device includes storing the IC layout diagram in the cell library 1607, the layout diagram 1609, or through the network 1614 of the integrated circuit layout diagram generation system 1600, which will be discussed below with reference to Figure 16 discussed.

[0138] In operation 1512, in some embodiments, one or more manufacturing operations, one or more photolithographic exposures are performed based on the IC layout diagram. Non-limiting examples of performing one or more manufacturing operations (such as one or more photolithographic exposures) based on the IC layout diagram are discussed above in connection with Figure 14 and below in connection with Figure 17 discussed.

[0139] By performing some or all of the operations of method 1500, an IC layout diagram corresponding to the IC device is generated, where the ROM bit array includes each of the four rows, including a total of four ROM bits, including a first metal line that is one of the bit lines or source lines above the active region in the first front-side metal layer, and a second metal line that is the other of the bit lines and source lines below the active region in the first back-side metal layer, thereby enabling the benefits described above with respect to IC devices 100-400, 700-100, 1200, and 1300.

[0140] Figure 16FIG. 0 is a block diagram of an IC layout generation system 1600 according to some embodiments. According to one or more embodiments, the methods of designing an IC layout described herein are realizable, e.g., according to some embodiments, using the IC layout generation system 1600.

[0141] In some embodiments, the IC layout generation system 1600 is a general computing device including a hardware processor 1602 and a non-transitory computer-readable storage medium 1604. Among other things, the storage medium 1604 is also encoded with computer program code 1606, i.e., a set of executable instructions. The execution of the instructions 1606 by the hardware processor 1602 represents (at least in part) an electronic design automation (EDA) tool that implements a part or all of the method, e.g., the method 1500 of generating an IC layout described above (hereinafter referred to as the process and / or method). Figure 15 The processor 1602 is electrically coupled to the computer-readable storage medium 1604 via a bus 1608. The processor 1602 is also electrically coupled to an I / O interface 1610 via the bus 1608. A network interface 1612 is also electrically connected to the processor 1602 via the bus 1608. The network interface 1612 is connected to a network 1614 such that the processor 1602 and the computer-readable storage medium 1604 can be connected to external components via the network 1614. The processor 1602 is configured to execute the computer program code 1606 encoded in the computer-readable storage medium 1604 to enable the IC layout generation system 1600 to be used to execute a part or all of the process and / or method. In one or more embodiments, the processor 1602 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0142] In one or more embodiments, the computer-readable storage medium 1604 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1604 includes semiconductor or solid state memory, magnetic tape, removable computer disks, random access memory (RAM), read-only memory (ROM), rigid disks, and / or optical disks. In one or more embodiments using optical disks, the computer-readable storage medium 1604 includes compact disk read-only memory (CD-ROM), compact disk read / write (CD-R / W), and / or digital video disk (DVD).

[0143]

[0144] ​In one or more embodiments, the computer-readable storage medium 1604 stores computer program code 1606, which is configured to enable the IC layout generation system 1600 (where such execution represents (at least in part) an EDA tool) to be available for performing some or all of the described processes and / or methods. In one or more embodiments, the computer-readable storage medium 1604 also stores information that facilitates the performance of some or all of the described processes and / or methods.

[0145] In one or more embodiments, the computer-readable storage medium 1604 stores a cell library 1607 including the cells disclosed herein, such as the IC layouts 100-400, 700-100, 1200, and / or 1300 discussed above with respect to Figures 1A - 13B the discussion of the IC layouts 100-400, 700-100, 1200, and / or 1300.

[0146] In one or more embodiments, the computer-readable storage medium 1604 stores a layout diagram 1609, including the IC layout diagrams disclosed herein, such as the IC layout tables 100-400, 700-100, 1200, and / or 1300 discussed above with respect to Figures 1A - 13B the discussion of the IC layout tables 100-400, 700-100, 1200, and / or 1300.

[0147] The IC layout generation system 1600 includes an I / O interface 1610. The I / O interface 1610 is coupled to an external circuit. In one or more embodiments, the I / O interface 1610 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor direction keys for passing information and commands to the processor 1602.

[0148] The IC layout generation system 1600 also includes a network interface 1612 coupled to the processor 1602. The network interface 1612 allows the system 1600 to communicate with a network 1614 to which one or more other computer systems are connected. The network interface 1612 includes a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the described processes and / or methods are implemented in two or more IC layout generation systems 1600.

[0149] The IC layout generation system 1600 is configured to receive information through the I / O interface 1610. The information received through the I / O interface 1610 includes one or more of instructions, data, design rules, a standard cell library, and / or other parameters for the processor 1602 to process. This information is transmitted to the processor 1602 via the bus 1608. The IC layout generation system 1600 is configured to receive UI-related information through the I / O interface 1610. This information is stored as a user interface (UI) 1642 in the computer-readable medium 1604.

[0150] In some embodiments, part or all of the process and / or method is implemented as an independent software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application that is part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in of a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by the IC layout generation system 1600. In some embodiments, tools such as those available from CADENCE DESIGN SYSTEMS, INC. are used or another suitable layout generation tool is used to generate a layout diagram including standard cells. The layout diagram including standard cells is generated using a tool such as those available from CADENCE DESIGN SYSTEMS, INC. or another suitable layout generation tool.

[0151] In some embodiments, these processes are implemented as the functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / built-in storage or storage units such as optical discs (such as DVDs), magnetic disks (such as hard disks), semiconductor memories (such as ROMs, RAMs, memory cards), and the like.

[0152] Figure 17 is a block diagram of an IC manufacturing system 1700 according to some embodiments and an associated IC manufacturing process. In some embodiments, based on the IC layout diagram, at least one of the following is manufactured using the manufacturing system 1700: (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0153] In Figure 17 , the IC manufacturing system 1700 includes entities that interact in the design, development, and manufacturing cycle and / or services related to manufacturing the IC device 1760, such as a design house 1720, a mask house 1730, and an IC fabrication plant / manufacturer ("Fab") 1750. The entities in the system 1700 are connected via a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or fewer other entities. In some embodiments, two or more of the design house 1720, the mask house 1730, and the IC fabrication plant 1750 are owned by a single larger company. In some embodiments, two or more of the design house 1720, the mask house 1730, and the IC fabrication plant 1750 coexist in a common facility and use common resources.

[0154] Design studio (or design team) 1720 generates an IC design layout 1722. The IC design layout 1722 includes various geometric patterns, e.g., one or more of the IC layouts 100 - 400, 700 - 100, 1200, or 1300 discussed above with respect to Figures 1A - 13B The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers of the various components that make up the IC device 1760 to be fabricated. The layers are combined to form various IC features. For example, a portion of the IC design layout 1722 includes various IC features such as active regions, gates, sources and drains, metal lines or vias for interlayer interconnects, and bond pad openings formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design studio 1720 implements appropriate design procedures to form the IC design layout 1722. The design process includes one or more of logic design, physical design, or placement and routing. The IC design layout 1722 is presented in the form of one or more data files having geometric pattern information. For example, the IC design layout 1722 can be represented in the GDSII file format or the DFII file format.

[0155] Masking chamber 1730 includes data preparation 1732 and mask fabrication 1744. The masking chamber 1730 uses the IC design layout 1722 to fabricate one or more masks 1745 for use in fabricating the individual layers of the IC device 1760 according to the IC design layout illustration 1722. The masking chamber 1730 performs mask data preparation 1732, in which the IC design layout 1722 is converted into a representative data file (RDF). The mask data preparation 1732 provides the RDF to the mask fabrication 1744. The mask fabrication 1744 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1745 or a semiconductor wafer 1753. The design layout 1722 is manipulated by the mask data preparation 1732 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fabrication plant 1750. In Figure 17 FIG., the mask data preparation 1732 and the mask fabrication 1744 are shown as separate elements. In some embodiments, the mask data preparation 1732 and the mask fabrication 1744 can be collectively referred to as mask data preparation.

[0156] In some embodiments, mask data preparation 1732 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 1722. In some embodiments, mask data preparation 1732 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0157] In some embodiments, mask data preparation 1732 includes a mask rule checker (MRC), which uses a set of mask creation rules to check the IC design layout 1722 that has already been processed in OPC. The set of mask generation rules includes certain geometric and / or connectivity restrictions to ensure sufficient margins to account for variability in the semiconductor manufacturing process, etc. In some embodiments, MRC modifies the IC design layout 1722 to compensate for limitations during mask manufacturing 1744, which may undo some of the modifications performed by OPC to meet the mask creation rules.

[0158] In some embodiments, mask data preparation 1732 includes lithography process checking (LPC), which simulates the process that will be implemented by the IC foundry 1750 to fabricate the IC device 1760. LPC simulates the process based on the IC design layout 1722 to create a simulated fabricated device, such as the IC device 1760. The process parameters in the LPC simulation can include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc. or combinations thereof. In some embodiments, after LPC creates the simulated fabricated device, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout 1722.

[0159] It should be understood that the above description of mask data preparation 1732 has been simplified for clarity. In some embodiments, data preparation 1732 includes additional features, such as a logic operation (LOP) that modifies the IC design layout 1722 according to manufacturing rules. Additionally, the processes applied to the IC design layout 1722 during data preparation 1732 can be performed in various different orders.

[0160] After mask data preparation 1732 and during mask manufacturing 1744, a mask 1745 or a set of masks 1745 is manufactured based on the modified IC design layout 1722. In some embodiments, mask manufacturing 1744 includes performing one or more lithographic exposures based on the IC design layout 1722. In some embodiments, based on the modified IC design layout 1722, a pattern is formed on the mask (photomask or reticle) 1745 using an electron beam (e-beam) or a mechanism of multiple electron beams. The mask 1745 can be formed using various techniques. In some embodiments, the mask 1745 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) or EUV beam, for exposing an image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary mask version of the mask 1745 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 1745 is formed using a phase shift technique. In the phase shift mask (PSM) version of the mask 1745, various features in the pattern formed on the phase shift mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask manufacturing 1744 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 1753, in an etching process to form various etched regions in the semiconductor wafer 1753, and / or in other suitable processes.

[0161] IC foundry 1750 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC foundry 1750 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end-of-line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end-of-line (BEOL) fabrication) for the interconnect and packaging of IC products, and a third manufacturing facility can provide other services for the foundry business.

[0162] IC foundry 1750 includes wafer manufacturing tools 1752 that are configured to perform various manufacturing operations on the semiconductor wafer 1753, thereby manufacturing the IC device 1760 according to a mask (e.g., mask 1745). In various embodiments, the manufacturing tools 1752 include one or more of a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes described herein.

[0163] IC fabricator 1750 uses mask 1745 fabricated by mask chamber 1730 to fabricate IC device 1760. Thus, IC fabricator 1750 uses IC design layout 1722 at least indirectly to fabricate IC device 1760. In some embodiments, semiconductor wafer 1753 is fabricated by IC fabricator 1750 using mask 1745 to form IC device 1760. In some embodiments, IC fabrication includes performing one or more photolithography exposures at least indirectly based on IC design layout 1722. Semiconductor wafer 1753 includes a silicon substrate or other suitable substrate with material layers formed thereon. Semiconductor wafer 1753 also includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent fabrication steps).

[0164] In some embodiments, the ROM array includes: a first row to a fourth row of four ROM bits, positioned along a corresponding first active region to a fourth active region on the front side of a semiconductor substrate; a first metal line to a fourth metal line, aligned with the first active region to the fourth active region in a first direction and located in a first front-side metal layer of the semiconductor substrate; and a fifth metal line to an eighth metal line, aligned with the first active region to the fourth active region in the first direction and located in a first back-side metal layer of the semiconductor substrate, wherein the first metal line to the fourth metal line includes one of a bit line or a source line of the ROM array, and the fifth metal line to the eighth metal line includes the other of the bit line or the source line of the ROM array. In some embodiments, each of the four ROM bits in each row of ROM bits includes a gate structure in a corresponding active region and two source / drain (S / D) structures adjacent to the gate structure, and three of the S / D structures in each row of ROM bits are shared by four ROM bits. In some embodiments, each of the first active region to the fourth active region extends between a first dummy gate structure and a second dummy gate structure, the first dummy gate structure and the second dummy gate structure and the gate structure of each of the four ROM bits in each row of ROM bits are spaced apart by a gate pitch, and the first dummy gate structure and the second dummy gate structure are separated by a distance corresponding to five times the gate pitch. In some embodiments, at least one of the four ROM bits in each row of ROM bits further includes: a front-side via structure located between one of the two S / D structures and a corresponding one of the first metal line to the fourth metal line; and a back-side via structure located between the other of the two S / D structures and a corresponding one of the fifth metal line to the eighth metal line. In some embodiments, the ROM array includes: a first gate electrode shared by the first ROM bit in each of the first row to the fourth row of ROM bits; a second gate electrode shared by the second ROM bit in each of the first row to the fourth row of ROM bits; a third gate electrode shared by the third ROM bit in each of the first row and the second row of ROM bits; a fourth gate electrode shared by the fourth ROM bit in each of the first row and the second row of ROM bits; a fifth gate electrode shared by the third ROM bit in each of the third row and the fourth row of ROM bits; and a sixth gate electrode shared by the fourth ROM bit in each of the third row and the fourth row of ROM bits.In some embodiments, the ROM array includes: the fifth to eighth rows of ROM bits, including corresponding fifth to eighth active regions, wherein the fifth active region is adjacent to the fourth active region, each of the fifth to eighth rows of ROM bits includes four ROM bits positioned along a respective one of the fifth to eighth active regions, the fifth gate electrode is also shared by the third ROM bit in each of the fifth and sixth rows of ROM bits, and the sixth gate electrode is also shared by the fourth ROM bit in each of the fifth and sixth rows of ROM bits; a seventh gate electrode, shared by the first ROM bit in each of the fifth to eighth rows of ROM bits; an eighth gate electrode, shared by the second ROM bit in each of the fifth to eighth rows of ROM bits; a ninth gate electrode, shared by the third ROM bit in each of the seventh and eighth rows of ROM bits; a tenth gate electrode, shared by the fourth ROM bit in each of the seventh and eighth rows of ROM bits; ninth to twelfth metal lines, aligned with the fifth to eighth active regions in the first direction and including one of the bit lines or the source lines located in the first front-side metal layer; and thirteenth to sixteenth metal lines, aligned with the fifth to eighth active regions in the first direction and including the other of the bit lines or the source lines located in the first back-side metal layer. In some embodiments, the ROM array includes: the first and second rows of pseudo-ROM bits include corresponding fifth and sixth active regions, wherein the fifth active region is adjacent to the fourth active region, each of the first and second rows of pseudo-ROM bits includes three pseudo-ROM bits positioned along a respective one of the fifth or sixth active regions, the fifth gate electrode is also shared by the second pseudo-ROM bit in each of the first and second rows of pseudo-ROM bits, and the sixth gate electrode is also shared by the third pseudo-ROM bit in each of the first and second rows of pseudo-ROM bits; a seventh gate electrode, shared by the first pseudo-ROM bit in each of the first and second rows of pseudo-ROM bits; ninth and tenth metal lines, aligned with the fifth and sixth active regions in the first direction and located in the first front-side metal layer; and eleventh and twelfth metal lines, aligned with the fifth and sixth active regions in the first direction and located in the first back-side metal layer. In some embodiments, the first to fourth metal lines include the bit lines, the ninth and tenth metal lines include the pseudo-bit lines of the ROM array, the fifth to eighth metal lines, the eleventh and twelfth metal lines include the source lines, and each pseudo-ROM bit includes a first back-side via structure and a second back-side via structure located between a respective one of the fifth or sixth active regions and a respective one of the eleventh or twelfth metal lines.In some embodiments, the first metal line to the fourth metal line, the ninth metal line, and the tenth metal line include the source line, the fifth metal line to the eighth metal line include the bit line, the eleventh metal line and the twelfth metal line include the pseudo-bit line of the ROM array, and each pseudo-ROM bit includes a first front via structure and a second front via structure located between a corresponding fifth active region or sixth active region and a corresponding ninth metal line or tenth metal line. In some embodiments, the ROM array includes: first gate electrodes to fourth gate electrodes, shared by corresponding first ROM bits to fourth ROM bits in each of the first row and the second row of ROM bits, wherein the first gate electrodes to fourth gate electrodes are electrically connected to corresponding first word lines to fourth word lines through corresponding first gate vias to fourth gate vias; and fifth gate electrodes to eighth gate electrodes, shared by corresponding first ROM bits to fourth ROM bits in each of the third row and the fourth row of ROM bits, wherein the fifth gate electrodes to eighth gate electrodes are electrically connected to corresponding first word lines to fourth word lines through corresponding fifth gate vias to eighth gate vias. In some embodiments, the first gate electrodes to fourth gate electrodes are continuous with the corresponding fifth gate electrodes to eighth gate electrodes.

[0165] In some embodiments, an IC device includes: a first active region to a fourth active region, extending in a semiconductor substrate between a first dummy gate structure and a second dummy gate structure, wherein each of the first active region to the fourth active region includes five source / drain (S / D) structures; a plurality of gate electrodes, extending through the first active region to the fourth active region, wherein the plurality of gate electrodes are offset from each of the first dummy gate structure and the second dummy gate structure by a gate pitch, and the distance between the first dummy gate structure and the second dummy gate structure corresponds to five times the gate pitch; a first metal line to a fourth metal line, aligned with the first active region to the fourth active region in a first direction and located in a first front-side metal layer of the semiconductor substrate; a fifth metal line to an eighth metal line, aligned with the first active region to the fourth active region in the first direction and located in a first back-side metal layer of the semiconductor substrate; a front-side via structure, located between a first S / D structure among the five S / D structures of each of the first active region to the fourth active region and one of the first metal line to the fourth metal line; and a back-side via structure, located between a second S / D structure among the five S / D structures of each of the first active region to the fourth active region and one of the fifth metal line to the eighth metal line. In some embodiments, the first S / D structure and the second S / D structure among the five S / D structures of each of the first active region to the fourth active region are adjacent to the same gate electrode among the plurality of gate electrodes. In some embodiments, the plurality of gate electrodes includes: a first gate electrode and a second gate electrode, extending through each of the first active region to the fourth active region; a third gate electrode and a fourth gate electrode, extending through each of the first active region and the second active region; and a fifth gate electrode and a sixth gate electrode, aligned with the third gate electrode and the fourth gate electrode and extending through each of the third active region and the fourth active region, and the IC device further includes: a ninth metal line to a twelfth metal line, located in the first front-side metal layer and electrically connected to the first gate electrode, the second gate electrode, the fourth gate electrode, and the fifth gate electrode through a gate via structure; a first isolation structure, located between the third gate electrode and the fifth gate electrode; and a second isolation structure, located between the fourth gate electrode and the sixth gate electrode. In some embodiments, the plurality of gate electrodes includes: a first gate electrode to a fourth gate electrode, extending through each of the first active region and the second active region; and a fifth gate electrode to an eighth gate electrode, aligned with the first gate electrode to the fourth gate electrode and extending through each of the third active region and the fourth active region, and the IC device further includes a ninth metal line to a sixteenth metal line located in the first front-side metal layer and electrically connected to the first gate electrode to the eighth gate electrode through a gate via structure. In some embodiments, the first gate electrode to the fourth gate electrode is continuous with the fifth gate electrode to the eighth gate electrode.

[0166] In some embodiments, a method of fabricating an IC device includes: forming a first active region to a fourth active region on a front side of a semiconductor substrate; forming a first metal-like definition (MD) segment to a fifth MD segment on each of the first active region to the fourth active region; constructing a plurality of gate structures, wherein constructing the plurality of gate structures includes: constructing a first dummy gate structure and a second dummy gate structure above an end point of each of the first active region to the fourth active region; and constructing a plurality of gate electrodes extending across the first active region to the fourth active region, wherein the plurality of gate structures include a gate pitch, and the first dummy gate structure and the second dummy gate structure are spaced apart by a distance corresponding to five times the gate pitch; forming a front side via structure on the MD segment among the five MD segments on each of the first active region to the fourth active region; forming a first metal wire to a fourth metal wire in a first front side metal layer of the semiconductor substrate and covering the first active region to the fourth active region, and one of the first metal wire to the fourth metal wire is formed on the front side via structure; forming a back side via structure, the back side via structure straddling the MD segment among the five MD segments on each of the first active region to the fourth active region on one of the first active region to the fourth active region; and forming a fifth metal wire to an eighth metal wire in a first back side metal layer of the semiconductor substrate and below the first active region to the fourth active region, and one of the fifth metal wire to the eighth metal wire is formed on the back side via structure. In some embodiments, forming the front side via structure and forming the back side via structure include forming the front side via structure and the back side via structure adjacent to the same gate electrode among the plurality of gate electrodes. In some embodiments, constructing the plurality of gate electrodes includes: constructing a first gate electrode and a second gate electrode across each of the first active region to the fourth active region; constructing a third gate electrode and a fourth gate electrode across each of the first active region and the second active region; and constructing a fifth gate electrode and a sixth gate electrode across each of the third active region and the fourth active region and separated from the third gate electrode and the fourth gate electrode by an isolation structure, and the method further includes: forming a gate via structure on each of the first gate electrode, the second gate electrode, the fourth gate electrode, and the fifth gate electrode; and forming a ninth metal wire to a twelfth metal wire on the gate via structure. In some embodiments, constructing the plurality of gate electrodes includes: constructing a first gate electrode to a fourth gate electrode extending through each of the first active region and the second active region; and constructing a fifth gate electrode to an eighth gate electrode on each of the third active region and the fourth active region and separated from the first gate electrode to the fourth gate electrode by an isolation structure, and the method further includes: forming a gate via structure on each of the first gate electrode to the eighth gate electrode; and forming a ninth metal wire to a sixteenth metal wire on the gate via structure.

[0167] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages as those introduced in the embodiments herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A read-only memory array, comprising: first to fourth rows of four read-only memory bits are positioned on the front side of the semiconductor substrate along corresponding first to fourth active regions; First to fourth metal lines are aligned with the first to fourth active regions in a first direction and are located in a first front metal layer of the semiconductor substrate; as well as The fifth to eighth metal lines are aligned with the first to fourth active areas in the first direction and are located in the first backside metal layer of the semiconductor substrate. in, The first to fourth metal lines include one of a bit line or a source line of the read-only memory array, and The fifth to eighth metal lines include the other of the bit lines or the source lines of the read-only memory array.

2. The read-only memory array according to claim 1, wherein: Each of the four ROM bits of each row of ROM bits includes a gate structure in a corresponding active region and two source / drain structures adjacent to the gate structure, and The three source / drain structures of each row of ROM bits are shared by the four ROM bits.

3. The read-only memory array according to claim 2, wherein: Each of the first to fourth active regions extends between a first dummy gate structure and a second dummy gate structure, The first dummy gate structure and the second dummy gate structure and the gate structure of each of the four ROM bits of each row of ROM bits are spaced apart by a gate pitch, and The first dummy gate structure and the second dummy gate structure are separated by a distance corresponding to five times the gate pitch.

4. The read-only memory array according to claim 2, wherein: At least one of the four read-only memory bits of each row of read-only memory bits further comprises: a front-side via structure located between one of the two source / drain structures and a corresponding one of the first to fourth metal lines; and A backside via structure is located between the other of the two source / drain structures and a corresponding one of the fifth metal line to the eighth metal line.

5. The read-only memory array according to claim 1 , further comprising: a first gate electrode shared by a first ROM bit in each of the first to fourth rows of ROM bits; a second gate electrode shared by a second ROM bit in each of the first to fourth rows of ROM bits; a third gate electrode shared by a third ROM bit in each of the first and second rows of ROM bits; a fourth gate electrode shared by a fourth ROM bit in each of the first and second rows of ROM bits; a fifth gate electrode shared by a third ROM bit in each of the third and fourth rows of ROM bits; and A sixth gate electrode is shared by a fourth ROM bit in each of the third and fourth rows of ROM bits.

6. The read-only memory array according to claim 5, further comprising: The fifth to eighth rows of read-only memory bits include corresponding fifth to eighth active regions, wherein: The fifth active region is adjacent to the fourth active region, each of the fifth to eighth rows of read-only memory bits includes four read-only memory bits positioned along a corresponding one of the fifth to eighth active regions, The fifth gate electrode is also shared by a third ROM bit in each of the fifth and sixth rows of ROM bits, and said sixth gate electrode is also shared by a fourth read-only memory bit of each of said fifth and sixth rows of read-only memory bits; a seventh gate electrode shared by a first ROM bit in each of the fifth to eighth rows of ROM bits; an eighth gate electrode shared by a second ROM bit in each of the fifth to eighth rows of ROM bits; a ninth gate electrode shared by a third ROM bit in each of the seventh and eighth rows of ROM bits; a tenth gate electrode shared by a fourth ROM bit in each of the seventh and eighth rows of ROM bits; ninth to twelfth metal lines aligned with the fifth to eighth active regions in the first direction and including one of the bit line or the source line located in the first front-side metal layer; and Thirteenth to sixteenth metal lines are aligned with the fifth to eighth active regions in the first direction and include the other of the bit line or the source line in the first backside metal layer.

7. The read-only memory array according to claim 5, further comprising: The first and second rows of pseudo read-only memory bits include corresponding fifth and sixth active regions, wherein: The fifth active region is adjacent to the fourth active region, each of the first row and the second row of dummy read-only memory bits comprises three dummy read-only memory bits positioned along a respective one of the fifth active region or the sixth active region, The fifth gate electrode is also shared by a second pseudo ROM bit in each of the first and second rows of pseudo ROM bits, and the sixth gate electrode is also shared by a third pseudo ROM bit of each of the first and second rows of pseudo ROM bits; a seventh gate electrode shared by a first dummy ROM bit in each of the first and second rows of dummy ROM bits; a ninth metal line and a tenth metal line, aligned with the fifth active region and the sixth active region in the first direction and located in the first front-side metal layer; and An eleventh metal line and a twelfth metal line are aligned with the fifth active region and the sixth active region in the first direction and are located in the first backside metal layer.

8. An integrated circuit device comprising: First to fourth active regions extending in the semiconductor substrate between the first dummy gate structure and the second dummy gate structure, wherein each of the first to fourth active regions includes five source / drain structures; A plurality of gate electrodes extending through the first active region to the fourth active region, wherein: The plurality of gate electrodes are offset from each of the first dummy gate structure and the second dummy gate structure by a gate pitch, and The first dummy gate structure and the second dummy gate structure are separated by a distance corresponding to five times the gate pitch; First to fourth metal lines are aligned with the first to fourth active regions in a first direction and are located in a first front metal layer of the semiconductor substrate; Fifth to eighth metal lines are aligned with the first to fourth active regions in the first direction and are located in the first backside metal layer of the semiconductor substrate; a front-side via structure located between a first source / drain structure of the five source / drain structures of each of the first to fourth active regions and one of the first to fourth metal lines; and A backside via structure is located between a second source / drain structure of the five source / drain structures of each of the first to fourth active regions and one of the fifth to eighth metal lines.

9. The integrated circuit device according to claim 8, wherein: A first source / drain structure and a second source / drain structure of the five source / drain structures of each of the first to fourth active regions are adjacent to the same gate electrode of the plurality of gate electrodes.

10. A method of manufacturing an integrated circuit device, the method comprising: forming first to fourth active regions on the front side of the semiconductor substrate; forming first to fifth metal-shaped defining sections on each of the first to fourth active regions; Constructing a plurality of gate structures, wherein constructing the plurality of gate structures comprises: constructing a first dummy gate structure and a second dummy gate structure over an end point of each of the first to fourth active regions; and A plurality of gate electrodes extending from the first active region to the fourth active region are constructed, wherein The plurality of gate structures include a gate pitch, and The first dummy gate structure and the second dummy gate structure are separated by a distance corresponding to five times the gate pitch; forming a front-side via structure on a metal-shaped defined section among five metal-shaped defined sections on each of the first active area to the fourth active area; A first metal line to a fourth metal line formed in a first front side metal layer of the semiconductor substrate and overlying the first active region to the fourth active region, wherein one of the first metal line to the fourth metal line is formed on the front side via structure; forming a backside via structure that crosses a metal-like defined section among five metal-like defined sections on each of the first to fourth active regions on one of the first to fourth active regions; and Fifth to eighth metal lines are formed in the first backside metal layer of the semiconductor substrate and below the first to fourth active regions, and one of the fifth to eighth metal lines is formed on the backside via structure.

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